Insulating Coating Patents (Class 257/632)
  • Patent number: 10741414
    Abstract: To suppress a change in electrical characteristics and to improve reliability in a semiconductor device using a transistor including an oxide semiconductor. The semiconductor device includes a gate electrode over an insulating surface, an oxide semiconductor film overlapping with the gate electrode, a gate insulating film which is between the gate electrode and the oxide semiconductor film and is in contact with a surface of the oxide semiconductor film, a protective film in contact with an opposite surface of the surface of the oxide semiconductor film, and a pair of electrodes in contact with the oxide semiconductor film. In the gate insulating film or the protective film, the amount of gas having a mass-to-charge ratio m/z of 17 released by heat treatment is greater than the amount of nitrogen oxide released by heat treatment.
    Type: Grant
    Filed: May 2, 2017
    Date of Patent: August 11, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Yasuharu Hosaka, Toshimitsu Obonai, Junichi Koezuka, Yukinori Shima, Masahiko Hayakawa, Takashi Hamochi, Suzunosuke Hiraishi
  • Patent number: 10714618
    Abstract: A semiconductor device includes a substrate having a fin active region pattern having a protruding shape, a device isolation layer pattern covering a side surface of a lower portion of the fin active region pattern, a spacer pattern covering a side surface of a portion of the fin active region pattern that protrudes from a top surface of the device isolation layer pattern, and a source/drain region in contact with a top surface of the fin active region pattern and a top surface of the spacer pattern.
    Type: Grant
    Filed: September 13, 2018
    Date of Patent: July 14, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Geum-jung Seong, Bo-ra Lim, Jeong-yun Lee, Ah-reum Ji
  • Patent number: 10658518
    Abstract: Magnesium Zinc Oxide (MZO)—based high voltage thin film transistor (MZO-HVTFT) is built on a transparent substrate, such as glass. The device has the circular drain and ring-shaped source and gate to reduce non-uniformity of the electric field distribution. Controlled Mg doping in the channel and modulated Mg doping in a transition layer located at the channel-gate dielectric interface improve the device's operating stability and increase its blocking voltage capability over 600V. The MZO HVTFT can be used for fabricating the micro-inverter in photovoltaic system on glass (PV-SOG), and for self-powered smart glass.
    Type: Grant
    Filed: August 18, 2017
    Date of Patent: May 19, 2020
    Assignee: RUTGERS, THE STATE UNIVERSITY OF NEW JERSEY
    Inventors: Yicheng Lu, Wen-Chiang Hong, Chieh-Jen Ku, Kuang Sheng, Rui Li
  • Patent number: 10651234
    Abstract: A device and method for providing the device are described. The device includes a substrate, a MnxN layer overlying the substrate, a multi-layered structure that is non-magnetic at room temperature and a first magnetic layer. The MnxN layer has 2?x?4.75. The multi-layered structure comprises alternating layers of Co and E, wherein E comprises at least one other element that includes Al. The composition of the multi-layered structure is represented by Co1-xEx, with x being in the range from 0.45 to 0.55. The first magnetic layer includes a Heusler compound. The first magnetic layer is in contact with the multi-layered structure and the first magnetic layer forms part of a magnetic tunnel junction.
    Type: Grant
    Filed: August 31, 2018
    Date of Patent: May 12, 2020
    Assignees: Samsung Electronics Co., Ltd.
    Inventors: Jaewoo Jeong, Mahesh G. Samant, Stuart S. P. Parkin, Yari Ferrante
  • Patent number: 10604411
    Abstract: [Problem] Provided is a method for producing a silica sol capable of providing consistent production of the silica sol having a uniform particle size of silica particles in any particle size of the silica particles. [Solution] A method for producing a silica sol is a method including a step of mixing liquid (A) containing an alkaline catalyst, water, and a first organic solvent with liquid (B) containing an alkoxysilane or its condensate and a second organic solvent, and liquid (C1) having a pH of 5.0 or higher and lower than 8.0 and containing water or liquid (C2) containing water and being free of an alkaline catalyst to make a reaction liquid.
    Type: Grant
    Filed: July 25, 2016
    Date of Patent: March 31, 2020
    Assignee: FUJIMI INCORPORATED
    Inventors: Keiji Ashitaka, Masaaki Ito, Jun Shinoda
  • Patent number: 10607831
    Abstract: A semiconductor structure and a method for fabricating the same. The semiconductor structure includes a gallium arsenide substrate, a thiourea-based passivation layer in contact with at least a top surface of the gallium arsenide substrate, and a capping layer in contact with the thiourea-based passivation layer. The method includes passivating a gallium arsenide substrate utilizing thiourea to form a passivation layer in contact with at least a top surface of the gallium arsenide substrate. The method further includes forming a capping layer in contact with at least a top surface of the passivation layer, and annealing the capping layer and the passivation layer.
    Type: Grant
    Filed: May 4, 2017
    Date of Patent: March 31, 2020
    Assignee: International Business Machines Corporation
    Inventors: Yun Seog Lee, Ning Li, Qinglong Li, Devendra K. Sadana
  • Patent number: 10546759
    Abstract: To suppress a change in electrical characteristics and to improve reliability in a semiconductor device using a transistor including an oxide semiconductor. The semiconductor device includes a gate electrode over an insulating surface, an oxide semiconductor film overlapping with the gate electrode, a gate insulating film which is between the gate electrode and the oxide semiconductor film and is in contact with a surface of the oxide semiconductor film, a protective film in contact with an opposite surface of the surface of the oxide semiconductor film, and a pair of electrodes in contact with the oxide semiconductor film. In the gate insulating film or the protective film, the amount of gas having a mass-to-charge ratio m/z of 17 released by heat treatment is greater than the amount of nitrogen oxide released by heat treatment.
    Type: Grant
    Filed: May 2, 2017
    Date of Patent: January 28, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Yasuharu Hosaka, Toshimitsu Obonai, Junichi Koezuka, Yukinori Shima, Masahiko Hayakawa, Takashi Hamochi, Suzunosuke Hiraishi
  • Patent number: 10546745
    Abstract: A method of processing semiconductor material includes applying an organosulfur solution to a top surface of a semiconductor material, the organosulfur solution having at least one organosulfur compound. The at least one organosulfur compound has at least one sulfur atom double bonded to a carbon atom and a pH of not less than 8. An organosulfur solution may be applied at temperatures above 25° C. to increase sulfur deposition rates and increase sulfur coverage on a surface of a semiconductor material.
    Type: Grant
    Filed: December 18, 2017
    Date of Patent: January 28, 2020
    Assignee: International Business Machines Corporation
    Inventors: Yun Seog Lee, Joel Pereira de Souza, Devendra K. Sadana, Marinus Hopstaken
  • Patent number: 10542623
    Abstract: A porous polyimide shaped article has a thickness in a range from 550 ?m to 3,000 ?m and has a relative dielectric constant of 1.8 or less and a dielectric loss tangent of 0.01 or less at 1 MHz. The porous polyimide shaped article satisfies the following formula: 1.2?A?1.6 wherein A represents a square root of a ratio of a pore size D84 where a cumulative percentage by number of pores from smaller sizes is 84% to a pore size D16 where the cumulative percentage by number of the pores from smaller sizes is 16% ((D84/D16)1/2) in a pore size distribution measured by mercury intrusion porosimetry.
    Type: Grant
    Filed: October 23, 2018
    Date of Patent: January 21, 2020
    Assignee: FUJI XEROX CO., LTD.
    Inventors: Hajime Sugahara, Hidekazu Hirose, Katsumi Nukada, Tomoya Sasaki, Kosaku Yoshimura, Akira Imai
  • Patent number: 10533093
    Abstract: The object of the present invention is to provide silica particles which are surface-treated with a silicon compound uniformly and have improved surface characteristics and affinity with a resin. The silica particles according the present invention are surface-treated with a specific silicon compound, wherein C/Si ratio from X-ray photoelectron spectroscopy (XPS) is not less than 0.05.
    Type: Grant
    Filed: February 9, 2015
    Date of Patent: January 14, 2020
    Assignee: NIPPON SHOKUBAI CO., LTD.
    Inventors: Yuji Ono, Hideki Oishi, Shoichi Shibazaki
  • Patent number: 10510585
    Abstract: A method includes forming a carbon-containing layer with a carbon atomic percentage greater than about 25 percent over a first hard mask layer, forming a capping layer over the carbon-containing layer, forming a first photo resist over the capping layer, and etching the capping layer and the carbon-containing layer using the first photo resist as a first etching mask. The first photo resist is then removed. A second photo resist is formed over the capping layer. The capping layer and the carbon-containing layer are etched using the second photo resist as a second etching mask. The second photo resist is removed. A third photo resist under the carbon-containing layer is etched using the carbon-containing layer as etching mask. A dielectric layer underlying the third photo resist is etched to form via openings using the third photo resist as etching mask. The via openings are filled with a conductive material.
    Type: Grant
    Filed: May 16, 2017
    Date of Patent: December 17, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Kai Chen, Jung-Hau Shiu, Chia Cheng Chou, Chung-Chi Ko, Tze-Liang Lee, Chih-Hao Chen, Shing-Chyang Pan
  • Patent number: 10475580
    Abstract: There are provided an oxide dielectric having excellent properties and a solid state electronic device (e.g., a capacitor, a semiconductor device, or a small electromechanical system) having such an oxide dielectric. An oxide layer 30 includes an oxide dielectric (possibly including inevitable impurities) including bismuth (Bi) and niobium (Nb) and having a first crystal phase of a pyrochlore-type crystal structure and a second crystal phase of a ?-BiNbO4-type crystal structure. The oxide layer 30 has a controlled content of the first crystal phase and a controlled content of the second crystal phase, in which the first crystal phase has a dielectric constant that decreases with increasing temperature of the oxide layer 30 in a temperature range of 25° C. or more and 120° C. or less, and the second crystal phase has a dielectric constant that increases with increasing temperature of the oxide layer 30 in the temperature range.
    Type: Grant
    Filed: July 10, 2015
    Date of Patent: November 12, 2019
    Assignees: JAPAN ADVANCED INSTITUTE OF SCIENCE AND TECHNOLOGY, ADAMANT NAMIKI PRECISION JEWEL CO., LTD.
    Inventors: Tatsuya Shimoda, Satoshi Inoue, Tomoki Ariga
  • Patent number: 10424636
    Abstract: A power semiconductor device includes a semiconductor substrate including at least one electrical structure. The at least one electrical structure has a blocking voltage of more than 20V. Further, the power semiconductor device includes an electrically insulating layer structure formed over at least a portion of a lateral surface of the semiconductor substrate. The electrically insulating layer structure embeds one or more local regions for storing charge carriers. Further, the one or more local regions includes in at least one direction a dimension of less than 200 nm.
    Type: Grant
    Filed: December 21, 2016
    Date of Patent: September 24, 2019
    Assignee: Infineon Technologies AG
    Inventors: Andreas Haertl, Martin Brandt, Andre Rainer Stegner, Martin Stutzmann
  • Patent number: 10402019
    Abstract: Provided is a display device that includes a display panel defined with an active area displaying an image and an inactive area outside the active area, the display panel including a substrate having a first surface and a second surface opposite the first surface; a plurality of pixels on the first surface of the substrate in the active area, each pixel including a pixel drive circuit; a transparent conductive layer on the second surface of the substrate covering the active area and a part of the inactive area; and a metal pattern on the second surface of the substrate in the inactive area, the metal pattern electrically connected to the transparent conductive layer, receiving an electrical signal and having a lower resistance than the transparent conductive layer, wherein the metal pattern serves as a conductive path to reduce a potential difference with respect to the electrical signal in an entire area of the transparent conductive layer compared to a display device without the metal pattern.
    Type: Grant
    Filed: October 21, 2016
    Date of Patent: September 3, 2019
    Assignee: LG DISPLAY CO., LTD.
    Inventors: HeungJu Jo, JeongKweon Park, Chan Park, SangHyun Kwon
  • Patent number: 10347483
    Abstract: Structure or device comprising a hexagonal crystal layer or hexagonal crystal substrate, and a (001)-oriented rare earth nitride epitaxial layer on the hexagonal crystal layer or hexagonal crystal substrate.
    Type: Grant
    Filed: May 29, 2017
    Date of Patent: July 9, 2019
    Inventors: Franck Natali, Stéphane Ange Vézian, Jay Ross Peng Cheong Chan, Benjamin John Ruck, Harry Joseph Trodahl
  • Patent number: 10347487
    Abstract: Apparatus and methods of forming an apparatus can include one or more cell contacts in an integrated circuit in a variety of applications. In various embodiments, a resist underlayer can be formed on a dielectric spacer formed on a structure for a cell contact, where the structure can include a patterned area of pillars on a silicon-rich dielectric anti-reflective coating region disposed on a dielectric region. The resist underlayer, the dielectric spacer, the patterned area of pillars, the silicon-rich dielectric anti-reflective coating, and the dielectric region can be processed to form an array of columns in the dielectric region. Regions between the columns of the array of columns can be filled with conductive material, forming the cell contact. Additional apparatus, systems, and methods are disclosed.
    Type: Grant
    Filed: November 14, 2017
    Date of Patent: July 9, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Che-Chi Lee, Hiromitsu Oshima
  • Patent number: 10283352
    Abstract: Semiconductor devices and methods of making semiconductor devices with a barrier layer comprising manganese nitride are described. Also described are semiconductor devices and methods of making same with a barrier layer comprising Mn(N) and, optionally, an adhesion layer.
    Type: Grant
    Filed: March 13, 2018
    Date of Patent: May 7, 2019
    Assignee: Applied Materials, Inc.
    Inventors: Feng Q. Liu, Ben-Li Sheu, David Knapp, David Thompson
  • Patent number: 10249541
    Abstract: A method for fabricating a nanosheet semiconductor structure includes forming a first nanosheet field effect transistor (FET) structure having a first inner spacer comprised of a first material and a second nanosheet FET structure having second inner spacer comprised of a second material. The first material is different than the second material. The first nanosheet FET structure is formed by creating a first inner spacer formation within a first silicon germanium (SiGe) channel, wherein the first SiGe channel is comprised in a first channel region of a first FET region. The second nanosheet FET structure is formed by creating a second inner spacer formation within a second SiGe channel, wherein the second SiGe channel is comprised in a second channel region of a second FET region.
    Type: Grant
    Filed: June 27, 2018
    Date of Patent: April 2, 2019
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Peng Xu
  • Patent number: 10236177
    Abstract: A method for depositing a germanium tin (Ge1-xSnx) semiconductor is disclosed. The method may include; providing a substrate within a reaction chamber, heating the substrate to a deposition temperature and exposing the substrate to a germanium precursor and a tin precursor. The method may further include; depositing a germanium tin (Ge1-xSnx) semiconductor on the surface of the substrate, and exposing the germanium tin (Ge1-xSnx) semiconductor to a boron dopant precursor. Semiconductor device structures including a germanium tin (Ge1-xSnx) semiconductor formed by the methods of the disclosure are also provided.
    Type: Grant
    Filed: August 22, 2017
    Date of Patent: March 19, 2019
    Assignee: ASM IP Holding B.V..
    Inventors: David Kohen, Harald Benjamin Profijt
  • Patent number: 10229973
    Abstract: A semiconductor device includes a semiconductor substrate of a first conductivity type, having a first principal surface and a second principal surface, a silicon carbide semiconductor layer of the first conductivity type, disposed on the first principal surface, a first electrode disposed on the silicon carbide semiconductor layer, and a second electrode disposed on the second principal surface and forming an ohmic junction with the semiconductor substrate. The semiconductor device satisfies 0.13?Rc/Rd, where Rc is the contact resistance between the second principal surface and the second electrode at room temperature and Rd is the resistance of the silicon carbide semiconductor layer in a direction normal to the first principal surface at room temperature.
    Type: Grant
    Filed: April 3, 2017
    Date of Patent: March 12, 2019
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventor: Masao Uchida
  • Patent number: 10224414
    Abstract: A method for forming semiconductor devices with spacers is provided. SiCO spacers are formed on sides of features. Protective coverings are formed over first parts of the SiCO spacers, wherein second parts of the sidewalls of the SiCO spacers are not covered by the protective coverings. A conversion process is provided to the second parts of the SiCO spacers which are not covered by the protective coverings, which changes a physical property of the second parts of the SiCO spacers which are not covered by the protective coverings, wherein the protective coverings protects the first parts of the SiCO spacers from the conversion process.
    Type: Grant
    Filed: December 16, 2016
    Date of Patent: March 5, 2019
    Assignee: Lam Research Corporation
    Inventors: Straford A. Wild, Brian Tessier
  • Patent number: 10177023
    Abstract: In embodiments, manufacturing a protective cover for an electrostatic chuck comprises coating a top surface and side walls of a conductive wafer with a plasma resistant ceramic, masking an inner region of a bottom surface of the conductive wafer, coating inner region of the bottom surface with the plasma resistant ceramic, and grinding the inner region of the bottom surface to a flatness of less than approximately 300 microns. In embodiments, a protective cover is manufactured by a process comprising applying a mask to an outer perimeter of a bottom surface of a plasma resistant ceramic wafer, coating the bottom surface of the plasma resistant ceramic wafer with an electrically conductive layer, and removing the mask, wherein an inner region of the bottom surface of the plasma resistant ceramic wafer is coated with the conductive layer.
    Type: Grant
    Filed: December 13, 2017
    Date of Patent: January 8, 2019
    Assignee: APPLIED MATERIALS, INC.
    Inventor: Vijay D. Parkhe
  • Patent number: 10177165
    Abstract: A method for fabricating a semiconductor integrated circuit (IC) having a SONOS memory device and a logic/analog device requiring different gate oxide layers comprises steps as follows: A substrate having a high voltage region, a memory region and a logic/analog is firstly provided. Next, a first gate oxide layer is formed on the high voltage region, the memory region and the logic/analog. The first gate oxide layer is then patterned to expose the logic/analog region and to define a first channel area and a second channel area respectively on the memory region and the high voltage region. Subsequently, a silicon oxide-silicon nitride-silicon oxide (ONO) structure is formed on the first channel area. A second gate oxide layer is then formed on the logic/analog and patterned to define a third channel area.
    Type: Grant
    Filed: July 5, 2017
    Date of Patent: January 8, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Ping-Chia Shih, Chun-Yao Wang, Ming-Hua Tsai, Wan-Chun Liao
  • Patent number: 10177028
    Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to fully aligned via structures having relaxed gapfills and methods of manufacture. The method includes: selectively depositing a capping material on a conductive material within a plurality of interconnect structures to form capped interconnect structures; depositing at least one insulator material over the capped interconnect structures; forming a fully aligned via structure through the at least one insulator material to expose the capping material; filling the fully aligned via structure with an alternative metal; and depositing a metal material on the alternative metal in the fully aligned via structure.
    Type: Grant
    Filed: July 7, 2017
    Date of Patent: January 8, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Nicholas V. LiCausi, Errol Todd Ryan
  • Patent number: 10177062
    Abstract: Embodiments are directed to a method of passivating a surface of a high-mobility semiconductor and resulting structures having a reduced interface defect density. A semiconductor layer is formed on a substrate. A surface of the semiconductor layer is contacted with a sulfur source including thiourea at a temperature of up to about 90 degrees Celsius to form a sulfur passivation layer on the surface of the semiconductor layer. A dielectric layer is formed on the sulfur passivation layer and a minimum of interface trap density distribution at an interface between the semiconductor layer and the dielectric layer is less than about 2.0×1011 cm?2eV?1.
    Type: Grant
    Filed: November 17, 2017
    Date of Patent: January 8, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Joel P. de Souza, Yun Seog Lee, Kunal Mukherjee, Devendra K. Sadana
  • Patent number: 10170388
    Abstract: Embodiments are directed to a method of passivating a surface of a high-mobility semiconductor and resulting structures having a reduced interface defect density. A semiconductor layer is formed on a substrate. A surface of the semiconductor layer is contacted with a sulfur source including thiourea at a temperature of up to about 90 degrees Celsius to form a sulfur passivation layer on the surface of the semiconductor layer. A dielectric layer is formed on the sulfur passivation layer and a minimum of interface trap density distribution at an interface between the semiconductor layer and the dielectric layer is less than about 2.0×1011 cm?2 eV?1.
    Type: Grant
    Filed: November 17, 2017
    Date of Patent: January 1, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Joel P. de Souza, Yun Seog Lee, Kunal Mukherjee, Devendra K. Sadana
  • Patent number: 10079146
    Abstract: A resist underlayer film composition for lithography, including: a silane: at least one among a hydrolyzable organosilane, a hydrolysis product thereof, and a hydrolysis-condensation product thereof, wherein the silane includes a silane having a cyclic organic group containing as atoms making up the ring, a carbon atom, a nitrogen atom, and a hetero atom other than a carbon and nitrogen atoms. The hydrolyzable organosilane may be a hydrolyzable organosilane of Formula (1), wherein, at least one group among R1, R2, and R3 is a group wherein a —Si(X)3 group bonds to C1-10 alkylene group, and other group(s) among R1, R2, and R3 is(are) a hydrogen atom, C1-10 alkyl group, or C6-40 aryl group; a cyclic organic group of 5-10 membered ring containing atoms making up the ring, a carbon atom, at least one of nitrogen, sulfur or oxygen atoms; and X is an alkoxy group, acyloxy group, or halogen atom.
    Type: Grant
    Filed: September 13, 2013
    Date of Patent: September 18, 2018
    Assignee: NISSAN CHEMICAL INDUSTRIES, LTD.
    Inventors: Yuta Kanno, Makoto Nakajima, Kenji Takase, Satoshi Takeda, Hiroyuki Wakayama
  • Patent number: 10014237
    Abstract: A circuit board includes an insulating substrate; a metal circuit sheet joined to a first principal surface of the insulating substrate; and a heat dissipating sheet made of metal and joined to a second principal surface of the insulating substrate, the second principal surface being opposite the first principal surface. The thickness of the heat dissipating sheet is at least 3.75 times the thickness of the metal circuit sheet. The size of metal grains contained in the heat dissipating sheet is smaller than the size of metal grains contained in the metal circuit sheet, and decreases with increasing distance from the second principal surface of the insulating substrate.
    Type: Grant
    Filed: December 14, 2015
    Date of Patent: July 3, 2018
    Assignee: KYOCERA CORPORATION
    Inventors: Shinichi Kooriyama, Narutoshi Ogawa, Masashi Konagai, Kensou Ochiai, Noritaka Niino
  • Patent number: 10002766
    Abstract: A method of fabricating high-k/metal gate semiconductor device by incorporating an enhanced annealing process is provided. The enhanced annealing process in accordance with the disclosure can be operated at relatively low temperature and high pressure and thus can improve the k value and repair the above-mentioned deficiencies of the HK layer. Under the enhanced annealing process in accordance with the disclosure, H+ can be diffused from the ammonia gas and to repair the broken bonds because of high pressure, while avoiding adversely impact the NiSi and implanted ions in the HK layer due to the low temperature. The enhanced annealing process in accordance with the disclosure can be performed between 300° C. to 500° C. at a pressure of 15-20 atm for 15 to 50 minutes in some embodiments.
    Type: Grant
    Filed: February 10, 2017
    Date of Patent: June 19, 2018
    Assignee: SHANGHAI HUALI MICROELECTRONICS CORPORATION
    Inventor: Zhenping Wen
  • Patent number: 9984949
    Abstract: Embodiments are directed to a method of passivating a surface of a high-mobility semiconductor and resulting structures having a reduced interface defect density. A semiconductor layer is formed on a substrate. A surface of the semiconductor layer is contacted with a sulfur source including thiourea at a temperature of up to about 90 degrees Celsius to form a sulfur passivation layer on the surface of the semiconductor layer. A dielectric layer is formed on the sulfur passivation layer and a minimum of interface trap density distribution at an interface between the semiconductor layer and the dielectric layer is less than about 2.0×1011 cm?2 eV?1.
    Type: Grant
    Filed: January 12, 2017
    Date of Patent: May 29, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Joel P. de Souza, Yun Seog Lee, Kunal Mukherjee, Devendra K. Sadana
  • Patent number: 9972684
    Abstract: A method for forming a compressively strained semiconductor substrate includes forming a lattice adjustment layer on a semiconductor substrate by forming compound clusters within an epitaxially grown semiconductor matrix. The lattice adjustment layer includes a different lattice constant than the semiconductor substrate. A rare earth oxide is grown and lattice matched to the lattice adjustment layer. A semiconductor layer is grown and lattice matched to the rare earth oxide and includes a same material as the semiconductor substrate such that the semiconductor layer is compressively strained.
    Type: Grant
    Filed: March 8, 2017
    Date of Patent: May 15, 2018
    Assignee: International Business Machines Corporation
    Inventors: Karthik Balakrishnan, Pouya Hashemi, Nicolas J. Loubet, Alexander Reznicek
  • Patent number: 9963542
    Abstract: A silicone-modified epoxy resin which yields a cured product having low gas permeability and excellent strength; a composition of the silicone-modified epoxy resin; and an epoxy resin cured product obtainable by curing the composition, are provided. An epoxy resin represented by the following Formula (1): wherein R1 represents a hydrocarbon group having 1 to 6 carbon atoms; X represents an organic group having a norbornane epoxy structure, or a hydrocarbon group having 1 to 6 carbon atoms; n represents an integer from 1 to 3; plural R1s and plural Xs present in the formula may be respectively identical or different; and two or more of plural Xs represent an organic group having a norbornane epoxy structure.
    Type: Grant
    Filed: March 25, 2015
    Date of Patent: May 8, 2018
    Assignees: Shin-Etsu Chemical Co., Ltd., Nippon Kayaku Kabushiki Kaisha
    Inventors: Toshio Shiobara, Junichi Sawada, Miyuki Wakao, Tsutomu Kashiwagi, Naofusa Miyagawa, Yoshihiro Kawada, Chie Sasaki, Naosuke Taniguchi
  • Patent number: 9960151
    Abstract: A semiconductor device includes a chip, a plurality of first bumps, and a plurality of second bumps. The chip includes an active surface. The first bumps are disposed on the active surface along a first direction. The second bumps are disposed on the active surface along a second direction parallel to the first direction, wherein one of the second bumps is located between adjacent two of the first bumps, a closest distance from the second bumps to the fan-out region is smaller than a closest distance from the first bumps to the fan-out region, and a first width of one of the first bumps is larger than a second width of one of the second bumps.
    Type: Grant
    Filed: August 2, 2016
    Date of Patent: May 1, 2018
    Assignee: Novatek Microelectronics Corp.
    Inventors: Chieh-Hsiang Chang, Wen-Ching Huang, Kuo-Yuan Lu, Huang-Chin Tang
  • Patent number: 9935060
    Abstract: A method for processing a wafer in accordance with various embodiments may include: removing wafer material from an inner portion of the wafer to form a structure at an edge region of the wafer to at least partially surround the inner portion of the wafer, and printing material into the inner portion of the wafer using the structure as a printing mask. A method for processing a wafer in accordance with various embodiments may include: providing a carrier and a wafer, the wafer having a first side and a second side opposite the first side, the first side of the wafer being attached to the carrier, the second side having a structure at an edge region of the wafer, the structure at least partially surrounding an inner portion of the wafer; and printing material onto at least a portion of the second side of the wafer.
    Type: Grant
    Filed: February 13, 2017
    Date of Patent: April 3, 2018
    Assignee: Infineon Technologies AG
    Inventors: Srinivasa Reddy Yeduru, Karl Heinz Gasser, Stefan Woehlert, Karl Mayer, Francisco Javier Santos Rodriguez
  • Patent number: 9929192
    Abstract: A radiation detector for detecting ultraviolet energy having a single crystal UV radiation detector material and an amorphous support layer disposed directly on the single crystal UV radiation detector material with the single crystal UV radiation detector material having a c-axis aligned along a direction of the ultraviolet energy being detected.
    Type: Grant
    Filed: September 28, 2016
    Date of Patent: March 27, 2018
    Assignee: Raytheon Company
    Inventors: Delmar L. Barker, Jeffrey Clarke, Charles W. Hicks
  • Patent number: 9916975
    Abstract: Semiconductor devices and methods of making semiconductor devices with a barrier layer comprising manganese nitride are described. Also described are semiconductor devices and methods of making same with a barrier layer comprising Mn(N) and, optionally, an adhesion layer.
    Type: Grant
    Filed: October 21, 2015
    Date of Patent: March 13, 2018
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Feng Q. Liu, Ben-Li Sheu, David Knapp, David Thompson
  • Patent number: 9875900
    Abstract: A method of fabricating a tunnel oxide layer for a semiconductor memory device, the method comprising: fabricating on a substrate a first oxide layer by an in-situ-steam-generation process; and fabricating at least one further oxide layer by a furnace oxidation process, wherein during fabrication of the at least one further oxide layer, reactive gases penetrate the first oxide layer and react with the silicon substrate to form at least a first portion of the at least one further oxide layer beneath the first oxide layer.
    Type: Grant
    Filed: April 13, 2017
    Date of Patent: January 23, 2018
    Assignee: X-FAB SEMICONDUCTOR FOUNDRIES AG
    Inventors: Eng Gek Hee, Ka Siong Wisley Ung
  • Patent number: 9876195
    Abstract: The present disclosure provides a method of packaging an OLED apparatus, an OLED packaging apparatus and a display device, and relates to the field of the OLED. The method includes steps: forming a first inorganic thin film layer on an OLED to be packaged; forming a groove on a surface of the first inorganic thin film layer; forming a second organic thin film layer within the groove; and forming a third inorganic thin film layer covering the first inorganic thin film layer and the second organic thin film layer.
    Type: Grant
    Filed: September 8, 2016
    Date of Patent: January 23, 2018
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., ORDOS YUANSHENG OPTOELECTRONICS CO., LTD.
    Inventors: Fuyi Cui, Xu Chen, Quanqin Sun
  • Patent number: 9863033
    Abstract: What is specified is a method for producing a coating comprising the following steps: —providing a material source having a top surface and a main coating direction, —providing a substrate holder having a top surface, —providing at least one base layer, having a coating surface remote from the substrate holder, on the top surface of the substrate, —attaching the substrate holder to a rotating arm, which has a length along a main direction of extent of the rotating arm, —setting the length of the rotating arm in such a manner that a normal angle (?) throughout the method is at least 30° and at most 75°, —applying at least one coating to that side of the base layer which has the coating surface by means of the material source, wherein—during the coating process with the coating, the substrate holder is rotated about a substrate axis of rotation running along the main direction of extent of the rotating arm.
    Type: Grant
    Filed: June 11, 2015
    Date of Patent: January 9, 2018
    Assignee: OSRAM OPTO SEMICONDUCTORS GMBH
    Inventors: Martin Lemberger, Michael Schmal, Julian Ikonomov
  • Patent number: 9840641
    Abstract: A silicone resin liquid composition containing a silicone resin is provided. The 29Si-NMR measurement of the resin exhibits a ratio of the area of signals assigned to A3 silicon atoms to the area of all signals derived from silicon atoms of 51% to 69%. An A3 silicon atom represents a silicon atom to which are bonded three oxygen atoms bonded to another silicon atom.
    Type: Grant
    Filed: January 24, 2014
    Date of Patent: December 12, 2017
    Assignee: Sumitomo Chemical Company, Limited
    Inventors: Masayuki Takashima, Gaku Yoshikawa, Tsuyoshi Kameda
  • Patent number: 9812530
    Abstract: Thermal condensation is employed to obtain a finned structure including strained silicon germanium fins having vertical side walls and a germanium content that may be high relative to silicon. A hard mask is used directly on a low-germanium content silicon germanium layer. The hard mask is patterned and fins are formed beneath the hard mask from the silicon germanium layer. Thermal condensation in an oxidizing ambient causes the formation of regions beneath the hard mask that have a high germanium content. The hard mask is trimmed to a target critical dimension. The regions beneath the hard mask and adjoining oxide material are subjected to reactive ion etch, resulting in the formation of high-germanium content fins with planar, vertically extending sidewalls.
    Type: Grant
    Filed: March 13, 2016
    Date of Patent: November 7, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Karthik Balakrishnan, John Bruley, Pouya Hashemi, Ali Khakifirooz, John A. Ott, Alexander Reznicek
  • Patent number: 9786495
    Abstract: A method for evaluating a semiconductor film of a semiconductor device which is configured to include an insulating film, the semiconductor film, and a conductive film and to have a region where the semiconductor film and the conductive film overlap with each other with the insulating film provided therebetween, includes a step of performing plasma treatment after formation of the insulating film, and a step of calculating a peak value of resistivity of a microwave in the semiconductor film by a microwave photoconductive decay method after the plasma treatment, so that the hydrogen concentration in the semiconductor film is estimated.
    Type: Grant
    Filed: September 16, 2015
    Date of Patent: October 10, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Akihisa Shimomura, Naoki Okuno, Mitsuhiro Ichijo, Noriyoshi Suzuki, Tetsuhiro Tanaka, Sachiaki Tezuka
  • Patent number: 9765429
    Abstract: A method for depositing a film on a polymer substrate is disclosed. The method includes exposing a polymer substrate to a liquid comprising a first reactant to provide a plurality of reactive sites over the polymer substrate, wherein the first reactant comprises aluminum or boron; and introducing a second reactant comprising silicon in a vapor form to said plurality of reactive sites that provide a catalytic growth of the film, wherein the growth of the film is self-limited. In certain embodiments, the film can include silica, aluminum silicate, or borosilicate.
    Type: Grant
    Filed: September 4, 2014
    Date of Patent: September 19, 2017
    Assignee: President and Fellows of Harvard College
    Inventor: Philippe P. Derouffignac
  • Patent number: 9716173
    Abstract: A method for forming a compressively strained semiconductor substrate includes forming a lattice adjustment layer on a semiconductor substrate by forming compound clusters within an epitaxially grown semiconductor matrix. The lattice adjustment layer includes a different lattice constant than the semiconductor substrate. A rare earth oxide is grown and lattice matched to the lattice adjustment layer. A semiconductor layer is grown and lattice matched to the rare earth oxide and includes a same material as the semiconductor substrate such that the semiconductor layer is compressively strained.
    Type: Grant
    Filed: October 13, 2016
    Date of Patent: July 25, 2017
    Assignee: International Business Machines Corporation
    Inventors: Karthik Balakrishnan, Pouya Hashemi, Nicolas J. Loubet, Alexander Reznicek
  • Patent number: 9713250
    Abstract: A handle substrate having at least one metallization region is provided on a stressor layer that is located above a base substrate such that the at least one metallization region is in contact with a surface of the stressor layer. An upper portion of the base substrate is spalled, i.e., removed, to provide a structure comprising, from bottom to top, a spalled material portion of the base substrate, the stressor layer and the handle substrate containing the at least one metallization region in contact with the surface of the stressor layer.
    Type: Grant
    Filed: October 7, 2015
    Date of Patent: July 18, 2017
    Assignees: International Business Machines Corporation, KING ABDULAZIZ CITY FOR SCIENCE AND TECHNOLOGY
    Inventors: Turki bin Saud bin Mohammed Al-Saud, Stephen W. Bedell, Keith E. Fogel, Paul A. Lauro, Devendra K. Sadana
  • Patent number: 9680182
    Abstract: A composition suitable as a solid polymer electrolyte for a lithium ion battery comprises a mixture of polyoctahedral silsesquioxane-phenyl7(BF3Li)3 and a poly(ethylene oxide).
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: June 13, 2017
    Assignee: TEMPLE UNIVERSITY—OF THE COMMONWEALTH SYSTEM OF HIGHER EDUCATION
    Inventors: Stephanie L. Wunder, Parameswara Rao Chinnam
  • Patent number: 9634115
    Abstract: One illustrative method disclosed herein includes, among other things, forming a first high-k protection layer on the source/drain regions and adjacent the sidewall spacers of a transistor device, removing a sacrificial gate structure positioned between the sidewall spacers so as to thereby define a replacement gate cavity, forming a replacement gate structure in the replacement gate cavity, forming a second high-k protection layer above an upper surface of the spacers, above an upper surface of the replacement gate structure and above the first high-k protection layer, and removing portions of the second high-k protection layer positioned above the first high-k protection layer.
    Type: Grant
    Filed: June 11, 2014
    Date of Patent: April 25, 2017
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Ruilong Xie, Chanro Park, Xiuyu Cai
  • Patent number: 9601371
    Abstract: Low capacitance and high reliability interconnect structures and methods of manufacture are disclosed. The method includes forming a copper based interconnect structure in an opening of a dielectric material. The method further includes forming a capping layer on the copper based interconnect structure. The method further includes oxidizing the capping layer and any residual material formed on a surface of the dielectric material. The method further includes forming a barrier layer on the capping layer by outdiffusing a material from the copper based interconnect structure to a surface of the capping layer. The method further includes removing the residual material, while the barrier layer on the surface of the capping layer protects the capping layer.
    Type: Grant
    Filed: October 14, 2015
    Date of Patent: March 21, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Daniel C. Edelstein, Son V. Nguyen, Takeshi Nogami, Deepika Priyadarshini, Hosadurga K. Shobha
  • Patent number: 9578736
    Abstract: A handle substrate having at least one metallization region is provided on a stressor layer that is located above a base substrate such that the at least one metallization region is in contact with a surface of the stressor layer. An upper portion of the base substrate is spalled, i.e., removed, to provide a structure comprising, from bottom to top, a spalled material portion of the base substrate, the stressor layer and the handle substrate containing the at least one metallization region in contact with the surface of the stressor layer.
    Type: Grant
    Filed: December 23, 2014
    Date of Patent: February 21, 2017
    Assignees: International Business Machines Corporation, King Abdulaziz City for Science and Technology
    Inventors: Turki bin Saud bin Mohammed Al-Saud, Stephen W. Bedell, Keith E. Fogel, Paul A. Lauro, Devendra K. Sadana
  • Patent number: 9577125
    Abstract: The present invention is based on a unique design of a novel structure, which incorporates two quantum dots of a different bandgap separated by a tunneling barrier. Upconversion is expected to occur by the sequential absorption of two photons. In broad terms, the first photon excites an electron-hole pair via intraband absorption in the lower bandgap dot, leaving a confined hole and a relatively delocalized electron. The second absorbed photon can lead, either directly or indirectly, to further excitation of the hole, enabling it to then cross the barrier layer. This, in turn, is followed by radiative recombination with the delocalized electron.
    Type: Grant
    Filed: April 22, 2014
    Date of Patent: February 21, 2017
    Assignee: YEDA RESEARCH AND DEVELOPMENT CO. LTD.
    Inventors: Dan Oron, Zvi Deutsch, Lior Neeman