Abstract: A busbar assembly of the present invention includes a plurality of busbars disposed in parallel in a common plane with a gap between adjacent busbars, and an insulative resin layer including a gap filling part and a first surface-side laminate part, the first surface-side laminate part having a plurality of first surface-side center openings that expose predetermined parts of first surfaces of the plurality of busbars respectively to form a plurality of exposure regions, the insulative resin layer being formed by an insulative resin material that is transparent in a half-cured state and nontransparent in a completely cured state.

Abstract: Manufacturing a low-K dielectric organic/inorganic aerogel composite material and its application are provided. The manufacturing method comprises: (1) mixing; (2) hydrolysis; (3) condensation; (4) aging; (5) drying; (6) impregnating polymer solution; (7) phase separation and drying; and (8) cross-linking and curing. The manufacturing method can produce a low-K dielectric organic/inorganic aerogel composite material having a high strength. The low-K dielectric aerogel is in a porous structure, and its porosity is higher than 70% and its density is from 0.12 g/cm3 to 0.45 g/cm3. The dielectric property of the low-K dielectric aerogel decreases along with an increase of its porosity, wherein a dielectric constant thereof is from 1.28 to 1.89, and a dielectric loss thereof is from 0.052 to 0.023. The low-k dielectric aerogel can be used for a dielectric layer in a high-frequency circuit, an insulation layer in a semiconductor device or a microwave circuit in a communication integrated circuit.

Abstract: Provided is a sulfide all-solid battery having an anode current collector of powerful adhesiveness which is difficult to be sulfurized. The sulfide all-solid-state battery including: a cathode layer; an anode layer; and a sulfide solid electrolyte layer disposed between the cathode layer and the anode layer, wherein the anode layer has an anode mixture layer, and an anode current collector on a face of the anode mixture layer, the face being on an opposite side of the sulfide solid electrolyte layer, the anode current collector is electrolytic iron foil that does not substantially contain other elements, and the anode current collector has surface roughness Ra of 0.2 ?m to 0.6 ?m, and surface roughness Rz of 2 ?m to 6 ?m.

Abstract: The present application relates to a method for manufacturing a solar cell. In the method, a wafer including a substrate and a doped conducting layer is provided. A doped conducting layer is disposed at least on the first surface and the portion of the first side surface, thereby covering the textured structure. A passivating contact layer is formed on the second surface of the substrate. A first passivation layer is formed on the doped conducting layer. The first passivation layer covers the first surface and at least the portion of the first side surface, thereby covering at least the doped conducting layer. A second passivation layer is formed on the passivating contact layer. The second passivation layer covers the second surface, thereby covering the passivating contact layer.

Abstract: A painting target surface of a resin bumper is painted by discharging a paint mist from a spray gun toward the painting target surface with a charged conductor arranged in contact with an opposite side to the painting target surface. The paint mist is uncharged or is charged with electric charges having an opposite polarity to that of the conductor and at a potential having a lower absolute value than that of the conductor.

Abstract: Integrated circuit devices and methods of forming the same are provided. A method according to the present disclosure includes providing a workpiece including a semiconductor substrate, a first ILD layer over the semiconductor substrate, and a first metal feature in the first ILD layer; depositing a second metal feature over the workpiece such that the second metal feature is electrically coupled to the first metal feature; patterning the second metal feature to form a first trench adjacent to the first metal feature; depositing a blocking layer over the workpiece, wherein the blocking layer selectively attaches to the first ILD layer; depositing a barrier layer over the workpiece, wherein the barrier layer selectively forms over the second metal feature relative to the first ILD layer; and depositing a second ILD layer over the workpiece.

Abstract: A method for manufacturing an integrated circuit includes patterning a plurality of photomask layers over a substrate, partially backfilling the patterned plurality of photomask layers with a first material using atomic layer deposition, completely backfilling the patterned plurality of photomask layers with a second material using atomic layer deposition, removing the plurality of photomask layers to form a masking structure comprising at least one of the first and second materials, and transferring a pattern formed by the masking structure to the substrate and removing the masking structure. The first material includes a silicon dioxide, silicon carbide, or carbon material, and the second material includes a metal oxide or metal nitride material.

Abstract: Amino-functionalized cyclic oligosiloxanes, which have at least three silicon and three oxygen atoms as well as at least one organoamino group and methods for making the oligosiloxanes are disclosed. Methods for depositing silicon and oxygen containing films using the organoamino-functionalized cyclic oligosiloxanes are also disclosed.

Abstract: A mesa (34) includes a resonator and a second conductivity type contact layer (24). Grooves (32) are provided on both sides of the mesa (34). The first conductivity type contact layer (12) and a side face of the mesa (34) including an end face of the resonator construct an L shape (50). The first conductivity type contact layer (12) constructs bottom surfaces of the L shape (50) and the grooves (32). A side face of the groove (32) includes a slope (38) near the bottom surface (46) and a side face (42) above. A side face of the L shape (50) includes a slope (40) near the bottom surface (48) and a side face (44) above. A first electrode (28) is connected to the first conductivity type contact layer (12) at the bottom surface (46) of the groove (32). A second electrode (30) is connected to the second conductivity type contact layer (24) above the mesa (34).

Abstract: Semiconductor devices and methods of forming the same are provided. A semiconductor device according to the present disclosure includes a first semiconductor channel member and a second semiconductor channel member over the first semiconductor channel member and a porous dielectric feature that includes silicon and nitrogen. In the semiconductor device, the porous dielectric feature is sandwiched between the first and second semiconductor channel members and a density of the porous dielectric feature is smaller than a density of silicon nitride.

Abstract: A method of selectively forming a film on a substrate includes: a preparation process of preparing a substrate having a surface to which a metal film and an insulating film are exposed; a first removal process of removing a natural oxide film on the metal film; a first film forming process of forming a self-assembled monolayer, which suppresses formation of a titanium nitride film, on the insulating film by providing the substrate with a compound for forming the self-assembled monolayer, the compound having a functional group containing fluorine and carbon; a second film forming process of forming a titanium nitride film on the metal film; an oxidation process of oxidizing the surface of the substrate; and a second removal process of removing a titanium oxide film, which is formed on the metal film and the self-assembled monolayer, by providing the surface of the substrate with the compound.

Abstract: A process for building a 3-Dimensional NOR memory array avoids the challenge of etching a conductor material that is aimed at providing local word lines at a fine pitch. The process defines the local word lines between isolation shafts that may be carried out at a lower aspect ratio than would be required for etching the conductor material.

Abstract: Various embodiments herein relate to methods, apparatus, and systems for etching a feature in a substrate. Typically the feature is etched in a dielectric-containing stack. The etching process involves cyclically etching the feature and depositing a protective film on sidewalls of the partially etched feature. These stages are repeated until the feature reaches its final depth. The protective film may have a particular composition, for example including at least one of a tungsten carbonitride, a tungsten sulfide, tin, a tin-containing compound, molybdenum, a molybdenum-containing compound, a ruthenium carbonitride, a ruthenium sulfide, an aluminum carbonitride, an aluminum sulfide, zirconium, and a zirconium-containing compound. A number of optional steps may be taken including, for example, doping the mask layer, pre-treating the substrate prior to deposition, removing the protective film from the sidewalls, and oxidizing any remaining protective film.

Abstract: Semiconductor structures and fabrication methods are provided. An exemplary fabrication method includes providing a to-be-etched layer; forming a first sacrificial film on the to-be-etched layer; and forming a plurality of discrete first sidewall spacers and sidewall trenches on the first sacrificial film. Each sidewall trench is located between two adjacent first sidewall spacers; the first sidewall trenches include a first sidewall trench and a second sidewall trench, and a width of the second sidewall trench is greater than that of the first sidewall trench. The method also includes forming a second sidewall spacer in the first sidewall trench to fill the first sidewall trench; and etching the first sacrificial film using the first sidewall spacers and the second sidewall spacer as an etching mask to form a plurality of discrete first sacrificial layers on the to-be-etched layer.

Abstract: Methods of forming silicon nitride. Silicon nitride is formed on a substrate by atomic layer deposition at a temperature of less than or equal to about 275° C. The as-formed silicon nitride is exposed to a plasma. The silicon nitride may be formed as a portion of silicon nitride and at least one other portion of silicon nitride. The portion of silicon nitride and the at least one other portion of silicon nitride may be exposed to a plasma treatment. Methods of forming a semiconductor structure are also disclosed, as are semiconductor structures and silicon precursors.

Abstract: A process for producing a monocrystalline layer of GaAs material comprises the transfer of a monocrystalline seed layer of SrTiO3 material to a carrier substrate of silicon material followed by epitaxial growth of a monocrystalline layer of GaAs material.

Abstract: A semiconductor device is provided. The semiconductor device includes an electric field (E-field) suppression layer formed over a termination region. The E-field suppression layer is patterned with openings over metal contact areas. The E-field suppression layer has a thickness such that an electric field strength above the E-field suppression layer is below a dielectric strength of an adjacent material when the semiconductor device is operating at or below a maximum voltage.

Abstract: The present application provides a semiconductor device with an air gate spacer for reducing parasitic capacitance and a method for manufacturing the semiconductor device. The semiconductor device includes a stacking structure, a first sidewall spacer and a second sidewall spacer. The stacking structure stands on a semiconductor substrate. The first and second sidewall spacers cover a sidewall of the stacking structure. An air gap is sealed between the first and second sidewall spacers. A top end of the air gap is substantially aligned with top ends of the first and second sidewall spacers. A top portion of the air gap is tapered toward a top end of the air gap.

Abstract: The disclosed technology generally relates to forming a thin film comprising titanium nitride (TiN), and more particularly to forming by a cyclical vapor deposition process the thin film comprising (TiN).

Abstract: A support for a semiconductor structure includes a charge-trapping layer on a base substrate. The charge-trapping layer consists of a polycrystalline main layer and, interposed in the main layer or between the main layer and the base substrate, at least one intermediate polycrystalline layer composed of a silicon and carbon alloy or carbon. The intermediate layer has a resistivity greater than 1000 ohm·cm.

Abstract: In a method for manufacturing a semiconductor device, a first interlayer dielectric layer is formed over a substrate. First recesses are formed in the first interlayer dielectric layer. First metal wirings are formed in the first recesses. A first etch-resistance layer is formed in a surface of the first interlayer dielectric layer between the first metal wirings but not on upper surfaces of the first metal wirings. A first insulating layer is formed on the first etch-resistance layer and the upper surfaces of the first metal wirings.

Abstract: Disclosed are a display panel and a display device. The display panel includes: a substrate and a pixel array, where the pixel array is located on a side of the substrate, and the pixel array includes at least one inorganic insulating layer, and an edge of the inorganic insulating layer are located in the non-display area; a first repair layer, where the first repair layer is located in the non-display area, the first repair layer is located on a side of the inorganic insulating layer facing away from the substrate, the first repair layer covers the edge of the inorganic insulating layer, the first repair layer is in contact with the substrate, and the first repair layer has a repair function; and a light source, where the light source is located in the non-display area and configured to provide light to the first repair layer to trigger the repair function.

Abstract: A method of processing a semiconductor wafer is provided. The method includes providing a semiconductor wafer having a front side and a back side, the semiconductor wafer provided with a circuit layer at the front side and a patterned surface at the back side, forming a sacrificial layer on the back side, mounting a tape on the sacrificial layer, the sacrificial layer isolating the patterned surface from the tape, wherein adhesion strength between the sacrificial layer and the patterned surface is larger than that between the sacrificial layer and the tape, dicing the semiconductor wafer at the back side through the tape, defining individual chips on the semiconductor wafer, and expanding the tape to separate the chips from each other.

Abstract: Methods for forming electrical contacts with CdTe layers, methods for forming photovoltaic devices, methods for passivating a CdTe surface, and photovoltaic devices are described.

Abstract: Structures with altered crystallinity and methods associated with forming such structures. A semiconductor layer has a first region containing polycrystalline semiconductor material, defects, and atoms of an inert gas species. Multiple fins are arranged over the first region of the semiconductor layer. The structure may be formed by implanting the semiconductor layer with inert gas ions to modify a crystal structure of the semiconductor layer in the first region and a second region between the first region and a top surface of the semiconductor layer. An annealing process is used to convert the first region of the semiconductor layer to a polycrystalline state and the second region of the semiconductor layer to a monocrystalline state. The fins are patterned from the second region of the semiconductor layer and another semiconductor layer epitaxially grown over the second region of the semiconductor layer.

Abstract: The invention relates to methods of processing a wafer, having on one side a device area with a plurality of devices. In particular, the invention relates to a method which comprises providing a protective film, and applying the protective film to the side of the wafer being opposite to the one side, so that at least a central area of a front surface of the protective film is in direct contact with the side of the wafer being opposite to the one side. The method further comprises applying an external stimulus to the protective film during and/or after applying the protective film to the side of the wafer being opposite to the one side, so that the protective film is attached to the side of the wafer being opposite to the one side, and processing the one side of the wafer and/or the side of the wafer being opposite to the one side.

Abstract: The present disclosure provides a method in accordance with some embodiments. The method includes forming a mandrel over a substrate, the mandrel having a first sidewall and a second sidewall opposing the first sidewall; forming a first fin on the first sidewall and a second fin on the second sidewall; depositing a dielectric material covering the first fin, the second fin, and the mandrel; partially removing the dielectric material, thereby exposing the second fin; etching the second fin without etching the first fin and the mandrel; removing the dielectric material; and removing the mandrel.

Abstract: [Problem] Provided is a method for producing a silica sol capable of providing consistent production of the silica sol having a uniform particle size of silica particles in any particle size of the silica particles. [Solution] A method for producing a silica sol is a method including a step of mixing liquid (A) containing an alkaline catalyst, water, and a first organic solvent with liquid (B) containing an alkoxysilane or its condensate and a second organic solvent, and liquid (C1) having a pH of 5.0 or higher and lower than 8.0 and containing water or liquid (C2) containing water and being free of an alkaline catalyst to make a reaction liquid.

Abstract: A method for fabricating a semiconductor device includes forming a first wiring layer, the first wiring layer including a first metal wiring and a first interlayer insulating film wrapping the first metal wiring on a substrate, forming a first via layer, the first via layer including a first via that is in electrical connection with the first metal wiring, and a second interlayer insulating film wrapping the first via on the first wiring layer, and forming a second wiring layer, the second wiring layer including a second metal wiring that is in electrical connection with the first via, and a third interlayer insulating film wrapping the second metal wiring on the first via layer, wherein the third interlayer insulating film contains deuterium and is formed through chemical vapor deposition using a first gas containing deuterium and a second gas containing hydrogen.

Abstract: There is provided a technique that includes: (a) forming a first film including a cyclic structure composed of silicon and carbon and also including nitrogen so as to fill a recess formed in a surface of a substrate by performing a cycle a predetermined number of times, the cycle including non-simultaneously performing: supplying a precursor including the cyclic structure and also including halogen to the substrate having the recess formed on its surface; and supplying a nitriding agent to the substrate; (b) converting the first film into a second film including the cyclic structure and also including oxygen by supplying a first oxidizing agent to the substrate; and (c) converting the second film into a third film including silicon and oxygen and not including carbon and nitrogen by supplying a second oxidizing agent to the substrate.

Abstract: The present disclosure, in some embodiments, relates to a method of forming an integrated circuit device. The method may be performed by forming a conductive line over a substrate and in contact with a liner. A dielectric barrier layer is formed on the conductive line. The dielectric barrier layer includes an interfacial layer contacting the conductive line, a middle layer contacting the interfacial layer, and an upper layer contacting the middle layer. The interfacial layer and the liner collectively completely surround the conductive line. An inter-level dielectric layer is formed along sidewalls of the upper layer.

Abstract: A semiconductor device includes a semiconductor substrate divided into a pad region and a cell region and having an active surface and an inactive surface opposite to the active surface, a plurality of metal lines on the active surface of the semiconductor substrate, passivation layers on the active surface of the semiconductor substrate, and a plurality of bumps in the cell region. The passivation layers include a first passivation layer covering the plurality of metal lines and having a non-planarized top surface along an arrangement profile of the plurality of metal lines, and a second passivation layer on the non-planarized top surface of the first passivation layer and having a planarized top surface on which the plurality of bumps are disposed.

Abstract: A multilayer composite structure and a method of preparing a multilayer composite structure are provided. The multilayer composite structure comprises a semiconductor handle substrate having a minimum bulk region resistivity of at least about 500 ohm-cm; a Group IVA nitride layer in contact with the semiconductor handle substrate, the Group IVA nitride layer selected from the group consisting of carbon nitride, silicon carbon nitride, and a combination thereof; a dielectric layer in contact with the Group IVA nitride layer; and a semiconductor device layer in contact with the dielectric layer.

Abstract: The present disclosure provides a preparation method of the electroconductive polyimide and a display panel. The preparation method may include: providing aminated carbon nanotubes; and mixing the aminated carbon nanotubes with diamine and dianhydride in a predetermined reaction condition to form a mixture, such that the aminated carbon nanotubes react with the diamine and the dianhydride to generate the electroconductive polyimide. According to the above method, the electroconductive polyimide can be prepared through the reaction between the aminated carbon nanotubes, the diamine, and the dianhydride.

Abstract: A semiconductor device disclosed includes a semiconductor substrate, an electrode layer arranged over the semiconductor substrate, and a conductive member provided in an opening and electrically connected to the electrode layer, and the opening penetrates the semiconductor substrate and reaches the electrode layer. The conductive member includes a metal portion and a barrier metal portion provided between a side surface of the opening and the metal portion, the barrier metal portion includes a first layer and a second layer provided between the first layer and the metal portion, and the second layer is denser than the first layer.

Abstract: To suppress a change in electrical characteristics and to improve reliability in a semiconductor device using a transistor including an oxide semiconductor. The semiconductor device includes a gate electrode over an insulating surface, an oxide semiconductor film overlapping with the gate electrode, a gate insulating film which is between the gate electrode and the oxide semiconductor film and is in contact with a surface of the oxide semiconductor film, a protective film in contact with an opposite surface of the surface of the oxide semiconductor film, and a pair of electrodes in contact with the oxide semiconductor film. In the gate insulating film or the protective film, the amount of gas having a mass-to-charge ratio m/z of 17 released by heat treatment is greater than the amount of nitrogen oxide released by heat treatment.

Abstract: A semiconductor device includes a substrate having a fin active region pattern having a protruding shape, a device isolation layer pattern covering a side surface of a lower portion of the fin active region pattern, a spacer pattern covering a side surface of a portion of the fin active region pattern that protrudes from a top surface of the device isolation layer pattern, and a source/drain region in contact with a top surface of the fin active region pattern and a top surface of the spacer pattern.

Abstract: Magnesium Zinc Oxide (MZO)—based high voltage thin film transistor (MZO-HVTFT) is built on a transparent substrate, such as glass. The device has the circular drain and ring-shaped source and gate to reduce non-uniformity of the electric field distribution. Controlled Mg doping in the channel and modulated Mg doping in a transition layer located at the channel-gate dielectric interface improve the device's operating stability and increase its blocking voltage capability over 600V. The MZO HVTFT can be used for fabricating the micro-inverter in photovoltaic system on glass (PV-SOG), and for self-powered smart glass.

Abstract: A device and method for providing the device are described. The device includes a substrate, a MnxN layer overlying the substrate, a multi-layered structure that is non-magnetic at room temperature and a first magnetic layer. The MnxN layer has 2?x?4.75. The multi-layered structure comprises alternating layers of Co and E, wherein E comprises at least one other element that includes Al. The composition of the multi-layered structure is represented by Co1-xEx, with x being in the range from 0.45 to 0.55. The first magnetic layer includes a Heusler compound. The first magnetic layer is in contact with the multi-layered structure and the first magnetic layer forms part of a magnetic tunnel junction.

Abstract: [Problem] Provided is a method for producing a silica sol capable of providing consistent production of the silica sol having a uniform particle size of silica particles in any particle size of the silica particles. [Solution] A method for producing a silica sol is a method including a step of mixing liquid (A) containing an alkaline catalyst, water, and a first organic solvent with liquid (B) containing an alkoxysilane or its condensate and a second organic solvent, and liquid (C1) having a pH of 5.0 or higher and lower than 8.0 and containing water or liquid (C2) containing water and being free of an alkaline catalyst to make a reaction liquid.

Abstract: A semiconductor structure and a method for fabricating the same. The semiconductor structure includes a gallium arsenide substrate, a thiourea-based passivation layer in contact with at least a top surface of the gallium arsenide substrate, and a capping layer in contact with the thiourea-based passivation layer. The method includes passivating a gallium arsenide substrate utilizing thiourea to form a passivation layer in contact with at least a top surface of the gallium arsenide substrate. The method further includes forming a capping layer in contact with at least a top surface of the passivation layer, and annealing the capping layer and the passivation layer.

Abstract: A method of processing semiconductor material includes applying an organosulfur solution to a top surface of a semiconductor material, the organosulfur solution having at least one organosulfur compound. The at least one organosulfur compound has at least one sulfur atom double bonded to a carbon atom and a pH of not less than 8. An organosulfur solution may be applied at temperatures above 25° C. to increase sulfur deposition rates and increase sulfur coverage on a surface of a semiconductor material.

Abstract: To suppress a change in electrical characteristics and to improve reliability in a semiconductor device using a transistor including an oxide semiconductor. The semiconductor device includes a gate electrode over an insulating surface, an oxide semiconductor film overlapping with the gate electrode, a gate insulating film which is between the gate electrode and the oxide semiconductor film and is in contact with a surface of the oxide semiconductor film, a protective film in contact with an opposite surface of the surface of the oxide semiconductor film, and a pair of electrodes in contact with the oxide semiconductor film. In the gate insulating film or the protective film, the amount of gas having a mass-to-charge ratio m/z of 17 released by heat treatment is greater than the amount of nitrogen oxide released by heat treatment.

Abstract: A porous polyimide shaped article has a thickness in a range from 550 ?m to 3,000 ?m and has a relative dielectric constant of 1.8 or less and a dielectric loss tangent of 0.01 or less at 1 MHz. The porous polyimide shaped article satisfies the following formula: 1.2?A?1.6 wherein A represents a square root of a ratio of a pore size D84 where a cumulative percentage by number of pores from smaller sizes is 84% to a pore size D16 where the cumulative percentage by number of the pores from smaller sizes is 16% ((D84/D16)1/2) in a pore size distribution measured by mercury intrusion porosimetry.

Abstract: The object of the present invention is to provide silica particles which are surface-treated with a silicon compound uniformly and have improved surface characteristics and affinity with a resin. The silica particles according the present invention are surface-treated with a specific silicon compound, wherein C/Si ratio from X-ray photoelectron spectroscopy (XPS) is not less than 0.05.

Abstract: A method includes forming a carbon-containing layer with a carbon atomic percentage greater than about 25 percent over a first hard mask layer, forming a capping layer over the carbon-containing layer, forming a first photo resist over the capping layer, and etching the capping layer and the carbon-containing layer using the first photo resist as a first etching mask. The first photo resist is then removed. A second photo resist is formed over the capping layer. The capping layer and the carbon-containing layer are etched using the second photo resist as a second etching mask. The second photo resist is removed. A third photo resist under the carbon-containing layer is etched using the carbon-containing layer as etching mask. A dielectric layer underlying the third photo resist is etched to form via openings using the third photo resist as etching mask. The via openings are filled with a conductive material.

Abstract: There are provided an oxide dielectric having excellent properties and a solid state electronic device (e.g., a capacitor, a semiconductor device, or a small electromechanical system) having such an oxide dielectric. An oxide layer 30 includes an oxide dielectric (possibly including inevitable impurities) including bismuth (Bi) and niobium (Nb) and having a first crystal phase of a pyrochlore-type crystal structure and a second crystal phase of a ?-BiNbO4-type crystal structure. The oxide layer 30 has a controlled content of the first crystal phase and a controlled content of the second crystal phase, in which the first crystal phase has a dielectric constant that decreases with increasing temperature of the oxide layer 30 in a temperature range of 25° C. or more and 120° C. or less, and the second crystal phase has a dielectric constant that increases with increasing temperature of the oxide layer 30 in the temperature range.

Abstract: A power semiconductor device includes a semiconductor substrate including at least one electrical structure. The at least one electrical structure has a blocking voltage of more than 20V. Further, the power semiconductor device includes an electrically insulating layer structure formed over at least a portion of a lateral surface of the semiconductor substrate. The electrically insulating layer structure embeds one or more local regions for storing charge carriers. Further, the one or more local regions includes in at least one direction a dimension of less than 200 nm.

Abstract: Provided is a display device that includes a display panel defined with an active area displaying an image and an inactive area outside the active area, the display panel including a substrate having a first surface and a second surface opposite the first surface; a plurality of pixels on the first surface of the substrate in the active area, each pixel including a pixel drive circuit; a transparent conductive layer on the second surface of the substrate covering the active area and a part of the inactive area; and a metal pattern on the second surface of the substrate in the inactive area, the metal pattern electrically connected to the transparent conductive layer, receiving an electrical signal and having a lower resistance than the transparent conductive layer, wherein the metal pattern serves as a conductive path to reduce a potential difference with respect to the electrical signal in an entire area of the transparent conductive layer compared to a display device without the metal pattern.

Abstract: Apparatus and methods of forming an apparatus can include one or more cell contacts in an integrated circuit in a variety of applications. In various embodiments, a resist underlayer can be formed on a dielectric spacer formed on a structure for a cell contact, where the structure can include a patterned area of pillars on a silicon-rich dielectric anti-reflective coating region disposed on a dielectric region. The resist underlayer, the dielectric spacer, the patterned area of pillars, the silicon-rich dielectric anti-reflective coating, and the dielectric region can be processed to form an array of columns in the dielectric region. Regions between the columns of the array of columns can be filled with conductive material, forming the cell contact. Additional apparatus, systems, and methods are disclosed.