Abstract: The invention is a method for constructing an integrated circuit structure and an apparatus produced by the method. The method generally comprises constructing an integrated circuit structure by disposing a layer of doped oxide, the dopant being iso-electronic to silicon, and then reflowing the layer of doped oxide. Thus, the apparatus of the invention is an integrated circuit structure comprising a reflowed layer of doped oxide wherein the dopant is iso-electronic to silicon. In one particular embodiment, the method generally comprises constructing an integrated circuit feature on a substrate; disposing a layer of doped oxide, the dopant being iso-electronic to silicon, over the integrated circuit feature and the substrate in a substantially conformal manner; reflowing the layer of doped oxide; and etching the insulating layer and the oxide.

Abstract: In accordance with the invention, a silicon gate field effect device is provided with improved control over the distribution of dopants by forming thin buried layer of oxide within the silicon gate. In essence, a silicon gate device is fabricated by the steps of forming a gate dielectric on a silicon substrate and forming a first layer of the silicon gate (amorphous or polycrystalline) on the dielectric. A thin layer of oxide is formed on the first gate layer, and a second silicon gate layer is formed on the oxide, producing a silicon gate containing a thin buried oxide layer. Dopants are then implanted through the second gate layer and the buried oxide, and the device is finished in a conventional manner. The buried oxide layer, acting as a sieve, maintains high dopant concentration near the interface between the gate and minimizes dopant outdiffusion through the gate.

Abstract: Low k dielectrics such as black diamond have a tendency to delaminate from the edges of a silicon wafer, causing multiple problems, including blinding of the alignment mark. This problem has been overcome by inserting a layer of silicon nitride between the low k layer and the substrate. A key requirement is that said layer of silicon nitride be under substantial compressive stress (at least 5×109 dynes/cm2). In the case of a layer of black diamond, on which material the invention is particularly focused, a nucleating layer is also inserted between the silicon nitride and the black diamond. A process for laying down the required layers is described together with an example of applying the invention to a dual damascene structure.

Abstract: A method and apparatus for endpointing a planarization process of a microelectronic substrate. In one embodiment, the microelectronic substrate can include a semiconductor base, a first material, such as an oxide, disposed on the base, a second material, such as a nitride, disposed on the first material to stiffen the first material, and an endpointing material, such as polysilicon, disposed on the second material. The endpointing material can have a hardness and/or a fracture resistance that is less than a hardness and/or a fracture resistance of the stiffening material and, in one embodiment, can have a coefficient of friction that is different than surrounding material of the microelectronic substrate so as to be detected when exposed to a planarizing medium.

Abstract: A method of fabricating the parts and assembling them into a complex structure, such as a silicon tower or boat for removably supporting a plurality of silicon wafers during thermal processing. A preferred embodiment of the tower includes four legs secured on their ends to two bases. A plurality of slots are cut in the legs allowing slidable insertion of the wafers and support for them. The legs preferably have a rounded wedge shape with a curved front surface of small radius cut with the slots and a back surface that is either flat or curved with a substantially larger radius. Preferably, the legs are machined from virgin polysilicon formed by chemical vapor deposition from silane. The bases may be either virgin poly or monocrystalline silicon and be either integral or composed of multiple parts. Virgin polysilicon is preferably annealed to above 1025° C. before machining. Silicon parts may be joined by applying a spin-on glass between the parts and annealing the assembly.

Abstract: The fixed charge in a borophosphosilicate glass insulating film deposited on a semiconductor device is reduced by reacting an organic precursor such as TEOS with O3. When done at temperatures higher than approximately 480 degrees C., the carbon level in the resulting film appears to be reduced, resulting in a higher threshold voltage for field transistor devices.

Abstract: Lateral bipolar transistor, in which a thin diffusion barrier (4) is applied to a base region (10) between an emitter region (9) and a collector region (11), and there is present, on said barrier, a base electrode (8) which is provided for low-resistance supply, is connected to a heavily doped base terminal region and consists of polysilicon, for example, into which dopant is diffused out from said base terminal region.

Abstract: An ultra-large scale integrated circuit is manufactured by using silicon-based, low dielectric constant materials which are spin-coated, dried, cured, and capped in-situ in chemical vapor deposition equipment. The low dielectric constant material is spun on, processed in chemical vapor deposition equipment, subject to chemical-mechanical polishing, and then processed by a conventional photolithographic process for depositing conductors. The material is then reprocessed for each successive layer of conductor separated by dielectric.

Abstract: A substrate, preferably silicon, or other suitable material has a layer of glass material disposed thereon. The glass material of the present disclosure has a substantially increased uniformity due to the reduction in bubbles as well as a relatively smooth top surface. By virtue of the reduction in the number and size of the bubbles in the glass the dielectric properties of the glass are more uniform. Additionally, the fact that the surface of the glass is much more smooth reduces the potential of prior structures to have an unacceptably thin glass layer due to the need to grind the surface smooth.

Abstract: A method for decreasing CHC degradation is provided. The method includes providing a semiconductor device (10) having at least one metal layer (28) completed. Then, a planarizing dielectric layer (30) is added to the semiconductor device (10). The semiconductor device (10) is heated in a hydrogen rich environment until hydrogen completely saturates the semiconductor device (10).

Abstract: The invention includes a semiconductor wafer assembly, comprising: a) a semiconductor wafer substrate; and b) alternating first and second layers over the semiconductor wafer substrate, the alternating layers comprising at least one first layer and at least one second layer, the first layer comprising a first material and the second layer comprising a second material, the second material comprising atoms selected from the group consisting of yttrium, lanthanides, actinides, calcium, magnesium and mixtures thereof.

Abstract: A semiconductor device that allows improvement in adhesion between insulation films having a 2-layered structure together with improvement of planarization and film characteristics, and a fabrication method thereof are obtained. In the fabrication method of the semiconductor device, an insulation film of a 2-layered structure having at least an upper layer and a lower layer is formed on a semiconductor substrate. Then, impurities are introduced into the upper insulation film under a condition where impurities arrive at least at the interface between the upper insulation film and the lower insulation film. By improving the adhesion between the upper and lower insulation films, the upper insulation film does not easily peel off.

Abstract: A method and apparatus for endpointing a planarization process of a microelectronic substrate. In one embodiment, the microelectronic substrate can include a semiconductor base, a first material, such as an oxide, disposed on the base, a second material, such as a nitride, disposed on the first material to stiffen the first material, and an endpointing material, such as polysilicon, disposed on the second material. The endpointing material can have a hardness and/or a fracture resistance that is less than a hardness and/or a fracture resistance of the stiffening material and, in one embodiment, can have a coefficient of friction that is different than surrounding material of the microelectronic substrate so as to be detected when exposed to a planarizing medium.

Abstract: A semiconductor device includes a F-doped interlayer insulation film and a high-refractive index insulation film having a refractive index higher than a refractive index of the F-doped interlayer insulation film, such that the high-refractive index insulation film is disposed at least one of a top side and a bottom side of the F-doped interlayer insulation film.

Abstract: A semiconductor device includes an interlayer insulating film disposed between upper and lower wiring layers, the interlayer insulating film having a two-layered structure including an upper insulating film and a lower insulating film, the upper insulating film is formed in an ozone (O3) concentration higher than that of the lower insulating film. The interlayer insulating film may be composed, for example, of O3 tetra etyl ortho silicate (TEOS) boron phospho silicate glass (BPSG). The semiconductor device makes it possible to have the interlayer insulating film sufficiently planarized by a reflow process, and to prevent precipitation of impurities at a surface of the interlayer insulating film. Alternatively, the interlayer insulating film may have a multi-layered structure including a three or more of insulating films, in which a top insulating film is formed in a higher ozone concentration than that of the other insulating films.

Abstract: A semiconductor structure having a first conductive trace fabricated adjacent to a second conductive trace over an insulating layer. A dielectric material is located over and between the first and second conductive traces. A borderless contact extends through the dielectric material to contact the first conductive trace. An air gap is formed in the dielectric material between the first and second conductive traces, thereby increasing the capacitance between the first and second traces. The air gap has a first portion with a first width adjacent to the borderless contact, and a second portion with a second width away from the borderless contact. The second width is greater than the first width, and the second portion of the air gap is substantially longer than the first portion of the air gap. The first portion of the air gap is offset toward the second trace.

Abstract: A polysilicon resistor structure for use within integrated circuits and a method by which the polysilicon resistor structure may be formed. A first insulating layer which is formed from a glasseous material is formed directly upon the surface of a semiconductor substrate. A polysilicon resistor is formed in contact with the first insulating layer. A second insulating layer is formed directly upon the first insulating layer and over the polysilicon resistor. The second insulating layer is formed from a silicon oxide material deposited through a Plasma Enhanced Chemical Vapor Deposition process employing silane as the silicon source material.

Abstract: Within a method for forming a halogen doped glass layer, such as a fluorosilicate glass (FSG) layer, there is first provided a substrate. There is then formed over the substrate a first halogen doped glass layer. There is then formed upon the first halogen doped glass layer a barrier layer. There is then formed upon the barrier layer a second halogen doped glass layer. Finally, there is then planarized the second halogen doped glass layer, while not penetrating the barrier layer, to form a planarized halogen doped glass layer.

Abstract: An interlevel dielectric and a method for making same wherein boron is introduced into the dielectric though an implantation process. During the implantation process, either the boron-10 or the boron-11 boron isotope may be selected and introduced into the dielectric. Boron is introduced to make the dielectric flow at lower temperatures. Selectively implanting boron-10 or boron-11 during implantation, as opposed to buying boron comprising a specific boron isotope from a supplier and introducing boron during CVD, lowers the production costs. Furthermore, introducing boron into the dielectric during the implantation process as opposed to during deposition of the dielectric during a CVD process, the dielectric layer is free of "boron" bumps. Boron-bearing dielectrics can be made to made to flow at lower temperatures than dielectrics which do not contain boron.

Abstract: The invention proposes methods for producing integrated circuits wherein the dielectric constant between closely spaced and adjacent metal lines is approaching 1. One method of the invention uses low-melting-point dielectric to form a barrier forming a void between conductive lines. Another method of the invention uses sidewall film to form a similar barrier.

Abstract: The formation of a graded passivation layer is disclosed. In one embodiment, a method includes four steps. In the first step, at least one transistor on a semiconductor substrate is provided. In the second step, at least one metallization layer is formed over the at least one transistor. In the third step, an oxide layer is deposited over the at least one metallization layer. Finally, in the fourth step, an ion implantation of a predetermined dopant is applied to create a graded passivation film over the at least one metallization layer.

Abstract: A method of processing a semiconductive material wafer includes, a) providing a semiconductive material wafer having integrated circuitry fabricated within discrete die areas on the wafer, the discrete die areas having bond pads formed therewithin; b) cutting at least partially into the semiconductive material wafer about the die areas to form a series of die cuts, the cuts having edges; c) depositing an insulative material over the wafer and to within the cuts to at least partially cover the cut edges and to at least partially fill the cuts with the insulative material; d) removing the insulative material from being received over the bond pads and leaving the insulative material within the die cuts; and e) after the removing, cutting into and through the insulative material within the die cuts and through the wafer. A semiconductor chip includes an outer surface having conductive bond pads proximately associated therewith. Side edges extend from the outer surface.

Abstract: A semiconductor structure having a first conductive trace fabricated adjacent to a second conductive trace over an insulating layer. A dielectric material is located over and between the first and second conductive traces. A borderless contact extends through the dielectric material to contact the first conductive trace. An air gap is formed in the dielectric material between the first and second conductive traces, thereby increasing the capacitance between the first and second traces. The air gap has a first portion with a first width adjacent to the borderless contact, and a second portion with a second width away from the borderless contact. The second width is greater than the first width, and the second portion of the air gap is substantially longer than the first portion of the air gap. The first portion of the air gap is offset toward the second trace.

Abstract: A method for planarizing integrated circuit topographies, wherein, after a first layer of spin-on glass is deposited, a layer of low-temperature oxide is deposited before a second layer of spin-on glass.

Abstract: A method for making a device and the device itself which utilizes a passivation layer displaying improved crack resistance is disclosed. This is accomplished through the incorporation of boron into a PSG passivation layer. The temperature of the passivation deposition may need to be kept to a temperature low enough so that the boron compound used for the boron source does not decompose prior to reacting with other reactacts.

Abstract: After wiring patterns are formed on an insulating film covering the surface of a substrate, an insulating film such as plasma CVD SiO.sub.2 is formed covering the wiring patterns. A hydrogen silsesquioxane resin film with a flat surface is formed by spin coating or the like on the insulating film. Thereafter, the resin film is changed into a pre-ceramic silicon oxide film by performing heat treatment in an inert gas atmosphere. On this pre-ceramic silicon oxide film, an insulating film such as plasma enhanced CVD SiO.sub.2 film is formed and another wiring layer is formed on the insulating film. This method of forming a multi-layer wiring structure allows an interlayer insulating film to be planarized, and improves a yield of wiring formation.

Abstract: A semiconductor device including an insulation film superior in both planarization and water resistance is obtained. In this semiconductor device, a first insulation film including impurities is formed on a conductive layer. A film is formed between the first insulation film and the conductive layer for substantially preventing impurities from entering the conductive layer. Water resistance of the first insulation film is improved since impurities are included in the first insulation film. By using an insulation film superior in planarization as the first insulation film, a first insulation film superior in both planarization and water resistance can be obtained. The film provided between the first insulation film and the conductive layer prevents the impurities of the first insulation film from entering the conductive layer. Therefore, reduction in the reliability of the conductive layer can be prevented.

Abstract: A low dielectric insulation layer for an integrated circuit structure material, and a method of making same, are disclosed. The low dielectric constant insulation layer comprises a porous insulation layer, preferably sandwiched between non-porous upper and lower insulation layers. The presence of some gases such as air or an inert gas, or a vacuum, in the porous insulation material reduces the overall dielectric constant of the insulation material, thereby effectively reducing the capacitance of the structure. The porous insulation layer is formed by a chemical vapor deposition of a mixture of the insulation material and a second extractable material; and then subsequently selectively removing the second extractable material, thereby leaving behind a porous matrix of the insulation material, comprising the low dielectric constant insulation layer.

Abstract: The invention proposes methods for producing integrated circuits wherein the dielectric constant between closely spaced and adjacent metal lines is approaching 1. One method of the invention uses low-melting-point dielectric to form a barrier form a void between conductive lines. Another method of the invention uses sidewall film to form a similar barrier.

Abstract: A semiconductor element-housing package which hermetically houses a semiconductor element for protection against moisture in the atmosphere by bonding an insulating substrate and a lid by means of a sealing material, with a moisture absorbent having surface pores 10-100 .ANG. in radius which is mixed in the insulating substrate and/or the sealing material formed of a resin.

Abstract: A MOS type transistor with a gate is formed on the surface of a semiconductor substrate, and thereafter an interlayer insulating film and a first level wiring layer on the insulating film are formed. The wiring layer is patterned to cover the gate electrode. A second level interlayer insulating film is formed covering the wiring layer 16, and a second level wiring layer is formed on the second level interlayer insulating film. The second level interlayer insulating film is a laminate of a silicon oxide film formed by plasma CVD using tetraethoxysilane, a spin-on-glass (SOG) film, and another similar silicon oxide film, sequentially formed in this order. An auxiliary electrode layer (blocking layer) of the first level wiring layer covering the gate electrode prevents moisture contents from being diffused from the second level interlayer insulating film toward the gate electrode.

Abstract: A process and resulting product is described for forming an oxide in a semiconductor substrate which comprises initially implanting the substrate with atoms of a noble gas, then oxidizing the implanted substrate at a reduced temperature, e.g., less than 900.degree. C., to form oxide in the implanted region of the substrate, and then etching the oxidized substrate to remove a portion of the oxide. The resulting oxidation produces a dual layer of oxide in the substrate. The upper layer is an extremely porous and frothy layer of oxide, while the lower layer is a more dense oxide. The upper porous layer of oxide can be selectively removed from the substrate by a mild etch, leaving the more dense oxide layer in the substrate. Further oxide can then be formed adjacent the dense layer of oxide in the substrate, either by oxide deposition over the dense oxide or by growing further oxide beneath the dense oxide layer.

Abstract: The present invention provides a structure and method of manufacturing an interlevel/intermetal dielectric layer for a semiconductor device. The method begins by forming a stepped pattern 16 on a semiconductor structure 12. A barrier layer 20 composed of silicon oxide is formed on the semiconductor substrate so as to cover the surface of the stepped pattern 16. A first insulating layer 22 composed of silicon oxide is then formed over the barrier layer 20. A high P (phosphorous) content silicon glass layer 24 preferably is formed over the first insulating layer 22. The high P content silicon glass layer 24 has a phosphorous concentration in a range of about 4 and 10 weight percent. Next, in an important step, a graded P content silicon glass layer 26 is formed over the high P content silicon glass layer 24. The graded P content silicon glass layer 26 has a phosphorous concentration in a range of about 0.1 and 4 weight percent.

Abstract: Disclosed is a process for depositing a conformal polymer coating on selected areas of a silicon substrate. The substrate is first exposed through a mask to a gaseous plasma so as to form a film of desired pattern, the plasma comprising a compound having strong electron donating characteristics. Then, the patterned film and the remaining substrate not covered by the film are exposed to the vapor of a monomer, which condenses and polymerizes on the exposed substrate surfaces, but not on the film. The film serves to inhibit substantial deposition of the coating, so as to provide a selective deposition, where the coating is formed only on those areas of the substrate where desired.

Abstract: A semiconductor device in which the elution quantity of boron and phosphorus from a BPSG film in a process of washing a wafer is controlled low so as to realize sufficient flattening and in which a reflow processing temperature is lowered by increasing concentrations of boron and phosphorus in the BPSG film. A first BPSG film in which the boron concentration is 3.5 wt % to 4.5 wt % and the phosphorus concentration is 5.5 wt % to 6.5 wt % is formed through a polysilicon wiring layer on a semiconductor substrate by a CVD method using an inorganic material source such as SiH.sub.4, B.sub.2 H.sub.6, PH.sub.3, O.sub.2 or an organic material source such as TEOS, TMOP, TMB, or O.sub.3. A gas flow rate is then changed so as to form a second BPSG film having a boron concentration of 2.0 wt % to 3.0 wt % and a phosphorus concentration of 5.5 wt % to 6.5 wt %.

Abstract: A process for producing a glass-coated article having a silicon substrate and the article produced thereby are provided. According to the process of the present invention, a layer of glass wetting agent material is formed on the substrate to improve wetting of a glass material to the article. A desired thickness of the glass material is applied to the layer of wetting agent material. The article is then fired and subjected to ambient conditions sufficient to melt the glass material and to form a substantially uniform layer of glass material that is substantially devoid of void pockets and deformities. Particular utility for the present invention is found in the areas of fabrication of electronic circuit boards and semiconductor devices, although other utilities are contemplated.

Abstract: A low dielectric insulation layer for an integrated circuit structure material, and a method of making same, are disclosed. The low dielectric constant insulation layer comprises a porous insulation layer, preferably sandwiched between non-porous upper and lower insulation layers. The presence of some gases such as air or an inert gas, or a vacuum, in the porous insulation material reduces the overall dielectric constant of the insulation material, thereby effectively reducing the capacitance of the structure. The porous insulation layer is formed by a chemical vapor deposition of a mixture of the insulation material and a second extractable material; and then subsequently selectively removing the second extractable material, thereby leaving behind a porous matrix of the insulation material, comprising the low dielectric constant insulation layer.

Abstract: A multilevel metallization is deposited on a microelectronic device base structure (40). The process includes depositing a glassy dielectric layer (48) of a thickness that is from about two to about three times as thick as the topography thickness (D) of the base structure (40). The glassy dielectric layer (48) is heated to a temperature above its glass transition temperature to flow the glassy dielectric layer (48). The glassy dielectric layer (48) is thinned to a preselected thickness, and a first patterned metallization layer (54) is deposited. The process further includes depositing an interlevel dielectric layer (58), dry etching the interlevel dielectric layer (58) to thin the interlevel dielectric layer (58) and, optionally, depositing additional interlevel dielectric layer (58') material to achieve a preselected thickness. A second patterned metallization layer (64) is deposited over the interlevel dielectric layer ( 58/58').

Abstract: An interconnect structure and method is described herein. First, interconnect lines 14a-d are formed on a semiconductor body 10. Then, a dielectric layer 20 is coated over the semiconductor body and the interconnect lines 14a-d to a thickness sufficient to more than fill the gaps between adjacent interconnect lines. The dielectric layer 20 is baked and then cured at a elevated temperature greater than the baking temperature. By using baking, then curing, the dielectric layer 20 inside the gaps has a lower density than that above interconnect lines and that in open fields. The removal of dielectric layer from the top of the interconnect lines by etchback is optional. Finally, a layer of silicon dioxide 12 is deposited over the interconnect lines 14a-d and the dielectric layer 20. In one embodiment, contact vias 11 are then etched through the silicon dioxide 12 and dielectric layer 20 to the interconnect lines 14a-c. Preferably, the dielectric material is spun on.

Abstract: A method of passivating a semiconductor device, comprises depositing a first dielectric passivation layer on the surface of the device, forming at least one planarization layer over the first passivation layer from an inorganic spin-on glass solution containing phosphorus and silicon organometallic molecules that are pre-reacted to form at least one Si.O.P bond between the phosphorus and silicon organometallic molecules, and subsequently depositing a second dielectric passivation layer on said at least one planarization layer(s). This results in improved step coverage of the underlying topography and permits much better protection against moisture related degradation than standard vapor phase deposited passivation layers even when the thickness of such layers is increased.

Abstract: A field oxide structure is formed within a cavity formed in a semiconductor substrate. The cavity has a U-shaped cross section. A layer of thermal oxide covers the walls and bottom of the cavity, and a region of reflowable glass or spin on glass fills the cavity. A layer of undoped oxide, having an upper surface coplanar with the substrate upper surface is formed over the cavity, so that the spin on or reflowable glass is completely surrounded by either thermal oxide or an undoped oxide layer.

Abstract: A semiconductor device and a method for forming the same. The semiconductor device comprises an insulating or semiconductor substrate, a thermally-contractive insulating film which is formed on said substrate and provided with grooves, and a semiconductor film which is formed on the thermally-contractive insulating film and divided in an islandish form through the grooves. The thermally-contractive insulating film is contracted in a heat process after the semiconductor film is formed.

Abstract: An electrically programmable read only memory device store data bits in the form of electric charges accumulated in floating gate electrodes of the memory cells, and a spin-on glass film is incorporated in an inter-level insulating film structure over the memory cells so as to create a smooth surface for wirings, wherein a silicon oxynitride film is inserted between the floating gate electrodes and the spin-on-glass film for preventing the accumulated electric charges from undesirable ion-containing water diffused from the spin-on-glass film.

Abstract: An integrated circuit has a silicon mesa disposed on a substrate and a field insulator structure in proximity to the mesa and having an opening over a top mesa surface. The opening, which exposes sidewalls in the structure, is positioned with respect to the mesa and has dimensions such that the structure is disposed to overlap a region of the mesa along an outer mesa periphery. A layer of polysilicon extends along a top surface of the structure and into the opening and adjacent to the mesa top surface. An insulator is disposed between the poly layer and the mesa top surface, the insulator having a layer of thermal gate oxide disposed adjacent to the poly layer and having a layer of pyrogenic oxide disposed between the thermal gate oxide layer and the mesa top surface.

Abstract: A semiconductor memory device is fabricated on a semiconductor substrate and comprises a memory cell array having a plurality of memory cells and located in a predetermined cell area of the semiconductor substrate, a rampart structure formed outside the memory cell array and having an outer wall gently sloping down, an upper insulating layer convering the memory cells and the rampart structure, and at least one wiring layer formed on the upper insulating layer and extending over at least one of the memory cells and the rampart structure, whereby the wiring layer is prevented from non-conformal step coverage and any disconnection.