Abstract: A semiconductor device and methods of forming a semiconductor device are disclosed. In the methods, a layer, such as an insulating interlayer, is formed on a substrate. A first trench is formed in the layer, and a mask layer is formed in the first trench. The mask layer has a first thickness from a bottom surface of the first trench to the top of the mask layer. The mask layer is patterned to form a mask that at least partially exposes a sidewall of the first trench. A portion of the mask adjacent to the exposed sidewall of the first trench has a second thickness smaller than the first thickness. The layer is etched to form a second trench using the mask as an etching mask. The second trench is in fluid communication with the first trench. A conductive pattern is formed in the first trench and the second trench.

Abstract: An integrated circuit includes a substrate and passivation layers. The passivation layers include a bottom dielectric layer formed over the substrate for passivation, a doped dielectric layer formed over the bottom dielectric layer for passivation, and a top dielectric layer formed over the doped dielectric layer for passivation.

Abstract: A nonvolatile semiconductor memory device includes: a first semiconductor region having first conductivity; a channel formation region in which a channel inversion layer having second conductivity is formed; a second semiconductor region having the second conductivity; a third semiconductor region having the second conductivity; a laminated insulating film formed on the channel formation region; and a control electrode formed on the laminated insulating film. The laminated insulating film includes a first insulating film, a charge storage film, and a second insulating film in order from the channel formation region side. The control electrode extends to above one of the second semiconductor region and the third semiconductor region. The charge storage film present between an extended portion of the control electrode and the second semiconductor region or the third semiconductor region is removed and a portion where the charge storage film is removed is filled with a third insulating film.

Abstract: A semiconductor memory device has a substrate having a semiconductor layer, an n-type semiconductor region formed beneath a main surface of the semiconductor layer, a plurality of cell gates being aligned at a space from each other and including a gate insulating film formed on the main surface of the semiconductor layer, a charge storage layer formed on the gate insulating film, a charge block layer formed on the charge storage layer and a control gate electrode formed on the charge block layer, an insulating film between cells formed on the main surface of the semiconductor layer between the cell gates, and a carbon accumulation region formed in the insulating film between the cells and has a maximum concentration of a carbon element in a region within 2 nm from an interface between the semiconductor layer and the insulating film between the cells.

Abstract: A manufacturing method of a semiconductor device includes a first electrode formation step of forming a control gate electrode above a surface of a semiconductor substrate with a control gate insulating film interposed between the control gate electrode and the semiconductor substrate, a step of forming a storage node insulating film on the surface of the semiconductor substrate, and a second electrode formation step of forming a memory gate electrode on a surface of the storage node insulating film. The second electrode formation step includes a step of forming a memory gate electrode layer on the surface of the storage node insulating film, a step of forming an auxiliary film, having an etching rate slower than that of the memory gate electrode layer, on a surface of the memory gate electrode layer, and a step of performing anisotropic etching on the memory gate electrode layer and the auxiliary film.

Abstract: A fast, reliable, highly integrated memory device formed of a carbon nanotube memory device and a method for forming the same, in which the carbon nanotube memory device includes a substrate, a source electrode, a drain electrode, a carbon nanotube having high electrical and thermal conductivity, a memory cell having excellent charge storage capability, and a gate electrode. The source electrode and drain electrode are arranged with a predetermined interval between them on the substrate and are subjected to a voltage. The carbon nanotube connects the source electrode to the drain electrode and serves as a channel for charge movement. The memory cell is located over the carbon nanotube and stores charges from the carbon nanotube. The gate electrode is formed in contact with the upper surface of the memory cell and controls the amount of charge flowing from the carbon nanotube into the memory cell.

Abstract: Methods for protecting semiconductor devices from plasma charging damage are disclosed. An example disclosed method includes depositing an etching stop layer on a substrate with at least one predetermined structure; depositing a premetallic dielectric layer and a charge preservation layer on the entire surface of the etching stop layer; depositing an insulating layer on the surface of the resulting structure; and forming an metallic interconnect on the insulating layer.

Abstract: The inventors have conducted vigorous studies, and discovered as a result that it is possible to form a silver layer having a high reflectance of about 90 to 99% in a visible light are a by setting a grain size of an outermost surface of a silver plated layer within a range of 0.5 ?m or more to 30 ?m or less.

Abstract: Rare earth metal containing compounds of the formula Sr2LuSbO6 and Sr2LaSbO6 have been prepared as high critical temperature thin film superconductor structures, and can be used in other ferroelectrics, pyroelectrics, piezoelectrics, and hybrid device structures.

Abstract: A method of manufacturing a flash memory device wherein a stacked structure of an oxide and nitride or the reverse is applied to insulation spacers provided on sidewalls of gates for forming source/drain regions. After completing the source/drain regions, spacers are formed on sidewalls of the gates by using an oxide film as a contacting buffer, thus minimizing the interference between gates and reducing the stress to cells, overcoming the disturbance of threshold voltage.

Abstract: A three-dimensionally formed circuit sheet comprises a resin film and a circuit pattern formed of an electrically conductive paste on the resin film. The electrically conductive paste contains, as a binder, a resin that is three-dimensionally formable. The resin film and the circuit pattern are formed in a three-dimensional shape. A method for manufacturing the three-dimensionally formed circuit sheet is also provided. The method comprises forming a circuit pattern on a resin film using an electrically conductive paste by means of printing, wherein the electrically conductive paste contains a resin that is three-dimensionally formable, and press molding the resin film including the circuit pattern into a three-dimensional shape. Additionally, a three-dimensionally formed circuit component comprising a three-dimensionally formed circuit sheet and a base member and a method for manufacturing the same are disclosed.

Abstract: There are included a semiconductor substrate provided with a desirable element region, an electrode pad formed to come in contact with a surface of the semiconductor substrate or a wiring layer provided on the surface of the semiconductor substrate, a bonding pad formed on a surface of the electrode pad through an intermediate layer, and a resin insulating film for covering a peripheral edge of the bonding pad such that an interface of the bonding pad and the intermediate layer is not exposed to a side wall.

Abstract: A memory cell structure and control of the memory operation are simplified, and the cost of production is decreased, by way of a semiconductor nonvolatile memory having a transistor including a gate electrode provided on a p-type semiconductor substrate via a gate insulating film, and a source region and a drain region, which are a pair of n-type impurity diffusion regions in the surface layer region of the semiconductor substrate at positions sandwiching the gate electrodes therebetween. A first resistance-varying portion and a second resistance-varying portion are sandwiched by the source region, drain region and channel-forming region. The n-type impurity concentration in the resistance-varying portions is lower than in the source and drain regions.

Abstract: An asymmetric-area memory cell, and a fabrication method for forming an asymmetric-area memory cell, are provided. The method comprises: forming a bottom electrode having an area; forming a CMR memory film overlying the bottom electrode, having an asymmetric area; and, forming a top electrode having an area, less than the bottom electrode area, overlying the CMR film. In one aspect, the CMR film has a first area adjacent the top electrode and a second area, greater than the first area, adjacent the bottom electrode. Typically, the CMR film first area is approximately equal to the top electrode area, although the CMR film second area may be less than the bottom electrode area.

Abstract: A method of improving flash memory performance. The method includes: providing a substrate having a gate structure thereon, the gate structure having a gate dielectric layer, a first polysilicon layer, an interploy dielectric layer, and a second polysilicon layer; then, depositing an gate insulating layer to enclose the gate structure, for forming side wall spacers; next, performing a first anneal on the substrate and the enclosed gate structure; then, performing a cell reoxidation on the substrate and the enclosed gate structure by dilute oxidation process using mixed gas comprising oxygen O2 and nitrogen N2. The invention reduces encroachment issues in the interpoly dielectric layer and the tunnel oxide and improves gate coupling ratio (GCR).

Abstract: A method and device for reducing interface area of a memory device. A poly-2 layer is formed above a substrate at an interface between a memory array and a periphery of the memory device. The poly-2 layer is etched proximate to the memory array. The poly-2 layer is etched proximate to the periphery such that a portion of the poly-2 layer remains at the interface.

Abstract: A memory device and fabricating method thereof. In the memory device of the present invention, a substrate has a plurality of deep trenches, wherein the deep trenches formed in the adjacent rows are staggered. A deep trench capacitor and a control gate are disposed in each deep trench successively. Word lines are disposed on the control gates respectively, and each word line is electrically coupled to the control gate thereunder. Diffusion regions are disposed in the substrate and surrounding the deep trenches respectively to serve as sources of vertical transistors. Each diffusion region is electrically connected to the surrounding deep trench capacitor. Active areas are disposed on the rows of the control gates respectively along a second direction. The regions where each active area overlaps the control gates have at least one indentation.

Abstract: A complementary field effect transistor comprises: a semiconductor substrate; an n-type field effect transistor provided on the semiconductor substrate; and a p-type field effect transistor provided on the semiconductor substrate. The n-type field effect transistor has: a first gate insulating film containing an oxide including an element selected from the group consisting of group IV metals and Lanthanoid metals, and further containing a compound of the element and a group III element; a first gate electrode provided on the first gate insulating film; and n-type source and drain regions formed on both sides of the first gate electrode.

Abstract: A semiconductor device includes a substrate that further includes source, drain and channel regions. The device may further include a bottom oxide layer formed upon the substrate, a charge storage layer formed upon the bottom oxide layer, and a steam oxide layer thermally grown upon the charge storage layer. The device may also include an alumina oxide layer formed upon the steam oxide layer and a gate electrode formed upon the alumina oxide layer.

Abstract: Dielectric materials including elements of Si, C, O and H having specific values of mechanical properties (tensile stress, elastic modulus, hardness cohesive strength, crack velocity in water) that result in a stable ultra low k film which is not degraded by water vapor or integration processing are provided. The dielectric materials have a dielectric constant of about 2.8 or less, a tensile stress of less than 45 MPa, an elastic modulus from about 2 to about 15 GPa, and a hardness from about 0.2 to about 2 GPa. Electronic structures including the dielectric materials of the present invention as well as various methods of fabricating the dielectric materials are also provided.

Abstract: A charge trapping semiconductor device is particularly suited as a replacement for conventional pull-up and load elements such as NDR diodes, passive resistors, and conventional FETs. The device includes a charge trapping layer formed at or extremely near to an interface between a substrate (which can be silicon or SOI) and a gate insulation layer. The charge trapping device can be shut off during static operations to further reduce power dissipation.

Abstract: The present invention is a high-frequency current essentially of M—X—Y, where M is Fe, Co, and/or Ni, X is an element other than M or Y, and Y is F, N, and/or O. The maximum value ??max of the loss factor ?? of this material exists at 100 MHz to 10 GHz. A relative bandwidth bwr is not greater than 200% where the relative bandwidth bwr is obtained between two frequencies at which the value of ?? is 50% of ??max and normalizing the frequency bandwidth at the center frequency.

Abstract: A process for providing regions of substantially lower fluorine content in a fluorine-containing dielectric comprises exposing the fluorine-containing dielectric to a reactive species to form volatile byproducts.

Abstract: A passivation method includes disassociating ammonia so as to expose at least interfaces between silicon-containing and passivation structures to at least hydrogen species derived from the ammonia and forming an encapsulant layer that is positioned so as to substantially contain the hydrogen species in the presence of the interfaces. The hydrogen passivation reduces a concentration of dangling silicon bonds at the interfaces by as much as about two orders of magnitude or greater. The encapsulant layer, which may include silicon nitride, prevents hydrogen species from escaping therethrough as high temperature processes are subsequently conducted. Once high temperature processes have been completed, portions of the encapsulant layer may be removed, as needed, to provide access to features of the semiconductor device structure that underlie the encapsulant layer. Semiconductor device structures that have been passivated in such a manner are also disclosed.

Abstract: A composite containing nano magnetic particles is provided. The composite includes nano magnetic particles in a dielectric matrix. The matrix is made of an inorganic material such as silica, alumina, or hydrosilsesquioxane, or an organic material such as polyimide, polymethyl methacrylate, or methyl silsesquioxane. The nano magnetic particles consist of Fe2O3, chromium oxide, europium oxide, NiZn-ferrite, MnZn-ferrite, yttrium-iron garnet, or indium In.

Abstract: A method of forming a layer of silicon carbide wherein silicon clusters are dissociated in a gas phase. Silicon clusters may be dissociated by a silicon-etching gas such as a group VII-containing component. A semiconductor device is also disclosed having a layer formed by the methods of the invention.

Abstract: In integrated circuit that yields the advantages of contemporary processing technologies and yet is irreparably damaged by ionizing radiation. An integrated circuit is designed and fabricated with contemporary processing technologies in well-known fashion, except that certain devices, called “safeguard” devices, are added to the integrated circuit. The safeguard devices are fabricated so that they, and not the other devices on the integrated circuit, are susceptible to ionizing radiation. Furthermore, the safeguard devices are coupled to the utile devices on the integrated circuit in such a manner than when the integrated circuit is bombarded with ionizing radiation the safeguard devices short and destroy the functionality of the utile devices, and, therefore, the functionality of the integrated circuit.

Abstract: A material layer which contains nitrogen atoms is formed on a first wiring or at a side surface of a first wiring. When etching for forming a via hole is carried out, nitrogen atoms contained in the material layer bind with CF molecules, CF2 molecules, CF3 molecules and the like contained in an etching gas, and compounds thus formed adhere to a surface of a silicon dioxide layer at side walls and a bottom portion of a via hole. As a result, once the material layer is exposed during etching for forming a via hole, thereafter, the etching rate decreases. Accordingly, even if there is misalignment of a via hole pattern with respect to a first wiring pattern when the via hole pattern is formed by lithography, etching of the silicon dioxide layer does not proceed to an underlying silicon substrate. Thus, short circuits are not formed between the first wiring and the silicon substrate via a second wiring layer which is deposited later.

Abstract: A method is provided for depositing a barrier layer on a substrate using a gaseous mixture that includes a hydrocarbon-containing gas and a silicon-containing gas. The gaseous mixture is provided to a process chamber and is used to form a plasma for depositing the barrier layer. The barrier layer is deposited with a thickness less than 500 Å. Suitable hydrocarbon-containing gases include alkanes and suitable silicon-containing gases include silanes.

Abstract: A semiconductor component with passivation includes at least two double passivating layers, of which an uppermost is applied to a planar surface of a layer located therebelow. The double passivating layers include two layers of different dielectric materials, for example silicon oxide and silicon nitride. The respective thicknesses of the individual passivating layers can be adapted to dimensions of the structuring of the layer to which the passivation is applied. This produces a reliable passivation which is particularly suitable for capacitively measuring fingerprint sensors.

Abstract: The present invention is a dielectric film and its method of fabrication. The dielectric film of the present invention includes silicon oxygen fluorine and nitrogen wherein the interlayer dielectric comprises between 0.01-0.1 atomic percent nitrogen.

Abstract: Substrate bombardment during HDP deposition of carbon-doped silicon oxide film results in filling the gaps between metal lines with carbon-doped low k dielectric material. This leads to the placement of low k dielectric between the narrow metal lines while the films over the metal lines have higher dielectric constant due to removal of carbon from these films during ion bombardment. Films over the metal lines have properties similar to silicon dioxide and are ready for sequential integration processes.

Abstract: A charge trapping structure for use with an n-channel metal-insulator-semiconductor field-effect transistor (MISFET) is disclosed. A dielectric layer is formed close to a channel region of the MISFET, and includes a number of trapping sites which are arranged and have a concentration sufficient to temporarily store energetic electrons induced by an electric field to move from the channel into the trapping sites. The trapped electrons set up a counter field that depletes the channel of carriers, and as a bias voltage across the channel increases, the device exhibits negative differential resistance (NDR). The charge trapping structure, as well as the rest of the device, are formed using conventional CMOS processing techniques.

Abstract: A method of fabricating an integrated circuit having reduced threshold voltage shift is provided. A nonconducting region is formed on the semiconductor substrate and active regions are formed on the semiconductor substrate. The active regions are separated by the nonconducting region. A barrier layer and a dielectric layer are deposited over the nonconducting region and over the active regions. Heat is applied to the integrated circuit causing the barrier layer to anneal.

Abstract: A passivation method includes disassociating ammonia so as to expose at least interfaces between silicon-containing and passivation structures to at least hydrogen species derived from the ammonia and forming an encapsulant layer that is positioned so as to substantially contain the hydrogen species in the presence of the interfaces. The hydrogen passivation reduces a concentration of dangling silicon bonds at the interfaces by as much as about two orders of magnitude or greater. The encapsulant layer, which may include silicon nitride, prevents hydrogen species from escaping therethrough as high temperature processes are subsequently conducted. Once high temperature processes have been completed, portions of the encapsulant layer may be removed, as needed, to provide access to features of the semiconductor device structure that underlie the encapsulant layer. Semiconductor device structures that have been passivated in such a manner are also disclosed.

Abstract: A low dielectric constant material having a first fluorine concentration in a near-surface portion and a second fluorine concentration in an interior portion provides an insulator suitable for use in integrated circuits. In a further aspect of the present invention, fluorine is depleted from a near-surface portion of a fluorine containing dielectric material by a reducing plasma. Fluorine in fluorinated low-k dielectric materials, such as SiOF, amorphous fluorinated carbon (a-F:C) and parylene-AF4, can react with surrounding materials such as metals and Si3N4, causing blisters and delamination. Treatment of these fluorinated low-k dielectric materials in a reducing plasma, which may be produced from precursor gases such as H2 or NH3, depletes the surface region of fluorine and hence reduces reaction with surrounding materials and F outgassing. By selecting an appropriate point in the integration flow, specific interfaces which are most susceptible to F-attack can be targeted for depletion.

Abstract: The reliability, electromigration resistance, adhesion, and electrical contact resistance of planarized, in-laid metallization patterns, e.g., of copper, are enhanced by a process comprising selectively depositing on the planarized, upper surfaces of the metallization features at least one thin layer comprising at least one passivant element for the metal of the features, reacting the at least one passivant element to chemically reduce any deleterious oxide layer present at the upper surfaces of the metallization features, and diffusing the at least one passivant element for a distance below the upper surface to form a passivated top interface. The passivated top interfaces advantageously exhibit reduced electromigration and improved adhesion to overlying metallization with lower ohmic contact resistance. Planarization, as by CMP, may be performed subsequent to reaction/diffusion to remove any elevated, reacted and/or unreacted portions of the at least one thin layer.

Abstract: A composite containing nano magnetic particles is provided. The composite includes nano magnetic particles in a dielectric matrix. The matrix is made of an inorganic material such as silica, alumina or hydrosilsesquioxane, or an organic material such as polyimide, polymethyl methacrylate (PMMA) or methyl silsesquioxane. The nano magnetic particles consist of (y-Fe2O3), chromium oxide (CrO2), europium oxide (EuO), NiZn-ferrite, MnZn-ferrite, Yittrium-iron garnet or indium (In).

Abstract: The invention includes a semiconductor wafer assembly, comprising: a) a semiconductor wafer substrate; and b) alternating first and second layers over the semiconductor wafer substrate, the alternating layers comprising at least one first layer and at least one second layer, the first layer comprising a first material and the second layer comprising a second material, the second material comprising atoms selected from the group consisting of yttrium, lanthanides, actinides, calcium, magnesium and mixtures thereof.

Abstract: Within a method for forming a halogen doped glass layer, such as a fluorosilicate glass (FSG) layer, there is first provided a substrate. There is then formed over the substrate a first halogen doped glass layer. There is then formed upon the first halogen doped glass layer a barrier layer. There is then formed upon the barrier layer a second halogen doped glass layer. Finally, there is then planarized the second halogen doped glass layer, while not penetrating the barrier layer, to form a planarized halogen doped glass layer.

Abstract: Compounds of the general formula A.sub.4 MeSb.sub.3 O.sub.12 wherein A is either barium (Ba) or strontium (Sr) and Me is an alkali metal ion selected from the group consisting of lithium (Li), sodium (Na) and potassium (K) have been prepared and included in high critical temperature thin film superconductors, ferroelectrics, pyroelectrics, piezoelectrics, and hybrid device structures.

Abstract: Fluorine bearing spacers on the sidewalls of gate electrodes of a semiconductor device are provided to suppress hot carrier injection in the semiconductor device. In accordance with one embodiment of the invention, a semiconductor device is formed by forming at least one gate electrode on a surface of a substrate and forming fluorine bearing spacers on the sidewalls of the gate electrode. The fluorine bearing spacers may, for example, be formed of an NF.sub.3 -doped glass material.

Abstract: A structure of a memory cell in a memory device is taking an interface between a silicon nitride layer and a oxide layer. The memory cell includes: a polysilicon layer on a substrate, a silicon nitride layer on the polysilicon layer, an oxide layer on the silicon nitride layer, and a conductor layer on the oxide layer. The order of forming the silicon nitride layer and the oxide layer can be reversed either for another alternative structure of the memory cell.

Abstract: An insulating film having a low dielectric constant lower than that of silicon oxide is arranged between a silicon support layer and a silicon active layer. A channel region, source/drain regions, and a device isolation region are formed in the active layer. A gate electrode is arranged on the channel region through a gate insulating film. The active layer is covered with a TEOS film in which contact holes are formed. The contact holes are filled with wiring layers connected to the source/drain regions and the gate electrode.

Abstract: The present invention provides an insulating film formed on a surface of a substrate and made of a material containing oxygen, wherein a charge correction is carried out at a 1s peak position of a carbon adsorbed on a surface of the insulating film, and relative amounts between first to fourth peaks obtained when an oxygen 1s peak of the insulating film is decomposed by a same half width of 1.208 eV into a first peak at the oxygen 1s peak site obtained from an .alpha.-quartz crystal charge corrected similarly, and second to fourth peaks at positions of +0.87 eV, -0.35 eV and -0.83 eV, respectively from the oxygen 1s peak position, have relationship of that the third peak is higher than the second and fourth peaks, and the first peak is higher than the third peak, when a portion about 1 nm thick from the surface of the substrate of the insulating film is analyzed by a photoelectronic spectral method for an photoelectron extracting angle of 15.degree. or less.

Abstract: A semiconductor device which contains an electrode or an interconnection subjected to a high voltage prevents current leakage due to polarization of a mold resin. In this semiconductor device, a glass coat film 13a covering a semiconductor element has an electrical conductivity in a range defined by the following formula (1) under the conditions of temperature between 17.degree. C. and 145.degree. C.:conductivity.gtoreq.1.times.10.sup.-10 /E (1)(E: an electric field intensity ?V/cm!, E.gtoreq.2.times.10.sup.4 ?V/cm!)Owing to employment of the electrically conductive glass coat film, an electron current flowing through the conductive glass coat film suppresses an electric field caused by polarization of a mold resin.

Abstract: An electromagnetic interference suppressing body is provided for suppressing electromagnetic interference by undesirable electromagnetic waves. The body can have a conductive support element and a non-conductive soft magnetic layer provided on at least one surface. The electromagnetic interference suppressing body may be used in circuit board electronic equipment and in a hybrid integrated circuit element having an active element and a passive element mounted on a circuit board.

Abstract: A semiconductor component with at least one lateral semiconductor structure with a high breakdown voltage including a substrate, a dielectric layer adjoining the substrate, a low-doped semiconductor zone disposed on the dielectric layer and heavily doped semiconductor zones of the semiconductor component which project into the low-doped semiconductor zone from the direction of the outer surface of the semiconductor component. Fixed charges, which reduce the electrical field strength in the blocking component of the lateral structure, are embedded inside the dielectric layer adjoining the substrate at least opposite that area of the low-doped semiconductor zone which, in the blocking state of the semiconductor component, has a high voltage in respect to the substrate.

Abstract: A structure for a semiconductor device includes a plurality of memory cell areas, a multilayer interconnection structure including an interfacial insulating film and connecting the plurality of memory cell areas, the multilayer interconnection structure being insulated and planarized by the interfacial insulating film, and peripheral circuits adjacent to the plurality of memory cell areas, the peripheral circuits intersecting at a portion, wherein the multilayer interconnection structure includes an inflow-preventing layer for preventing an inflow of the interfacial insulating film at the portion where the peripheral circuits intersect.

Abstract: A semiconductor device which contains an electrode or an interconnection subjected to a high voltage prevents current leakage due to polarization of a mold resin. In this semiconductor device, a glass coat film 13a covering a semiconductor element has an electrical conductivity in a range defined by the following formula (1) under the conditions of temperature between 17.degree. C. and 145.degree. C.:conductivity.gtoreq.1.times.10.sup.-10 /E . . . (1)(E: an electric field intensity ?V/cm!, E.gtoreq.2.times.10.sup.4 ?V/cm!)Owing to employment of the electrically conductive glass coat film, an electron current flowing through the conductive glass coat film suppresses an electric field caused by polarization of a mold resin.