Abstract: A non-volatile memory cell is disclosed. In one example, the non-volatile memory cell includes: a substrate; a first oxide layer over the substrate; a floating gate over the first oxide layer; a second oxide layer over the floating gate; and a control gate at least partially over the second oxide layer. At least one of the first oxide layer and the second oxide layer comprises fluorine.

Abstract: An epitaxial base is provided. The epitaxial base includes a substrate and a carbon nanotube layer. The substrate has an epitaxial growth surface and defines a plurality of grooves and bulges on the epitaxial growth surface. The carbon nanotube layer covers the epitaxial growth surface, wherein a first part of the carbon nanotube layer attached on top surface of the bulges, and a second part of the carbon nanotube layer attached on bottom surface and side surface of the grooves.

Abstract: A method and device for transferring a chip (18) situated on a transfer substrate (26) to a contact substrate (50), and for contacting the chip with the contact substrate, in which the chip, the back side (19) of which is attached adhesively to a support surface of the transfer substrate facing the contact substrate, is charged with laser energy from behind through the transfer substrate, and the chip contacts (59, 60) thereof that are arranged opposite a contact surface (58) of the contact substrate are brought into contact with substrate contacts (56, 57) arranged on the contact surface by means of a pressing device (45, 46) from behind through the transfer substrate, and a thermal bond is created between the chip contacts and the substrate contacts.

Abstract: An integrated circuit includes a substrate and passivation layers. The passivation layers include a bottom dielectric layer formed over the substrate for passivation, a doped dielectric layer formed over the bottom dielectric layer for passivation, and a top dielectric layer formed over the doped dielectric layer for passivation.

Abstract: A semiconductor chip has devices formed on a first principal plane of a semiconductor substrate, wherein a second principal plane of the semiconductor substrate is planarized, and an organic film having plus charges on an outer side is provided on the second principal plane.

Abstract: This invention concerns an electronic device for the control and readout of the electron or hole spin of a single dopant in silicon. The device comprises a silicon substrate in which there are one or more ohmic contact regions. An insulating region on top of the substrate. First and second barrier gates spaced apart to isolate a small region of charges to form an island of a Single Electron Transistor (SET). A third gate over-lying both the first and second barrier gates, but insulated from them, the third gate being able to generate a gate-induced charge layer (GICL) in the beneath it. A fourth gate in close proximity to a single dopant atom, the dopant atom being encapsulated in the substrate outside the region of the GICL but close enough to allow spin-dependent charge tunnelling between the dopant atom and the SET island under the control of gate potentials, mainly the fourth gate.

Abstract: The present invention is a method and an apparatus for optical modulation, for example for use in optical communications links. In one embodiment, an apparatus for optical modulation includes a first silicon layer having one or more trenches formed therein, a dielectric layer lining the first silicon layer, and a second silicon layer disposed on the dielectric layer and filling the trenches.

Abstract: A semiconductor structure. The semiconductor structure includes a semiconductor layer, a charge accumulation layer on top of the semiconductor layer, a doped region in direct physical contact with the semiconductor layer; and a device layer on and in direct physical contact with the charge accumulation layer. The charge accumulation layer includes trapped charges of a first sign. The doped region and the semiconductor layer forms a P?N junction diode. The P?N junction diode includes free charges of a second sign opposite to the first sign. The trapped charge in the charge accumulation layer exceeds a preset limit above which semiconductor structure is configured to malfunction. A first voltage is applied to the doped region. A second voltage is applied to the semiconductor layer. A third voltage is applied to the device layer. The third voltage exceeds the first voltage and the second voltage.

Abstract: A semiconductor device has a semiconductor (e.g., a silicon substrate), an electrically conductive region (e.g., a source region and a drain region) which is in contact with the semiconductor to form a Schottky junction, and an insulator. The insulator is in contact with the semiconductor and the electrically conductive region, and has a fixed-charge containing region which contains a fixed charge and extends across a boundary between the semiconductor and the electrically conductive region.

Abstract: A semiconductor chip has devices formed on a first principal plane of a semiconductor substrate, wherein a second principal plane of the semiconductor substrate is planarized, and an organic film having plus charges on an outer side is provided on the second principal plane.

Abstract: An electret device includes an electret film capable of storing charges and a charge outflow inhibition film formed on an upper surface of a region having a high charge density in the electret film and inhibiting the charges stored in the electret film from flowing out.

Abstract: A manufacturing method of a semiconductor device includes a first electrode formation step of forming a control gate electrode above a surface of a semiconductor substrate with a control gate insulating film interposed between the control gate electrode and the semiconductor substrate, a step of forming a storage node insulating film on the surface of the semiconductor substrate, and a second electrode formation step of forming a memory gate electrode on a surface of the storage node insulating film. The second electrode formation step includes a step of forming a memory gate electrode layer on the surface of the storage node insulating film, a step of forming an auxiliary film, having an etching rate slower than that of the memory gate electrode layer, on a surface of the memory gate electrode layer, and a step of performing anisotropic etching on the memory gate electrode layer and the auxiliary film.

Abstract: A method of fabricating memory devices is provided. First, a charge storage structure including a gate dielectric structure is formed on the substrate in sequence to form a charge trapping layer. Then, a gate conductive layer is formed above the charge storage structure. Afterwards, the gate conductive layer and at least a part of the charge storage structure are patterned. The cross section of the patterned charge storage structure is then become a trapezoid or a trapezoid analogue, which has the shorter side near the gate conductive layer and the longer side near the substrate.

Abstract: A semiconductor device has a semiconductor (e.g., a silicon substrate), an electrically conductive region (e.g., a source region and a drain region) which is in contact with the semiconductor to form a Schottky junction, and an insulator. The insulator is in contact with the semiconductor and the electrically conductive region, and has a fixed-charge containing region which contains a fixed charge and extends across a boundary between the semiconductor and the electrically conductive region.

Abstract: A one-time programmable, dual-bit memory device comprises one MOS storage transistor having a semiconductor substrate, first and second active regions formed under the surface of the substrate being separated by a part of the substrate forming a channel region, a gate formed on the surface of the said substrate in line with the channel region and whose respective distal ends are aligned with a part of the first active region and with a part of the second active region, respectively, which gate is permanently held at ground potential, and a gate oxide layer running between the gate and the surface of the substrate. The intact or broken down state between the gate and the first active region determines a stored value of a first bit, and the intact or broken down state between the gate and the second active region determines a stored value of a second bit.

Abstract: An insulating film includes a first metal, oxygen, fluorine and one of a second metal or nitrogen, and satisfies {k×[X]?[F]}/2?8.4 atomic %, wherein the fluorine amount [F], the one element amount [X], and a valence number difference k between the first and second metals or between oxygen and nitrogen.

Abstract: A memory cell structure and control of the memory operation are simplified, and the cost of production is decreased, by way of a semiconductor nonvolatile memory having a transistor including a gate electrode provided on a p-type semiconductor substrate via a gate insulating film, and a source region and a drain region, which are a pair of n-type impurity diffusion regions in the surface layer region of the semiconductor substrate at positions sandwiching the gate electrodes therebetween. A first resistance-varying portion and a second resistance-varying portion are sandwiched by the source region, drain region and channel-forming region. The n-type impurity concentration in the resistance-varying portions is lower than in the source and drain regions.

Abstract: A process for producing an integrated electronic circuit. The process begins with the production of a first electronic component and a second electronic component that are superposed on top of a substrate. A volume of temporary material is formed on the substrate at the position of the second electronic component. The first electronic component is then produced above the volume of temporary material relative to the substrate, and then the second electronic component is produced using at least one shaft for access to the temporary material. The first electronic component may be an active component and the second electronic component may be a passive component.

Abstract: A complementary field effect transistor comprises: a semiconductor substrate; an n-type field effect transistor provided on the semiconductor substrate; and a p-type field effect transistor provided on the semiconductor substrate. The n-type field effect transistor has: a first gate insulating film containing an oxide including an element selected from the group consisting of group IV metals and Lanthanoid metals, and further containing a compound of the element and a group III element; a first gate electrode provided on the first gate insulating film; and n-type source and drain regions formed on both sides of the first gate electrode.

Abstract: A semiconductor device includes a foundation having a first conductive region, and an inter-connection layer provided separate from the foundation. A first region occupying a range from the foundation to the interconnection layer is filled with gas or provided with a first interlayer dielectric film. A first connection plug provided in the first region electrically connects the first conductive region and the interconnection layer. A dielectric first support plug is provided in the first region so that so that the gas can be filled or the first interlayer dielectric film can be provided between the first connection plug and the first support plug. Further, the first plug extends from the interconnection layer to the foundation, and has a second Young's modulus.

Abstract: A charge trapping semiconductor device is particularly suited as a replacement for conventional pull-up and load elements such as NDR diodes, passive resistors, and conventional FETs. The device includes a charge trapping layer formed at or extremely near to an interface between a substrate (which can be silicon or SOI) and a gate insulation layer. The charge trapping device can be shut off during static operations to further reduce power dissipation.

Abstract: A process for providing regions of substantially lower fluorine content in a fluorine-containing dielectric comprises exposing the fluorine-containing dielectric to a reactive species to form volatile byproducts.

Abstract: Described are preferred processes for conditioning semiconductor devices with deuterium to improve operating characteristics and decrease depassivation which occurs during the course of device operation. Also described are semiconductor devices which can be prepared by such processes.

Abstract: A hybrid lead frame having leads for conventional lead-to-I/O wire bonding, and leads for power and ground bussing that extend over a surface of the semiconductor die are provided where the leads for bussing are held in place by lead-lock tape to prevent bending and/or other movement of the bussing leads during manufacturing. More specifically, the lead-lock tape is transversely attached across a plurality of bussing leads proximate to and outside of the position where the die is to be attached.

Abstract: Porous insulation films 28, 40, 50 are formed of an insulation forming material including a silicon compound having a skeleton containing C—C bonds, a pore forming compound which is decomposed or evaporated by a heat treatment, and a solvent which dissolves the silicon compound with the pore forming compound, whereby the porous insulation film can have good mechanical strength and low dielectric constant.

Abstract: The present invention is a dielectric film and its method of fabrication. The dielectric film of the present invention includes silicon oxygen fluorine and nitrogen wherein the interlayer dielectric comprises between 0.01-0.1 atomic percent nitrogen.

Abstract: Substrate bombardment during HDP deposition of carbon-doped silicon oxide film results in filling the gaps between metal lines with carbon-doped low k dielectric material. This leads to the placement of low k dielectric between the narrow metal lines while the films over the metal lines have higher dielectric constant due to removal of carbon from these films during ion bombardment. Films over the metal lines have properties similar to silicon dioxide and are ready for sequential integration processes.

Abstract: A method of fabricating an integrated circuit having reduced threshold voltage shift is provided. A nonconducting region is formed on the semiconductor substrate and active regions are formed on the semiconductor substrate. The active regions are separated by the nonconducting region. A barrier layer and a dielectric layer are deposited over the nonconducting region and over the active regions. Heat is applied to the integrated circuit causing the barrier layer to anneal.

Abstract: A low dielectric constant material having a first fluorine concentration in a near-surface portion and a second fluorine concentration in an interior portion provides an insulator suitable for use in integrated circuits. In a further aspect of the present invention, fluorine is depleted from a near-surface portion of a fluorine containing dielectric material by a reducing plasma. Fluorine in fluorinated low-k dielectric materials, such as SiOF, amorphous fluorinated carbon (a-F:C) and parylene-AF4, can react with surrounding materials such as metals and Si3N4, causing blisters and delamination. Treatment of these fluorinated low-k dielectric materials in a reducing plasma, which may be produced from precursor gases such as H2 or NH3, depletes the surface region of fluorine and hence reduces reaction with surrounding materials and F outgassing. By selecting an appropriate point in the integration flow, specific interfaces which are most susceptible to F-attack can be targeted for depletion.

Abstract: According to various disclosed embodiments, a conductor is patterned in a dielectric. The conductor can be patterned, for example, in the shape of a square spiral. The conductor can comprise, for example, copper, aluminum, or copper-aluminum alloy. The dielectric can be, for example, silicon oxide or a low-k dielectric. A spin-on matrix containing high permeability particles is then deposited adjacent to the patterned conductor. The high permeability particles comprise material having a permeability substantially higher than the permeability of the dielectric. The high permeability particles can comprise, for example, nickel, iron, nickel-iron alloy, or magnetic oxide. As a result, an inductor having a high inductance value is achieved without lowering the quality factor of the inductor.

Abstract: This invention embodies an improved process for annealing integrated circuits to repair fabrication-induced damage. An integrated circuit is annealed in a pressurized sealed chamber in which a forming gas comprising hydrogen is present. Pressurization of the chamber reduces the contribution made by the final anneal step to total thermal exposure by increasing the diffusion rate of the hydrogen into the materials from which the integrated circuit is fabricated. Ideally, the forming gas contains, in addition to hydrogen, at least one other gas such as nitrogen or argon that will not react with hydrogen and, thus, reduce the danger of explosion. However, the integrated circuit may be annealed in an ambiance containing only hydrogen gas that is maintained at a pressure greater than ambient atmospheric pressure.

Abstract: A push-up pin used for separating a semiconductor element attached by adhesive to an adhesive sheet of a semiconductor element pushing-up device in a die bonding apparatus from the adhesive sheet by pushing up the semiconductor element from the rear surface side of the adhesive sheet includes a tip end portion having a shape for applying pushing-up pressure with the thicknesses of the adhesive sheet and the adhesive kept constant when the pushing-up pressure for pushing up the semiconductor element from the rear surface side of the adhesive sheet is applied, and a base portion for supporting the tip end portion.

Abstract: A memory cell provides point defect trap sites in an insulator for storing data charges. Single electrons are stored on respective point defect trap sites and a resulting parameter, such as transistor drain current, is detected. By adjusting the density of the point defect trap sites, more uniform step changes in drain current are obtained as single electrons are stored on or removed from respective trap sites. By also adjusting the trapping energy of the point defect trap sites, the memory cell provides either volatile data storage, similar to a dynamic random access memory (DRAM), or nonvolatile data storage, similar to an electrically erasable and programmable read only memory (EEPROM). The memory cell is used for storing binary or multi-state data.

Abstract: A 1200 dpi LED may be manufactured without highly accurate mask alignment and provide good light radiation efficiency. A first interlayer dielectric is formed on a semiconductor substrate and has a plurality of first windows formed therein and aligned in a row. A diffusion region is formed in the semiconductor substrate through each of the first windows. An electrode is formed to have an area in contact with the corresponding diffusion region. Another electrode is formed on the other side of the substrate. A second interlayer dielectric is formed on the first interlayer dielectric such that the second interlayer dielectric does not overlap the area of the electrode and does not extend to a first perimeter of the area.

Abstract: A EEPROM 140 has a storage transistor 160 with a gate insulating layer 104 of BPSG and a polysilicon gate 112.2 of the same layer as the polysilicon gate 112.1 of the FET transistor 150. The BPSG layer 104 has POHC traps that capture holes injected into N well 103.2. A positive voltage applied to N well 103.2 programs the storage transistor 160 off. Applying a positive voltage to the gate 112.2 neutralizes the holes stored in layer 104 and erases the memory of transistor 160.

Abstract: Reduction in the net charge at the interface of a dielectric and a semiconductor material is achieved by placing atomic species in the dielectric near the interface. Preferably, these species are selected from the group of alkaline earth metals. The presence of these atoms results in a redistribution of the electronic density near the interface. The placement of the atoms is effected by ion implantation followed by multiple annealing steps at alternating low and high temperatures.

Abstract: A structure and method for creating an integrated circuit passivation (24) comprising, a circuit (16), a dielectric (18), and metal plates (20) over which an insulating layer (26) is disposed that electrically and hermetically isolates the circuit (16), and a discharge layer (32) that is deposited to form a passivation (24) that protects the circuit (16) from electrostatic discharges caused by, e.g., a finger, is disclosed.

Abstract: Fluorine bearing spacers on the sidewalls of gate electrodes of a semiconductor device are provided to suppress hot carrier injection in the semiconductor device. In accordance with one embodiment of the invention, a semiconductor device is formed by forming at least one gate electrode on a surface of a substrate and forming fluorine bearing spacers on the sidewalls of the gate electrode. The fluorine bearing spacers may, for example, be formed of an NF.sub.3 -doped glass material.

Abstract: A semiconductor device and a method of manufacturing the semiconductor device. The device includes: (1) a substrate composed at least in part of silicon and (2) a film located over the substrate and having a substantial concentration of an isotope of hydrogen located in the film.

Abstract: An insulating film having a low dielectric constant lower than that of silicon oxide is arranged between a silicon support layer and a silicon active layer. A channel region, source/drain regions, and a device isolation region are formed in the active layer. A gate electrode is arranged on the channel region through a gate insulating film. The active layer is covered with a TEOS film in which contact holes are formed. The contact holes are filled with wiring layers connected to the source/drain regions and the gate electrode.

Abstract: The thin film transistor of this invention is formed on a substrate and includes an active layer and a first insulating film and a second insulating film sandwiching the active layer, wherein the overall polarity of fixed charges contained in the first insulating film is the reverse of the overall polarity of fixed charges contained in the second insulating film.

Abstract: A EEPROM 140 has a storage transistor 160 with a gate insulating layer 104 of BPSG and a polysilicon gate 112.2 of the same layer as the polysilicon gate 112.1 of the FET transistor 150. The BPSG layer 104 has POHC traps that capture holes injected into N well 103.2. A positive voltage applied to N well 103.2 programs the storage transistor 160 off. Applying a positive voltage to the gate 112.2 neutralizes the holes stored in layer 104 and erases the memory of transistor 160.

Abstract: A semiconductor component with at least one lateral semiconductor structure with a high breakdown voltage including a substrate, a dielectric layer adjoining the substrate, a low-doped semiconductor zone disposed on the dielectric layer and heavily doped semiconductor zones of the semiconductor component which project into the low-doped semiconductor zone from the direction of the outer surface of the semiconductor component. Fixed charges, which reduce the electrical field strength in the blocking component of the lateral structure, are embedded inside the dielectric layer adjoining the substrate at least opposite that area of the low-doped semiconductor zone which, in the blocking state of the semiconductor component, has a high voltage in respect to the substrate.

Abstract: A semiconductor component has a semiconductor body with at least on pn-junction therein, extending to the surface of the semiconductor body, and has a passivation layer composed of boron-doped, amorphous, hydrogenous carbon (A-C:H) which covers at least the portion of the pn-junction extending to the surface, the boron content of the passivation layer being between 0.1 per mil and 4% by weight. The passivation layer is manufactured on the semiconductor body by deposition from a high-frequency, low-pressure plasma which is generated in a mixture of gaseous, organic compounds containing carbon and hydrogen and gaseous, organic boron compounds.

Abstract: A method of obtaining high quality passivation layers on silicon carbide surfaces by oxidizing a sacrificial layer of a silicon-containing material on a silicon carbide portion of a device structure to substantially consume the sacrificial layer to produce an oxide passivation layer on the silicon carbide portion that is substantially free of dopants that would otherwise degrade the electrical integrity of the oxide layer.

Abstract: A charge or carrier injection transistor including a substrate, a gate electrode and an electric potential barrier layer forming an electric potential barrier against charges (either holes or electrons) injected by the gate electrode towards the substrate. A source and a drain are formed in the substrate on opposite sides of the gate electrode. A conduction channel, between the source and the drain, is formed on the substrate by charges passing through the electric potential barrier by a voltage applied to the gate electrode. When the applied voltage is removed, this channel disappears. That is, the transistor is ON when the charges from the gate electrode pass through the electric potential barrier and is OFF when no charges pass through it, thereby the charges perform a transistor switching function.

Abstract: A method for passivating an integrated circuit includes the RF sputtering of a hard passivation layer on the surface of the integrated circuit. The hard passivation layer can be a ceramic material such as various doped and undoped titanates, zirconates, niobates, tantalates, stanates, hafnates, and manganates, in either their ferroelectric or non-ferroelectric phases. Other exotic, hard, and usually non-ferroelectric materials not normally found in integrated circuit processing such as carbides may also be used. If the integrated circuit sought to be passivated contains ferroelectric devices, the hard passivation layer can be fabricated out of the same material used in the integrated ferroelectric devices. An optional silicon dioxide insulating layer can be deposited on the surface of the integrated circuit before the hard passivation layer is deposited. The optional silicon dioxide layer is used to prevent any possible contamination of the integrated circuit by the passivation layer.

Abstract: Reduced soft errors in charge-sensitive circuit elements such as volatile memory cells 200 occur by using boron-11 to the exclusion of boron-10 or essentially free of boron-10 in borosilicate glass 230, 240 deposited on the substrate 206 directly over the arrays of memory cells. Boron-10 exhibits a high likelihood of fission to release a 1.47 MeV alpha particle upon capture of a naturally occurring cosmic ray neutron. This capture occurs frequently in boron-10 because of its high neutron capture cross-section. Boron-11 does not fission.

Abstract: A power semiconductor component having integrated protection against electrostatic destruction is published. Such a semiconductor component (1) comprises a semiconductor substrate (10) having at least one MOS structure whose gate (7) is arranged insulated from the semiconductor substrate (10). Such structures are susceptible to destruction by a dielectric breakdown of the insulation layer, caused by electrostatic charging. According to the invention, this insulating layer between-the gate electrode (3) and the main electrode (2) is now replaced by a semi-insulating layer (9) so that a limited current flow becomes possible between the gate (7) and the main electrode (2) and it is no longer possible for any potential difference to build up.

Abstract: A layer of dopant is implanted in the passivation of a semiconductor die to facilitate testing of the die by a scanning electron microscope voltage contrast system. The layer of dopant is capacitively coupled to circuits under the passivation and is coupled to ground to allow charge to bleed to ground through a high resistivity path. The resistivity is low enough to allow E-beam charge bleed off, but not bleed off of higher frequency capacitive coupled signals. The disclosure is also applicable to photo generated electron voltage contrast.