Abstract: Disclosed herein are related to performing layout verification of a layout design of an integrated circuit having a slanted layout component. In one aspect, a slanted layout component having a side slanted from a base axis by an offset angle is detected. In one aspect, a first location of a vertex of the slanted layout component according to the offset angle is transformed to obtain a second location of a rotated vertex of a rotated layout component. In one aspect, layout verification is performed on the rotated layout component with respect to the base axis.

Abstract: An electronic package is formed by disposing an electronic element and a lead frame having a plurality of conductive posts on a carrier structure having an antenna function, and encapsulating the electronic element and the lead frame with an encapsulant. The encapsulant is defined with a first encapsulating portion and a second encapsulating portion lower than the first encapsulating portion. The electronic element is positioned in the first encapsulating portion, and the plurality of conductive posts are positioned in the second encapsulating portion. End surfaces of the plurality of conductive posts are exposed from a surface of the second encapsulating portion so as to be electrically connected to a connector.

Abstract: An assembly is provided. The assembly includes a packaged semiconductor device and an outer enclosure enclosing the packaged semiconductor device. The packaged semiconductor device includes at least four opposing sides. The outer enclosure includes a magnetic material and a non-magnetic region arranged adjacent to the at least four opposing sides of the packaged semiconductor device.

Abstract: A semiconductor package using a polymer substrate is disclosed and may include a polymer cavity structure comprising first metal traces, a micro-electro mechanical systems (MEMS) device and a semiconductor die bonded to a first surface within a cavity of the cavity structure, and a substrate coupled to the cavity structure and comprising second metal traces coupled to the first metal traces. The substrate may enclose the MEMS device and the semiconductor die. Ground traces may be on external surfaces of the polymer cavity structure. Ball lands may be on a surface of the substrate opposite to a surface with the second metal traces. The first metal traces may extend from the first surface of the polymer cavity structure up a sidewall of the cavity and to conductive patterns on a top surface of the polymer cavity structure.

Abstract: A package structure includes a mounting pad having a mounting surface; a semiconductor chip having a magnetic device, a first magnetic field shielding, and a molding. The semiconductor chip comprises a first surface perpendicular to a thickness direction of the semiconductor chip, a second surface opposite to the first surface, wherein the second surface is attached to the mounting surface of the mounting pad, and a third surface connecting the first surface and the second surface. The first magnetic field shielding including a plurality of segments laterally at least partially surrounding the semiconductor chip, wherein a bottom surface of the first magnetic field shielding is attached to the mounting surface of the mounting pad, wherein the mounting surface comprises first portion free from overlapping with the first magnetic field shielding from a top view perspective. The molding surrounding the mounting pad and in direct contact with the mounting surface.

Abstract: A chip package structure is provided. The chip package structure includes a chip. The chip package structure includes a conductive ring-like structure over and electrically insulated from the chip. The conductive ring-like structure surrounds a central region of the chip. The chip package structure includes a first solder structure over the conductive ring-like structure. The first solder structure and the conductive ring-like structure are made of different materials.

Abstract: The present invention provides a semiconductor device including an insulating layer, a conductive layer bonded to one main surface of the insulating layer, a semiconductor element arranged such that the upper surface of the semiconductor element faces a direction same as the one main surface of the insulating layer, an upper electrode provided on the upper surface of the semiconductor element, a wiring member that has one end electrically bonded to the upper electrode of the semiconductor element and has another end electrically bonded to the conductive layer, and has a hollow portion, a first sealing material, and a second sealing material, in which the first sealing material seals at least part of the semiconductor element so as to be in contact with the semiconductor element, and the second sealing material seals the wiring member so as to be in contact with the wiring member.

Abstract: An IC device includes an interlayer dielectric (ILD), a first tower structure embedded in the ILD, and a first ring region including a portion of the ILD that extends around the first tower structure. The first tower structure includes a plurality of first conductive patterns in a plurality of metal layers, and a plurality of first vias between the plurality of metal layers along a thickness direction of the IC device. The plurality of first conductive patterns and the plurality of first vias are coupled to each other to form the first tower structure. The plurality of first conductive patterns is confined by the first ring region, without extending beyond the first ring region. The first tower structure is a dummy tower structure.

Abstract: An electronic device includes a substrate comprising outward terminals. An electronic component is connected to the outward terminals. External interconnects are connected to the outward terminals and include a first external interconnect connected to a first outward terminal. A lower shield is adjacent to the substrate bottom side and is laterally between the external interconnects. The lower shield is electrically isolated from the first external interconnect by one or more of 1) a dielectric buffer interposed between the lower shield and the first external interconnect; or 2) the lower shield including a first part and a second part, the first part being laterally separated from the second part by a first gap, wherein the first part laterally surrounds lateral sides of the first external interconnect; and the second part is vertically interposed between the first outward terminal and the first external interconnect.

Abstract: A semiconductor package includes a multilayer package substrate including a first layer including a first dielectric and first metal layer including a first metal trace and a second layer including a second dielectric layer. An integrated circuit (IC) die includes bond pads, with a bottom side of the IC die attached to the first metal trace. Metal pillars are through the second dielectric layer connecting to the first metal trace. A third layer on the second layer includes a third dielectric layer on the second layer extending to a bottom side of the semiconductor package, and a second metal layer including second metal traces including inner second metal traces connected to the bond pads and outer second metal traces over the metal pillars, and filled vias providing externally accessible contact pads that connect the second metal traces to a bottom side of the semiconductor package.

Abstract: A semiconductor device including: a semiconductor substrate; a temperature sensing unit provided on a front surface of the semiconductor substrate; an anode pad and a cathode pad electrically connected with the temperature sensing unit; a front surface electrode being set to a predetermined reference potential; and a bidirectional diode unit electrically connected in a serial bidirectional way between the cathode pad and the front surface electrode is provided. The bidirectional diode unit may be arranged between the anode pad and the cathode pad on the front surface.

Abstract: Provided is packages and method of fabricating the same. The package includes a first die, a second die, and an inductor. The second die is bonded to the first die through a bonding structure thereof. The inductor is located in the bonding structure. The inductor includes a spiral pattern parallel to top surfaces of the first die and the second die, and the spiral pattern includes at least a turn.

Abstract: Reduced-power dynamic data circuits with wide-band energy recovery are described herein. In one embodiment, a circuit system comprises at least one sub-circuit in which at least one of the sub-circuits includes a capacitive output node that is driven between low and high states in a random manner for a time period and an inductive circuit path coupled to the capacitive output node. The inductive circuit path includes a transistor switch and an inductor connected in series to discharge and recharge the output node to a bias supply. A pulse generator circuit generates a pulse width that corresponds to a timing for driving the output node.

Abstract: In one example, embedded die package, including a layer having an exposed boundary, wherein at least a portion of the exposed boundary comprises organic material. The package also includes at least one integrated circuit die positioned in the layer and within the exposed boundary. The package also includes a dielectric material positioned in the layer and between the at least one integrated circuit and structure adjacent the at least one integrated circuit.

Abstract: Embodiments of the invention include a microelectronic device that includes a first substrate having radio frequency (RF) components and a second substrate that is coupled to the first substrate. The second substrate includes a first conductive layer of an antenna unit for transmitting and receiving communications at a frequency of approximately 4 GHz or higher. A mold material is disposed on the first and second substrates. The mold material includes a first region that is positioned between the first conductive layer and a second conductive layer of the antenna unit with the mold material being a dielectric material to capacitively couple the first and second conductive layers of the antenna unit.

Abstract: A housing for a power semiconductor module arrangement includes sidewalls and a lid. The lid includes a first layer of a first material having a plurality of openings, and second layer of a second material that is different from the first material. The second layer completely covers a bottom surface of the first layer. The second layer includes a plurality of protrusions, each protrusion extending into a different one of the plurality of openings of the first layer such that each of the plurality of openings is completely covered by one of the protrusions.

Abstract: Two approaches for on-chip ESD detection include variable dielectric width capacitor, and vertical metal-oxide-semiconductor (MOS) capacitor MOSCAP array. The variable dielectric width capacitor approach employs metal plates terminated with sharp corners to enhance local electric field and facilitate ready breakdown of a thin dielectric between the metal plates. The vertical MOSCAP array is composed of a capacitor array connected in series. Both approaches are incorporated in an example 22 nm fully depleted silicon-on-insulator. Vertical MOSCAP arrays detect ESD events starting from about 6 V with about 6 V granularity, while the variable dielectric width capacitor is suitable for detection of high ESD voltage from about 40 V and above.

Abstract: One way to stop electromagnetic fields from leaking outside of a module is an electric wall. Embodiments of the present disclosure are directed to emulating an electric wall with through vias. The through vias may be arranged around cavities in the printed circuit board. The density of the through vias may be selected based on an expected wavelength of the electromagnetic fields. The printed circuit board may then self-isolate components within the cavities from the electromagnetic fields.

Abstract: Semiconductor structures including a deep trench isolation structure and methods of forming a semiconductor structure including a deep trench isolation structure. The semiconductor structure includes a semiconductor substrate having a device region, and a deep trench isolation structure in the semiconductor substrate. The deep trench isolation structure further includes a first portion, a second portion adjacent to the first portion, and a conductor layer in the first portion and the second portion. The conductor layer in the first portion of the deep trench isolation structure surrounds the device region. The conductor layer in the second portion of the deep trench isolation structure defines an electrical connection to the semiconductor substrate.

Abstract: A semiconductor device assembly is provided. The assembly includes a redistribution layer (RDL) including a plurality of external contacts on a first side and a plurality of internal contacts on a second side opposite the first side. The assembly further includes a first die at least partially embedded in the RDL and having an active surface between the first side and the second side of the RDL. The assembly further includes one or more second dies disposed over the controller die and the RDL, wherein the one or more second dies electrically coupled to the internal contacts. The assembly further includes an encapsulant at least partially encapsulating the one or more second dies.

Abstract: A gift card system and method for purchasing both physical and digital gift cards at a kiosk, both physical and virtual, is disclosed. The system/method includes a gift card distribution kiosk located at a retail establishment or online that provides a user with access to a multitude of different forms of gift cards that may be purchased and printed onto a customizable card with a personalized message. The kiosk includes a kiosk processor interface, a gift card dispenser, a card reader and gift card management server connected to a network. The gift card management server, through the kiosk processor interface, provides vendor options to users to select and pay via the card reader. The kiosk may be used to redeem unused user gift cards for a reduced value user selected gift card, reduced cash value, full value store card, rewards points, bank debit, and/or electronic code user towards online purchases.

Abstract: A module substrate, a sealing resin portion, and a shield are provided. The shield is provided to cover each of the sealing resin portion and a peripheral side surface of the module substrate. The shield is connected to a ground electrode. On the peripheral side surface, the shield is separated into a first surface side and a second surface side.

Abstract: A semiconductor device has a semiconductor wafer including a plurality of semiconductor die. An insulating layer is formed over the semiconductor wafer. A portion of the insulating layer is removed by LDA to expose a portion of an active surface of the semiconductor die. A first conductive layer is formed over a contact pad on the active surface of the semiconductor die. The semiconductor wafer is singulated to separate the semiconductor die. The semiconductor die is disposed over a carrier with the active surface of the semiconductor die offset from the carrier. An encapsulant is deposited over the semiconductor die and carrier to cover a side of the semiconductor die and the exposed portion of the active surface. An interconnect structure is formed over the first conductive layer. Alternatively, a MUF material is deposited over a side of the semiconductor die and the exposed portion of the active surface.

Abstract: A method includes performing an anisotropic etching on a semiconductor substrate to form a trench. The trench has vertical sidewalls and a rounded bottom connected to the vertical sidewalls. A damage removal step is performed to remove a surface layer of the semiconductor substrate, with the surface layer exposed to the trench. The rounded bottom of the trench is etched to form a slant straight bottom surface. The trench is filled to form a trench isolation region in the trench.

Abstract: Disclosed is a packaging method for circuit units, wherein the circuit units comprise a silicon layer substrate and a silicon dioxide layer overlaid on the silicon layer substrate. The packaging method for a circuit unit comprises: attaching a plurality of circuit units to a circuit baseplate in a spaced and inverted mode, wherein the silicon dioxide layer is attached to the circuit baseplate, and the silicon layer substrate faces away from the circuit baseplate; forming an insulator between the circuit units; removing the silicon layer substrate to expose the silicon dioxide layer; and forming an electromagnetic shielding layer on the silicon dioxide layer and the insulator.

Abstract: A transformer includes a first inductor, facing in a first direction and a second inductor, facing in a second direction, the second direction opposite to the first. In one example the first and the second inductors are arranged such that the first inductor's legs extend to an area of the second inductor's head, and the second inductor's legs extend to an area of the first inductor's head.

Abstract: A semiconductor package includes a first semiconductor device, a second semiconductor device vertically positioned above the first semiconductor device, and a ground shielded transmission path. The ground shielded transmission path couples the first semiconductor device to the second semiconductor device. The ground shielded transmission path includes a first signal path extending longitudinally between a first end and a second end. The first signal path includes a conductive material. A first insulating layer is disposed over the signal path longitudinally between the first end and the second end. The first insulating layer includes an electrically insulating material. A ground shielding layer is disposed over the insulating material longitudinally between the first end and the second end of the signal path. The ground shielding layer includes a conductive material coupled to ground.

Abstract: An electronic assembly according to an embodiment includes: a circuit board including a first edge surface and a trace having an electrical conductivity; an electronic element including a lateral edge spatially spaced apart from the first edge surface, and mounted on the circuit board and electrically connected to the trace; a protection layer including a second edge surface and disposed on the electronic element to substantially cover the electronic element; a magnetic field shielding film including a third edge surface and disposed on the protection layer; and a first metal layer.

Abstract: One example of a semiconductor package includes a first substrate, a second substrate, a semiconductor die, and a spacer. The semiconductor die is attached to the first substrate. The spacer is attached to the semiconductor die and attached to the second substrate via solder. A surface of the second substrate facing the spacer includes a plurality of recesses extending from proximate at least one edge of the spacer to contain a portion of the solder.

Abstract: In an embodiment, a device includes: a bottom integrated circuit die having a first front side and a first back side; a top integrated circuit die having a second front side and a second back side, the second back side being bonded to the first front side, the top integrated circuit die being free from through substrate vias (TSVs); a dielectric layer surrounding the top integrated circuit die, the dielectric layer being disposed on the first front side, the dielectric layer and the bottom integrated circuit die being laterally coterminous; and a through via extending through the dielectric layer, the through via being electrically coupled to the bottom integrated circuit die, surfaces of the through via, the dielectric layer, and the top integrated circuit die being planar.

Abstract: A nitride semiconductor device includes a semiconductor carrier, a first nitride-based chip, and first conformal connecting structures. The first nitride-based chip is disposed over the semiconductor carrier. The semiconductor carrier has a first planar surface. The first nitride-based chip has a second planar surface, first conductive pads, and first slanted surfaces. The first conductive pads are disposed in the second planar surface. The first slanted surfaces connect the second planar surface to the first planar surface. The first conformal connecting structures are disposed on the first planar surface and the first nitride-based chip. First obtuse angles are formed between the second planar surface and the first slanted surfaces. Each of the first conformal connecting structures covers one of the first slanted surfaces of the first nitride-based chip and one of the first obtuse angles and is electrically connected to the first conductive pads.

Abstract: Signal isolation for module with ball grid array. In some embodiments, a packaged module can include a packaging substrate having an underside, and an arrangement of conductive features implemented on the underside of the packaging substrate to allow the packaged module to be capable of being mounted on a circuit board. The arrangement of conductive features can include a signal feature implemented at a first region and configured for passing of a signal, and one or more shielding features placed at a selected location relative to the signal feature to provide an enhanced isolation between the signal feature and a second region of the underside of the packaging substrate.

Abstract: An LED light source includes a board, a holder, an LED, a fastener, a lens, a supporter, and an adhesive. The board has a first surface. The holder is arranged on or above the first surface. The LED is arranged on or above the first surface. The fastener fastens the LED to the first surface. The lens has an exterior shape larger than the LED as viewed in a plan view, and is arranged on or above an LED upper surface to refract LED light so as to direct the light outward. The supporter is arranged on an exterior with respect to the LED as viewed in a plan view on a lens surface facing the first surface. The supporter is held by the holder for positioning of the lens at a predetermined position on the first surface. The adhesive bonds the supporter and the board together.

Abstract: The present disclosure provides an in-mold injection molding process for a Printed Circuit Board Assembly (PCBA) soft material, including the following steps: 1) preheating a Polyethylene Terephthalate (PET) thin film; 2) printing patterns; 3) preparing a diaphragm A; 4) laminating a diaphragm on a Flexible Printed Circuit (FPC) board; 5) scraping printing ink; 6) scraping an adhesive; 7) preparing an inner diaphragm B; and 8) placing prepared diaphragm A and FPC board laminated diaphragm in a mold cavity of an injection mold of a Haitian 130T injection molding machine, preheating injection mold to 30° C., and injecting Thermoplastic Polyurethane (TPU) resin through an injection hole, so that diaphragm A is on an outer side of a product mobile phone protective shell, FPC board laminated diaphragm is on an inner side of the product mobile phone protective shell, and temperature of the TPU resin is at 180° C.

Abstract: A radio frequency front-end module, a manufacturing method thereof and a communication device are provided. The radio frequency front-end module includes a first base substrate and a metal bonding structure; a second functional substrate, including a second base substrate, a groove in the second base substrate, and a bonding metal layer; and a first radio frequency front-end component, at least partially located in the groove, the first base substrate and the second base substrate are oppositely arranged, and a surface of the second base substrate close to the first base substrate includes a groove surface inside the groove and a substrate surface outside the groove, and the bonding metal layer includes a first metal portion located on the groove surface and a second metal portion located on the substrate surface, the first radio frequency front-end component is at least partially surrounded by the first metal portion.

Abstract: A radio-frequency module includes a multilayer substrate, a first semiconductor device, and a second semiconductor device. The multilayer substrate includes a plurality of stacked layers, and has a first major face and a second major face. The first semiconductor device includes a first power amplifier circuit. The second semiconductor device includes at least one of a low-noise amplifier circuit, a switching circuit, or a control circuit. The first major face includes a first recess. The first semiconductor device is mounted over a bottom face of the first recess. The second semiconductor device is mounted over the first major face so as to overlie the first recess. The first semiconductor device is connected with a metallic via that extends through a portion of the multilayer substrate from the bottom face of the first recess to the second major face.

Abstract: A semiconductor package includes a substrate, first and second semiconductor chip structures on the substrate and spaced apart from each other in a first horizontal direction, a mold layer on the substrate and covering both the first and second semiconductor chip structures, and a supporting structure on the mold layer and distal from the upper surface of the substrate than both the first and second semiconductor chip structures in a vertical direction. The supporting structure includes first and second supporting portions, spaced apart from each other in a second horizontal direction that is perpendicular to the first horizontal direction and the vertical direction. Each of the first and second supporting portions has a bar shape or a linear shape extending in the first horizontal direction. At least one of the first supporting portion or the second supporting portion overlaps the first and second semiconductor chips in the vertical direction.

Abstract: A three-dimensional semiconductor memory device includes a peripheral circuit structure having peripheral circuits on a semiconductor substrate, and landing pads connected to the peripheral circuits, an electrode structure on the peripheral circuit structure, the electrode structure including vertically stacked electrodes, a planarized dielectric layer that covers the electrode structure, peripheral through plugs spaced apart from the electrode structure, the peripheral through plugs penetrating the planarized dielectric layer to connect to the landing pads, conductive lines connected through contact plugs, respectively, to the peripheral through plugs, and at least one dummy through plug adjacent to a first peripheral through plug of the peripheral through plugs, the at least one dummy through plug penetrating the planarized dielectric layer and being insulated from the conductive lines.

Abstract: Methods of forming a super high density metal-insulator-metal (SHDMIM) capacitor and semiconductor device are disclosed herein. A method includes depositing a first insulating layer over a semiconductor substrate and a series of conductive layers separated by a series of dielectric layers over the first insulating layer, the series of conductive layers including device electrodes and dummy metal plates. A first set of contact plugs through the series of conductive layers contacts one or more conductive layers of a first portion of the series of conductive layers. A second set of contact plugs through the series of dielectric layers avoids contact of a second portion of the series of conductive layers, the second portion of the series of conductive layers electrically floating.

Abstract: A semiconductor device package and a fabrication method thereof are disclosed. The semiconductor package comprises: a substrate having a first face and an opposing second face, wherein the first face is mounted with a first semiconductor component and a plurality of connectors; and a first shielding member covering the first semiconductor component and a first group of the plurality of connectors, while exposing a second group of the plurality of connectors.

Abstract: Embodiments include a semiconductor package, a package on package system, and a method of forming the semiconductor package. The semiconductor package includes a first redistribution layer, a stack of dies on the first redistribution layer, a second redistribution layer over the stack of dies and the first redistribution layer, and a plurality of interconnects coupled to the stack of dies and the first and second redistribution layers. The interconnects may extend substantially vertical from a top surface of the first redistribution layer to a bottom surface of the second redistribution layer. The semiconductor package may also include a mold layer between the first redistribution layer and the second redistribution layer. The plurality of interconnects may be through mold vertical wire interconnects. The first and second redistribution layers may be dual-sided redistribution layers. The semiconductor package may further include adhesive layers coupled to the stack of dies.

Abstract: A semiconductor structure is provided, including: a substrate and a dielectric layer arranged on the substrate; a conductive plug, wherein a first part of the conductive plug is arranged in the substrate, and a second part of the conductive plug is arranged in the dielectric layer; and an isolation ring structure at least surrounding the second part of the conductive plug.

Abstract: A stacked semiconductor device includes a cooling structure to increase the cooling efficiency of the stacked semiconductor device. The cooling structure includes various types of cooling components integrated into the stacked semiconductor device that are configured to remove and/or dissipate heat from dies of the stacked semiconductor device. In this way, the cooling structure reduces device failures and permits the stacked semiconductor device to operate at greater voltages, greater speeds, and/or other increased performance parameters by removing and/or dissipating heat from the stacked semiconductor device.

Abstract: Embodiments of this application disclose a package structure and a communications device to which the package structure is applied. The package structure includes a substrate, a die, and a bonding layer configured to bond the die to the substrate. Charged particles are disposed in the bonding layer. An electrode is disposed on a surface of the die away from the bonding layer. A potential of the electrode is opposite to that of the charged particle. The package structure further includes a first shielding structure. A potential of the substrate is zero. The first shielding structure is located on an outer surface of the die and is located between the bonding layer and the electrode, to prevent the charged particles from migrating to the electrode.

Abstract: An electronic package structure, an electronic substrate, and a method of manufacturing an electronic package structure are provided. The electronic package structure includes a substrate. The substrate includes a bonding region and an alignment structure. The bonding region is located at a side of the substrate and configured to bond with an electronic component. The alignment structure is located at the side of the substrate and out of the bonding region and configured to providing a fiducial mark for position-aligning, wherein the alignment structure comprises a first region and a second region visually distinct from the first region.

Abstract: An electronic package is provided, which stacks an electronic structure as an integrated voltage regulator on an electronic component to facilitate close-range cooperation with the electronic component for electrical transmission.

Abstract: A three-dimensional semiconductor memory device includes: a peripheral circuit structure; and a cell array structure on the peripheral circuit structure. The peripheral circuit structure includes a lower wiring on a substrate, a stopping insulating layer on the lower wiring, a contact via on the lower wiring, a floating via on the stopping insulating layer, and an upper wiring on the contact via. The floating via does not contact the lower wiring. The contact via contacts the lower wiring through a via hole in the stopping insulating layer. The upper wiring contacts the contact via.

Abstract: An electronic package is formed by disposing an electronic element and a lead frame having a plurality of conductive posts on a carrier structure having an antenna function, and encapsulating the electronic element and the lead frame with an encapsulant. The encapsulant is defined with a first encapsulating portion and a second encapsulating portion lower than the first encapsulating portion. The electronic element is positioned in the first encapsulating portion, and the plurality of conductive posts are positioned in the second encapsulating portion. End surfaces of the plurality of conductive posts are exposed from a surface of the second encapsulating portion so as to be electrically connected to a connector.

Abstract: Provided are a power module and a heat sink system. The power module includes a first circuit board, a second circuit board, at least one discrete component and an encapsulation body. One discrete component includes a lead frame and at least one chip, the lead frame is disposed between the first circuit board and the second circuit board, the lead frame includes two end faces and multiple mounting lateral surfaces connected in sequence, an angle is formed between one end face and one mounting lateral surface, one of the two end faces is electrically connected to the first circuit board and the other of the two end faces is electrically connected to the second circuit board, and the chip is disposed on each of the multiple mounting lateral surfaces. The encapsulation body is configured to pot a space between the first circuit board and the second circuit board.

Abstract: A module comprises: a wiring board; a first component, a second component and a third component mounted on a first main surface; a shield structure mounted on the first main surface; a first sealing resin that seals the first component and the like; and a shield film that covers an upper surface of the first sealing resin and the like, the shield structure including a top side portion and at least one sidewall portion bent from the top side portion and thus extending therefrom, the top side portion including the top side portion's conductive layer and a magnetic layer therein, the sidewall portion including the sidewall portion's conductive layer therein, the top side portion's conductive layer and the sidewall portion's conductive layer being electrically connected to a ground conductor, the magnetic layer in the top side portion being located over the first component.