With Shielding (e.g., Electrical Or Magnetic Shielding, Or From Electromagnetic Radiation Or Charged Particles) Patents (Class 257/659)
  • Patent number: 10439587
    Abstract: Methods of manufacturing an electronic device formed in a cavity may include providing a first substrate having a first side wall including a first metal formed along a periphery on a bottom surface thereof and surrounding an electronic circuit disposed on the bottom surface, providing a second substrate having a second side wall including a second metal and a third metal formed along a periphery on a top surface thereof, aligning the first substrate with the second substrate with the first side wall opposing and contacting the second side wall to internally define a cavity between the bottom surface of the first substrate, the top surface of the second substrate, the first side wall ,and the second side wall, and heating and bonding the first substrate and the second substrate by transient liquid phase bonding.
    Type: Grant
    Filed: December 1, 2017
    Date of Patent: October 8, 2019
    Assignee: SKYWORKS SOLUTIONS, INC.
    Inventor: Atsushi Takano
  • Patent number: 10431555
    Abstract: Disclosed herein is a method of manufacturing a semiconductor package including a semiconductor chip sealed by a sealing synthetic resin. The method includes preparing a wiring board in which upstanding encircling walls with side-surface shield layers embedded therein surround mounts on which semiconductor chips are to be mounted, mounting the semiconductor chips on the mounts surrounded by the upstanding encircling walls on the wiring board, supplying a sealing synthetic resin to spaces surrounded by the upstanding encircling walls thereby to produce an sealed board, dividing the sealed board along projected dicing lines into individual semiconductor packages, and forming an upper-surface shield layer for blocking electromagnetic waves on the semiconductor packages.
    Type: Grant
    Filed: January 24, 2018
    Date of Patent: October 1, 2019
    Assignee: DISCO CORPORATION
    Inventors: Byeongdeck Jang, Youngsuk Kim
  • Patent number: 10431368
    Abstract: A coil electronic component includes a magnetic body, wherein the magnetic body includes a substrate, and a coil part including patterned insulating films disposed on the substrate, a first plating layer formed between the patterned insulating films by plating, and a second plating layer disposed on the first plating layer.
    Type: Grant
    Filed: August 31, 2016
    Date of Patent: October 1, 2019
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Woon Chul Choi, Ji Hye Oh, Jung Hyuk Jung, Han Wool Ryu
  • Patent number: 10429436
    Abstract: The disclosure relates to a device for measuring an electrical characteristic of a substrate comprising a support made of a dielectric material having a bearing surface, the support comprising an electrical test structure having a contact surface flush with the bearing surface of the support, the bearing surface of the support and the contact surface of the electrical test structure being suitable for coming into close contact with a substrate. The measurement device also comprises at least one connection bump contact formed on another surface of the support and electrically linked to the electrical test structure. This disclosure also relates to a system for characterizing a substrate and a method for measuring a characteristic of a substrate employing the measurement device.
    Type: Grant
    Filed: January 19, 2016
    Date of Patent: October 1, 2019
    Assignee: Soitec
    Inventors: Cédric Malaquin, Jean-Pierre Raskin, Eric Desbonnets
  • Patent number: 10424556
    Abstract: An electronic component package includes a substrate and an electronic component mounted to the substrate, the electronic component including a bond pad. A first antenna terminal is electrically connected to the bond pad, the first antenna terminal being electrically connected to a second antenna terminal of the substrate. A package body encloses the electronic component, the package body having a principal surface. An antenna is formed on the principal surface by applying an electrically conductive coating. An embedded interconnect extends through the package body between the substrate and the principal surface and electrically connects the second antenna terminal to the antenna. Applying an electrically conductive coating to form the antenna is relatively simple thus minimizing the overall package manufacturing cost. Further, the antenna is relatively thin thus minimizing the overall package size.
    Type: Grant
    Filed: August 15, 2016
    Date of Patent: September 24, 2019
    Assignee: Amkor Technology, Inc.
    Inventors: Jong Ok Chun, Nozad Karim, Richard Chen, Giuseppe Selli, Michael Kelly
  • Patent number: 10418305
    Abstract: A chip on film package includes a base film, a patterned circuit layer, a chip and a heat dissipation sheet. The base film includes a first surface and a mounting region located on the first surface. The patterned circuit layer is disposed on the first surface. The chip is disposed on the mounting region and electrically connected to the patterned circuit layer. The heat dissipation sheet includes a first adhesive layer disposed over the base film, a second adhesive layer disposed over the first adhesive layer, and a graphite layer disposed between the first adhesive layer and the second adhesive layer, wherein at least one of the first adhesive layer and the second adhesive layer is a double-sided adhesive with carrier, which comprises two adhesives and a carrier disposed between the two adhesives.
    Type: Grant
    Filed: January 30, 2019
    Date of Patent: September 17, 2019
    Assignee: Novatek Microelectronics Corp.
    Inventors: Wen-Ching Huang, Chien-Chen Ko, Ling-Chieh Li
  • Patent number: 10418332
    Abstract: A semiconductor device has a partition fence disposed between a first attach area and a second attach area on a substrate. A first electrical component is disposed over the first attach area. A second electrical component is disposed over the second attach area. The partition fence extends above and along a length of the first electrical component and second electrical component. An encapsulant is deposited over the substrate, first electrical component, second electrical component, and partition fence. A portion of the encapsulant is removed to expose a surface of the partition fence and planarizing the encapsulant. A shielding layer is formed over the encapsulant and in contact with the surface of the partition fence. The combination of the partition fence and shielding layer compartmentalize the first electrical component and second electrical component for physical and electrical isolation to reduce the influence of EMI, RFI, and other inter-device interference.
    Type: Grant
    Filed: March 13, 2017
    Date of Patent: September 17, 2019
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: Goo Lee, KyungMoon Kim, SooSan Park, KeoChang Lee
  • Patent number: 10411609
    Abstract: The present disclosure reduces heat concentration on switching elements. A plurality of high-side transistors are connected in parallel to constitute high-side switching element. A plurality of low-side transistors are connected in parallel to constitute low-side switching element. The plurality of high-side transistors are arranged, one by one, next to the plurality of low-side transistors.
    Type: Grant
    Filed: December 3, 2018
    Date of Patent: September 10, 2019
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Junichi Yukawa, Yoshihiko Maeda, Satoshi Okawa
  • Patent number: 10408919
    Abstract: In accordance with an embodiment, a packaged radio frequency (RF) circuit includes a radio frequency integrated circuit (RFIC) disposed on a substrate that has plurality of receiver circuits coupled to receive ports at a first edge of the RFIC, and a first transmit circuit coupled to a first transmit port at a second edge of the RFIC. The packaged RF circuit also includes a receive antenna system disposed on the package substrate adjacent to the first edge of the RFIC and a first transmit antenna disposed on the package substrate adjacent to the second edge of the RFIC and electrically coupled to the first transmit port of the RFIC. The receive antenna system includes a plurality of receive antenna elements that are each electrically coupled to a corresponding receive port.
    Type: Grant
    Filed: December 13, 2018
    Date of Patent: September 10, 2019
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Saverio Trotta, Ashutosh Baheti, Ismail Nasr, Ngoc-Hoa Huynh, Martin Richard Niessner
  • Patent number: 10403609
    Abstract: A system-in-package device includes at least three electrical device components arranged in a common package. A first electrical device component includes a first vertical dimension, a second electrical device component includes a second vertical dimension and a third electrical device component comprises a third vertical dimension. The first electrical device component and the second electrical device component are arranged side by side in the common package. Further, the third electrical device component is arranged on top of the first electrical device component in the common package. At least a part of the third electrical device component is arranged vertically between a front side level of the second electrical device component and a back side level of the second electrical device component.
    Type: Grant
    Filed: December 21, 2015
    Date of Patent: September 3, 2019
    Assignee: Intel IP Corporation
    Inventors: Christian Geissler, Sven Albers, Georg Seidemann, Andreas Wolter, Klaus Reingruber, Thomas Wagner, Marc Dittes
  • Patent number: 10403581
    Abstract: Electronic device packages utilizing a stiffener coupled to a substrate with a magnetic lossy bonding layer to attenuate or absorb electromagnetic signals such as radio frequency interference (RFI) along with related systems and method are disclosed.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: September 3, 2019
    Assignee: Intel Corporation
    Inventors: Jaejin Lee, Hao-Han Hsu, Chung-Hao J. Chen, Dong-Ho Han
  • Patent number: 10396004
    Abstract: A wafer level chip scale package is described. The wafer level chip scale package comprises a plurality of redistribution layer (RDL) traces connected to a silicon wafer through openings through a first polymer layer to metal pads on a top surface of the silicon wafer. A plurality of underbump metal (UBM) layers each contact one of the plurality of RDL traces through openings in a second polymer layer over the first polymer layer. A plurality of solder bumps lie on each UBM layer. A metal plating layer lies under the first polymer layer and does not contact any of the plurality of RDL traces. At least one separator lies between at least two of the plurality of RDL traces. The separator is a metal fencing between the two neighboring RDL traces or an air gap between the two neighboring RDL traces.
    Type: Grant
    Filed: January 25, 2018
    Date of Patent: August 27, 2019
    Assignee: Dialog Semiconductor (UK) Limited
    Inventors: Habeeb Mohiuddin Mohammed, Rajesh Subraya Aiyandra
  • Patent number: 10396039
    Abstract: A lead frame includes: a second terminal that is disposed to surround terminals on a package plane and can be grounded; and a conductive member that covers molded resin and is electrically connected to the second terminal.
    Type: Grant
    Filed: December 9, 2014
    Date of Patent: August 27, 2019
    Assignee: Mitsubishi Electric Corporation
    Inventors: Hiroyuki Mizutani, Hidenori Ishibashi, Hideharu Yoshioka, Kiyoshi Ishida
  • Patent number: 10396040
    Abstract: An electronic package is provided, which includes: a carrier; a plurality of electronic elements disposed on the carrier; a bather frame disposed on the carrier and positioned between adjacent two of the electronic elements; an encapsulant formed on the carrier and encapsulating the electronic elements and the bather frame with a portion of the bather frame protruding from the encapsulant; and a shielding element disposed on the encapsulant and being in contact with the portion of the bather frame protruding from the encapsulant. Therefore, the electronic package has an electromagnetic interference (EMI) shielding effect improved. The present disclosure further provides a method for fabricating the electronic package.
    Type: Grant
    Filed: May 9, 2018
    Date of Patent: August 27, 2019
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Yue-Ying Jian, Wei-Ping Wang, Tsung-Ming Li, En-Li Lin, Kaun-I Cheng, Yu-De Chu
  • Patent number: 10388612
    Abstract: A semiconductor device has a first component. A modular interconnect structure is disposed adjacent to the first component. A first interconnect structure is formed over the first component and modular interconnect structure. A shielding layer is formed over the first component, modular interconnect structure, and first interconnect structure. The shielding layer provides protection for the enclosed semiconductor devices against EMI, RFI, or other inter-device interference, whether generated internally or from external semiconductor devices. The shielding layer is electrically connected to an external low-impedance ground point. A second component is disposed adjacent to the first component. The second component includes a passive device. An LC circuit includes the first component and second component. A semiconductor die is disposed adjacent to the first component. A conductive adhesive is disposed over the modular interconnect structure.
    Type: Grant
    Filed: July 31, 2017
    Date of Patent: August 20, 2019
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: Yaojian Lin, Byung Joon Han, Rajendra D. Pendse, Il Kwon Shim, Pandi C. Marimuthu, Won Kyoung Choi, Linda Pei Ee Chua
  • Patent number: 10373898
    Abstract: A semiconductor device includes a lead frame comprising a first terminal and a second terminal for grounding, a sealing resin which covers the lead frame, an exposed part which is a part of the second terminal and is exposed from the sealing resin and a conductive material which covers the surface of the sealing resin and contacts the second terminal at the exposed part.
    Type: Grant
    Filed: March 2, 2017
    Date of Patent: August 6, 2019
    Assignee: Mitsubishi Electric Corporation
    Inventors: Yuji Iwai, Katsumi Miyawaki
  • Patent number: 10375832
    Abstract: An apparatus including a die including a device side with contact points and lateral sidewalls defining a thickness of the die; a build-up carrier coupled to the die, the build-up carrier including a plurality of alternating layers of patterned conductive material and insulating material, wherein at least one of the layers of patterned conductive material is coupled to one of the contact points of the die; and an interference shield including a conductive material disposed on the die and a portion of the build-up carrier. The apparatus may be connected to a printed circuit board. A method including forming a build-up carrier adjacent a device side of a die including a plurality of alternating layers of patterned conductive material and insulating material; and forming a interference shield on a portion of the build-up carrier.
    Type: Grant
    Filed: December 1, 2015
    Date of Patent: August 6, 2019
    Assignee: Intel Corporation
    Inventors: Digvijay A. Raorane, Kemal Aygun, Daniel N. Sobieski, Drew W. Delaney
  • Patent number: 10373940
    Abstract: Provided is a stacked semiconductor package, which has various kinds of semiconductor chips with various sizes and is capable of miniaturization. The stacked semiconductor package includes a base substrate layer and a sub semiconductor package disposed on a top surface of the base substrate layer. The sub semiconductor package includes a plurality of sub semiconductor chips spaced apart from one another, and a sub mold layer filling spaces between the plurality of sub semiconductor chips to surround side surfaces of the plurality of sub semiconductor chips. The stacked semiconductor package includes at least one main semiconductor chip stacked on the sub semiconductor package, the at least one main semiconductor chip being electrically connected to the base substrate layer through first electrical connection members.
    Type: Grant
    Filed: November 8, 2017
    Date of Patent: August 6, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Dong-ha Lee
  • Patent number: 10361149
    Abstract: A device includes a passive-on-glass (POG) structure and an interface layer. The POG structure includes a passive component and at least one contact pad on a first surface of a glass substrate. The interface layer has a second surface on the first surface of the glass substrate such that the passive component and the at least one contact pad are located between the first surface of the glass substrate and the interface layer. The interface layer includes at least one land grid array (LGA) pad formed on a third surface of the interface layer, where the third surface of the interface layer is opposite the second surface of the interface layer. The interface layer also includes at least one via formed in the interface layer configured to electrically connect the at least one contact pad with the at least one LGA pad.
    Type: Grant
    Filed: August 10, 2016
    Date of Patent: July 23, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Chengjie Zuo, Mario Francisco Velez, Changhan Hobie Yun, David Francis Berdy, Daeik Daniel Kim, Jonghae Kim
  • Patent number: 10356914
    Abstract: A method of lamination of dielectric circuit materials is provided. The method includes preparing first and second circuit layers of dielectric materials, stacking the first and second circuit layers with circuit trace elements interposed between the first and second circuit layers and ultrasonically welding the second circuit layer onto the first circuit layer around the circuit trace elements.
    Type: Grant
    Filed: October 21, 2016
    Date of Patent: July 16, 2019
    Assignee: RAYTHEON COMPANY
    Inventors: Patrick J. Kocurek, Sankerlingam Rajendran
  • Patent number: 10354971
    Abstract: The invention concerns a method for producing a chip module having a carrier substrate and at least one chip arranged on the carrier substrate, as well as a contact conductor arrangement for connecting chip pads to contacts arranged on a contact face of the chip module, in which method the front face of the chip which is provided with the chip pads is secured to the carrier substrate and then the contact conductor arrangement is formed by structuring of a contact material layer of the carrier substrate.
    Type: Grant
    Filed: November 25, 2014
    Date of Patent: July 16, 2019
    Assignee: PAC TECH—PACKAGING TECHNOLOGIES GMBH
    Inventors: Ghassem Azdasht, Thorsten Teutsch, Ricardo Geelhaar
  • Patent number: 10354792
    Abstract: A transformer structure includes a circuit board, a current bearing plate, a transformer iron core, two wire windings and two plate windings. The circuit board is provided with a rectification filter circuit at least including a filter inductor, a filter capacitor and a rectification switch. The filter inductor is formed by a current guide plate on the circuit board and an inductor iron core sleeved on the current guide plate. The current bearing plate is stacked on the circuit board and electrically connected to the rectification filter circuit. The transformer iron core is on the circuit board. The two plate windings are plate materials, and are wound for at least one turn on the transformer iron core and fixed on the circuit board. The plate windings are electrically connected to the current guide plate and the current bearing plate to jointly withstand a current flowing through the transformer structure.
    Type: Grant
    Filed: October 23, 2017
    Date of Patent: July 16, 2019
    Assignee: SEA SONIC ELECTRONICS CO., LTD.
    Inventors: Sheng-Chien Chou, Chih-Sheng Chang
  • Patent number: 10347574
    Abstract: Integrated fan-out packages and methods of forming the same are disclosed. An integrated fan-out package includes a first semiconductor chip, a plurality of through integrated fan-out vias, an encapsulation layer and a redistribution layer structure. The first semiconductor chip includes a heat dissipation layer, and the heat dissipation layer covers at least 30 percent of a first surface of the first semiconductor chip. The through integrated fan-out vias are aside the first semiconductor chip. The encapsulation layer encapsulates the through integrated fan-out vias. The redistribution layer structure is at a first side of the first semiconductor chip and thermally connected to the heat dissipation layer of the first semiconductor chip.
    Type: Grant
    Filed: January 22, 2018
    Date of Patent: July 9, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shin-Puu Jeng, Dai-Jang Chen, Hsiang-Tai Lu, Hsien-Wen Liu, Chih-Hsien Lin, Shih-Ting Hung, Po-Yao Chuang
  • Patent number: 10347588
    Abstract: After forming a first electromagnetic radiation blocking layer over a front side of a device wafer, the device wafer is bonded to a handle substrate from the front side. A semiconductor substrate in the device wafer is thinned from its backside. Trenches are formed extending through the device wafer and the first electromagnetic radiation blocking layer such that the device wafer is singulated into semiconductor dies. A second electromagnetic radiation blocking layer portion is formed on a backside surface of and sidewalls surfaces of each of the semiconductor dies such that each of the semiconductor dies are fully encapsulated by the first and second electromagnetic radiation blocking layer portions.
    Type: Grant
    Filed: July 18, 2018
    Date of Patent: July 9, 2019
    Assignees: International Business Machines Corporation, JOHNSON & JOHNSON VISION CARE, INC.
    Inventors: Paul S. Andry, Cornelia K. Tsang, Adam Toner
  • Patent number: 10342131
    Abstract: The present disclosure relates to a PCB laminated structure, including a first substrate; a second substrate disposed to overlap with the first substrate on the top and bottom; and an interposer assembly provided between the first substrate and the second substrate to allow electromagnetic connection between the first and second substrates, wherein the interposer assembly includes a housing configured to form a closed region along a top surface circumference of the first substrate and a bottom surface circumference of the second substrate to support the first and second substrates; a signal via connected to the first and second substrates, respectively, to transmit electromagnetic signals between the first substrate and the second substrate; and a ground via connected to the housing to serve as a ground, and spaced a set distance from the signal via at one side of the signal via.
    Type: Grant
    Filed: July 20, 2018
    Date of Patent: July 2, 2019
    Assignee: LG ELECTRONICS INC.
    Inventors: Jaehyuk Kim, Kyungcheol Paek, Chaejoo Lim
  • Patent number: 10331602
    Abstract: A semiconductor integrated circuit includes a bus signal line and a test signal line arranged adjacent to the bus signal line. The semiconductor integrated circuit has a system mode, which is an operation mode that uses the bus signal line, and a scan mode, which is an operation mode that uses the test signal line. The semiconductor integrated circuit fixes the logic level of the test signal line adjacent to the bus signal line in the system mode that uses the bus signal line. The semiconductor integrated circuit fixes the logic level of the bus signal line adjacent to the test signal line in the scan mode that uses the test signal line.
    Type: Grant
    Filed: March 3, 2017
    Date of Patent: June 25, 2019
    Assignee: MEI FUJITSU SEMICONDUCTOR LIMITED
    Inventor: Seiji Goto
  • Patent number: 10331827
    Abstract: A method for performing simulation includes determining whether a model is available for a channel. A model for the channel is generated using signal attenuation parameters provided by a user in response to determining that the model is unavailable. The model includes crosstalk characteristics from crosstalk parameters provided by the user.
    Type: Grant
    Filed: June 27, 2013
    Date of Patent: June 25, 2019
    Assignee: Altera Corporation
    Inventors: Masashi Shimanouchi, Peng Li, Hsinho Wu
  • Patent number: 10325866
    Abstract: Electronic device package technology is disclosed. In one example, an electronic device package can include a bottom surface and a side surface extending from the bottom surface. The side surface can be oriented at a non-perpendicular angle relative to the bottom surface. In another example, an electronic device package can include a top planar surface having a first area, a bottom planar surface having a second area, and a side surface extending between the top surface and the bottom surface. The second area can be larger than the first area. In yet another example, an electronic device package can include a substrate defining a plane, an electronic component disposed on the substrate, and a layer of material disposed about a lateral side of the electronic component. The layer of material can be oriented at an angle of less than 90 degrees relative to the plane.
    Type: Grant
    Filed: December 19, 2017
    Date of Patent: June 18, 2019
    Assignee: Intel Corporation
    Inventors: Eric Li, Joshua Heppner, Rajendra Dias, Mitul Modi
  • Patent number: 10325859
    Abstract: Some features pertain to a stacked package apparatus that includes a shield at least partially surrounding the apparatus, a first substrate including a plurality of first pads, the plurality of first pads coupled to the shield, and a second substrate, the second substrate over the first substrate and coupled to the first substrate, the second substrate including a plurality of second pads, the plurality of second pads coupled to the shield.
    Type: Grant
    Filed: April 3, 2018
    Date of Patent: June 18, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Daeik Kim, Jie Fu, Manuel Aldrete
  • Patent number: 10320071
    Abstract: Aspects of this disclosure relate to methods of selectively shielded radio frequency modules. A radio frequency module can be provided with a radio frequency component and an antenna. A shielding layer can be formed over a portion of the radio frequency module such that the radio frequency component is shielded by the shielding layer and the antenna is unshielded by the shielding layer.
    Type: Grant
    Filed: April 18, 2017
    Date of Patent: June 11, 2019
    Assignee: Skyworks Solutions, Inc.
    Inventors: Hoang Mong Nguyen, Anthony James LoBianco, Gregory Edward Babcock, Darren Roger Frenette, George Khoury
  • Patent number: 10317512
    Abstract: In accordance with an embodiment, a packaged radio frequency (RF) circuit includes a radio frequency integrated circuit (RFIC) disposed on a substrate that has plurality of receiver circuits coupled to receive ports at a first edge of the RFIC, and a first transmit circuit coupled to a first transmit port at a second edge of the RFIC. The packaged RF circuit also includes a receive antenna system disposed on the package substrate adjacent to the first edge of the RFIC and a first transmit antenna disposed on the package substrate adjacent to the second edge of the RFIC and electrically coupled to the first transmit port of the RFIC. The receive antenna system includes a plurality of receive antenna elements that are each electrically coupled to a corresponding receive port.
    Type: Grant
    Filed: November 30, 2015
    Date of Patent: June 11, 2019
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Saverio Trotta, Ashutosh Baheti, Ismail Nasr, Ngoc-Hoa Huynh, Martin Richard Niessner
  • Patent number: 10319892
    Abstract: A light-emitting element mounting substrate includes a substrate including insulating resin, a first conductor layer formed on a first surface of the substrate and having an element mounting portion, a second conductor layer formed on a second surface of the substrate on the opposite side of the first surface, metal blocks formed such that the metal blocks are penetrating through the first conductor layer, the substrate and the second conductor layer and positioned in the element mounting portion of the first conductor layer, and through-hole conductors formed adjacent to the metal blocks respectively such that the through-hole conductors electrically connect the first conductor layer and the second conductor layer and that a diameter of each metal block is larger than a diameter of each through-hole conductor.
    Type: Grant
    Filed: February 12, 2018
    Date of Patent: June 11, 2019
    Assignee: IBIDEN CO., LTD.
    Inventors: Takahisa Hirasawa, Kiyotaka Tsukada
  • Patent number: 10305024
    Abstract: Provided is a magnetic shield having improved shielding properties from an external magnetic field. A magnetic shield MS1 has in-plane magnetization as remanent magnetization, and is adapted to generate a perpendicular component in the magnetization direction by applying a magnetic field in the perpendicular direction to the magnetic shield.
    Type: Grant
    Filed: October 30, 2017
    Date of Patent: May 28, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Tetsuhiro Suzuki
  • Patent number: 10292259
    Abstract: An electronic device disclosed herein includes a first conductor layer, a first nonconducting layer, and a second conductor layer in a stacked arrangement. A signal carrying conductive via is formed in the first nonconducting layer and extends between the first conductor layer and the second conductor layer. A shielding conductive via is formed in the first nonconducting layer, is not electrically coupled to the signal carrying conductive via, and substantially completely surrounds the signal carrying conductive via in spaced apart relation thereto.
    Type: Grant
    Filed: April 29, 2016
    Date of Patent: May 14, 2019
    Assignee: STMicroelectronics (Grenoble 2) SAS
    Inventors: Laurent Marechal, Richard Rembert, Jerome Lopez
  • Patent number: 10290609
    Abstract: Some embodiments of the present disclosure provide a semiconductor device. The semiconductor device includes: a bottom package; wherein an area of a contact surface between the conductor and the through via substantially equals a cross-sectional area of the through via, and the bottom package includes: a molding compound; a through via penetrating through the molding compound; a die molded in the molding compound; and a conductor on the through via. An associated method of manufacturing the semiconductor device is also disclosed.
    Type: Grant
    Filed: March 13, 2017
    Date of Patent: May 14, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Jing-Cheng Lin, Ying-Ching Shih, Pu Wang, Chen-Hua Yu
  • Patent number: 10290585
    Abstract: A method for fabricating a radio-frequency (RF) module is disclosed, the method including forming or providing a first assembly that includes a packaging substrate and an RF component mounted thereon, the first assembly further including one or more shielding-wirebonds formed relative to the RF component, and forming an overmold over the packaging substrate to substantially encapsulate the RF component and the one or more shielding-wirebonds, the overmold formed by compression molding that includes reducing a volume of melted resin in a direction having a component perpendicular to a plane defined by the packaging substrate.
    Type: Grant
    Filed: May 26, 2016
    Date of Patent: May 14, 2019
    Assignee: Skyworks Solutions, Inc.
    Inventors: Hoang Mong Nguyen, Luis Eduardo Herrera, Sergio Joaquin Gonzalez Flores, Matthew Sean Read, Anthony James Lobianco, Heliodoro Osuna
  • Patent number: 10276386
    Abstract: Signal relay board for power semiconductor modules enabling electrical connection between power semiconductor modules and a drive unit driving same. A first wire layer, a second wire layer, a third wire layer, and a fourth wire layer of a multiphase wire portion are assigned with a first control wire layer serving as a path to provide a control signal to a first semiconductor device of the modules, a first ground wire layer serving as a path to provide a ground potential to a low potential side terminal of the first semiconductor device of the semiconductor modules, a second control wire layer serving as a path to provide a control signal to a second semiconductor device of the modules, and a second ground wire layer serving as a path to provide a ground potential to the second semiconductor device of the modules.
    Type: Grant
    Filed: June 29, 2017
    Date of Patent: April 30, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Ryohei Makino, Motoyoshi Kubouchi, Kiyoshi Takahashi
  • Patent number: 10269724
    Abstract: A method of manufacturing a semiconductor package that includes a package substrate preparing step of preparing a package substrate where semiconductor devices are placed in respective areas demarcated by a plurality of grid-like projected dicing lines and sealed by a layer of sealing resin; a protective film covering step of coating external connection electrodes with a liquid resin thereby to form a protective film thereon; a dividing step of cutting the package substrate along the projected dicing lines with a cutting blade; an electromagnetic wave shield film forming step of applying a metal film to an upper surface of the sealing resin on each of the semiconductor packages and side surfaces of each of the semiconductor packages, thereby forming an electromagnetic wave shield film for blocking electromagnetic waves; and a protective film removing step of removing the protective film.
    Type: Grant
    Filed: February 13, 2017
    Date of Patent: April 23, 2019
    Assignee: DISCO CORPORATION
    Inventor: Katsuhiko Suzuki
  • Patent number: 10269726
    Abstract: Disclosed herein is an electronic circuit package includes a substrate having a power supply pattern, a first electronic component mounted on a first region of a front surface of the substrate, a mold resin that covers the front surface of the substrate so as to embed the first electronic component therein, and a laminated film covering an upper surface of the mold resin, the laminated film including a magnetic film and a first metal film. The first metal film is connected to the power supply pattern. The magnetic film is selectively thick on the first region.
    Type: Grant
    Filed: July 5, 2017
    Date of Patent: April 23, 2019
    Assignee: TDK CORPORATION
    Inventors: Kenichi Kawabata, Toshio Hayakawa, Toshiro Okubo
  • Patent number: 10256193
    Abstract: A semiconductor device includes a package substrate, a semiconductor die attached to a first major surface of the package substrate, and a plurality of wire bonds attached between the semiconductor die and the first major surface of the package substrate. The device further includes a conductive plate over the semiconductor die, plurality of wire bonds, and package substrate wherein a first major surface of the conductive plate faces the first major surface of the package substrate. The device further includes a plurality of conductive extensions attached to the first major surface of the conductive plate, wherein each conductive extension extends from the first major surface of the conductive plate and between two adjacent wire bonds of the plurality of wire bonds.
    Type: Grant
    Filed: November 29, 2017
    Date of Patent: April 9, 2019
    Assignee: NXP USA, Inc.
    Inventors: James S. Golab, Robert Joseph Wenzel, Stanley Andrew Cejka
  • Patent number: 10256200
    Abstract: An electronic component package and a method of manufacturing the same are provided. The electronic component package includes a frame having a through-hole, an electronic component disposed in the through-hole of the frame, and a redistribution part disposed at one side of the frame and the electronic component. One or more first wiring layers of the frame are electrically connected to the electronic component through the redistribution part.
    Type: Grant
    Filed: January 22, 2018
    Date of Patent: April 9, 2019
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Dae Hyun Park, Han Kim, Kang Heon Hur, Young Gwan Ko, Jung Ho Shim
  • Patent number: 10242887
    Abstract: A semiconductor device includes a carrier and a plurality of semiconductor die disposed over the carrier. An encapsulant is deposited over the semiconductor die. A composite layer is formed over the encapsulant to form a panel. The carrier is removed. A conductive layer is formed over the panel. An insulating layer is formed over the conductive layer. The carrier includes a glass layer, a second composite layer formed over the glass layer, and an interface layer formed over the glass layer. The composite layer and encapsulant are selected to tune a coefficient of thermal expansion of the panel. The panel includes panel blocks comprising an opening separating the panel blocks. The encapsulant or insulating material is deposited in the opening. A plurality of support members are disposed around the panel blocks. An interconnect structure is formed over the conductive layer.
    Type: Grant
    Filed: August 10, 2017
    Date of Patent: March 26, 2019
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventor: Yaojian Lin
  • Patent number: 10242953
    Abstract: Embodiments of the present invention relate to a semiconductor package with a metal-plated shield. Surfaces of molding compound are roughened by an abrasion process such that the surfaces have an unnatural surface roughness that is rougher than a natural surface roughness. The roughened surfaces provide better adhesion of the metal-plated shield to the roughened surfaces than to untreated surfaces (e.g., surfaces with the natural surface roughness). A catalyst material can be deposited on the roughened surfaces of the molding compound before a metal layer is coated on the roughened surfaces of the molding compound to speed up the time for the metal layer to adhere to the roughened surfaces of the molding compound. The metal-plated shield can include plurality of metal layers plated on top of each other.
    Type: Grant
    Filed: May 27, 2016
    Date of Patent: March 26, 2019
    Assignee: Utac Headquarters PTE. Ltd
    Inventors: Suebphong Yenrudee, Chanapat Kongpoung, Sant Hongsongkiat, Siriwanna Ounkaew, Chatchawan Injan, Saravuth Sirinorakul
  • Patent number: 10242716
    Abstract: A semiconductor device includes a substrate, a nonvolatile semiconductor memory disposed on a surface of the substrate, and a controller disposed on a surface of the controller. The substrate has a slit on an edge on which interface connection terminals are formed, a ground pattern, first and second wiring patterns that are electrically connected to the ground pattern and extend in a direction in which the slit extends, and a through hole that is formed between the first and second wiring patterns and is large enough along a dimension between the first and second wiring patterns to span substantially all of the spacing between the first and second wiring patterns.
    Type: Grant
    Filed: March 2, 2017
    Date of Patent: March 26, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Naoki Kimura
  • Patent number: 10236262
    Abstract: Embodiments of the invention provide a system for protecting an integrated circuit (IC) device from attacks, the IC device (100) comprising a substrate (102) having a front surface (20) and a back surface (21), the IC device further comprising a front side part (101) arranged on the front surface of the substrate (102) and stacked layers, at least one of said layers comprising a data layer comprising wire carrying data, the front side part having a front surface (13). The system comprises an internal shield (12) arranged in a layer located below said data layer and a verification circuit configured to check the integrity of at least one portion of the internal shield.
    Type: Grant
    Filed: December 28, 2016
    Date of Patent: March 19, 2019
    Inventors: Sylvain Guilley, Thibault Porteboeuf, Jean-Luc Danger
  • Patent number: 10236234
    Abstract: A chip on film package includes a base film, a patterned circuit layer, a solder resist layer, a chip and a graphite sheet. The base film includes a first surface and a mounting region located on the first surface. The patterned circuit layer is disposed on the first surface. The solder resist layer partially covers the patterned circuit layer. The chip is disposed on the mounting region and electrically connected to the patterned circuit layer. The graphite sheet covers at least a part of the solder resist layer, wherein an outer edge of the graphite sheet is substantially aligned with an outer edge of the solder resist layer.
    Type: Grant
    Filed: February 23, 2018
    Date of Patent: March 19, 2019
    Assignee: Novatek Microelectronics Corp.
    Inventors: Wen-Ching Huang, Chien-Chen Ko
  • Patent number: 10224290
    Abstract: Electromagnetically shielded electronic device technology is disclosed. In an example, a method of making an electronic device package can comprise providing a substrate having a conductor pad and an electronic component. The method can also comprise forming a conformal insulating layer on the substrate and electronic component. The conformal insulating layer conforms to the electronic component. The method can further comprise exposing the conductor pad. In addition, the method can comprise forming an electrically conductive electromagnetic interference (EMI) layer on the insulating layer and in contact with the conductor pad.
    Type: Grant
    Filed: December 24, 2015
    Date of Patent: March 5, 2019
    Assignee: Intel Corporation
    Inventors: Rajendra Dias, Takashi Kumamoto, Yoshishiro Tomita, Mitul Modi, Joshua Heppner, Eric Li
  • Patent number: 10212804
    Abstract: An electronic device may include a circuit board, an IC carried by the circuit board, and an RF shield above the IC. The circuit board may include a dielectric layer, and a thermally conductive body in the dielectric layer. The thermally conductive body may have a first heat transfer surface coupled to the IC. The thermally conductive body may extend laterally within the dielectric layer and outward past the RF shield and defining a second heat transfer surface. The electronic device may include a heat sink coupled to the second heat transfer surface.
    Type: Grant
    Filed: January 16, 2017
    Date of Patent: February 19, 2019
    Assignee: HARRIS GLOBAL COMMUNICATIONS, INC.
    Inventors: John R. McIntyre, Kevin Dell, Timothy W. Burks
  • Patent number: 10204661
    Abstract: A semiconductor device includes a printed circuit board having a first surface and a second surface on a side opposite to the first surface. First pads are on the first surface of the printed circuit board. An interface part is mounted on the printed circuit board via the first pads and is configured to transfer a signal between the interface part and a host device. Second pads are also on the first surface and insulated from the interface part. A semiconductor memory and a controller are mounted on the first surface. First solder balls electrically connect the first pads and the controller. Second solder balls electrical connect the second pads and the controller. A plurality of third pads are disposed on the second surface and electrically connected to the second pads allowing direct connections to the controller and memory via the second pads.
    Type: Grant
    Filed: March 2, 2015
    Date of Patent: February 12, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Manabu Matsumoto, Isao Ozawa
  • Patent number: 10204869
    Abstract: An integrated circuit package includes at least one first chip mounted in a first region of a mounting surface of a printed circuit board, a molding unit covering the mounting surface and surrounding the at least one first chip, an electromagnetic shielding film covering a surface of the molding unit and surrounding the at least one first chip, and a second chip mounted in a second region of the mounting surface. The second chip is exposed outside the electromagnetic shielding film and is spaced apart from the printed circuit board, with the molding unit being between the second chip and the printed circuit board.
    Type: Grant
    Filed: April 10, 2018
    Date of Patent: February 12, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Chan-hee Jeong, Soo-jae Park, Young-hoon Kim, In-ku Kang, Hee-yeol Kim