With Shielding (e.g., Electrical Or Magnetic Shielding, Or From Electromagnetic Radiation Or Charged Particles) Patents (Class 257/659)
  • Patent number: 10923532
    Abstract: According to one embodiment, a magnetic memory device includes a semiconductor substrate, a first lower area provided on the semiconductor substrate, and including a plurality of magnetoresistive effect elements, a second lower area provided on the semiconductor substrate, and being adjacent to the first lower area, a first upper area provided above the first lower area, and including a first material film formed of an insulating material or a semiconductor material, and a second upper area provided above the second lower area, being adjacent to the first upper area, and including a second material film formed of an insulating material different from a material of the first material film.
    Type: Grant
    Filed: September 16, 2016
    Date of Patent: February 16, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Akiyuki Murayama
  • Patent number: 10923434
    Abstract: A semiconductor package may include a chip disposed on a substrate, a conductive structure disposed on the substrate to include a conductive structure frame including a side surface facing at least one side surface of the chip and to include conductive structure fingers extending from the conductive structure frame toward an edge of the substrate, and an electromagnetic interference (EMI) shielding layer covering the chip and the conductive structure and contacting a side surface of an end of one or more of the conductive structure fingers.
    Type: Grant
    Filed: November 7, 2018
    Date of Patent: February 16, 2021
    Assignee: SK hynix Inc.
    Inventors: Bok Kyu Choi, Juil Eom, Sang Joon Lim
  • Patent number: 10910286
    Abstract: Wafer-level system-in-package packaging method and package structure are provided. The method includes: forming a bonding structure, where the bonding structure includes a device wafer and a plurality of chips bonded to the device wafer, where the plurality of chips contains one or more first chips to-be-shielded; forming an encapsulation layer covering the plurality of chips; forming a trench in the encapsulation layer to surround each first chip of the one or more first chips; and forming a conductive material in the trench and on the encapsulation layer, where the conductive material includes a shielding housing, the shielding housing including a conductive sidewall formed in the trench and a conductive layer formed on a portion of the encapsulation layer above the each first chip and connected with the conductive sidewall.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: February 2, 2021
    Assignee: Ningbo Semiconductor International Corporation
    Inventors: Hailong Luo, Clifford Ian Drowley
  • Patent number: 10910293
    Abstract: A leadframe includes a die pad having a plurality of sides which collectively define the rectangular die pad area including at least two securing sides that include a linear portion with a cantilever interrupting the linear portion. The die pad has a top surface defining a top plane and a bottom surface defining a bottom plane. Lead terminals are beyond the die pad. The cantilevers have a fixed end and a free end opposite the fixed ends that enables flexing or bending responsive to a received force. The free ends include a distal end with an electronic component locking feature. The fixed ends are positioned beyond the die pad area, and the electronic component locking feature extends inward over the rectangular die pad area for providing mechanical support and for securing the electronic component.
    Type: Grant
    Filed: October 28, 2019
    Date of Patent: February 2, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: ChienHao Wang, Bob Lee, YuhHarng Chien
  • Patent number: 10896880
    Abstract: A semiconductor package includes a substrate. A high-frequency chip and a circuit component susceptible to high-frequency interference are disposed on a top surface of the substrate. A first ground ring is disposed on the substrate around the high-frequency chip. A first metal-post reinforced glue wall is disposed on the first ground ring to surround the high-frequency chip. A second ground ring is disposed on the top of the substrate around the circuit component. A second metal-post reinforced glue wall is disposed on the second ground ring to surround the circuit component. Mold-flow channels are disposed in the first and second metal-post reinforced glue walls. A molding compound covers at least the high-frequency chip and the circuit component. A conductive layer is disposed on the molding compound and is coupled to the first metal-post reinforced glue wall and/or the second metal-post reinforced glue wall.
    Type: Grant
    Filed: December 17, 2019
    Date of Patent: January 19, 2021
    Inventors: Shiann-Tsong Tsai, Hsien-Chou Tsai, Hsien-Wei Tsai, Yen-Mei Tsai Huang
  • Patent number: 10892238
    Abstract: A circuit structure including a first signal line and a second signal line is provided. The first signal line includes a first line segment, a first ball grid array pad, and a first through hole disposed between the first line segment and the first ball grid array pad. The second signal line includes a second line segment, a second ball grid array pad, and a second through hole disposed between the second line segment and the second ball grid array pad. In a plan view, a line connecting the center of the first ball grid array pad and the center of the second ball grid array pad has a first distance, a line connecting the center of the first through hole and the center of the second through hole has a second distance, and the first distance is less than the second distance. A chip package is also provided.
    Type: Grant
    Filed: May 16, 2019
    Date of Patent: January 12, 2021
    Assignees: Global Unichip Corporation, Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yuan-Hung Lin, Sheng-Fan Yang, Yu-Cheng Sun
  • Patent number: 10892099
    Abstract: A fringe capacitor with a shielded the top capacitor plate is formed in multiple interconnect layers to include a first plate having a first defined finger structure located in one or more middle interconnect layers to form a top capacitor plate; a set of second plates located in the middle interconnect layer(s) and bottom and top interconnect layers that are connected to form a bottom capacitor plate which includes a second plate in the middle interconnect layer(s) having defined finger structures that are interleaved with the first defined finger structure of the top capacitor plate to vertically and horizontally sandwich the top capacitor plate; and a set of shield layers formed to surround and shield the top capacitor plate on lateral sides, where the set of shield layers are connected to a reference voltage, thereby shielding the top capacitor plate from parasitic capacitance.
    Type: Grant
    Filed: December 18, 2017
    Date of Patent: January 12, 2021
    Assignee: NXP USA, Inc.
    Inventors: Mohammad N. Kabir, Paul L. Hunt, Rakesh Shiwale, Brandt Braswell
  • Patent number: 10867911
    Abstract: A method includes forming a coil over a carrier, encapsulating the coil in an encapsulating material, planarizing a top surface of the encapsulating material until the coil is exposed, forming at least one dielectric layer over the encapsulating material and the coil, and forming a plurality of redistribution lines extending into the at least one dielectric layer. The plurality of redistribution lines is electrically coupled to the coil.
    Type: Grant
    Filed: July 25, 2018
    Date of Patent: December 15, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Tsung-Hsien Chiang, Hao-Yi Tsai, Hung-Yi Kuo, Ming Hung Tseng
  • Patent number: 10867879
    Abstract: A device package includes a first die directly bonded to a second die at an interface, wherein the interface comprises a conductor-to-conductor bond. The device package further includes an encapsulant surrounding the first die and the second die and a plurality of through vias extending through the encapsulant. The plurality of through vias are disposed adjacent the first die and the second die. The device package further includes a plurality of thermal vias extending through the encapsulant and a redistribution structure electrically connected to the first die, the second die, and the plurality of through vias. The plurality of thermal vias is disposed on a surface of the second die and adjacent the first die.
    Type: Grant
    Filed: November 9, 2018
    Date of Patent: December 15, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Sung-Feng Yeh, Ming-Fa Chen, Hsien-Wei Chen, Tzuan-Horng Liu
  • Patent number: 10854556
    Abstract: A semiconductor package device includes a substrate, a die, a package body, a shielding layer, a solder mask layer, an insulating film and an interconnection element. The die is disposed on a top surface of the substrate. The package body is disposed on the top surface of the substrate to cover the die. The shielding layer is disposed on the package body and is electrically connected to a grounding element of the substrate. The solder mask layer is disposed on a bottom surface of the substrate. The insulating film is disposed on the solder mask layer. The interconnection element is disposed on the bottom surface of the substrate. A first portion of the interconnection element is covered by the insulating film, and a second portion of the interconnection element is exposed from the insulating film.
    Type: Grant
    Filed: October 12, 2016
    Date of Patent: December 1, 2020
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING KOREA, INC.
    Inventors: Kyungsic Yu, Yangwon Lee, Seokbong Kim
  • Patent number: 10854557
    Abstract: A semiconductor device includes: an island that is formed by a metallic layer including a single metallic layer or a plurality of different metallic layers; a semiconductor chip provided upon an upper surface of the island, and having a pair of side portions mutually opposing each other; a plurality of signal terminals disposed at an external periphery of at least the pair of side portions of the semiconductor chip, and formed by the metallic layer; a grounding terminal disposed at an external periphery of the plurality of signal terminals, and formed by the metallic layer; electrically conductive connection members that are connected between each of a plurality of electrodes of the semiconductor chip and each of the plurality of signal terminals; sealing resin that seals the island, the semiconductor chip, the electrically conductive connection members, the plurality of signal terminals, and the grounding terminal, so that a lower surface of the island, lower surfaces of the plurality of signal terminals, an
    Type: Grant
    Filed: May 19, 2016
    Date of Patent: December 1, 2020
    Assignees: AOI Electronics Co., Ltd., Mitsubishi Electric Corporation
    Inventors: Shuichi Sawamoto, Koji Iwabu, Katsuhiro Takao, Akihito Hirai, Joichi Saito
  • Patent number: 10840188
    Abstract: A semiconductor device includes a substrate having a first surface, a second surface opposite to the first surface, and a side surface extending between the first surface and the second surface; a pad electrode provided on the first surface of the substrate; an internal wiring provided in the substrate, and electrically connected to the pad electrode; a first wiring provided in the substrate, and exposed from the substrate at the side surface; an insulator provided between the first wiring and the internal wiring so as to separate the first wiring from the internal wiring; a semiconductor chip provided on the substrate, and electrically connected to the pad electrode; and a resin covering the semiconductor chip.
    Type: Grant
    Filed: February 25, 2019
    Date of Patent: November 17, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Atsushi Kataoka
  • Patent number: 10825781
    Abstract: A packaged semiconductor device has a conductive film that covers a first major surface and surrounding side surfaces of an integrated circuit die. The conductive film provides five-sided shielding of the integrated circuit die. A metal heat sink may be attached to an exposed major surface of the conductive film for dissipating heat generated by the die.
    Type: Grant
    Filed: August 1, 2018
    Date of Patent: November 3, 2020
    Assignee: NXP B.V.
    Inventors: Chia Hao Kang, Chung Hsiung Ho
  • Patent number: 10825782
    Abstract: Semiconductor devices with a conformal coating in contact with a ground plane at a bottom side of the semiconductor devices and associated systems and methods are disclosed herein. In one embodiment, a semiconductor device includes a semiconductor die coupled to a first surface of a package substrate. The semiconductor device can also include a molded material covering at least a portion of the package substrate and the semiconductor die. The semiconductor device can also include a ground plane in the package substrate and exposed through an opening in a second surface of the package substrate opposite the first surface. The semiconductor device can also include a conformal coating coupled to the ground plane through the opening that can shield the semiconductor device from electromagnetic interference.
    Type: Grant
    Filed: December 27, 2018
    Date of Patent: November 3, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Avishesh Dhakal, Gary A. Monroe
  • Patent number: 10818608
    Abstract: Disclosed microelectronic assemblies employ an integrated interposer cage to reduce electromagnetic interference with (and from) high-frequency components. One illustrative embodiment includes: at least one IC die having drive cores for a plurality of oscillators, the IC die attached in a flip-chip configuration to a (interposer) substrate, the substrate having: multiple inductors electrically coupled to said drive cores and each enclosed within a corresponding conductive cage integrated into the substrate to reduce mutual coupling between the inductors and noise coupled through substrate.
    Type: Grant
    Filed: April 10, 2017
    Date of Patent: October 27, 2020
    Assignee: Credo Technology Group Limited
    Inventors: Xike Liu, Yifei Dai
  • Patent number: 10818609
    Abstract: The present disclosure provides a package structure, including a semiconductor chip having a magnetic device, wherein the semiconductor chip includes a first surface perpendicular to a thickness direction of the semiconductor chip, a second surface opposite to the first surface, and a third surface connecting the first surface and the second surface, and a first magnetic field shielding at least partially surrounding the third surface.
    Type: Grant
    Filed: July 13, 2018
    Date of Patent: October 27, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Harry-Hak-Lay Chuang, Chia-Hsiang Chen, Meng-Chun Shih, Ching-Huang Wang, Tien-Wei Chiang
  • Patent number: 10811609
    Abstract: A manufacturing method of a display device includes a layering process including steps of forming a PI layer on a carrier glass substrate, forming a base coat layer to cover the PI layer, and forming a TFT layer and a light-emitting element layer on the base coat layer, an exposing process including a step of exposing an end surface of the PI layer, and a peeling process including a step of peeling the carrier glass substrate from the PI layer by irradiating the lower face of the PI layer with a laser light beam.
    Type: Grant
    Filed: September 6, 2017
    Date of Patent: October 20, 2020
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Mayuko Sakamoto, Tetsunori Tanaka
  • Patent number: 10804247
    Abstract: A chip package structure is provided. The chip package structure includes a chip structure. The chip package structure includes a first ground bump below the chip structure. The chip package structure includes a conductive shielding film disposed over the chip structure and extending onto the first ground bump. The conductive shielding film is electrically connected to the first ground bump.
    Type: Grant
    Filed: October 15, 2018
    Date of Patent: October 13, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chen-Hua Yu, An-Jhih Su, Jing-Cheng Lin, Po-Hao Tsai
  • Patent number: 10804119
    Abstract: A semiconductor device has a semiconductor die or component, including an IPD, disposed over an attach area of a penetrable film layer with a portion of the semiconductor die or component embedded in the penetrable film layer. A conductive layer is formed over a portion of the film layer within the attach area and over a portion of the film layer outside the attach area. An encapsulant is deposited over the film layer, conductive layer, and semiconductor die or component. The conductive layer extends outside the encapsulant. An insulating material can be disposed under the semiconductor die or component. A shielding layer is formed over the encapsulant. The shielding layer is electrically connected to the conductive layer. The penetrable film layer is removed. The semiconductor die or component disposed over the film layer and covered by the encapsulant and shielding layer form an SIP module without a substrate.
    Type: Grant
    Filed: March 15, 2017
    Date of Patent: October 13, 2020
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: OhHan Kim, KyungHwan Kim, WoonJae Beak, HunTeak Lee, InSang Yoon
  • Patent number: 10797375
    Abstract: A wafer level package with at least one integrated antenna element includes a chip layer with at least one chip, a dielectric layer as well as an antenna layer arranged between the chip layer and the dielectric layer.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: October 6, 2020
    Assignee: Fraunhofer-Gesellschaft zur Foerderung der angewandten Forschung e.V.
    Inventors: Ivan Ndip, Tanja Braun
  • Patent number: 10797001
    Abstract: Three-dimensional integrated circuit (3DIC) structures are disclosed. A 3DIC structure includes a first die and a second die bonded to the first die. The first die includes a first integrated circuit region and a first seal ring region around the first integrated circuit region, and has a first alignment mark within the first integrated circuit region. The second die includes a second integrated circuit region and a second seal ring region around the second integrated circuit region, and has a second alignment mark within the second seal ring region and corresponding to the first alignment mark.
    Type: Grant
    Filed: October 15, 2019
    Date of Patent: October 6, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jie Chen, Hsien-Wei Chen, Ying-Ju Chen
  • Patent number: 10797642
    Abstract: Semiconductor devices and methods relating to the semiconductor devices are provided. A semiconductor device includes a resonant clock circuit. The semiconductor device further includes an inductor. The semiconductor device also includes a magnetic layer formed of a magnetic material disposed in between a portion of the resonant clock circuit and the inductor. Clock signals of the resonant clock circuit are utilized by the magnetic layer.
    Type: Grant
    Filed: December 14, 2017
    Date of Patent: October 6, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Bruce B. Doris, Rajiv V. Joshi, Naigang Wang
  • Patent number: 10790268
    Abstract: A semiconductor device has a first substrate and a semiconductor die disposed over the first substrate. A conductive pillar is formed on the first substrate. A first encapsulant is deposited over the first substrate and semiconductor die after forming the conductive pillar. A groove is formed in the first encapsulant around the conductive pillar. A first passive device is disposed over a second substrate. A second encapsulant is deposited over the first passive device and second substrate. The first substrate is mounted over the second substrate. A shielding layer is formed over the second encapsulant. A second passive device can be mounted over the second substrate opposite the first passive device and outside a footprint of the first substrate.
    Type: Grant
    Filed: March 17, 2020
    Date of Patent: September 29, 2020
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: DeokKyung Yang, HunTeak Lee, HeeSoo Lee
  • Patent number: 10790244
    Abstract: In an embodiment, a device includes: a conductive shield on a first dielectric layer; a second dielectric layer on the first dielectric layer and the conductive shield, the first and second dielectric layers surrounding the conductive shield, the second dielectric layer including: a first portion disposed along an outer periphery of the conductive shield; a second portion extending through a center region of the conductive shield; and a third portion extending through a channel region of the conductive shield, the third portion connecting the first portion to the second portion; a coil on the second dielectric layer, the coil disposed over the conductive shield; an integrated circuit die on the second dielectric layer, the integrated circuit die disposed outside of the coil; and an encapsulant surrounding the coil and the integrated circuit die, top surfaces of the encapsulant, the integrated circuit die, and the coil being level.
    Type: Grant
    Filed: January 26, 2018
    Date of Patent: September 29, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tzu-Sung Huang, Chen-Hua Yu, Hung-Yi Kuo, Hao-Yi Tsai, Ming Hung Tseng
  • Patent number: 10777599
    Abstract: According to one embodiment, the interconnect layers include a first interconnect layer and a second interconnect layer. The second interconnect layer is provided on the first interconnect layer. The insulating layer is provided between the plurality of interconnect layers. The barrier metal film is provided at a surface of the first interconnect layer but not provided at a surface of the second interconnect layer. The plugs connect the first interconnect layer and the second interconnect layer, and are provided between the first interconnect layer and the second interconnect layer. The plugs are arranged at a spacing of 200 ?m or less along a longitudinal direction of the second interconnect layer.
    Type: Grant
    Filed: February 13, 2019
    Date of Patent: September 15, 2020
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventors: Hayato Nasu, Yasushi Itabashi
  • Patent number: 10777461
    Abstract: A method of manufacturing chip package is disclosed. The method includes steps of providing a wafer with an upper surface and a lower surface opposite thereto, in which a plurality of conductive pads are disposed on the upper surface; forming a plurality of conductive bumps on the corresponding conductive pads; thinning the wafer from the lower surface towards the upper surface; forming an insulating layer under the lower surface; etching the upper surface of the wafer to form a plurality of trenches exposing the insulating layer; forming a passivation layer covering an inner wall of each of the trenches; and dicing the passivation layer and the insulating layer along each of the trenches to form a plurality of chip packages.
    Type: Grant
    Filed: May 6, 2019
    Date of Patent: September 15, 2020
    Assignee: COMCHIP TECHNOLOGY CO., LTD.
    Inventors: Chien-Chih Lai, Hung-Wen Lin
  • Patent number: 10766768
    Abstract: A semiconductor layer having an opening and a MEMS resonator formed in the opening is disposed between first and second substrates to encapsulate the MEMS resonator. An electrical contact that extends from the opening to an exterior of the MEMS device is formed at least in part within the semiconductor layer and at least in part within the first substrate.
    Type: Grant
    Filed: September 10, 2019
    Date of Patent: September 8, 2020
    Assignee: SiTime Corporation
    Inventors: Aaron Partridge, Markus Lutz, Pavan Gupta
  • Patent number: 10770403
    Abstract: A fan-out semiconductor package includes a connection member including an insulating layer and a redistribution layer, a semiconductor chip disposed on the connection member, an encapsulant encapsulating the semiconductor chip, and an electromagnetic radiation blocking layer disposed above the semiconductor chip and including a base layer in which a plurality of degassing holes are formed and a porous blocking portion filled in the plurality of degassing holes.
    Type: Grant
    Filed: November 21, 2018
    Date of Patent: September 8, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Mi Ja Han, Han Kim, Seong Chan Park
  • Patent number: 10771875
    Abstract: In at least one embodiment, a micro-electro-mechanical systems (MEMS) microphone assembly is provided. The assembly includes an enclosure, a MEMS transducer, and a plurality of substrate layers. The single MEMS transducer is positioned within the enclosure. The plurality of substrate layers support the single MEMS transducer. The plurality of substrate layers define a first transmission mechanism to enable a first side of the single MEMS transducer to receive an audio input signal and a second transmission mechanism to enable a second side of the single MEMS transducer to receive the audio input signal.
    Type: Grant
    Filed: December 10, 2018
    Date of Patent: September 8, 2020
    Assignee: Harman International Industries, Incorporated
    Inventors: John C. Baumhauer, Jr., Fengyuan Li, Larry A. Marcus, Alan D. Michel, Marc Reese
  • Patent number: 10770418
    Abstract: A fan-out semiconductor package includes: a first connection member having a through-hole; a semiconductor chip disposed in the through-hole and having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface; an encapsulant encapsulating at least portions of the first connection member and the inactive surface of the semiconductor chip; a second connection member disposed on the first connection member and the active surface of the semiconductor chip; a resin layer disposed on the encapsulant; and a rear redistribution layer embedded in the encapsulant so that one surface thereof is exposed by the encapsulant, wherein the resin layer covers at least portions of the exposed one surface of the rear redistribution layer, and the rear redistribution layer is electrically connected to the redistribution layer of the first connection member through connection members formed in first openings penetrating through the resin layer and the encapsulant.
    Type: Grant
    Filed: March 9, 2018
    Date of Patent: September 8, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Da Hee Kim, Young Gwan Ko
  • Patent number: 10765046
    Abstract: Disclosed are EMI shielded packages, electronic device packages, and related methods. EMI shielded packages are formed by applying an insulating material to a first side of a substrate strip, separating the substrate strip into segments, adhering the insulating material of the segments to a solid conductor, applying a conductive paste around lateral sides of the segments, curing the conductive paste, and cutting through the conductive paste and the solid conductor to form the EMI packages. An electronic device package includes a substrate including electronic circuitry, an EMI shield, and an insulating material insulating the substrate from the EMI shield. The EMI shield includes a solid conductor adhered to the insulating material, and a cured conductive paste at least partially surrounding a lateral edge of the substrate. The cured conductive paste electrically connects the solid conductor to a conductive terminal in a lateral side of the substrate.
    Type: Grant
    Filed: March 1, 2019
    Date of Patent: September 1, 2020
    Assignee: Intel Corporation
    Inventor: Robert Sankman
  • Patent number: 10756033
    Abstract: Wireless modules having a semiconductor package attached to an antenna package and cap package are disclosed. The semiconductor package may have one or more electronic components disposed thereon. The antenna package may be communicatively coupled to the semiconductor package using by one or more coupling pads. The antenna package may further have one or more radiating elements for transmitting and or receiving wireless signals. The cap package may also be attached to the semiconductor package on a side opposing the side on which the antenna package is disposed. The cap package may provide routing and/or additional antenna elements. The cap package may also allow for thermal grease to be dispensed therethrough. The antenna package, the cap package, and the semiconductor package may have dissimilar number of interconnect layers and/or dissimilar materials of construct.
    Type: Grant
    Filed: June 3, 2016
    Date of Patent: August 25, 2020
    Assignee: Intel IP Corporation
    Inventors: Sidharth Dalmia, Igal Yehuda Kushnir
  • Patent number: 10741528
    Abstract: A semiconductor device includes a first die; a first metal enclosure directly contacting and vertically extending below the first die, wherein the first metal enclosure peripherally encircles a first enclosed space; a second die directly contacting the first metal enclosure opposite the first die; a second metal enclosure directly contacting and vertically extending below the second die, wherein the second metal enclosure peripherally encircles a second enclosed space; and an enclosure connection mechanism directly contacting the first metal enclosure and the second metal enclosure for electrically coupling the first metal enclosure and the second metal enclosure.
    Type: Grant
    Filed: May 20, 2019
    Date of Patent: August 11, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Wei Zhou, Bret K. Street
  • Patent number: 10741502
    Abstract: Disclosed herein is a multilayer circuit board that includes a plurality of conductor layers laminated with insulating layers interposed therebetween. The plurality of conductor layers include a first conductor layer, a second conductor layer, and a first shield layer disposed between the first and second conductor layers. The first shield layer is smaller in conductor thickness than the first and second conductor layers and is connected to none of the plurality of conductor layers within its surface.
    Type: Grant
    Filed: November 9, 2018
    Date of Patent: August 11, 2020
    Assignee: TDK CORPORATION
    Inventors: Masashi Katsumata, Yoshihiro Suzuki, Reo Hanada
  • Patent number: 10734324
    Abstract: A fan-out semiconductor package includes a core member having a first through-hole and including wiring layers; a first semiconductor chip disposed in the first through-hole and having first connection pads formed on a lower side of the first semiconductor chip; a first encapsulant covering the core member and the first semiconductor chip; a connection member disposed below the core member and the first semiconductor chip and including redistribution layers; a first stack chip disposed on the first encapsulant and electrically connected to the wiring layers through a first connection conductor; and a second encapsulant disposed on the first encapsulant and covering the first stack chip. The first semiconductor chip includes DRAM and/or a controller, the first stack chip includes a stack type NAND flash, and the first connection pads of the first semiconductor chip are electrically connected to the wiring layers through the redistribution layers.
    Type: Grant
    Filed: October 25, 2018
    Date of Patent: August 4, 2020
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Yun Tae Lee, Eun Jung Jo, Han Kim
  • Patent number: 10734285
    Abstract: In some embodiments, a method for bonding semiconductor wafers is provided. The method includes forming a first integrated circuit (IC) over a central region of a first semiconductor wafer. A first ring-shaped bonding support structure is formed over a ring-shaped peripheral region of the first semiconductor wafer, where the ring-shaped peripheral region of the first semiconductor wafer encircles the central region of the first semiconductor wafer. A second semiconductor wafer is bonded to the first semiconductor wafer, such that a second IC arranged on the second semiconductor wafer is electrically coupled to the first IC.
    Type: Grant
    Filed: November 2, 2018
    Date of Patent: August 4, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Sheng-Chan Li, Cheng-Hsien Chou, Cheng-Yuan Tsai, Chih-Hui Huang, Kuo-Ming Wu
  • Patent number: 10730745
    Abstract: A microelectromechanical system (MEMS) semiconductor device has a first and second semiconductor die. A first semiconductor die is embedded within an encapsulant together with a modular interconnect unit. Alternatively, the first semiconductor die is embedded within a substrate. A second semiconductor die, such as a MEMS die, is disposed over the first semiconductor die and electrically connected to the first semiconductor die through an interconnect structure. In another embodiment, the first semiconductor die is flip chip mounted to the substrate, and the second semiconductor die is wire bonded to the substrate adjacent to the first semiconductor die. In another embodiment, first and second semiconductor die are embedded in an encapsulant and are electrically connected through a build-up interconnect structure. A lid is disposed over the semiconductor die. In a MEMS microphone embodiment, the lid, substrate, or interconnect structure includes an opening over a surface of the MEMS die.
    Type: Grant
    Filed: June 1, 2017
    Date of Patent: August 4, 2020
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: Yaojian Lin, Il Kwon Shim
  • Patent number: 10727086
    Abstract: An optical sensor packaging system and method can include: providing an embedded substrate, the embedded substrate including an embedded chip coupled to a redistribution pad with a redistribution line connecting therebetween; mounting an optical sensor to the embedded substrate, the optical sensor including a photo sensitive material formed on a photo sensitive area of an active optical side of the optical sensor; wire-bonding the optical sensor to the embedded substrate with a first bond wire connected from the active optical side to the redistribution pad; and encapsulating the optical sensor, the first bond wire, and the photo sensitive material with an over-mold, the over-mold formed with a top surface co-planar to a surface of the photo sensitive material, the over-mold forming a vertically extended boarder around the photo sensitive material and around the optical sensing area, and the over-mold formed above the first bond wire.
    Type: Grant
    Filed: February 21, 2019
    Date of Patent: July 28, 2020
    Assignee: Maxim Integrated Products, Inc.
    Inventors: Saurabh Nilkanth Athavale, Yi-Sheng Anthony Sun, Zhiyong Wang, Tie Wang
  • Patent number: 10727082
    Abstract: A semiconductor device includes a semiconductor die. A dielectric material surrounds the semiconductor die to form an integrated semiconductor package. There is a contact coupling to the integrated semiconductor package and configured as a ground terminal for the semiconductor package. The semiconductor device further has an EMI (Electric Magnetic Interference) shield substantially enclosing the integrated semiconductor package, wherein the EMI shield is coupled with the contact through a path disposed in the integrated semiconductor package.
    Type: Grant
    Filed: August 28, 2015
    Date of Patent: July 28, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Shou Zen Chang, Chun-Lin Lu, Kai-Chiang Wu, Ching-Feng Yang, Vincent Chen, Chuei-Tang Wang, Yen-Ping Wang, Hsien-Wei Chen, Wei-Ting Lin
  • Patent number: 10700410
    Abstract: An Antenna-in-Package (AiP) includes an interface layer, an integrated circuit die disposed on the interface layer, a molding compound disposed on the interface layer and encapsulating the integrated circuit die, and a plurality of solder balls disposed on a bottom surface of the interface layer. The interface layer includes an antenna layer, and an insulating layer between the antenna layer and the ground reflector layer. The antenna layer includes a first antenna region and a second antenna region spaced apart from the first antenna region. The integrated circuit die is interposed between the first antenna region and the second antenna region. The first antenna region is disposed adjacent to a first edge of the integrated circuit die, and the second antenna region is disposed adjacent to a second edge of the integrated circuit die, which is opposite to the first edge.
    Type: Grant
    Filed: September 27, 2018
    Date of Patent: June 30, 2020
    Assignee: MEDIATEK INC.
    Inventors: Yen-Ju Lu, Wen-Chou Wu
  • Patent number: 10686008
    Abstract: Methods of magnetically shielding an MRAM structure on all six sides in a thin wire or thin flip chip bonding package and the resulting devices are provided. Embodiments include forming a first metal layer embedded between an upper and a lower portion of a PCB substrate, the first metal layer having a pair of metal filled vias laterally separated; attaching a semiconductor die to the upper portion of the PCB substrate between the pair of metal filled vias; connecting the semiconductor die electrically to the PCB substrate through the pair of metal filled vias; removing a portion of the upper portion of the PCB substrate outside of the pair of metal filled vias down to the first metal layer; and forming a second metal layer over and on four opposing sides of the semiconductor die, the second metal layer landed on the first metal layer.
    Type: Grant
    Filed: March 11, 2019
    Date of Patent: June 16, 2020
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Shan Gao, Boo Yang Jung
  • Patent number: 10679949
    Abstract: The invention provides a semiconductor package assembly. The semiconductor package assembly includes a substrate having a first pad and a second pad thereon. A logic die is mounted on the substrate. The logic die includes a first logic die pad coupled to the first pad. A memory die is mounted on the substrate. The memory die includes a first memory die pad. A first redistribution layer (RDL) trace has a first terminal and a second terminal. The first terminal is coupled to the first pad through the first memory die pad. The second terminal is coupled to the second pad rather than the first pad.
    Type: Grant
    Filed: January 20, 2017
    Date of Patent: June 9, 2020
    Assignee: MediaTek Inc.
    Inventors: Sheng-Mou Lin, Duen-Yi Ho
  • Patent number: 10658302
    Abstract: Apparatuses relating generally to a microelectronic package having protection from electromagnetic interference are disclosed. In an apparatus thereof, a platform has an upper surface and a lower surface opposite the upper surface and has a ground plane. A microelectronic device is coupled to the upper surface of the platform. Wire bond wires are coupled to the ground plane with a pitch. The wire bond wires extend away from the upper surface of the platform with upper ends of the wire bond wires extending above an upper surface of the microelectronic device. The wire bond wires are spaced apart from one another to provide a fence-like perimeter to provide an interference shielding cage. A conductive layer is coupled to at least a subset of the upper ends of the wire bond wires for electrical conductivity to provide a conductive shielding layer to cover the interference shielding cage.
    Type: Grant
    Filed: March 7, 2018
    Date of Patent: May 19, 2020
    Assignee: Invensas Corporation
    Inventors: Shaowu Huang, Javier A. Delacruz
  • Patent number: 10658342
    Abstract: In a general aspect, a method for producing a circuit assembly can include coupling a first side of a first semiconductor die with a first side of a first substrate and a first side of a second substrate, the first substrate having a first electrically isolated metal layer disposed on a second side. The method can also include coupling a first side of a second semiconductor die with a second side of the second substrate and a first side of a third substrate, the third substrate having a second electrically isolated metal layer disposed on a second side. The method can further include coupling at least one conductive connector between the second substrate and the third substrate, the at least one conductive connector electrically coupling the second substrate with the third substrate.
    Type: Grant
    Filed: September 9, 2019
    Date of Patent: May 19, 2020
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Mankyo Jong, Changyoung Park
  • Patent number: 10643928
    Abstract: An electronic device includes first and second component carrier packages having respective embedded electronic components and at least one respective external terminal. The second component carrier package is mounted on the first component carrier package by electrically and mechanically connecting the at least one respective external terminals. The first component carrier package further includes an electromagnetic radiation shielding structure formed as an electrically conductive coating and being configured for at least partially shielding electromagnetic radiation from propagating between an exterior and an interior of the first component carrier package.
    Type: Grant
    Filed: November 30, 2016
    Date of Patent: May 5, 2020
    Assignee: AT&S (China) Co. Ltd.
    Inventor: Mikael Tuominen
  • Patent number: 10643973
    Abstract: Semiconductor packages are provided. The semiconductor package includes a first semiconductor chip to which a first elevated pillar bump is connected, a second semiconductor chip stacked on the first semiconductor chip to leave revealed the first elevated pillar bump and configured to include a first chip pad disposed on a center region of the second semiconductor chip, a third semiconductor chip offset and stacked on the second semiconductor chip to leave revealed the first chip pad, and a chip supporter supporting an overhang of the third semiconductor chip.
    Type: Grant
    Filed: September 24, 2018
    Date of Patent: May 5, 2020
    Assignee: SK hynix Inc.
    Inventor: Ki Jun Sung
  • Patent number: 10645797
    Abstract: Embodiments herein disclose techniques for electronic apparatuses including a printed circuit board (PCB) and an electromagnetic interference (EMI) shield for the PCB. An electronic apparatus may include a PCB with a plurality of layers including a ground layer. The PCB may include a cutout through the plurality of layers of the PCB. An EMI shield may be mounted to a bottom side of the PCB along an edge of the cutout, where the EMI shield may be coupled to the ground layer through an ohmic contact. The EMI shield may be flat. Other embodiments may also be described and claimed.
    Type: Grant
    Filed: July 26, 2017
    Date of Patent: May 5, 2020
    Assignee: Intel Corporation
    Inventors: Dong-Ho Han, Timothy Swettlen
  • Patent number: 10636830
    Abstract: An image-capturing element manufacturing method includes: preparing a first substrate having a plurality of pixels that are two-dimensionally continuously arrayed; preparing a second substrate having a plurality of circuit blocks that respectively have connection terminals to a power supply and a reference potential and that are electrically independent from each other, each of the plurality of circuit blocks having at least some of circuits to read out signals from the plurality of pixels; laminating the first substrate and the second substrate to electrically couple the plurality of circuit blocks and the plurality of pixels overlapping therewith; and cutting circuit blocks around at least one of the plurality of circuit blocks and pixels overlapping therewith to form a laminate in which the plurality of pixels are laminated onto the at least one of the plurality of circuit blocks.
    Type: Grant
    Filed: July 30, 2018
    Date of Patent: April 28, 2020
    Assignee: NIKON CORPORATION
    Inventors: Tadashi Narui, Toru Takagi
  • Patent number: 10636753
    Abstract: A semiconductor device has a semiconductor die and an encapsulant deposited over the semiconductor die. A first conductive layer is formed with an antenna over a first surface of the encapsulant. A second conductive layer is formed with a ground plane over a second surface of the encapsulant with the antenna located within a footprint of the ground plane. A conductive bump is formed on the ground plane. A third conductive layer is formed over the first surface of the encapsulant. A fourth conductive layer is formed over the second surface of the encapsulant. A conductive via is disposed adjacent to the semiconductor die prior to depositing the encapsulant. The antenna is coupled to the semiconductor die through the conductive via. The antenna is formed with the conductive via between the antenna and semiconductor die. A PCB unit is disposed in the encapsulant.
    Type: Grant
    Filed: November 8, 2018
    Date of Patent: April 28, 2020
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: Pandi Chelvam Marimuthu, Andy Chang Bum Yong, Aung Kyaw Oo, Yaojian Lin
  • Patent number: 10630246
    Abstract: Embodiments include packaged semiconductor devices and methods of manufacturing packaged semiconductor devices. A semiconductor die includes a conductive feature coupled to a bottom surface of the die. The conductive feature only partially covers the bottom die surface to define a conductor-less region that spans a portion of the bottom die surface. The die is encapsulated by attaching the encapsulant material to the bottom die surface (e.g., including over the conductor-less region). The encapsulant material includes an opening that exposes the conductive feature. After encapsulating the die, a heatsink is positioned within the opening, and a surface of the heatsink is attached to the conductive feature. Because the heatsink is attached after encapsulating the die, the heatsink sidewalls are not directly bonded to the encapsulant material.
    Type: Grant
    Filed: October 9, 2017
    Date of Patent: April 21, 2020
    Assignee: NXP USA, Inc.
    Inventors: David F. Abdo, Jeffrey K. Jones