With Shielding (e.g., Electrical Or Magnetic Shielding, Or From Electromagnetic Radiation Or Charged Particles) Patents (Class 257/659)
  • Patent number: 11329396
    Abstract: An antenna package having a cavity structure is provided, wherein a cavity substrate having an accommodation portion formed therethrough is disposed on one surface of an antenna substrate having a signal processing element formed thereon, so as to prevent occurrence of deformation and breakage thereof in the process of mounting the antenna package. The provided antenna package having the cavity structure comprises: an antenna substrate, on the upper surface of which multiple radiation patches are formed and on the lower surface of which multiple signal processing elements are formed; and a cavity substrate which has an accommodation portion formed therethrough to receive the multiple signal processing elements and is disposed on the lower surface of the antenna substrate.
    Type: Grant
    Filed: October 18, 2018
    Date of Patent: May 10, 2022
    Assignee: AMOTECH CO., LTD.
    Inventors: Hyun Joo Park, Hyung Il Baek, Kyung Hyun Ryu, Se Ho Lee, Yun Sik Seo, Gwang Lyong Go, Han Ju Do
  • Patent number: 11322418
    Abstract: In an assembly in which a space between two elements is filled with a filler containing resin, a configuration that can limit both the size of the assembly and the cost of the fillers is provided. Assembly 10 of stacked elements has: first element 2 having first surface 21; resin layer 61 that is arranged on first surface 21 and that contains a plurality of fillers F; and second element 4 that is arranged on resin layer 61 and that has second surface 41 that is in contact with resin layer 61. In a section that is perpendicular to second surface 41, the average flattening ratio of fillers F2 that are in contact with second surface 41 is larger than the average flattening ratio of fillers F1, F3 that are not in contact with second surface 41. Here, the flattening ratio is a ratio of the maximum length of the filler in a direction parallel to second surface 41 to the maximum thickness of the filler in a direction perpendicular to second surface 41.
    Type: Grant
    Filed: November 15, 2019
    Date of Patent: May 3, 2022
    Assignee: TDK Corporation
    Inventors: Yongfu Cai, Shuhei Miyazaki
  • Patent number: 11322434
    Abstract: Disclosed embodiments include folded, top-to-bottom interconnects that couple a die side of an integrated-circuit package substrate, to a board as a complement to a ball-grid array for a flip-chip-mounted integrated-circuit die on the die side. The folded, top-to-bottom interconnect is in a molded frame that forms a perimeter around an infield to receive at least one flip-chip IC die. Power, ground and I/O interconnections shunt around the package substrate, and such shunting includes voltage regulation that need not be routed through the package substrate.
    Type: Grant
    Filed: June 25, 2020
    Date of Patent: May 3, 2022
    Assignee: Intel Corporation
    Inventors: Jiun Hann Sir, Poh Boon Khoo, Eng Huat Goh
  • Patent number: 11322433
    Abstract: In some examples, a package comprises first and second terminals and a conductive pathway coupling the first and second terminals. The conductive pathway is configured to generate a magnetic field. The package comprises a conductive member aligned with and coupled to the conductive pathway. The conductive pathway and the conductive member have a common shape. The package also comprises an insulative layer coupled to the conductive member and a die coupled to the insulative layer and having a circuit configured to measure the magnetic field. The circuit faces the conductive pathway.
    Type: Grant
    Filed: April 7, 2020
    Date of Patent: May 3, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Enis Tuncer, Alejandro Hernandez-Luna
  • Patent number: 11309193
    Abstract: A semiconductor device has a semiconductor die or component, including an IPD, disposed over an attach area of a penetrable film layer with a portion of the semiconductor die or component embedded in the penetrable film layer. A conductive layer is formed over a portion of the film layer within the attach area and over a portion of the film layer outside the attach area. An encapsulant is deposited over the film layer, conductive layer, and semiconductor die or component. The conductive layer extends outside the encapsulant. An insulating material can be disposed under the semiconductor die or component. A shielding layer is formed over the encapsulant. The shielding layer is electrically connected to the conductive layer. The penetrable film layer is removed. The semiconductor die or component disposed over the film layer and covered by the encapsulant and shielding layer form an SIP module without a substrate.
    Type: Grant
    Filed: September 2, 2020
    Date of Patent: April 19, 2022
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: OhHan Kim, KyungHwan Kim, WoonJae Beak, HunTeak Lee, InSang Yoon
  • Patent number: 11309302
    Abstract: Manufacturing method of semiconductor package includes following steps. Bottom package is provided. The bottom package includes a die and a redistribution structure electrically connected to die. A first top package and a second top package are disposed on a surface of the redistribution structure further away from the die. An underfill is formed into the space between the first and second top packages and between the first and second top packages and the bottom package. The underfill covers at least a side surface of the first top package and a side surface of the second top package. A hole is opened in the underfill within an area overlapping with the die between the side surface of the first top package and the side surface of the second top package. A thermally conductive block is formed in the hole by filling the hole with a thermally conductive material.
    Type: Grant
    Filed: June 10, 2020
    Date of Patent: April 19, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Wei Chen, Chih-Hua Chen, Hsin-Yu Pan, Hao-Yi Tsai, Lipu Kris Chuang, Tin-Hao Kuo
  • Patent number: 11309246
    Abstract: Electronic package structures and systems are described in which a 3D interconnect structure is integrated into a package redistribution layer and/or chiplet for power and signal delivery to a die. Such structures may significantly improve input output (IO) density and routing quality for signals, while keeping power delivery feasible.
    Type: Grant
    Filed: February 5, 2020
    Date of Patent: April 19, 2022
    Assignee: Apple Inc.
    Inventors: Sanjay Dabral, Zhitao Cao, Kunzhong Hu, Jun Zhai
  • Patent number: 11302647
    Abstract: The present disclosure provides for a semiconductor device package and a method for manufacturing the same. The semiconductor device package includes a substrate, a conductive element and conductive layers. The substrate has a first surface, a second surface opposite to the first surface and a lateral surface extending between the first surface and the second surface. The conductive element is disposed on the first surface of the substrate. The conductive layers have a first portion on the conductive element and a second portion on the lateral surface of the substrate. A number of layers of the first portion of the conductive layers is different from a number of layers of the second portion of the conductive layers.
    Type: Grant
    Filed: May 14, 2020
    Date of Patent: April 12, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Ming-Hung Chen, Hui-Ping Jian, Wei-Zhen Qiu
  • Patent number: 11302632
    Abstract: A semiconductor device includes a first high resistance pattern and a second high resistance pattern that are disposed along an X axis and are separated from each other, a coupling pattern that couples the first high resistance pattern and the second high resistance pattern, and a signal wiring disposed at a layer above the first high resistance pattern, the second high resistance pattern, and the coupling pattern. The coupling pattern includes a first portion that overlaps an end portion of the first high resistance pattern in a plan view at the layer above the first high resistance pattern, the coupling pattern includes a second portion that overlaps an end portion of the second high resistance pattern in a plan view at a layer above the second high resistance pattern, and the signal wiring is disposed along a Y axis that intersects the X axis in a plan view between an end of the coupling pattern at the first portion side and an end of the coupling pattern at the second portion side.
    Type: Grant
    Filed: August 21, 2020
    Date of Patent: April 12, 2022
    Inventor: Noboru Itomi
  • Patent number: 11282776
    Abstract: A chip package and method of fabricating the same are described herein. The chip package includes a high speed data transmission line that has an inter-die region through which a signal transmission line couples a first die to a second die. The signal transmission line has a resistance greater than an equivalent base resistance (EBR) of a copper line, which reduces oscillation within the transmission line.
    Type: Grant
    Filed: February 22, 2018
    Date of Patent: March 22, 2022
    Assignee: XILINX, INC.
    Inventors: Jaspreet Singh Gandhi, Vadim Heyfitch
  • Patent number: 11282775
    Abstract: A chip package assembly having pillars extending between an interconnect layer and solder balls, and methods for manufacturing the same are provide. The pillars decouple stress from the interconnect layer, making crack initiation and propagation to the interconnect layer less likely, resulting in a more robust assembly. In one example, a chip package assembly is provided that includes an integrated circuit (IC) die, an interconnect layer and a plurality of pillars. The IC dies includes a die body containing functional circuitry. The body has a lower surface, an upper surface and sides. The IC die includes contact pads coupled to the functional circuitry and exposed on the lower surface of the die body. The interconnect layer is formed on the lower surface of the body. The plurality of pillars are formed on the interconnect layer and electrically couple to the contact pads through routing formed through the interconnect layer.
    Type: Grant
    Filed: July 30, 2020
    Date of Patent: March 22, 2022
    Assignee: XILINX, INC.
    Inventors: Jaspreet Singh Gandhi, Suresh Ramalingam
  • Patent number: 11282756
    Abstract: An organic interposer includes polymer matrix layers embedding redistribution interconnect structures, package-side bump structures, die-side bump structures and connected to a distal subset of the redistribution interconnect structures through a respective bump connection via structure. At least one metallic shield structure may laterally surround a respective one of the die-side bump structures. Shield support via structures may laterally surround a respective one of the bump connection via structures. Each metallic shield structure and the shield support via structures may be used to reduce mechanical stress applied to the redistribution interconnect structures during subsequent attachment of a semiconductor die to the die-side bump structures.
    Type: Grant
    Filed: August 17, 2020
    Date of Patent: March 22, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Tsung-Yen Lee, Chin-Hua Wang, Ming-Chih Yew, Chia-Kuei Hsu, Po-Chen Lai, Po-Yao Lin, Shin-Puu Jeng
  • Patent number: 11276633
    Abstract: A semiconductor package includes; a semiconductor chip, a conductive pattern electrically connected to the semiconductor chip, a pad electrically connected to the conductive pattern, and a connection member disposed on and electrically connected to the pad. The pad includes a central portion and a peripheral portion at least partially surrounding the central portion and separated from the peripheral portion by a gap, and the connection member contacts at least one of a side surface of the central portion and an inner side surface of the peripheral portion.
    Type: Grant
    Filed: June 18, 2020
    Date of Patent: March 15, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Gayoung Kim, Duckgyu Kim
  • Patent number: 11264335
    Abstract: An anti-electromagnetic interference radio frequency module and an implementation method therefor. The anti-electromagnetic interference radio frequency module comprises a radio frequency module body, the inside of the radio frequency module body is provided with an electrical connection area (1) and a grounding area (2), a metal thin film structure (4) is attached to an upper surface and side surfaces of the radio frequency module body, and the metal thin film structure is connected to the grounding area, forming an anti-electromagnetic interference shielding layer structure which is integrated with the radio frequency module body. The radio frequency module achieves an anti-electromagnetic interference effect by means of the anti-electromagnetic interference shielding layer structure, so that electromagnetic interference generated around the radio frequency module is effectively isolated, thereby improving the performance of the radio frequency module.
    Type: Grant
    Filed: July 1, 2018
    Date of Patent: March 1, 2022
    Assignee: VANCHIP (TIANJIN) TECHNOLOGY CO., LTD.
    Inventors: Fujuan Jin, Yunfang Bai
  • Patent number: 11264363
    Abstract: A chip package structure is provided. The chip package structure includes a redistribution structure including a dielectric structure, a redistribution line, and a seal ring structure. The redistribution line and the seal ring structure are in the dielectric structure, the seal ring structure continuously surrounds the redistribution line, the seal ring structure includes a first seal ring and a second seal ring over and electrically connected to the first seal ring, and the redistribution structure has a first sidewall, a first surface, and a second surface opposite to the first surface. The chip package structure includes a chip structure over the first surface. The chip package structure includes a ground bump over the second surface. The chip package structure includes a conductive shielding film covering the chip structure and the first sidewall of the redistribution structure.
    Type: Grant
    Filed: September 14, 2020
    Date of Patent: March 1, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chen-Hua Yu, An-Jhih Su, Jing-Cheng Lin, Po-Hao Tsai
  • Patent number: 11258356
    Abstract: A cascaded configuration of regulator circuits can be co-integrated within a commonly-shared integrated circuit package (such as an integrated electronic module). Such co-integration can include placing a switched-mode regulator circuit in close proximity to a linear regulator circuit. Magnetic field coupling between the regulator circuits is generally a non-linear function of a separation between the circuits. The switched-mode regulator circuit can generate noise that may adversely impact the linear regulator output. Magnetic coupling between the regulator circuits within the module package can be suppressed or eliminated using a magnetic barrier. The barrier can be magnetically permeable and electrically non-conductive.
    Type: Grant
    Filed: July 31, 2019
    Date of Patent: February 22, 2022
    Assignee: Analog Devices International Unlimited Company
    Inventors: Zhengyang Liu, David Roy Ng
  • Patent number: 11251116
    Abstract: The present disclosure relates to a semiconductor module, especially a power semiconductor module, in which the heat dissipation is improved and the power density is increased. The semiconductor module may include at least two electrically insulating substrates, each having a first main surface and a second main surface opposite to the first main surface. On the first main surface of each of the substrates, at least one semiconductor device is mounted. An external terminal is connected to the first main surface of at least one of the substrates. The substrates are arranged opposite to each other so that their first main surfaces are facing each other.
    Type: Grant
    Filed: February 24, 2020
    Date of Patent: February 15, 2022
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Hamit Duran, Junfu Hu
  • Patent number: 11239143
    Abstract: A semiconductor structure includes a first substrate including a first surface and a second surface opposite to the first surface; a first conductive via extended through the first substrate; a second conductive via extended through the first substrate; and a third conductive via extended through the first substrate, wherein the second conductive via is disposed between the first conductive via and the third conductive via, the second conductive via is configured to connect to a signal source, and the first conductive via and the third conductive via are configured to connect to an electrical ground.
    Type: Grant
    Filed: August 5, 2019
    Date of Patent: February 1, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Pei-Haw Tsao, Tsung-Hsing Lu, Li-Huan Chu
  • Patent number: 11239179
    Abstract: A semiconductor package includes a substrate having thereon a high-frequency chip and a circuit component susceptible to high-frequency signal interference; a ground pad on the and between the high-frequency chip and the circuit component; a metal-post reinforced glue wall on the ground pad; a molding compound surrounding the metal-post reinforced glue wall and surrounding the high-frequency chip and the circuit component; and a conductive layer disposed on the molding compound and in contact with the metal-post reinforced glue wall. The metal-post reinforced glue wall comprises first metal posts and glue attached to the first metal posts. An interface between a base of each of the first metal posts and the ground pad has a root mean square (RMS) roughness that is less than 1.0 micrometer.
    Type: Grant
    Filed: July 13, 2020
    Date of Patent: February 1, 2022
    Inventors: Shiann-Tsong Tsai, Hsien-Chou Tsai, Hsien-Wei Tsai, Yen-Mei Tsai Huang
  • Patent number: 11240945
    Abstract: A shielding arrangement can be provided for a piece of high voltage equipment spaced from a neighboring object. The piece of high voltage equipment has a first electric potential and the neighboring object has a second electric potential. The shielding arrangement includes a resistor, a shield element for connection to the high voltage equipment via the resistor, and a capacitor connected in parallel with the resistor. A resistance of the resistor and a capacitance of the capacitor together define a time constant in a range of 10 ?s-50 ms.
    Type: Grant
    Filed: September 27, 2018
    Date of Patent: February 1, 2022
    Assignee: Hitachi Energy Switzerland AG
    Inventors: Mats Larsson, Dong Wu, Liliana Arevalo, Christer Tornkvist
  • Patent number: 11239178
    Abstract: A semiconductor package structure includes a substrate structure having a first surface and a second surface opposite to the first surface; at least two electronic components electrically connected to the first surface of the substrate structure; at least one shielding pad disposed on the first surface of the substrate structure; a plurality of vias connected to the at least one shielding pad; a plurality of shielding wirebonds disposed between the electronic components. Each of the shielding wirebonds includes a first bond and a second bond opposite to the first bond, the first bond and the second bond being electrically connected to the at least one shielding pad, and the vias being free from overlapping with any of the plurality of vias.
    Type: Grant
    Filed: November 25, 2019
    Date of Patent: February 1, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Chanyuan Liu, Han-Chee Yen, Kuo-Hsien Liao, Alex Chi-Hong Chan, Christophe Zinck
  • Patent number: 11227841
    Abstract: To maintain the integrity of electrical contacts at a build-up layer of a chip package, while reducing electrical interference caused by a chip connected to the build-up layer, the chip package can include a stiffener formed from an electrically conductive material and positioned between the chip and the build-up layer. The chip can electrically connect to the build-up layer through electrical connections that extend through the stiffener. Compared with a stiffener that extends only over a single chip of the chip package, the present stiffener can help prevent warpage or other mechanical deformities that can degrade electrical contacts away from the chip at the build-up layer. Compared with a stiffener that extends only over an area away from the chip, such as a peripheral area, the present stiffener can help reduce electrical interference in an area of the build-up layer near the chip.
    Type: Grant
    Filed: May 22, 2019
    Date of Patent: January 18, 2022
    Assignee: Intel Corporation
    Inventors: Bok Eng Cheah, Jackson Chung Peng Kong, Jenny Shio Yin Ong, Seok Ling Lim
  • Patent number: 11222911
    Abstract: A photoelectric conversion element encompasses a depletion-layer extension-promotion region having a p-type upper layer, a p-type photoelectric conversion layer in contact with the depletion-layer extension-promotion region, and an n-type surface-buried region buried in an upper portion of the photoelectric conversion layer, configured to implement a photodiode together with the photoelectric conversion layer. A first p-well is surrounded by a first n-tab, the first n-tab is surrounded by a second p-well, the second p-well is surrounded by a second n-tab, and the second n-tab is surrounded by a third p-well. An injection-blocking element blocks injection of carriers of opposite conductivity type to signal charges from the second p-well into the photoelectric conversion layer, and the inside of the photoelectric conversion layer is depleted by a voltage applied to the depletion-layer extension-promotion region.
    Type: Grant
    Filed: December 7, 2018
    Date of Patent: January 11, 2022
    Inventor: Shoji Kawahito
  • Patent number: 11222793
    Abstract: A semiconductor device has a semiconductor wafer including a plurality of semiconductor die. An insulating layer is formed over the semiconductor wafer. A portion of the insulating layer is removed by LDA to expose a portion of an active surface of the semiconductor die. A first conductive layer is formed over a contact pad on the active surface of the semiconductor die. The semiconductor wafer is singulated to separate the semiconductor die. The semiconductor die is disposed over a carrier with the active surface of the semiconductor die offset from the carrier. An encapsulant is deposited over the semiconductor die and carrier to cover a side of the semiconductor die and the exposed portion of the active surface. An interconnect structure is formed over the first conductive layer. Alternatively, a MUF material is deposited over a side of the semiconductor die and the exposed portion of the active surface.
    Type: Grant
    Filed: November 19, 2019
    Date of Patent: January 11, 2022
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: Yaojian Lin, Heinz-Peter Wirtz, Seung Wook Yoon, Pandi C. Marimuthu
  • Patent number: 11219144
    Abstract: Electromagnetic shields for sub-modules of electronic modules are disclosed. Electronic modules may include multiple sub-modules arranged on a substrate with an electromagnetic shield arranged to conformally cover the sub-modules as well as portions of the substrate that are uncovered by the sub-modules. Electromagnetic shields are disclosed that are configured to extend between sub-modules to form one or more divider walls. The one or more divider walls may be configured to extend below mounting surfaces of electronic components in the sub-modules to provide improved reduction of electromagnetic interference (EMI) or crosstalk between various sub-modules. Electromagnetic shields are also disclosed that form perimeter sidewalls that extend below mounting surfaces of electronic components of sub-modules to provide improved reduction of EMI from other modules or other external sources.
    Type: Grant
    Filed: April 22, 2019
    Date of Patent: January 4, 2022
    Assignee: Qorvo US, Inc.
    Inventors: Kelly M. Lear, Thomas Scott Morris, Jeffrey Miller, Jeffrey Dekosky
  • Patent number: 11211710
    Abstract: In an array antenna apparatus, a first height of top faces of plurality of antenna elements is greater than or equal to a second height of a first top of a first electronic component relative to a first primary surface. The first electronic component is the tallest among one or more electronic components mounted on fourth primary surfaces of one or more first external circuit boards. A third height of a second primary surface is greater than a fourth height of fourth primary surfaces. Accordingly, the array antenna apparatus has good antenna characteristics.
    Type: Grant
    Filed: March 8, 2018
    Date of Patent: December 28, 2021
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Yoichi Kitamura, Takumi Nagamine, Takayuki Nakao, Kiyoshi Ishida, Tetsu Owada
  • Patent number: 11205623
    Abstract: A microwave device includes: a multilayer resin substrate being a first multilayer resin substrate; an IC being a radio frequency circuit provided on the multilayer resin substrate and electrically connected to the multilayer resin substrate; a heat spreader provided on a side opposite to the multilayer resin substrate across the IC, and in contact with the IC; a mold resin covering the periphery of the IC and the heat spreader; and a conductive film covering the mold resin and the heat spreader, where an inner side of the conductive film is in contact with the heat spreader, and the conductive film is electrically connected to a ground via hole of the multilayer resin substrate.
    Type: Grant
    Filed: February 22, 2018
    Date of Patent: December 21, 2021
    Assignee: Mitsubishi Electric Corporation
    Inventors: Yukinobu Tarui, Makoto Kimura, Katsumi Miyawaki, Kiyoshi Ishida, Hiroaki Matsuoka
  • Patent number: 11205630
    Abstract: A composite integrated circuit (IC) device structure comprising a host chip and a chiplet. The host chip comprises a first device layer and a first metallization layer. The chiplet comprises a second device layer and a second metallization layer that is interconnected to transistors of the second device layer. A top metallization layer comprising a plurality of first level interconnect (FLI) interfaces is over the chiplet and host chip. The chiplet is embedded between a first region of the first device layer and the top metallization layer. The first region of the first device layer is interconnected to the top metallization layer by one or more conductive vias extending through the second device layer or adjacent to an edge sidewall of the chiplet.
    Type: Grant
    Filed: September 27, 2019
    Date of Patent: December 21, 2021
    Assignee: Intel Corporation
    Inventors: Adel Elsherbini, Patrick Morrow, Johanna Swan, Shawna Liff, Mauro Kobrinksy, Van Le, Gerald Pasdast
  • Patent number: 11201110
    Abstract: A semiconductor device package includes a conductive layer, a first conductive pillar, a circuit layer and a second conductive pillar. The conductive layer has a first surface. The first conductive pillar is disposed on the first surface of the conductive layer. The circuit layer is disposed over the conductive layer. The circuit layer has a first surface facing the conductive layer. The second conductive pillar is disposed on the first surface of the circuit layer. The first conductive pillar is physically spaced apart from the second conductive pillar and electrically connected to the second conductive pillar.
    Type: Grant
    Filed: July 31, 2019
    Date of Patent: December 14, 2021
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Min Lung Huang, Hung-Jung Tu, Hsin Hsiang Wang
  • Patent number: 11201386
    Abstract: A semiconductor device package and a method for manufacturing the same are provided. The semiconductor device package includes a circuit layer and an antenna module. The circuit layer has a first surface, a second surface opposite to the first surface and a lateral surface. The lateral surface extends between the first surface and the second surface. The circuit layer has an interconnection structure. The antenna module has an antenna pattern layer and is disposed on the first surface of the circuit layer. The lateral surface of the circuit layer is substantially coplanar with a lateral surface of the antenna module.
    Type: Grant
    Filed: October 31, 2019
    Date of Patent: December 14, 2021
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Cheng-Lin Ho, Chih-Cheng Lee, Chun Chen Chen, Yuanhao Yu
  • Patent number: 11201101
    Abstract: An electronic component has a base 10; an electronic element 20 provided on one side of the base 10; a connecting body 30 provided on one side of the electronic element 20; a heat dissipating block 40 provided on one side of the connecting body 30; an insulating part 50 provided between the connecting body 30 and the heat dissipating block 40; and a sealing part 90 in which the electronic element 20, the connecting body 30 and the insulating part 50 are sealed. At least a part of a surface on another side of the base 10 is exposed from the sealing part 90. At least a part of a surface on one side of the heat dissipating block 40 is exposed from the sealing part 90.
    Type: Grant
    Filed: October 26, 2017
    Date of Patent: December 14, 2021
    Assignee: SHINDENGEN ELECTRIC MANUFACTURING CO., LTD.
    Inventor: Norio Takatsu
  • Patent number: 11195802
    Abstract: A semiconductor package includes a semiconductor die, a redistribution structure and connective terminals. The redistribution structure is disposed on the semiconductor die and includes a first metallization tier disposed in between a pair of dielectric layers. The first metallization tier includes routing conductive traces electrically connected to the semiconductor die and a shielding plate electrically insulated from the semiconductor die. The connective terminals include dummy connective terminals and active connective terminals. The dummy connective terminals are disposed on the redistribution structure and are electrically connected to the shielding plate. The active connective terminals are disposed on the redistribution structure and are electrically connected to the routing conductive traces. Vertical projections of the dummy connective terminals fall on the shielding plate.
    Type: Grant
    Filed: June 5, 2020
    Date of Patent: December 7, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Cheng Wu, Chien-Chia Chiu, Cheng-Hsien Hsieh, Li-Han Hsu, Meng-Tsan Lee, Tsung-Shu Lin
  • Patent number: 11189573
    Abstract: A semiconductor package is described herein with electromagnetic shielding using metal layers and vias. In one example, the package includes a silicon substrate having a front side and a back side, the front side including active circuitry and an array of contacts to attach to a substrate, a metallization layer over the back side of the die to shield active circuitry from interference through the back side, and a plurality of through-silicon vias coupled to the back side metallization at one end and to front side lands of the array of lands at the other end to shield active circuitry from interference through the sides of the die.
    Type: Grant
    Filed: March 31, 2016
    Date of Patent: November 30, 2021
    Assignee: Intel Corporation
    Inventors: Vijay K. Nair, Digvijay Raorane
  • Patent number: 11189575
    Abstract: An integrated circuit (IC) package is described. The IC package includes a laminate substrate. The IC package also includes an active die on a surface of the laminate substrate. The IC package further includes fin-based thermal surface mount devices on the surface of the laminate substrate proximate the active die to provide an additional heat dissipation path.
    Type: Grant
    Filed: May 14, 2020
    Date of Patent: November 30, 2021
    Assignee: QUALCOMM Incorporated
    Inventors: Supatta Niramarnkarn, Bin Xu, Wen Yin, Yonghao An
  • Patent number: 11183465
    Abstract: A radio-frequency module having high design flexibility of a shield with less likelihood of variation in shielding characteristics is provided. A radio-frequency module includes a multilayer circuit board, a component mounted on a top surface of the multilayer circuit board, and a plurality of metal pins having a bent shape such that both end portions can be connected to the top surface of the multilayer circuit board. Each of the plurality of metal pins is provided upright on the top surface of the multilayer circuit board in a state where both end portions are connected to the top surface of the multilayer circuit board, and is arranged near the component to make up a shield member.
    Type: Grant
    Filed: September 3, 2019
    Date of Patent: November 23, 2021
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Yoshihito Otsubo
  • Patent number: 11178778
    Abstract: A high frequency module 1a includes a wiring board 2, multiple components 3a to 3d mounted on an upper surface 2a of the wiring board 2, a shield component 4 mounted between the component 3b and the component 3c, a sealing resin layer 5 that covers the components 3a to 3d and the shield component 4, and a shield film 6 that covers the surface of the sealing resin layer. A recess 10 is formed in an upper surface 5a of the sealing resin layer 5 so as to expose the shield component 4. The recess 10 is formed within a region surrounded by edges of the sealing resin layer 5 so as not to reach the side surfaces of the sealing resin layer 5. The shield film 6 further covers wall surfaces 10a of the recess 10 and part of the shield component 4 exposed through the recess 10.
    Type: Grant
    Filed: December 27, 2019
    Date of Patent: November 16, 2021
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Tadashi Nomura, Yuta Morimoto, Minoru Komiyama, Akio Katsube
  • Patent number: 11152310
    Abstract: A microwave device includes: a multilayer resin substrate being a first multilayer resin substrate; an IC being a radio frequency circuit provided on the multilayer resin substrate and electrically connected to the multilayer resin substrate; a heat spreader provided on a side opposite to the multilayer resin substrate across the IC, and in contact with the IC; a mold resin covering the periphery of the IC and the heat spreader; and a conductive film covering the mold resin and the heat spreader, where an inner side of the conductive film is in contact with the heat spreader, and the conductive film is electrically connected to a ground via hole of the multilayer resin substrate.
    Type: Grant
    Filed: February 22, 2018
    Date of Patent: October 19, 2021
    Assignee: Mitsubishi Electric Corporation
    Inventors: Yukinobu Tarui, Makoto Kimura, Katsumi Miyawaki, Kiyoshi Ishida, Hiroaki Matsuoka
  • Patent number: 11139257
    Abstract: According to certain aspects, a method for manufacturing packaged radio-frequency (RF) devices can include: providing a packaging substrate configured to receive a plurality of components, the packaging substrate including a first side and a second side; mounting a first circuit on the first side of the packaging substrate; implementing a first overmold structure on the first side of the packaging substrate, the first overmold structure substantially encapsulating the first component; mounting a second component on the second side of the packaging substrate, the second component being located in an area of the second side where redundant ground pins may be located; implementing a set of through-mold connections on the second side of the packaging substrate, the set of through-mold connections including signal pins and ground pins; forming a second overmold structure over the component and the set of through-mold connections; and removing a portion of the second overmold structure.
    Type: Grant
    Filed: December 1, 2019
    Date of Patent: October 5, 2021
    Assignee: Skyworks Solutions, Inc.
    Inventors: Howard E. Chen, Robert Francis Darveaux, Anthony James Lobianco
  • Patent number: 11139251
    Abstract: A semiconductor package includes a semiconductor chip having an active surface on which a connection pad is disposed and an inactive surface opposing the active surface, a first encapsulant covering at least portions of the inactive surface and a side surface of the semiconductor chip, a connection structure having first and second regions disposed sequentially on the active surface of the semiconductor chip, and including a redistribution layer electrically connected to the connection pad of the semiconductor chip and including a ground pattern layer, and a metal layer disposed on the upper surface of the first encapsulant, and extending from the upper surface of the first encapsulant to the side surface of the first region of the connection structure. The first region of the connection structure has a first width, and the second region has a second width, smaller than the first width.
    Type: Grant
    Filed: October 3, 2019
    Date of Patent: October 5, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Dongjoon Oh, Sukho Lee, Jusuk Kang
  • Patent number: 11139250
    Abstract: The present disclosure relates to a shielded integrated module, which includes a module substrate with a number of perimeter bond pads, at least one electronic component attached to the module substrate and encapsulated by a mold compound, a number of perimeter vertical shield contacts, and a shielding structure. The perimeter bond pads are surrounding the at least one electronic component and encapsulated by the mold compound. Each perimeter vertical shield contact is coupled to a corresponding perimeter bond pad and extends through the mold compound, such that a top tip of each perimeter vertical shield contact is exposed at a top surface of the mold compound. The shielding structure completely covers the top surface of the mold compound and is in contact with the perimeter vertical shield contacts.
    Type: Grant
    Filed: August 19, 2019
    Date of Patent: October 5, 2021
    Assignee: Qorvo US, Inc.
    Inventors: Mohsen Haji-Rahim, Howard Joseph Holyoak
  • Patent number: 11127714
    Abstract: A semiconductor device implements upper and lower arms for three phases by a plurality of semiconductor chips, an insulated circuit board, and a printed board, the printed board includes: a plurality of upper relay pattern layers arranged on one main surface of an insulating layer; an upper common pattern layer arranged on the one main surface of the insulating layer; a plurality of lower relay pattern layers arranged to be opposed to the upper relay pattern layers on another main surface opposite to the one main surface of the insulating layer; and a lower common pattern layer arranged to be opposed to the upper common pattern layer on the other main surface of the insulating layer, and control wires electrically connected to the semiconductor chips are partly provided in regions between the upper relay pattern layers and the upper common pattern layer.
    Type: Grant
    Filed: June 1, 2020
    Date of Patent: September 21, 2021
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Hideyo Nakamura
  • Patent number: 11121094
    Abstract: A semiconductor device includes a lead frame, an electronic device, a package body, and a first shield plate. The lead frame includes a die mount structure, signal leads, a first shield lead, a second shield lead, and a first shield mount that spans the first and second shield leads. The electronic device can be mounted to the die mount structure and can be coupled to the signal leads. The package body encapsulates the electronic device and the lead frame such that (i) each of the first shield lead, the second shield lead, and the signal leads includes an external portion that extends beyond the exterior surface of the package body, and (ii) the first shield mount extends beyond the exterior surface of the package body. The first shield plate can be coupled to the first shield mount.
    Type: Grant
    Filed: June 20, 2019
    Date of Patent: September 14, 2021
    Assignee: AMKOR TECHNOLOGY SINGAPORE HOLDING PTE. LTD.
    Inventors: Yoshio Matsuda, Kenji Nishikawa, Seiichiro Sato, Yoshihiko Ikemoto
  • Patent number: 11095090
    Abstract: A laser module includes an encapsulating support, at least one laser, a sealing gasket, and a pressing plate. Each laser includes a supporting plate and a laser body that is fixed to the supporting plate. The supporting plate is fixed on the encapsulating support, and a surface of an end of the laser body away from the supporting plate is a light exit end face. The sealing gasket is located on a surface of the supporting plate close to the light exit end face, and the sealing gasket has a first opening at a position corresponding to the laser body. A pressing plate is located on a surface of the sealing gasket away from the supporting plate; the pressing plate is fixedly connected to the encapsulating support, and the pressing plate has a second opening at a position corresponding to the first opening.
    Type: Grant
    Filed: July 3, 2018
    Date of Patent: August 17, 2021
    Assignee: Qingdao Hisense Laser Display Co., Ltd.
    Inventors: Longfei Shi, Xintuan Tian
  • Patent number: 11075180
    Abstract: A semiconductor device includes a semiconductor element having a plated portion on a part of a main surface and a protective member that seals surfaces of the semiconductor element except for the main surface, wherein the plated portion is electrically connected to a circuit in the semiconductor element.
    Type: Grant
    Filed: August 4, 2017
    Date of Patent: July 27, 2021
    Assignee: AOI Electronics Co., Ltd.
    Inventor: Katsuhiro Takao
  • Patent number: 11075186
    Abstract: A semiconductor package includes a substrate, a semiconductor chip and a heat dissipation structure. The semiconductor chip includes a first surface, a second surface opposite to the first surface, and at least one chip pad disposed adjacent to the first surface. The chip pad is electrically connected to the substrate. The heat dissipation structure is disposed adjacent to the second surface of the semiconductor chip and a portion of the substrate. An area of the heat dissipation structure is greater than an area of the semiconductor chip.
    Type: Grant
    Filed: February 9, 2017
    Date of Patent: July 27, 2021
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Ian Hu, Jia-Rung Ho, Jin-Feng Yang, Chih-Pin Hung, Ping-Feng Yang
  • Patent number: 11075243
    Abstract: An image sensor includes a substrate including a light-receiving region and a light-shielding region, a device isolation pattern in the substrate of the light-receiving region to define active pixels, and a device isolation region in the substrate of the light-shielding region to define reference pixels. An isolation technique of the device isolation pattern is different from that of the device isolation region.
    Type: Grant
    Filed: June 22, 2020
    Date of Patent: July 27, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Yun Ki Lee
  • Patent number: 11075193
    Abstract: A semiconductor package includes a connection structure including an insulating layer, a redistribution layer disposed on the insulating layer, and a connection via penetrating through the insulating layer and connected to the redistribution layer, a frame disposed on the connection structure and having a through-hole, a semiconductor chip disposed in the through-hole on the connection structure and having a connection pad disposed to face the connection structure, and a passive component disposed on the frame.
    Type: Grant
    Filed: May 21, 2019
    Date of Patent: July 27, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Myung Sam Kang, Young Gwan Ko, Yong Jin Park, Seon Hee Moon
  • Patent number: 11069626
    Abstract: A molding compound and a semiconductor arrangement with a molding compound are disclosed. The molding compound includes a matrix and a filler including filler particles. The filler particles each include a core with an electrically conducting or a semiconducting material and an electrically insulating cover.
    Type: Grant
    Filed: April 16, 2019
    Date of Patent: July 20, 2021
    Assignee: Infineon Technologies AG
    Inventors: Anton Mauder, Oliver Hellmund, Peter Irsigler, Hanno Melzner, Stefan Miethaner, Sebastian Schmidt, Hans-Joachim Schulze
  • Patent number: 11069623
    Abstract: Provided is a semiconductor package. The semiconductor package may include a substrate, a semiconductor chip on the substrate, a passive element on the substrate, a conductive structure on the substrate, and an interposer substrate on the semiconductor chip, the passive element, and the conductive structure. The interposer substrate may be electrically connected to the conductive structure. A height of the passive element may be greater than a height of the semiconductor chip.
    Type: Grant
    Filed: April 16, 2019
    Date of Patent: July 20, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Heungkyu Kwon
  • Patent number: 11062977
    Abstract: Various embodiments of the present application are directed towards an integrated circuit (IC) in which a shield structure blocks the migration of charge to a semiconductor device from proximate a through substrate via (TSV). In some embodiments, the IC comprises a substrate, an interconnect structure, the semiconductor device, the TSV, and the shield structure. The interconnect structure is on a frontside of the substrate and comprises a wire. The semiconductor device is on the frontside of the substrate, between the substrate and the interconnect structure. The TSV extends completely through the substrate, from a backside of the substrate to the wire, and comprises metal. The shield structure comprises a PN junction extending completely through the substrate and directly between the semiconductor device and the TSV.
    Type: Grant
    Filed: August 28, 2019
    Date of Patent: July 13, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Min-Feng Kao, Dun-Nian Yaung, Hsing-Chih Lin, Jen-Cheng Liu, Wei-Tao Tsai