With Shielding (e.g., Electrical Or Magnetic Shielding, Or From Electromagnetic Radiation Or Charged Particles) Patents (Class 257/659)
  • Patent number: 11830795
    Abstract: A semiconductor device includes a base plate, a substrate, a semiconductor element, a case, and a wiring terminal. The case is disposed on the base plate so as to cover the substrate and the semiconductor element. The wiring terminal is electrically connected to the semiconductor element. The case includes a first case unit and a second case unit that is separate from the first case unit. The wiring terminal includes a first wiring unit and a second wiring unit. The first wiring unit is disposed so as to protrude from an inside to an outside of the case, and is electrically connected to the semiconductor element. The second wiring unit is bent with respect to the first wiring unit and disposed outside the case. The first case unit and the second case unit are disposed so as to sandwich the first wiring unit.
    Type: Grant
    Filed: July 4, 2019
    Date of Patent: November 28, 2023
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Yuji Sato, Yoshinori Yokoyama, Motoru Yoshida, Jun Fujita
  • Patent number: 11823996
    Abstract: The present disclosure relates to a semiconductor module, especially a power semiconductor module, in which the heat dissipation is improved and the power density is increased. The semiconductor module may include at least two electrically insulating substrates, each having a first main surface and a second main surface opposite to the first main surface. On the first main surface of each of the substrates, at least one semiconductor device is mounted. An external terminal is connected to the first main surface of at least one of the substrates. The substrates are arranged opposite to each other so that their first main surfaces are facing each other.
    Type: Grant
    Filed: January 21, 2022
    Date of Patent: November 21, 2023
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Hamit Duran, Junfu Hu
  • Patent number: 11818889
    Abstract: A vertical memory device includes a substrate with a cell region, a through via region on opposite sides of the cell region, and a mold region surrounding the cell and through via regions, gate electrodes spaced apart from each other along a first direction vertical to an upper surface of the substrate, and extending in a second direction parallel to the upper surface of the substrate, a channel extending in the first direction on the cell region, and extending through at least a portion of the stacked gate electrodes, and a first mold including first and second layers alternately and repeatedly stacked along the first direction on the mold region, the first and second layers including different insulation materials from each other, and each of the second layers of the first mold being at the same height as and contact a corresponding one of the gate electrodes.
    Type: Grant
    Filed: January 3, 2022
    Date of Patent: November 14, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Junhyoung Kim, Seonho Yoon, Bonghyun Choi
  • Patent number: 11817438
    Abstract: Embodiments include systems in packages (SiPs) and a method of forming the SiPs. A SiP includes a package substrate and a first modularized sub-package over the package substrate, where the first modularized sub-package includes a plurality of electrical components, a first mold layer, and a redistribution layer. The SiP also includes a stack of dies over the package substrate, where the first modularized sub-package is disposed between the stack of dies. The SiP further includes a plurality of interconnects coupled to the stack of dies, the first modularized sub-package, and the package substrate, wherein the redistribution layer of the first modularized sub-package couples the stack of dies to the package substrate with the plurality of interconnects. The SiP may enable the redistribution layer of the first modularized sub-package to couple the electrical components to the stacked dies and the package substrate without a solder interconnect.
    Type: Grant
    Filed: January 14, 2019
    Date of Patent: November 14, 2023
    Assignee: Intel Corporationd
    Inventors: Hyoung Il Kim, Bilal Khalaf, Juan E. Dominguez, John G. Meyers
  • Patent number: 11810871
    Abstract: A self-destructing device includes a frangible substrate having at least one pre-weakened area. A heater is thermally coupled to the frangible substrate proximate to or at the pre-weakened area. When activated, the heater generates heat sufficient to initiate self-destruction of the frangible substrate by fractures that propagate from the pre-weakened area and cause the frangible substrate to break into many pieces.
    Type: Grant
    Filed: December 17, 2020
    Date of Patent: November 7, 2023
    Assignee: Palo Alto Research Center Incorporated
    Inventors: Christopher L. Chua, Norine Chang, Gregory Whiting
  • Patent number: 11810867
    Abstract: Apparatuses relating generally to a microelectronic package having protection from interference are disclosed. In an apparatus thereof, a substrate has an upper surface and a lower surface opposite the upper surface and has a ground plane. A first microelectronic device is coupled to the upper surface of the substrate. Wire bond wires are coupled to the ground plane for conducting the interference thereto and extending away from the upper surface of the substrate. A first portion of the wire bond wires is positioned to provide a shielding region for the first microelectronic device with respect to the interference. A second portion of the wire bond wires is not positioned to provide the shielding region. A second microelectronic device is coupled to the substrate and located outside of the shielding region. A conductive surface is over the first portion of the wire bond wires for covering the shielding region.
    Type: Grant
    Filed: August 23, 2022
    Date of Patent: November 7, 2023
    Assignee: Invensas LLC
    Inventors: Abiola Awujoola, Zhuowen Sun, Wael Zohni, Ashok S. Prabhu, Willmar Subido
  • Patent number: 11802040
    Abstract: The present invention discloses a system for protecting a MEMS product from an ESD event, including, a control circuit; a MEMS product, electrically connected with the control circuit; an ESD protection device, electrically connected with the control circuit, and electrically connected with the MEMS product in parallel; wherein, the ESD protection device comprises: a top electrode assembly electrically connected with the control circuit; a flexible beam comprising a first electrode layer electrically connected with the control circuit, a second electrode layer electrically connected with the MEMS product, and a moving metal contact electrically connected with the second electrode layer; a bottom electrode assembly having a bottom electrode layer electrically connected with the MEMS product and a fixed metal contact electrically connected with the bottom electrode layer and facing the moving metal contact.
    Type: Grant
    Filed: January 18, 2021
    Date of Patent: October 31, 2023
    Assignee: AAC Technologies Pte. Ltd.
    Inventor: David Molinero Giles
  • Patent number: 11804448
    Abstract: A module is provided with a substrate including a principal surface, a plurality of electronic components arranged on the principal surface, a sealing resin covering the principal surface and the plurality of electronic components and including a trench between any of the plurality of electronic components, a ground electrode arranged on the principal surface, a conductive layer covering the sealing resin, and a magnetic member. The conductive layer is electrically connected to the ground electrode by a connecting conductor arranged so as to penetrate the sealing resin. The magnetic member includes a magnetic plate member arranged so as to cover the sealing resin and a magnetic wall member arranged in a wall shape in the trench. The connecting conductor and the magnetic wall member both fill the trench in a state of being formed in the trench.
    Type: Grant
    Filed: March 25, 2021
    Date of Patent: October 31, 2023
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Yoshihito Otsubo, Tetsuya Oda
  • Patent number: 11798895
    Abstract: A quantum device (100) includes an interposer (112), a quantum chip (111) mounted on the interposer (112), and a shield part (150) provided so as to surround a quantum circuit region of the interposer (112) and the quantum chip (111). Accordingly, the quantum device (100) is able to prevent interference in the quantum circuit region due to exogenous noise.
    Type: Grant
    Filed: June 24, 2021
    Date of Patent: October 24, 2023
    Assignee: NEC CORPORATION
    Inventors: Kenji Nanba, Ayami Yamaguchi, Akira Miyata, Katsumi Kikuchi, Suguru Watanabe, Takanori Nishi, Hideyuki Satou
  • Patent number: 11791535
    Abstract: A radio frequency (RF) system including first and second planar RF devices coupled by non-galvanic interconnect. According to various embodiments, a first RF device and a second RF device are separated by a dielectric layer, each of the first and second RF devices including a plurality of pads disposed on surface and surrounded by a common electrode, the common electrode configured as a grounded metal shield, wherein pads of the first RF device and pads of the second RF device face each other to provide capacitive coupling between the pads. The disclosure may reduce complexity and size of the system, and offer more reliable and easily producible interconnection between elements of the RF system.
    Type: Grant
    Filed: September 28, 2021
    Date of Patent: October 17, 2023
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Mikhail Nikolaevich Makurin, Elena Aleksandrovna Shepeleva, Chongmin Lee
  • Patent number: 11791326
    Abstract: A multichip module with a vertical stack of a logic chip, a translator chip, and at least one memory chip. The multichip module includes a logic chip, a translator chip over and vertically connecting to the logic chip, and at least one memory chip above and vertically connecting to the translator chip where the translator chip is one of a chip with active devices or a passive chip.
    Type: Grant
    Filed: May 10, 2021
    Date of Patent: October 17, 2023
    Assignee: International Business Machines Corporation
    Inventors: Mukta Ghate Farooq, Arvind Kumar, Ravi Nair
  • Patent number: 11764161
    Abstract: Semiconductor device assemblies with improved ground connections, and associated systems and methods are disclosed. In one embodiment, a semiconductor device assembly may include one or more semiconductor dies mounted on an upper surface of a package substrate. Further, the package substrate includes a bond pad disposed on the upper surface, which may be designated as a ground node for the semiconductor device assembly. The bond pad may be electrically connected to an electromagnetic interference (EMI) shield of the semiconductor device assembly through a conductive component attached to the bond pad and configured to be in contact with the EMI shield at a sidewall surface or a top surface of the semiconductor device assembly, thereby forming the ground connection. Such ground connection may reduce a processing time to form the EMI shield while improving yield and reliability performance of the semiconductor device assemblies.
    Type: Grant
    Filed: December 6, 2019
    Date of Patent: September 19, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Jong Sik Paek, Youngik Kwon, Yeongbeom Ko
  • Patent number: 11764162
    Abstract: An electronic package and a manufacturing method thereof are provided, where a plurality of shielding wires are arranged on a carrier and spanning across an electronic component to cover the electronic component, so that the shielding wires serve as a shielding structure to protect the electronic component from the interference of external electromagnetic waves.
    Type: Grant
    Filed: August 19, 2020
    Date of Patent: September 19, 2023
    Assignee: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Ming-Fan Tsai, Chih-Wei Chen, Tsung-Hsien Tsai, Chao-Ya Yang, Chia-Yang Chen
  • Patent number: 11760627
    Abstract: A microelectromechanical system (MEMS) sensor package includes a laminate that provides physical support and electrical connection to a MEMS sensor. A resin layer is embedded within an opening of the laminate and a MEMS support layer is embedded within the opening by the resin layer. A MEMS structure of the MEMS sensor is located on the upper surface of the MEMS support layer.
    Type: Grant
    Filed: June 10, 2021
    Date of Patent: September 19, 2023
    Assignee: InvenSense, Inc.
    Inventors: Roberto Brioschi, Benyamin Gholami Bazehhour, Milena Vujosevic, Kazunori Hayata
  • Patent number: 11756904
    Abstract: A semiconductor device package includes a substrate, a reflector, a radiator and a first director. The reflector is disposed on a surface of the substrate. The radiator is disposed over the reflector. The first director is disposed over the radiator. The reflector, the radiator and the first director have different elevations with respect to the surface of the substrate. The radiator and the first director define an antenna.
    Type: Grant
    Filed: June 8, 2020
    Date of Patent: September 12, 2023
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Yuanhao Yu, Cheng-Lin Ho, Yu-Lin Shih, Shih-Chun Li
  • Patent number: 11756867
    Abstract: A power module is disclosed. A power module according to an embodiment of the present disclosure may include a first substrate and a second substrate spaced apart from each other, an electronic device unit provided on at least either one of the first and second substrates, and a lead frame unit provided between the first and second substrates. One side of the lead frame unit may be connected to an external circuit, and the other side thereof may be configured to electrically connect the first and second substrates. Accordingly, the lead frame unit may perform a function of electrically connecting the first and second substrates instead of a via spacer in the related art.
    Type: Grant
    Filed: September 30, 2020
    Date of Patent: September 12, 2023
    Assignee: LG ELECTRONICS INC.
    Inventors: Siho Choi, Seongmoo Cho, Oksun Yu, Kwangsoo Kim, Gun Lee
  • Patent number: 11756896
    Abstract: A semiconductor package structure and a method for manufacturing a semiconductor package structure are provided. The semiconductor package structure includes an electronic component, a conductive contact, and a first shielding layer. The electronic component has a first surface, a lateral surface angled with the first surface, and a second surface opposite to the first surface. The conductive contact is connected to the first surface of the electronic component. The first shielding layer is disposed on the lateral surface of the electronic component and a portion of the first surface of the electronic component. The first shielding layer contacts the conductive contact.
    Type: Grant
    Filed: December 3, 2020
    Date of Patent: September 12, 2023
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Cheng-Yuan Kung, Meng-Wei Hsieh
  • Patent number: 11742252
    Abstract: Several aspects of the present technology are directed toward fan-out packaged semiconductor devices having an integrated shield. The shield can include a conductive wall and a conductive cap over a redistribution structure. The shield can surround or at least partially enclose circuits placed or formed on the redistribution structure. The circuits and/or the conductive cap can be covered by an encapsulant, and the conductive cap can be on an upper surface of an encapsulant.
    Type: Grant
    Filed: September 23, 2021
    Date of Patent: August 29, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Fumitomo Watanabe, Keiyo Kusanagi
  • Patent number: 11735364
    Abstract: A multilayer electronic component includes a body including a dielectric layer and an internal electrode; and an external electrode including an electrode layer disposed on the body and connected to the internal electrode and a conductive resin layer disposed on the electrode layer, and the conductive resin layer includes a metal wire, a conductive metal, and a base resin.
    Type: Grant
    Filed: October 27, 2021
    Date of Patent: August 22, 2023
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Jun Hyeon Kim, Hae Sol Kang, Bon Seok Koo, San Kyeong, Chang Hak Choi, Jung Min Kim
  • Patent number: 11728248
    Abstract: A method of making a semiconductor device may include providing a large semiconductor die comprising conductive interconnects with a first encapsulant disposed over four side surfaces of the large semiconductor die, over the active surface of the large semiconductor die, and around the conductive interconnects. A first build-up interconnect structure may be formed over the large semiconductor die and over the first encapsulant. Vertical conductive interconnects may be formed over the first build-up interconnect structure and around an embedded device mount site. An embedded device comprising through silicon vias (TSVs) may be disposed over the embedded device mount site. A second encapsulant may be disposed over the build-up structure, and around at least five sides of the embedded device. A second build-up structure may be formed disposed over the planar surface and configured to be electrically coupled to the TSVs of the embedded device and the vertical conductive interconnects.
    Type: Grant
    Filed: June 16, 2022
    Date of Patent: August 15, 2023
    Assignee: Deca Technologies USA, Inc.
    Inventors: Robin Davis, Timothy L. Olson, Craig Bishop, Clifford Sandstrom
  • Patent number: 11710689
    Abstract: A semiconductor device package includes a substrate, a first solder paste, an electrical contact and a first encapsulant. The substrate includes a conductive pad. The first solder paste is disposed on the pad. The electrical contact is disposed on the first solder paste. The first encapsulant encapsulates a portion of the electrical contact and exposes the surface of the electrical contact. The electrical contact has a surface facing away from the substrate. A melting point of the electrical contact is greater than that of the first solder paste. The first encapsulant includes a first surface facing toward the substrate and a second surface opposite to the first surface. The second surface of the first encapsulant is exposed to air.
    Type: Grant
    Filed: December 8, 2020
    Date of Patent: July 25, 2023
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Chang-Lin Yeh, Yu-Chang Chen
  • Patent number: 11699665
    Abstract: A semiconductor module includes a main board and external terminals. A package substrate includes a core insulation layer, a conductive pattern disposed in the core insulation layer and electrically connected with the external terminals, an upper insulation pattern and a lower insulation pattern. At least one semiconductor chip is disposed on an upper surface of the package substrate and is electrically connected with the conductive pattern. A shielding plate is disposed on a molding member and lateral side surfaces of the package substrate and shields electromagnetic interference (EMI) emitted from the semiconductor chip. A shielding fence extends from an edge portion of a lower surface of the lower insulation pattern and directly contacts the upper surface of the main board. The shielding fence surrounds the external terminals and shields EMI emitted from the external terminals. A reinforcing member increases a strength of the shielding fence.
    Type: Grant
    Filed: February 10, 2021
    Date of Patent: July 11, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Beoungjun Choi
  • Patent number: 11699679
    Abstract: A semiconductor package including a first lower stack on a substrate and including first lower semiconductor chips, a redistribution substrate on the first lower stack, a redistribution connector electrically connecting the substrate to the redistribution substrate, a first upper stack on the redistribution substrate and including first upper semiconductor chips, a first upper connector electrically connecting the redistribution substrate to the first upper stack, a second upper stack horizontally spaced apart from the first upper stack and including second upper semiconductor chips, and a second upper connector electrically connecting the redistribution substrate to the second upper stack may be provided. The redistribution connector may be on one side of the redistribution substrate. The first upper connector may be on one side of the first upper stack. The second upper connector may be on one side of the second upper stack.
    Type: Grant
    Filed: May 27, 2021
    Date of Patent: July 11, 2023
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Tae-Ho Kang
  • Patent number: 11683880
    Abstract: Encapsulated PCB assembly (1) for electrical connection to a high- or medium-voltage power conductor in a power distribution network of a national grid, comprising a) a PCB (10), delimited by a peripheral edge (20) and comprising a high-tension pad (60, 62) on a voltage of at least one kilovolt, b) an electrically insulating encapsulation body (70) in surface contact with, and enveloping, the high-tension pad and at least a portion of the PCB edge adjacent to the high-tension pad, c) a shielding layer (80) on an external surface (90) of the encapsulation body and for being held on electrical ground or on a low voltage to shield at least a low-voltage portion of the PCB. The high-tension pad extends to the peripheral edge of the PCB.
    Type: Grant
    Filed: October 16, 2019
    Date of Patent: June 20, 2023
    Assignee: 3M INNOVATIVE PROPERTIES COMPANY
    Inventors: Gunther A. J. Stollwerck, Mark Gravermann, Jens Weichold, Sebastian Eggert-Richter, Michael H. Stalder
  • Patent number: 11664327
    Abstract: A semiconductor package has a substrate, a first component disposed over the substrate, an encapsulant deposited over the first component, and a second component disposed over the substrate outside the encapsulant. A metal mask is disposed over the second component. A shielding layer is formed over the semiconductor package. The metal mask after forming the shielding layer. The shielding layer is optionally formed on a contact pad of the substrate while a conic area above the contact pad that extends 40 degrees from vertical remains free of the encapsulant and metal mask while forming the shielding layer. Surfaces of the metal mask and encapsulant oriented toward the contact pad can be sloped. The metal mask can be disposed and removed using a pick-and-place machine.
    Type: Grant
    Filed: November 17, 2020
    Date of Patent: May 30, 2023
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: HunTeak Lee, KyungHwan Kim, HeeSoo Lee, ChangOh Kim, KyoungHee Park, JinHee Jung, OMin Kwon, JiWon Lee, YuJeong Jang
  • Patent number: 11658128
    Abstract: The embodiments herein relate to packages of semiconductor devices having a shielding element and methods of forming the same. An assembly is provided. The assembly includes a semiconductor chip having a passive component and a package within which the semiconductor chip is positioned in. The package includes a shielding element and a package conductive component, and the package conductive component is electrically coupled with the passive component of the semiconductor chip.
    Type: Grant
    Filed: August 19, 2021
    Date of Patent: May 23, 2023
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Ranjan Rajoo, Venkata Narayana Rao Vanukuru
  • Patent number: 11637078
    Abstract: A semiconductor package includes a first semiconductor device, a second semiconductor device vertically positioned above the first semiconductor device, and a ground shielded transmission path. The ground shielded transmission path couples the first semiconductor device to the second semiconductor device. The ground shielded transmission path includes a first signal path extending longitudinally between a first end and a second end. The first signal path includes a conductive material. A first insulating layer is disposed over the signal path longitudinally between the first end and the second end. The first insulating layer includes an electrically insulating material. A ground shielding layer is disposed over the insulating material longitudinally between the first end and the second end of the signal path. The ground shielding layer includes a conductive material coupled to ground.
    Type: Grant
    Filed: February 22, 2021
    Date of Patent: April 25, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Feng Wei Kuo, Wen-Shiang Liao, Chewn-Pu Jou, Huan-Neng Chen, Lan-Chou Cho, William Wu Shen
  • Patent number: 11632883
    Abstract: A method of manufacturing an electronic component includes temporarily fixing an electronic component body to a support with a temporary fixation material having an area smaller than that of the electronic component body interposed therebetween, disposing a shield resin layer having an area larger than that of an upper surface of the electronic component body on the upper surface of the electronic component body, and applying pressure to the shield resin layer via an elastic layer and causing the shield resin layer to adhere such that the shield resin layer extends from the upper surface that is the surface of the electronic component body opposite to the temporary fixation material to a bottom surface that is a surface of the electronic component body that faces the temporary fixation material via side surfaces of the electronic component body.
    Type: Grant
    Filed: August 27, 2021
    Date of Patent: April 18, 2023
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Yoshiharu Suemori
  • Patent number: 11626337
    Abstract: In one example, a semiconductor device comprises a main substrate comprising a first side and a main conductive structure, and a first component module over the first side of the main substrate. The first component module comprises a first electronic component and a first module encapsulant contacting a lateral side of the first electronic component. The semiconductor device further comprises a second component module over the first side of the main substrate. The second component module comprises a second electronic component and a second module encapsulant contacting a lateral side of the second electronic component. The semiconductor device further comprises a main encapsulant over a first side of the main substrate and between the first component module and the second component module. Other examples and related methods are also disclosed herein.
    Type: Grant
    Filed: May 19, 2020
    Date of Patent: April 11, 2023
    Assignee: Amkor Technology Singapore Holding Pte. Ltd.
    Inventor: Cheol Ho Lee
  • Patent number: 11610847
    Abstract: A semiconductor device has a first package layer. A first shielding layer is formed over the first package layer. The first shielding layer is patterned to form a redistribution layer. An electrical component is disposed over the redistribution layer. An encapsulant is deposited over the electrical component. A second shielding layer is formed over the encapsulant. The second shielding layer is patterned. The patterning of the first shielding layer and second shielding layer can be done with a laser. The second shielding layer can be patterned to form an antenna.
    Type: Grant
    Filed: May 7, 2021
    Date of Patent: March 21, 2023
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: ChangOh Kim, KyoungHee Park, SeongHwan Park, JinHee Jung
  • Patent number: 11605603
    Abstract: Embodiments may relate to a microelectronic package that includes a radio frequency (RF) chip coupled with a die by interconnects with a first pitch. The RF chip may further be coupled with a waveguide of a package substrate by interconnects with a second pitch that is different than the first pitch. The RF chip may facilitate conveyance of data to the waveguide as an electromagnetic signal with a frequency greater than approximately 20 gigahertz (GHz). Other embodiments may be described or claimed.
    Type: Grant
    Filed: April 29, 2019
    Date of Patent: March 14, 2023
    Assignee: Intel Corporation
    Inventors: Adel A. Elsherbini, Georgios Dogiamis, Telesphor Kamgaing, Henning Braunisch, Johanna M. Swan, Shawna M. Liff, Aleksandar Aleksov
  • Patent number: 11602089
    Abstract: In a high-frequency module provided with a shield member between components, improvement in the degree of freedom in design such as arrangement of components or the like is achieved while preventing damage to a wiring board. A high-frequency module (1a) includes a multilayer wiring board (2), a plurality of components (3a) and (3b) mounted on an upper surface (20a) of the multilayer wiring board (2), and a shield member (5) for shielding between the component (3a) and the component (3b), in which the shield member (5) is formed in a flat plate shape, with a plurality of metal pins (5a) each stacked in a thickness direction of the sealing resin layer (4) such that a length direction is made to be substantially parallel to the upper surface (20a) of the multilayer wiring board (2), and a resin molded portion (5b) for fixing the metal pins (5a).
    Type: Grant
    Filed: May 19, 2020
    Date of Patent: March 7, 2023
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Yoshihito Otsubo, Yosuke Matsushita
  • Patent number: 11594500
    Abstract: In a method of manufacturing a semiconductor package, a first semiconductor device is arranged on a package substrate. An electrostatic discharge structure is formed on at least one ground substrate pad exposed from an upper surface of the package substrate. A plurality of second semiconductor devices is stacked on the package substrate and spaced apart from the first semiconductor device, the electrostatic discharge structure being interposed between the first semiconductor device and the plurality of second semiconductor devices. A molding member is formed on the package substrate to cover the first semiconductor device and the plurality of second semiconductor devices.
    Type: Grant
    Filed: December 23, 2020
    Date of Patent: February 28, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Se-Jin Yoo, Hong-Sub Joo, Won-Gil Han
  • Patent number: 11587884
    Abstract: A patterned ground shield device includes a first patterned ground shield layer and a second patterned ground shield layer. The first patterned ground shield layer is located on a first layer, and the second patterned ground shield layer is located on a second layer. The first patterned ground shield layer includes a plurality of first strip-shaped structures, and each of the first strip-shaped structures includes an oxide diffusion material. The second patterned ground shield layer includes a plurality of second strip-shaped structures, and each of the second strip-shaped structures includes a conductive material, wherein the first strip-shaped structures and the second strip-shaped structures are disposed to each other in an interlaced manner.
    Type: Grant
    Filed: June 18, 2021
    Date of Patent: February 21, 2023
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Hsiao-Tsung Yen, Sheng-Hung Lin, Han-Chang Kang
  • Patent number: 11587840
    Abstract: Provided is a semiconductor device including: a substrate; an electrode layer provided on the substrate; a semiconductor chip being provided on the electrode layer, including a first side surface portion having a first angle with respect to a substrate surface of the substrate, and including a second side surface portion being provided below the first side surface portion and having a second angle smaller than the first angle with respect to the substrate surface; and a resin being provided around the electrode layer and the semiconductor chip and being in contact with the first side surface portion and the second side surface portion.
    Type: Grant
    Filed: September 4, 2020
    Date of Patent: February 21, 2023
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventor: Hideyuki Yamauchi
  • Patent number: 11581238
    Abstract: A heat spreading material is integrated into a composite die structure including a first IC die having a first dielectric material and a first electrical interconnect structure, and a second IC die having a second dielectric material and a second electrical interconnect structure. The composite die structure may include a composite electrical interconnect structure comprising the first interconnect structure in direct contact with the second interconnect structure at a bond interface. The heat spreading material may be within at least a portion of a dielectric area through which the bond interface extends. The heat spreading material may be located within one or more dielectric materials surrounding the composite interconnect structure, and direct a flow of heat generated by one or more of the first and second IC dies.
    Type: Grant
    Filed: May 12, 2021
    Date of Patent: February 14, 2023
    Assignee: Intel Corporation
    Inventors: Shawna Liff, Adel Elsherbini, Johanna Swan, Jimin Yao, Veronica Strong
  • Patent number: 11581268
    Abstract: A semiconductor package includes a semiconductor die, a redistribution structure and connective terminals. The redistribution structure is disposed on the semiconductor die and includes a first metallization tier disposed in between a pair of dielectric layers. The first metallization tier includes routing conductive traces electrically connected to the semiconductor die and a shielding plate electrically insulated from the semiconductor die. The connective terminals include dummy connective terminals and active connective terminals. The dummy connective terminals are disposed on the redistribution structure and are electrically connected to the shielding plate. The active connective terminals are disposed on the redistribution structure and are electrically connected to the routing conductive traces. Vertical projections of the dummy connective terminals fall on the shielding plate.
    Type: Grant
    Filed: December 6, 2021
    Date of Patent: February 14, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Cheng Wu, Chien-Chia Chiu, Cheng-Hsien Hsieh, Li-Han Hsu, Meng-Tsan Lee, Tsung-Shu Lin
  • Patent number: 11545733
    Abstract: The disclosure relates to a communication method and system for converging a 5th-Generation (5G) communication system for supporting higher data rates beyond a 4th-Generation (4G) system with a technology for Internet of Things (IoT). The disclosure may be applied to intelligent services based on the 5G communication technology and the IoT-related technology, such as smart home, smart building, smart city, smart car, connected car, health care, digital education, smart retail, security and safety services. An antenna module is provided. The antenna module includes a flexible printed circuit board (FPCB) including a first surface directed in a first direction and a second surface directed in a second direction that forms a predetermined first angle with respect to the first direction, a first antenna deployed on one surface of the first surface, and a second antenna deployed on one surface of the second surface.
    Type: Grant
    Filed: February 18, 2020
    Date of Patent: January 3, 2023
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Juneseok Lee, Junsig Kum, Kwanghyun Baek, Dohyuk Ha, Jinsu Heo, Youngju Lee, Jungyub Lee
  • Patent number: 11538813
    Abstract: A method for fabricating a static random access memory (SRAM) includes the steps of: forming a gate structure on a substrate; forming an epitaxial layer adjacent to the gate structure; forming a first interlayer dielectric (ILD) layer around the gate structure; transforming the gate structure into a metal gate; forming a contact hole exposing the epitaxial layer, forming a barrier layer in the contact hole, forming a metal layer on the barrier layer, and then planarizing the metal layer and the barrier layer to form a contact plug. Preferably, a bottom portion of the barrier layer includes a titanium rich portion and a top portion of the barrier layer includes a nitrogen rich portion.
    Type: Grant
    Filed: July 8, 2020
    Date of Patent: December 27, 2022
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Ching-Wen Hung, Chun-Hsien Lin, Chien-Hung Chen
  • Patent number: 11532567
    Abstract: A package includes a device die, a molding material molding the device die therein, and a through-via penetrating through the molding material. A redistribution line is on a side of the molding material. The redistribution line is electrically coupled to the through-via. A metal ring is close to edges of the package, wherein the metal ring is coplanar with the redistribution line.
    Type: Grant
    Filed: September 12, 2019
    Date of Patent: December 20, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chen-Hua Yu, Shin-Puu Jeng, Der-Chyang Yeh, Hsien-Wei Chen, Jie Chen
  • Patent number: 11521959
    Abstract: A method includes bonding a first device die to a second device die, encapsulating the first device die in a first encapsulant, performing a backside grinding process on the second device die to reveal through-vias in the second device die, and forming first electrical connectors on the second device die to form a package. The package includes the first device die and the second device die. The method further includes encapsulating the first package in a second encapsulant, and forming an interconnect structure overlapping the first package and the second encapsulant. The interconnect structure comprises second electrical connectors.
    Type: Grant
    Filed: July 9, 2020
    Date of Patent: December 6, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chen-Hua Yu, Hung-Yi Kuo, Chung-Shi Liu, Hao-Yi Tsai, Cheng-Chieh Hsieh, Tsung-Yuan Yu, Ming Hung Tseng
  • Patent number: 11521938
    Abstract: A chip package includes a first substrate, a second substrate, a first conductive layer, and a metal layer. The first substrate has a bottom surface and an inclined sidewall adjoining the bottom surface, and an obtuse angle is between the bottom surface and the inclined sidewall. The second substrate is over the first substrate and has a portion that laterally extends beyond the inclined sidewall of the first substrate. The first conductive layer is between the first substrate and the second substrate. The metal layer is on said portion of the second substrate, on the bottom surface and the inclined sidewall of the first substrate, and electrically connected to an end of the first conductive layer.
    Type: Grant
    Filed: January 4, 2021
    Date of Patent: December 6, 2022
    Assignee: XINTEC INC.
    Inventors: Chia-Ming Cheng, Shu-Ming Chang
  • Patent number: 11515282
    Abstract: Electromagnetic shields for electronic devices, and particularly electromagnetic shields with bonding wires for sub-modules of electronic devices are disclosed. Electronic modules are disclosed that include multiple sub-modules arranged on a substrate with an electromagnetic shield arranged on or over the sub-modules. Bonding wires are disclosed that form one or more bonding wire walls along the substrate. The one or more bonding wire walls may be located between sub-modules of a module and about peripheral boundaries of the module. The electromagnetic shield may be electrically coupled to ground by way of the one or more bonding wire walls. Portions of the electromagnetic shield and the one or more bonding wire walls may form divider walls that are configured to reduce electromagnetic interference between the sub-modules or from external sources.
    Type: Grant
    Filed: May 21, 2019
    Date of Patent: November 29, 2022
    Assignee: Qorvo US, Inc.
    Inventors: Kelly M. Lear, Jeffrey Miller, Joseph Edward Geniac, Rommel Quintero
  • Patent number: 11502072
    Abstract: A device package includes a first die directly bonded to a second die at an interface, wherein the interface comprises a conductor-to-conductor bond. The device package further includes an encapsulant surrounding the first die and the second die and a plurality of through vias extending through the encapsulant. The plurality of through vias are disposed adjacent the first die and the second die. The device package further includes a plurality of thermal vias extending through the encapsulant and a redistribution structure electrically connected to the first die, the second die, and the plurality of through vias. The plurality of thermal vias is disposed on a surface of the second die and adjacent the first die.
    Type: Grant
    Filed: July 21, 2020
    Date of Patent: November 15, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chen-Hua Yu, Yung-Chi Lin, Wen-Chih Chiou
  • Patent number: 11482478
    Abstract: An electronic device package includes a first die coupled to a substrate, a second die coupled with the first die, and a spacer element coupled to the second die to form a stacked structure that includes the first die, the second die, and the spacer element. An electrically conductive shield overlies the stacked structure. The shield has a first end coupled to the spacer element and a second end coupled to the substrate. Inter-chip bond wires may electrically interconnect the first and second dies, and the shield may additionally overlie the bond wires. The spacer element may extend above a surface of the second die at a height that is sufficient to prevent the shield from touching the inter-chip bond wires.
    Type: Grant
    Filed: July 23, 2020
    Date of Patent: October 25, 2022
    Assignee: NXP B.V.
    Inventors: Crispulo Estira Lictao, Jr., Chayathorn Saklang, Amornthep Saiyajitara, Chanon Suwankasab, Stephen Ryan Hooper, Bernd Offermann
  • Patent number: 11476201
    Abstract: A package includes a redistribution structure, a die package on a first side of the redistribution structure including a first die connected to a second die by metal-to-metal bonding and dielectric-to-dielectric bonding, a dielectric material over the first die and the second die and surrounding the first die, and a first through via extending through the dielectric material and connected to the first die and a first via of the redistribution structure, a semiconductor device on the first side of the redistribution structure includes a conductive connector, wherein a second via of the redistribution structure contacts the conductive connector of the semiconductor device, a first molding material on the redistribution structure and surrounding the die package and the semiconductor device, and a package through via extending through the first molding material to contact a third via of the redistribution structure.
    Type: Grant
    Filed: March 19, 2020
    Date of Patent: October 18, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY. LTD.
    Inventors: Ming-Fa Chen, Sung-Feng Yeh, Hsien-Wei Chen
  • Patent number: 11469259
    Abstract: Methods of forming integrated circuit devices include forming a sacrificial layer on a handling substrate and forming a semiconductor active layer on the sacrificial layer. The semiconductor active layer and the sacrificial layer may be selectively etched in sequence to define an semiconductor-on-insulator (SOI) substrate, which includes a first portion of the semiconductor active layer. A multi-layer electrical interconnect network may be formed on the SOI substrate. This multi-layer electrical interconnect network may be encapsulated by an inorganic capping layer that contacts an upper surface of the first portion of the semiconductor active layer. The capping layer and the first portion of the semiconductor active layer may be selectively etched to thereby expose the sacrificial layer.
    Type: Grant
    Filed: February 4, 2021
    Date of Patent: October 11, 2022
    Assignee: X Display Company Technology Limited
    Inventors: Christopher Bower, Etienne Menard, Matthew Meitl, Joseph Carr
  • Patent number: 11462484
    Abstract: An electronic package and manufacturing method thereof are provided. The electronic package includes a substrate, a first encapsulant, a wettable flank and a shielding layer. The substrate includes a first surface, a second surface opposite to the first surface and a side surface connecting the first surface and the second surface. The first encapsulant is disposed on the first surface of the substrate. The wettable flank is exposed from the side surface of the substrate. The shielding layer covers a side surface of the first encapsulant, wherein on the side surface of the substrate, the shielding layer is spaced apart from the wettable flank.
    Type: Grant
    Filed: October 8, 2020
    Date of Patent: October 4, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: You-Lung Yen, Bernd Karl Appelt, Kay Stephan Essig
  • Patent number: 11430743
    Abstract: A transistor includes a semiconductor substrate having first and second terminals. An interconnect structure, on an upper surface of the substrate, is formed of layers of dielectric material and electrically conductive material. The conductive material includes a first pillar connected with the first terminal, a second pillar connected with the second terminal, and a shield system between the first and second pillars. The shield system includes forked structures formed in at least two conductive layers of the interconnect structure and at least partially surrounding segments of the second pillar. The shield system may additionally include shield traces formed in a first conductive layer positioned between gate fingers and the first pillars and/or the shield system may include shield runners that are located in an electrically conductive layer that is below a topmost electrically conductive layer with the first pillar being connected to a runner in the topmost conductive layer.
    Type: Grant
    Filed: April 6, 2021
    Date of Patent: August 30, 2022
    Assignee: NXP USA, Inc.
    Inventors: Humayun Kabir, Michele Lynn Miera, Charles John Lessard, Ibrahim Khalil
  • Patent number: 11431830
    Abstract: Disclosed are various embodiments relating to a circuit board included in an electronic device and, according to one embodiment, the circuit board can comprise: at least one wire included on the circuit board, at least one conductive structure arranged on the circuit board in order to reinforce the circuit board, and arranged in order to electrically connect the at least one wire; and at least one conductive member included on the circuit board, and electrically connecting the at least one wire with the at least one conductive structure, and additional other various embodiments are possible.
    Type: Grant
    Filed: March 8, 2019
    Date of Patent: August 30, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Junghoon Park, Dongyup Lee, Hyunseok Kim, Yongseung Yi, Hoyeong Lim, Seunggoo Kang, Dongil Son, Hyangbok Lee