Abstract: A shock-isolated mounting device and a method and system are provided. For example, the shock-isolated mounting device includes an enclosure configured to support the mounting device, at least one damper attached between the mounting device and the enclosure, and a thermally-conductive element disposed on a surface of the mounting device and configured to thermally couple the mounting device to the enclosure. The thermally-conductive element facilitates the dissipation of heat generated by electronic components mounted onto the shock-isolated mounting device.

Abstract: An integrated circuit is attached to a chip carrier in a flip chip configuration. An electrically conductive conformal layer is disposed on a back surface of the substrate of the integrated circuit. The electrically conductive conformal layer contacts the semiconductor material in the substrate and extending onto, and contacting, a substrate lead of the chip carrier. The substrate lead of the chip carrier is electrically coupled to a substrate bond pad of the integrated circuit. The substrate bond pad is electrically coupled through an interconnect region of the integrated circuit to the substrate of the integrated circuit. A component is attached to the chip carrier and covered with an electrically insulating material. The electrically conductive conformal layer also extends at least partially over the electrically insulating material on the component. The electrically conductive conformal layer is electrically isolated from the component by the electrically insulating material on the component.

Abstract: In accordance with various embodiments of this disclosure, stray magnetic field mitigation in an MRAM memory such as a spin transfer torque (STT) random access memory (RAM), STTRAM is described. In one embodiment, retention of bitcell bit value storage states in an STTRAM may be facilitated by generating magnetic fields to compensate for stray magnetic fields which may cause bitcells of the memory to change state. In another embodiment, retention of bitcell bit value storage states in an STTRAM may be facilitated by selectively suspending access to a row of memory to temporarily terminate stray magnetic fields which may cause bitcells of the memory to change state. Other aspects are described herein.

Abstract: A semiconductor package including an organic interposer includes: the organic interposer including insulating layers and wiring layers formed on the insulating layers; a stiffener disposed on the interposer and having a through-hole; a first semiconductor chip disposed in the organic through-hole on the organic interposer; a second semiconductor chips disposed adjacent to the first semiconductor chip in the through-hole on the organic interposer; and an underfill resin filling at least portions of the through-hole and fixing the first semiconductor chip and the second semiconductor chip, wherein the connection pads of the first semiconductor chip and the second semiconductor chip are electrically connected to each other through the wiring layers of the organic interposer.

Abstract: A method for producing a radio-frequency antenna in a conductor structural element with an encompassing layer sequence, including: providing a rigid carrier having an underside and a top side; defining an antenna assignment section on the rigid carrier; applying at least one electrically insulating layer with a recess in such a way that the antenna assignment section is exposed; placing a radio-frequency substrate above the antenna assignment section with formation of a cavity between the rigid carrier and the radio-frequency substrate; aligning and fixing the radio-frequency substrate relative to the rigid carrier; laminating the layer construction prepared in this manner such that resin material of the at least one electrically insulating layer liquefies and encloses the radio-frequency substrate with the cavity being left free; cutting the antenna assignment section out of the rigid carrier from the outer underside (remote from the layer construction) of the rigid carrier.

Abstract: A semiconductor device comprising an on-mold antenna for transmitting and/or receiving a millimeter-wave radio frequency signal is provided. The semiconductor device includes a semiconductor layer; a polymer layer proximal to the semiconductor layer; a mold proximal to the polymer layer; a plurality of nodes proximal to the semiconductor layer and distal to the polymer layer; an antenna disposed on the mold; and a conductive element providing electrical communication between the antenna and a first node. The mold may be from 500 ?m to 1000 ?m thick, such as from 750 ?m to 800 ?m thick, such as about 775 ?m.

Abstract: Various embodiments of an integrated device package with integrated antennas are disclosed. In some embodiments, an antenna can be defined along a die pad of the package. In some embodiments, an antenna can be disposed in a first packaging component, and an integrated device die can be disposed in a second packaging component. The first and second packaging components can be stacked on one another and electrically connected. In some embodiments, a package can include one or a plurality of antennas disposed along a wall of a package body. The plurality of antennas can be disposed facing different directions from the package.

Abstract: According to one embodiment, a semiconductor device includes a first board including a plurality of terminals, a semiconductor chip flip-chip mounted to the first board, and an insulating layer covering the first board and the semiconductor chip. The plurality of terminals include at least one first terminal electrically connected to the semiconductor chip, and at least one second terminal that is not connected to the semiconductor chip, wherein the at least one second terminal is not covered by the insulating layer.

Abstract: In a general aspect, an apparatus can include a semiconductor die, a substrate, and a leadframe coupled to the substrate. The apparatus can include a conductive clip coupled to the semiconductor die. The leadframe can be disposed between the semiconductor die and the substrate, and the semiconductor die can be disposed between the conductive clip and the leadframe.

Abstract: An electronic package structure is provided, including a substrate with an electronic component, an antenna element and a shielding element disposed on the substrate. The shielding element is positioned between the antenna element and the electronic component to prevent electromagnetic interference (EMI) from occurring between the antenna element and the electronic component. A method for fabricating the electronic package structure is also provided.

Abstract: A fan-out semiconductor package includes: a first connection member having a through-hole; a semiconductor chip disposed in the through-hole and having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface; an encapsulant encapsulating at least portions of the first connection member and the inactive surface of the semiconductor chip; a second connection member disposed on the first connection member and the active surface of the semiconductor chip; a resin layer disposed on the encapsulant; and a rear redistribution layer embedded in the encapsulant so that one surface thereof is exposed by the encapsulant, wherein the resin layer covers at least portions of the exposed one surface of the rear redistribution layer, and the rear redistribution layer is electrically connected to the redistribution layer of the first connection member through connection members formed in first openings penetrating through the resin layer and the encapsulant.

Abstract: A circuit board includes an upper circuit and a lower surface that are opposite to each other, a plurality of heat sink bonding pads, and a plurality of heat sink conductive pads. The heat sink bonding pads are disposed on the upper surface and electrically insulated from one another, and are used to electrically connect to a heat sink. The heat sink conductive pads are disposed on the lower surface, electrically insulated from one another, and electrically connected to the heat sink bonding pads, respectively.

Abstract: Apparatuses relating generally to a microelectronic package having protection from interference are disclosed. In an apparatus thereof, a substrate has an upper surface and a lower surface opposite the upper surface and has a ground plane. A first microelectronic device is coupled to the upper surface of the substrate. Wire bond wires are coupled to the ground plane for conducting the interference thereto and extending away from the upper surface of the substrate. A first portion of the wire bond wires is positioned to provide a shielding region for the first microelectronic device with respect to the interference. A second portion of the wire bond wires is not positioned to provide the shielding region. A second microelectronic device is coupled to the substrate and located outside of the shielding region. A conductive surface is over the first portion of the wire bond wires for covering the shielding region.

Abstract: Method for producing a conductor structural element with a layer sequence having an internal layer substrate, including the steps: providing a rigid carrier having an underside and a top side; defining a cut-out section on the rigid carrier; applying at least one electrically insulating layer with a recess in such a way that the cut-out section is exposed; placing an internal layer substrate above the cut-out section with formation of a cavity between the rigid carrier and the internal layer substrate; aligning and fixing the internal layer substrate relative to the rigid carrier; laminating the layer construction prepared in this manner such that resin material of the at least one electrically insulating layer liquefies and encloses the internal layer substrate with the cavity being left free; producing a cut-out by cutting the cut-out section out of the rigid carrier from the outer underside of the rigid carrier.

Abstract: Disclosed is an electrode structure including an electrode body, a composite layer disposed on the electrode body; a surface of the composite layer away from the electrode body being set to be a finger contact surface in a case of fingerprint recognition, wherein the composite layer is made from composite materials formed by a cured main body glue and one-dimensional nano-conductor materials distributed in the main body glue; and an end of each of the one-dimensional nano-conductor materials exposed from the finger contact surface of the composite layer, and the other of each of the one-dimensional nano-conductor materials makes contact with the electrode body. A fingerprint recognition module including the electrode structure and a manufacturing method thereof are also disclosed.

Abstract: An electroacoustic transducer includes an ultrasonic element that includes a diaphragm and a support frame, a case body that accommodates the ultrasonic element, and fixing portions that join the support frame portion to a bottom plate portion of the case body. First and second main surfaces of the diaphragm face top and bottom plate portions of the case body, respectively, and a sound hole is provided in the case body. The fixing portions are partially provided along the circumferential direction of the support frame such that a space between the second main surface and the bottom plate portion communicates with a space around the ultrasonic element, and an acoustic path connecting the first main surface and the second main surface and the sound hole is provided in the case body. The fixing portions are defined by a die bonding agent including spherical spacers.

Abstract: A method of fabricating an interposer includes: providing a carrier substrate; forming a unit redistribution layer on the carrier substrate, the unit redistribution layer including a conductive via plug and a conductive redistribution line; and removing the carrier substrate from the unit redistribution layer. The formation of the unit redistribution layer includes: forming a first photosensitive pattern layer including a first via hole pattern; forming a second photosensitive pattern layer including a second via hole pattern and a redistribution pattern on the first photosensitive pattern layer; at least partially filling insides of the first via hole pattern, the second via hole pattern, and the redistribution pattern with a conductive material; and performing planarization to make a top surface of the unit redistribution layer flat.

Abstract: A method includes bonding a first device die with a second device die. The second device die is over the first device die. A passive device is formed in a combined structure including the first and the second device dies. The passive device includes a first and a second end. A gap-filling material is formed over the first device die, with the gap-filling material including portions on opposite sides of the second device die. The method further includes performing a planarization to reveal the second device die, with a remaining portion of the gap-filling material forming an isolation region, forming a first and a second through-vias penetrating through the isolation region to electrically couple to the first device die, and forming a first and a second electrical connectors electrically coupling to the first end and the second end of the passive device.

Abstract: A method for fabricating a radio-frequency (RF) module is disclosed, the method including forming or providing a first assembly that includes a packaging substrate and an RF component mounted thereon, the first assembly further including one or more shielding-wirebonds formed relative to the RF component, and forming an overmold over the packaging substrate to substantially encapsulate the RF component and the one or more shielding-wirebonds, the overmold formed by compression molding that includes reducing a volume of melted resin in a direction having a component perpendicular to a plane defined by the packaging substrate.

Abstract: A system in package (SiP) is disclosed that uses an EMI shield to inhibit EMI or other electrical interference on the components within the SiP. A metal shield may be formed on an upper surface of an encapsulant encapsulating the SiP. The metal shield may be electrically coupled to a ground layer in a printed circuit board (PCB) to form the EMI shield around the SiP. The metal shield may be electrically coupled to the ground layer using one or more conductive structures located in the encapsulant. The conductive structures may be located on a perimeter of the components in the SiP. The conductive structures may provide a substantially vertical connection between the substrate and the shield on the upper surface of the encapsulant.

Abstract: Embodiments of the present disclosure are directed towards techniques and configurations for designing and assembling a die capable of being adapted to a number of different packaging configurations. In one embodiment an integrated circuit (IC) die may include a semiconductor substrate. The die may also include an electrically insulative material disposed on the semiconductor substrate; a plurality of electrical routing features disposed in the electrically insulative material to route electrical signals through the electrically insulative material; and a plurality of metal features disposed in a surface of the electrically insulative material. In embodiments, the plurality of metal features may be electrically coupled with the plurality of electrical routing features. In addition, the plurality of metal features may have an input/output (I/O) density designed to enable the die to be integrated with a plurality of different package configurations. Other embodiments may be described and/or claimed.

Abstract: A touch panel with a fingerprint identification function includes a cover plate, a mask layer, a flexible substrate, and a fingerprint sensing array. The mask layer is disposed on the cover plate for defining an operating region and a non-operating region of the touch panel. The flexible substrate is disposed on the mask layer and at least in the non-operating region. The fingerprint sensing array is directly disposed on the flexible substrate in the non-operating region. Through the configuration that the fingerprint sensing array is disposed on the flexible substrate, the distance between the fingerprint sensing array and a user's fingers is reduced, thereby increasing the sensitivity of fingerprint identification.

Abstract: A semiconductor device has a semiconductor wafer including a plurality of semiconductor die. An insulating layer is formed over the semiconductor wafer. A portion of the insulating layer is removed by LDA to expose a portion of an active surface of the semiconductor die. A first conductive layer is formed over a contact pad on the active surface of the semiconductor die. The semiconductor wafer is singulated to separate the semiconductor die. The semiconductor die is disposed over a carrier with the active surface of the semiconductor die offset from the carrier. An encapsulant is deposited over the semiconductor die and carrier to cover a side of the semiconductor die and the exposed portion of the active surface. An interconnect structure is formed over the first conductive layer. Alternatively, a MUF material is deposited over a side of the semiconductor die and the exposed portion of the active surface.

Abstract: A transistor device includes a field plate extending from a source contact layer and defining an opening above a gate metal layer. Coplanar with the source contact layer, the field plate is positioned close to the channel region, which helps reduce its parasitic capacitance. Meanwhile, the opening allows a gate runner layer above the field plate to access and connect to the gate metal layer, which helps reduce the resistance of the gate structure. By vertically overlapping the metal gate layer, the field plate, and the gate runner layer, the transistor device may achieve fast switching performance without incurring any size penalty.

Abstract: A semiconductor package structure including an encapsulation body, an RFIC chip, a first antenna structure, and a second antenna structure is provided. The RFIC chip may be embedded in the encapsulation body. The first antenna structure may be disposed at a lateral side of the RFIC chip, electrically connected to the RFIC chip, and include a first conductor layer and a plurality of first patches opposite to the first conductor layer. The second antenna structure may be stacked on the RFIC chip, electrically connected to the RFIC chip, and include a second conductor layer and a plurality of second patches opposite to the second conductor layer. The first patches and the second patches are located at a surface of the encapsulation body. A first distance between the first conductor layer and the first patches is different from a second distance between the second conductor layer and the second patches.

Abstract: An electronic component mounting board includes: a circuit board having a wiring layer; a pocket part provided on a main surface of one side of the circuit board; a passive component housed in the pocket part; an active component arranged above the passive component and the main surface of the one side of the circuit board and connected to the passive component; and a shield layer formed of a material containing a magnetic material and provided between a bottom surface of the pocket part and a lower surface of the passive component.

Abstract: A semiconductor package structure includes a first semiconductor die, a second semiconductor die, a plurality of conductive elements, a first encapsulant and a second encapsulant. The second semiconductor die is disposed on the first semiconductor die. The conductive elements each comprises a first portion and a second portion and are disposed around the first semiconductor die and the second semiconductor die. The first encapsulant surrounds the first semiconductor die and the respective first portions of the conductive elements. The second encapsulant covers a portion of a top portion of the first semiconductor die and surrounds the respective second portions of the conductive elements.

Abstract: An interconnect substrate includes an insulating layer having a first resin layer and a second resin layer covering an upper surface of the first resin layer, a first conductive layer having an upper surface and side surfaces covered with the first resin layer, a lower surface of the first conductive layer being exposed from a lower surface of the first resin layer, and a second conductive layer including an interconnect pattern and a via interconnect, the interconnect pattern being disposed on an upper surface of the second resin layer, the via interconnect penetrating through both the second resin layer and the first resin layer to connect the interconnect pattern to the upper surface of the first conductive layer, wherein the first resin layer is made of a resin having a higher modulus of elasticity and a lower coefficient of elongation than the second resin layer.

Abstract: A semiconductor device package includes a radio frequency front end circuit configured to process radio frequency signals, a first antenna, an antenna substrate, and a first conductive barrier. The first antenna is configured to transmit/receive a first radio frequency signal. The antenna substrate includes the first antenna. The antenna substrate is configured to transfer the first radio frequency signal between the radio frequency front end circuit and the first antenna. The first conductive barrier is configured to electromagnetically and electrostatically isolate the first antenna.

Abstract: [Object] To provide a solid-state imaging device, with which degradation of properties of a solid-state image sensor under the influence of magnetic force lines generated from wiring arranged in the package is prevented, and a solid-state imaging apparatus including the same. [Solving Means] A solid-state imaging device according to the present technology includes a package, a seal glass, a solid-state image sensor, and a shield. The package includes wiring inside and a recess. The seal glass is joined to the package and closes the recess. The solid-state image sensor is housed in a space formed by the recess and the seal glass. The shield is housed in the space and arranged on the package. The shield prevents an arrival of magnetic force lines generated from the wiring at the solid-state image sensor.

Abstract: A semiconductor device having an EMI shield layer and/or EMI shielding wires, and a manufacturing method thereof, are provided. In an example embodiment, the semiconductor device includes a semiconductor die, an EMI shield layer shielding the semiconductor die, and an encapsulating portion encapsulating the EMI shield layer. In another example embodiment, the semiconductor device further includes EMI shielding wires extending from the EMI shield layer and shielding the semiconductor die.

Abstract: The present invention provides a heat dissipation assembly and an electronic device, where the heat dissipation assembly includes: a shielding element, where a via hole is disposed on the shielding element, the shielding element is electrically connected to ground copper of a PCB board, and a heat-generating electronic element is disposed on the PCB board; a heat pipe, located on the via hole, where the heat pipe is electrically connected to the shielding element, and the heat pipe, the PCB board, and the shielding element form an electromagnetic shielding can that is used to accommodate the heat-generating electronic element; and an elastic thermal interface material, disposed between the heat pipe and the heat-generating electronic element and mutually fitted to the heat pipe and the heat-generating electronic element.

Abstract: A packaged radio-frequency device is disclosed, including a packaging substrate configured to receive one or more components, the packaging substrate including a first side and a second side. The packaging substrate may include a first component mounted on the first side of the packaging substrate and a first overmold structure implemented on the first side of the packaging substrate, the first overmold structure substantially encapsulating the first component. The packaging substrate may further include a set of through-mold connections implemented on the second side of the packaging substrate, the set of through-mold connections including signal pins and ground pins, a second component mounted on the second side of the packaging substrate, the second component being located in an area of the second side configured to implement redundant ground pins and a second overmold structure substantially encapsulating one or more of the second component or the set of through-mold connections.

Abstract: A system to protect signal integrity includes a circuit board having a secure portion and a non-secure portion. The secure portion includes a protected circuit operable for storing security relevant data, and a secure portion power-supply element. The non-secure portion includes an unprotected circuit and a non-secure portion power-supply element corresponding to the secure portion power-supply element. The secure portion and the non-secure portion element are separated by an isolation gap. A coupling element bridges the isolation gap between the secure portion and the non-secure portion. The coupling element is electrically connected to the secure portion power-supply element within the secure portion and electrically connected to the non-secure portion power-supply portion.

Abstract: A chip package module includes an encapsulation layer, a chip, a substrate and a plurality of blind-hole electrodes. The encapsulation layer includes a first surface and a second surface opposite to the first surface. The chip includes a third surface and a fourth surface opposite to the third surface. A metal bump is fabricated on the third surface of the chip. The chip is embedded into the encapsulation layer from the first surface of the encapsulation layer. The metal bump is exposed from the first surface of the encapsulation layer. The substrate includes a metal layer, wherein the metal layer of the substrate is bonded to the chip through the metal bump. The plurality of blind-hole electrodes pass through the second surface of the encapsulation layer and are electrically connected to the metal layer of the substrate.

Abstract: An information processing apparatus includes a connector, a chassis main body, and a fixing portion. The connector has a connector main body and an attachment portion which has a hole for attachment. The fixing portion includes a pair of first locking portions and a projecting portion. The pair of first locking portions project from the chassis main body so as to be located on both sides of the connector when the connector is attached, and have a flange respectively which forms a void through which the attachment portion is inserted between the flange and the chassis main body. The projection portion projects from the chassis main body to an insertion path of the connector when the attachment portion is not inserted and is configured to be pushed by the attachment portion to retreat from the insertion path when the attachment portion is inserted.

Abstract: A method of making a transparent conductive material includes: preparing a reactive solution that contains a solvent, a metal salt which is dissolved in the solvent, and a powder of graphene oxide which is dispersed in the solvent; and simultaneously reducing metal ions of the metal salt and the graphene oxide in the reactive solution to form a plurality of core-shell nanowires, each of which includes a core of a metal reduced from the metal ions, and a shell of graphene surrounding the core.

Abstract: Magnetic random access memory (MRAM) fan-out wafer level packages with package level and chip level magnetic shielding and methods of forming these magnetic shields processed at the wafer-level are disclosed. The method includes providing a MRAM wafer prepared with a plurality of MRAM dies. The MRAM wafer is processed to form a magnetic shield layer over the front side of the MRAM wafer, and the wafer is separated into a plurality of individual dies. An individual MRAM die includes front, back and lateral surfaces and the magnetic shield layer is disposed over the front surface of the MRAM die. Magnetic shield structures are provided over the individual MRAM dies. The magnetic shield structure encapsulates and surrounds back and lateral surfaces of the MRAM die. An encapsulation layer is formed to cover the individual MRAM dies which are provided with magnetic shield structures.

Abstract: A fan-out semiconductor package includes: a core member having at least one through-hole formed therein and having a metal layer disposed on an internal surface thereof; an electronic component disposed in the through-hole; an encapsulant encapsulating the core member and the electronic component; a metal plate disposed on an upper surface of the encapsulant; and a wall penetrating the encapsulant to connect the metal layer and the metal plate to each other. The wall includes sections spaced apart from each other.

Abstract: Methods, systems, and computer program products are provided for protecting data stored on a device, even when the device is powered off. The device includes a first operating system and a security module. The first operating system (OS) is the main OS for the device, managing computer resources when the device is powered up in an “on” mode. The security module is separate from the main OS, and is configured to monitor for undesired tampering of the device. The security module is implemented in hardware that functions even when the device is turned off, and thus can protect data against unauthorized access even when the device is off. The security module may be implemented in the form of a circuit, a system-on-chip (SOC), a secondary OS that executes in a processor circuit separate from the processor hardware that operates the main OS, and/or in another manner.

Abstract: Semiconductor packages with electromagnetic interference (EMI) shielding and a method of manufacture therefor is disclosed. The semiconductor packages may house single electronic components or may be a system in a package (SiP) implementation. The EMI shielding may be provided on top of and along the periphery of the semiconductor package. The EMI shielding on the periphery may be formed of cured conductive ink or cured conductive paste disposed on sidewalls of molding that encapsulates the electronic component(s) provided on the semiconductor package. The top portion of the EMI shielding may be a laminated metal sheet provided on a top surface of the molding. The semiconductor package may further have vertical portions of the EMI shielding with conductive ink filled trenches in the molding that may separate one or more electronic components from other electronic components of the semiconductor package.

Abstract: Methods of manufacturing an electronic device formed in a cavity may include providing a first substrate having a first side wall including a first metal formed along a periphery on a bottom surface thereof and surrounding an electronic circuit disposed on the bottom surface, providing a second substrate having a second side wall including a second metal and a third metal formed along a periphery on a top surface thereof, aligning the first substrate with the second substrate with the first side wall opposing and contacting the second side wall to internally define a cavity between the bottom surface of the first substrate, the top surface of the second substrate, the first side wall ,and the second side wall, and heating and bonding the first substrate and the second substrate by transient liquid phase bonding.

Abstract: A coil electronic component includes a magnetic body, wherein the magnetic body includes a substrate, and a coil part including patterned insulating films disposed on the substrate, a first plating layer formed between the patterned insulating films by plating, and a second plating layer disposed on the first plating layer.

Abstract: The disclosure relates to a device for measuring an electrical characteristic of a substrate comprising a support made of a dielectric material having a bearing surface, the support comprising an electrical test structure having a contact surface flush with the bearing surface of the support, the bearing surface of the support and the contact surface of the electrical test structure being suitable for coming into close contact with a substrate. The measurement device also comprises at least one connection bump contact formed on another surface of the support and electrically linked to the electrical test structure. This disclosure also relates to a system for characterizing a substrate and a method for measuring a characteristic of a substrate employing the measurement device.

Abstract: Disclosed herein is a method of manufacturing a semiconductor package including a semiconductor chip sealed by a sealing synthetic resin. The method includes preparing a wiring board in which upstanding encircling walls with side-surface shield layers embedded therein surround mounts on which semiconductor chips are to be mounted, mounting the semiconductor chips on the mounts surrounded by the upstanding encircling walls on the wiring board, supplying a sealing synthetic resin to spaces surrounded by the upstanding encircling walls thereby to produce an sealed board, dividing the sealed board along projected dicing lines into individual semiconductor packages, and forming an upper-surface shield layer for blocking electromagnetic waves on the semiconductor packages.

Abstract: An electronic component package includes a substrate and an electronic component mounted to the substrate, the electronic component including a bond pad. A first antenna terminal is electrically connected to the bond pad, the first antenna terminal being electrically connected to a second antenna terminal of the substrate. A package body encloses the electronic component, the package body having a principal surface. An antenna is formed on the principal surface by applying an electrically conductive coating. An embedded interconnect extends through the package body between the substrate and the principal surface and electrically connects the second antenna terminal to the antenna. Applying an electrically conductive coating to form the antenna is relatively simple thus minimizing the overall package manufacturing cost. Further, the antenna is relatively thin thus minimizing the overall package size.

Abstract: A semiconductor device has a partition fence disposed between a first attach area and a second attach area on a substrate. A first electrical component is disposed over the first attach area. A second electrical component is disposed over the second attach area. The partition fence extends above and along a length of the first electrical component and second electrical component. An encapsulant is deposited over the substrate, first electrical component, second electrical component, and partition fence. A portion of the encapsulant is removed to expose a surface of the partition fence and planarizing the encapsulant. A shielding layer is formed over the encapsulant and in contact with the surface of the partition fence. The combination of the partition fence and shielding layer compartmentalize the first electrical component and second electrical component for physical and electrical isolation to reduce the influence of EMI, RFI, and other inter-device interference.

Abstract: A chip on film package includes a base film, a patterned circuit layer, a chip and a heat dissipation sheet. The base film includes a first surface and a mounting region located on the first surface. The patterned circuit layer is disposed on the first surface. The chip is disposed on the mounting region and electrically connected to the patterned circuit layer. The heat dissipation sheet includes a first adhesive layer disposed over the base film, a second adhesive layer disposed over the first adhesive layer, and a graphite layer disposed between the first adhesive layer and the second adhesive layer, wherein at least one of the first adhesive layer and the second adhesive layer is a double-sided adhesive with carrier, which comprises two adhesives and a carrier disposed between the two adhesives.

Abstract: In accordance with an embodiment, a packaged radio frequency (RF) circuit includes a radio frequency integrated circuit (RFIC) disposed on a substrate that has plurality of receiver circuits coupled to receive ports at a first edge of the RFIC, and a first transmit circuit coupled to a first transmit port at a second edge of the RFIC. The packaged RF circuit also includes a receive antenna system disposed on the package substrate adjacent to the first edge of the RFIC and a first transmit antenna disposed on the package substrate adjacent to the second edge of the RFIC and electrically coupled to the first transmit port of the RFIC. The receive antenna system includes a plurality of receive antenna elements that are each electrically coupled to a corresponding receive port.

Abstract: The present disclosure reduces heat concentration on switching elements. A plurality of high-side transistors are connected in parallel to constitute high-side switching element. A plurality of low-side transistors are connected in parallel to constitute low-side switching element. The plurality of high-side transistors are arranged, one by one, next to the plurality of low-side transistors.