With Means To Shield Device Contained In Housing Or Package From Charged Particles (e.g., Alpha Particles) Or Highly Ionizing Radiation (i.e., Hard X-rays Or Shorter Wavelength) Patents (Class 257/660)
  • Patent number: 10410975
    Abstract: A processed semiconductor wafer has layered elements that define electrical circuits and a double-seal ring surrounding each individual electrical circuit. The layered elements further define another double-seal ring that surrounds at least two electrical circuits. The processed semiconductor wafer can have additional layered elements that extend each of the double-seal rings that surround individual circuits or, that can extend the other double-seal ring. A method of fabricating such a processed semiconductor wafer. A device comprising two such electrical circuits.
    Type: Grant
    Filed: September 4, 2015
    Date of Patent: September 10, 2019
    Assignee: MICROSEMI SOLUTIONS (U.S.), INC.
    Inventors: Bruce Scatchard, Peter Onufryk, Chunfang Xie
  • Patent number: 10403587
    Abstract: A radio frequency circuit includes, a multilayer substrate having a grounded base metal and a plurality of insulating layers and wiring layers formed over the grounded base metal and having a recess surrounded by the plurality of insulating layers and wiring layers over the grounded base metal, an upper substrate having a through-hole penetrating the upper substrate, a first semiconductor chip mounted on the upper surface of the upper substrate and electrically coupled to a metal film formed on the lower surface of the upper substrate, a metal pillar formed on the upper surface of the grounded base metal in the recess, and a solder buried in the through-hole and bonded to the metal film and the upper surface of the metal pillar. The metal film is bonded to a ground wiring layer electrically coupled to the grounded base metal among the plurality of wiring layers.
    Type: Grant
    Filed: April 5, 2018
    Date of Patent: September 3, 2019
    Assignee: FUJITSU LIMITED
    Inventors: Masaru Sato, Yukiyasu Furukawa
  • Patent number: 10396011
    Abstract: The present disclosure relates to a thermally enhanced semiconductor package, which includes a module substrate, a thinned flip chip die over the module substrate, a mold compound component, a thermally conductive film, and a thermally enhanced mold compound component. The mold compound component resides over the module substrate, surrounds the thinned flip chip die, and extends above an upper surface of the thinned flip chip die to form a cavity over the upper surface of the thinned flip chip die. The thermally conductive film resides over at least the upper surface of the thinned flip chip at the bottom of the cavity. The thermally enhanced mold compound component resides over at least a portion of the thermally conductive film to fill the cavity.
    Type: Grant
    Filed: July 18, 2018
    Date of Patent: August 27, 2019
    Assignee: Qorvo US, Inc.
    Inventors: Julio C. Costa, Robert Aigner
  • Patent number: 10347560
    Abstract: The present disclosure relates to a thermally enhanced semiconductor package, which includes a module substrate, a thinned flip chip die over the module substrate, a mold compound component, a thermally conductive film, and a thermally enhanced mold compound component. The mold compound component resides over the module substrate, surrounds the thinned flip chip die, and extends above an upper surface of the thinned flip chip die to form a cavity over the upper surface of the thinned flip chip die. The thermally conductive film resides over at least the upper surface of the thinned flip chip at the bottom of the cavity. The thermally enhanced mold compound component resides over at least a portion of the thermally conductive film to fill the cavity.
    Type: Grant
    Filed: July 18, 2018
    Date of Patent: July 9, 2019
    Assignee: Qorvo US, Inc.
    Inventors: Julio C. Costa, Robert Aigner
  • Patent number: 10325830
    Abstract: A multipart lid is provided. The multipart lid may include a formed upper lid designed for maximum heat dissipation, a coined lower lid joined to the formed upper lid, where the coined lower lid comprises a coefficient of thermal expansion (CTE) substantially equal to a CTE of a first semiconductor component. A structure is provided. The structure may include a substrate, a first semiconductor component electrically connected and mounted on the substrate, one or more discrete components electrically connected and mounted on the substrate, a substrate mounted multipart lid covering both the semiconductor component and the one or more discrete components, where the multipart lid comprises a heat dissipating upper lid and a lower lid, where a coefficient of thermal expansion (CTE) of the lower lid substantially matches a CTE of the first semiconductor component.
    Type: Grant
    Filed: November 30, 2017
    Date of Patent: June 18, 2019
    Assignee: International Business Machines Corporation
    Inventors: Charles L. Arvin, Steven P. Ostrander, Krishna R. Tunga
  • Patent number: 10319686
    Abstract: A radiation-hard electronic device including a package structure, a semiconductor chip in a cavity within the package structure, an integrated circuit in the semiconductor chip, and structures for protection from radiation for protecting the integrated circuit from ionizing radiation. The structures for protection from radiation include a protective layer of gel, which occupies at least in part the cavity and coats the semiconductor chip.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: June 11, 2019
    Assignee: STMicroelectronics S.r.l.
    Inventor: Ignazio Bruno Mirabella
  • Patent number: 10297529
    Abstract: The present disclosure relates to a thermally enhanced semiconductor package, which includes a module substrate, a thinned flip chip die over the module substrate, a mold compound component, a thermally conductive film, and a thermally enhanced mold compound component. The mold compound component resides over the module substrate, surrounds the thinned flip chip die, and extends above an upper surface of the thinned flip chip die to form a cavity over the upper surface of the thinned flip chip die. The thermally conductive film resides over at least the upper surface of the thinned flip chip at the bottom of the cavity. The thermally enhanced mold compound component resides over at least a portion of the thermally conductive film to fill the cavity.
    Type: Grant
    Filed: July 18, 2018
    Date of Patent: May 21, 2019
    Assignee: Qorvo US, Inc.
    Inventors: Julio C. Costa, Robert Aigner
  • Patent number: 10269673
    Abstract: Packaged semiconductor devices and methods of packaging semiconductor devices are disclosed. In some embodiments, a packaged semiconductor device includes an integrated circuit die, a molding compound disposed around the integrated circuit die, and an interconnect structure disposed over the integrated circuit die and the molding compound. The molding compound is thicker than the integrated circuit die.
    Type: Grant
    Filed: February 27, 2018
    Date of Patent: April 23, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Chen-Hua Yu, Chung-Shi Liu, Chih-Fan Huang, Chih-Wei Lin, Wei-Hung Lin, Ming-Da Cheng
  • Patent number: 10269718
    Abstract: A rectangular semiconductor package and a method manufacturing the same described in the present disclosure features no carrier installed on a die cut from a wafer. In an embodiment, a first die on a top surface of a conductive routing layer is electrically connected to the conductive routing layer through a plurality of first metal wires, a plurality of conductive balls is installed on a bottom surface of the conductive routing layer, and a molding compound is used to encase the first die on the conductive routing layer. In another embodiment, a second die is added in the above rectangular semiconductor package and encased in the molding compound, as is the first die. Alternatively, the molding compound is processed such that the second die encapsulated in a package is stacked on the molding compound and electrically connected to the conductive routing layer.
    Type: Grant
    Filed: July 18, 2017
    Date of Patent: April 23, 2019
    Assignee: WALTON ADVANCED ENGINEERING INC.
    Inventors: Hong Chi Yu, Chun Jung Lin
  • Patent number: 10153253
    Abstract: A system-in-package apparatus includes a package substrate configured to carry at least one semiconductive device on a die side and a through-mold via package bottom interposer disposed on the package substrate on a land side. A land side board mates with the through-mold via package bottom interposer, and enough vertical space is created by the through-mold via package bottom interposer to allow space for at least one device disposed on the package substrate on the land side.
    Type: Grant
    Filed: November 21, 2016
    Date of Patent: December 11, 2018
    Assignee: Intel Corporation
    Inventors: Howe Yin Loo, Eng Huat Goh, Min Suet Lim, Bok Eng Cheah, Jackson Chung Peng Kong, Khang Choong Yong
  • Patent number: 10128203
    Abstract: A fan-out package structure is disclosed. The fan-out package structure includes an antenna main body; a redistribution layer (RDL); and an antenna auxiliary body in the RDL. An antenna system is also disclosed. The antenna system includes: an antenna main body, arranged to provide a first resonance; and an antenna auxiliary body, arranged to provide a second resonance through parasitic coupling to the antenna main body; wherein a dimension of the antenna main body is greater than a dimension of the antenna auxiliary body. An associated semiconductor packaging method is also disclosed.
    Type: Grant
    Filed: February 2, 2016
    Date of Patent: November 13, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Wei-Ting Chen, Tzu-Chun Tang, Ming Hung Tseng, In-Tsang Lin, Vincent Chen, Chuei-Tang Wang, Hung-Yi Kuo
  • Patent number: 10068831
    Abstract: The present disclosure relates to a thermally enhanced semiconductor package, which includes a module substrate, a thinned flip chip die over the module substrate, a mold compound component, a thermally conductive film, and a thermally enhanced mold compound component. The mold compound component resides over the module substrate, surrounds the thinned flip chip die, and extends above an upper surface of the thinned flip chip die to form a cavity over the upper surface of the thinned flip chip die. The thermally conductive film resides over at least the upper surface of the thinned flip chip at the bottom of the cavity. The thermally enhanced mold compound component resides over at least a portion of the thermally conductive film to fill the cavity.
    Type: Grant
    Filed: April 19, 2017
    Date of Patent: September 4, 2018
    Assignee: Qorvo US, Inc.
    Inventors: Julio C. Costa, Robert Aigner
  • Patent number: 10014260
    Abstract: Package structures and methods for forming the same are provided. A method for forming a package structure includes providing a carrier substrate. The method also includes forming a conductive layer over the carrier substrate. The method further includes forming a passivation layer over the conductive layer. The passivation layer includes openings that expose portions of the conductive layer. In addition, the method includes bonding integrated circuit dies to the portions of the conductive layer through bumps. There is a space between the integrated circuit dies and the passivation layer. The method also includes filling the space with a first molding compound. The first molding compound surrounds the bumps and the integrated circuit dies. The method further includes forming a second molding compound capping the first molding compound and the integrated circuit dies. The passivation layer has a sidewall that is covered by the second molding compound.
    Type: Grant
    Filed: November 10, 2016
    Date of Patent: July 3, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yi-Da Tsai, Cheng-Ping Lin, Wei-Hung Lin, Chih-Wei Lin, Ming-Da Cheng, Ching-Hua Hsieh, Chung-Shi Liu
  • Patent number: 9991194
    Abstract: A method of manufacture and a substrate for sensor packages is provided. The method involves premolding a lead frame with strips having V-grooves; cutting the substrate partially, and plating the exposed surfaces of the lead frame. The method subsequently involves attaching a die to a dies pad and connecting wires between the die and leads to form a sensor package. The sensor package is separated from the substrate by snapping along the score line. The substrate for assembly of sensor packages as well as substrate of sensor packages is manufactured using at least part of the method of manufacture.
    Type: Grant
    Filed: April 18, 2017
    Date of Patent: June 5, 2018
    Assignee: UBOTIC COMPANY LIMITED
    Inventors: Ming-Wa Tam, Ken Lik Hang Wan, Wa San Leung
  • Patent number: 9947624
    Abstract: The invention provides a semiconductor package assembly with a TSV interconnect. The semiconductor package assembly includes a first semiconductor package mounted on a base, having: a semiconductor die, a semiconductor substrate, and a first array of TSV interconnects and a second array of TSV interconnects formed through the semiconductor substrate, wherein the first array and second array of TSV interconnects are separated by an interval region. The assembly further includes a second semiconductor die mounted on the first semiconductor package, having a ground pad thereon. One of the TSV interconnects of the first semiconductor package has a first terminal coupled to the ground pad of the second semiconductor die and a second terminal coupled to an interconnection structure disposed on a front side of the semiconductor substrate.
    Type: Grant
    Filed: December 29, 2016
    Date of Patent: April 17, 2018
    Assignee: MediaTek Inc.
    Inventors: Ming-Tzong Yang, Cheng-Chou Hung, Wei-Che Huang, Yu-Hua Huang, Tzu-Hung Lin, Kuei-Ti Chan, Ruey-Beei Wu, Kai-Bin Wu
  • Patent number: 9924594
    Abstract: A printed circuit board (PCB) has a first, structured metalization arranged on its top side and at least one second metalization arranged below the first metalization in a vertical direction, parallel to the first metalization and insulated therefrom. Also on the PCB top side is a bare semiconductor chip having contact electrodes connected by bonding wires to corresponding contact pads of the first metalization on the PCB top side. A first portion of the contact electrodes and corresponding contact pads carry high voltage during operation. All high-voltage-carrying contact pads are conductively connected to the second metalization via plated-through holes. An insulation layer completely covers the chip and a delimited region of the PCB around the chip, and all high-voltage-carrying contact pads and the plated-through holes are completely covered by the insulation layer. A second portion of the contact electrodes and corresponding contact pads are under low voltages during operation.
    Type: Grant
    Filed: September 29, 2014
    Date of Patent: March 20, 2018
    Assignee: Infineon Technologies AG
    Inventors: Andre Arens, Juergen Hoegerl, Magdalena Hoier
  • Patent number: 9905546
    Abstract: A method for fabricating a package on package (PoP) structure is provided, which includes: providing a first packaging substrate having at least a first electronic element and a plurality of first support portions, wherein the first electronic element is electrically connected to the first packaging substrate; forming an encapsulant on the first packaging substrate for encapsulating the first electronic element and the first support portions; forming a plurality of openings in the encapsulant for exposing portions of surfaces of the first support portions; and providing a second packaging substrate having a plurality of second support portions and stacking the second packaging substrate on the first packaging substrate with the second support portions positioned in the openings of the encapsulant and bonded with the first support portions. As such, the encapsulant effectively separates the first support portions or the second support portions from one another to prevent bridging from occurring therebetween.
    Type: Grant
    Filed: March 14, 2014
    Date of Patent: February 27, 2018
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Shih-Hao Tung, Chang-Yi Lan, Lung-Yuan Wang, Cheng-Chia Chiang, Chu-Huei Huang
  • Patent number: 9842826
    Abstract: An integrated fan out package on package architecture is utilized along with a reference via in order to provide a reference voltage that extends through the InFO-POP architecture. If desired, the reference via may be exposed and then connected to a shield coating that can be used to shield the InFO-POP architecture. The reference via may be exposed by exposing either a top surface or a sidewall of the reference via using one or more singulation processes.
    Type: Grant
    Filed: July 15, 2015
    Date of Patent: December 12, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jing-Cheng Lin, Chen-Hua Yu, Po-Hao Tsai
  • Patent number: 9761537
    Abstract: Shielded radio-frequency (RF) module having reduced area. In some embodiments, an RF module can include a packaging substrate configured to receive a plurality of components, and a plurality of shielding wirebonds implemented on the packaging substrate and configured to provide RF shielding functionality for one or more regions on the packaging substrate. The packaging substrate can include a first area associated with implementation of each shielding wirebond. The RF module can further include one or more devices mounted on the packaging substrate. The packaging substrate can further include a second area associated with mounting of each of the one or more devices. Each device can be mounted with respect to a corresponding shielding wirebond such that the second area associated with the device overlaps at least partially with the first area associated with the corresponding shielding wirebond.
    Type: Grant
    Filed: September 29, 2015
    Date of Patent: September 12, 2017
    Assignee: Skyworks Solutions, Inc.
    Inventors: Howard E. Chen, Matthew Sean Read
  • Patent number: 9721905
    Abstract: According to an embodiment, a semiconductor package includes a semiconductor chip mounted on an interposer board, a encapsulant sealing the semiconductor chip, and a conductive shielding layer covering the encapsulant and at least part of a side surface of the interposer board. The interposer board has plural vias through an insulating substrate. A part of the plural vias has a cutting plane exposing to the side surface of the interposer board and cut in a thickness direction of the interposer board. The cutting plane of the via is electrically connected to the conductive shielding layer.
    Type: Grant
    Filed: May 31, 2016
    Date of Patent: August 1, 2017
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Keiju Yamada, Takashi Yamazaki, Masatoshi Fukuda, Yasuhiro Koshio
  • Patent number: 9698104
    Abstract: A wafer level packaging method entails providing electronic devices and providing a platform structure having cavities extending through the platform structure. The platform structure is mounted to a temporary support. One or more electronic devices are placed in the cavities with an active side of each electronic device facing the temporary support. The platform structure and the electronic devices are encapsulated in an encapsulation material to produce a panel assembly. Redistribution layers may be formed over the panel assembly, after which the panel assembly may be separated into a plurality of integrated electronic packages. The platform structure may be formed from a semiconductor material, and platform segments within each package provide a fan-out region for conductive interconnects, as well as provide a platform for a metallization layer and/or for forming through silicon vias.
    Type: Grant
    Filed: June 14, 2016
    Date of Patent: July 4, 2017
    Assignee: NXP USA, Inc.
    Inventors: Weng F. Yap, Michael B. Vincent
  • Patent number: 9685403
    Abstract: A semiconductor device has a plurality of conductive vias formed partially through a substrate. A conductive layer is formed over the substrate and electrically connected to the conductive vias. A semiconductor die is mounted over the substrate. An encapsulant is deposited over the semiconductor die and substrate. A trench is formed through the encapsulant around the semiconductor die. A shielding layer is formed over the encapsulant. The trench is formed partially through the substrate and the shielding layer is formed in the trench partially through the substrate. An insulating layer can be formed in the trench prior to forming the shielding layer. A portion of the substrate is removed to expose the conductive vias. An interconnect structure is formed over the substrate opposite the semiconductor die. The interconnect structure is electrically connected to the conductive vias. The shielding layer is electrically connected to the interconnect structure.
    Type: Grant
    Filed: July 14, 2014
    Date of Patent: June 20, 2017
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventor: Reza A. Pagaila
  • Patent number: 9673151
    Abstract: A semiconductor package is provided, including: a substrate having opposing first and second surfaces; a plurality of semiconductor components disposed on and electrically connected to the first surface; an encapsulant encapsulating the first surface and the semiconductor components and having at least one first groove that partitions the substrate into a plurality of package units, each of which has at least one of the semiconductor components; and a metal layer formed on the substrate and the encapsulant and encapsulating a periphery of the package units, with the second surface exposed from the metal layer, wherein the metal layer is formed along a wall surface of the first groove, to form a second groove corresponding in position to the first groove and having a metal surface. Therefore, the package units are isolated and form a multilayer isolated structure, including metal layers and air layers, and are electromagnetically shielded from one another.
    Type: Grant
    Filed: August 27, 2015
    Date of Patent: June 6, 2017
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Chih-Hsien Chiu, Hao-Ju Fang, Hsin-Lung Chung, Cho-Hsin Chang, Tsung-Hsien Tsai, Chia-Yang Chen, Chun-Chi Ke
  • Patent number: 9672976
    Abstract: A device may include a multiple inductive coils arranged concentrically for operating according multiple modes of wireless power transfer. The device may include multiple layers of magnetic shields to protect device components from the effects of the magnetic field used for power transfer. Construction and material of multiple layers of shields may be based on addressing individually the different parameters of the multiple modes of operation and based on the combined effect of the layers in each mode of operation. In some examples, the device may include first and second ferrite shields each having different magnetic properties.
    Type: Grant
    Filed: October 28, 2013
    Date of Patent: June 6, 2017
    Assignee: Nokia Corporation
    Inventors: Sakari Johannes Levo, Jari Juhani Muurinen
  • Patent number: 9653414
    Abstract: Consistent with an example embodiment, a semiconductor device comprises a device die having bond pads providing connection to device die circuitry and a QFN half-etched lead frame with a package boundary; the QFN half-etched lead frame has a top-side surface and an under-side surface. The QFN half-etched lead frame includes a sub-structure of I/O terminals and a die attach area, the die attach area facilitating device die attachment thereon and the terminal I/O terminals providing connection to the device die bond pads and additional terminals located about the corners of the sub-structure. An envelope of molding compound encapsulates the device die mounted on the top-side surface of the QFN half-etched lead frame. A RF (radio-frequency) shield layer is on the envelope of the molding compound, the RF shield electrically connected to the additional terminals via conductive connections defined in corresponding locations on the envelope of the molding compound.
    Type: Grant
    Filed: July 22, 2015
    Date of Patent: May 16, 2017
    Assignee: NXP B. V.
    Inventors: Jan Gulpen, Leonardus Antonius Elisabeth van Gemert
  • Patent number: 9648722
    Abstract: A printed circuit board assembly comprises a printed circuit board having at least one conductive layer supported by a substrate layer, and at least one power semiconductor device, wherein the at least one power semiconductor device is at least partly embedded in the substrate layer.
    Type: Grant
    Filed: January 15, 2015
    Date of Patent: May 9, 2017
    Assignee: Elektronik Systeme GmbH
    Inventor: Thomas E. Gerhäuβer
  • Patent number: 9642266
    Abstract: An electronic module for a vehicle includes a can housing and a circuit carrier having at least one connecting element. The circuit carrier is positioned in the can housing, and is cast with a cast material. The at least one connecting element protrudes from the cast material and is configured to connect at least one conductive element. The electronic module is positioned in the transmission and is configured to be operated.
    Type: Grant
    Filed: September 4, 2012
    Date of Patent: May 2, 2017
    Assignee: Robert Bosch GmbH
    Inventors: Martin Gerhaeusser, Martin Kowatsch
  • Patent number: 9576931
    Abstract: A method for fabricating a wafer level package is disclosed. A carrier is provided. A redistributed layer (RDL) layer is formed on the carrier. Semiconductor dies are mounted on the RDL layer. The semiconductor dies are molded with a molding compound, thereby forming a molded wafer. A grinding process is then performed to remove a central portion of the molding compound, thereby forming a recess and an outer peripheral ring portion surrounding the recess. The carrier is then removed to expose a lower surface of the RDL layer. Solder bumps or solder balls are formed on the lower surface of the RDL layer.
    Type: Grant
    Filed: February 19, 2016
    Date of Patent: February 21, 2017
    Assignee: INOTERA MEMORIES, INC.
    Inventor: Shing-Yih Shih
  • Patent number: 9576935
    Abstract: A method for fabricating semiconductor packages includes providing a first substrate having an aperture, providing a first semiconductor chip, connecting the first semiconductor chip to the first substrate, filling the aperture with a first insulating material and encapsulating the semiconductor chip with a second insulating material to create a first encapsulation body.
    Type: Grant
    Filed: April 16, 2014
    Date of Patent: February 21, 2017
    Assignee: Infineon Technologies AG
    Inventors: Michael Bauer, Ludwig Heitzer, Christian Stuempfl
  • Patent number: 9425154
    Abstract: A device includes a substrate having a front surface and a back surface; an integrated circuit device at the front surface of the substrate; and a metal plate on the back surface of the substrate, wherein the metal plate overlaps substantially an entirety of the integrated circuit device. A guard ring extends into the substrate and encircles the integrated circuit device. The guard ring is formed of a conductive material. A through substrate via (TSV) penetrates through the substrate and electrically couples to the metal plate.
    Type: Grant
    Filed: December 19, 2014
    Date of Patent: August 23, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Chung Chen, Chewn-Pu Jou, Sally Liu
  • Patent number: 9312177
    Abstract: Methods of using a screen-print mask for hybrid wafer dicing using laser scribing and plasma etch described. In an example, a method of dicing a semiconductor wafer having a plurality of integrated circuits separated by streets involves screen-printing a patterned mask above the semiconductor wafer, the patterned mask covering the integrated circuits and exposing the streets of the semiconductor wafer. The method also involves laser ablating the streets with a laser scribing process to expose regions of the semiconductor wafer between the integrated circuits. The method also involves plasma etching the semiconductor wafer through the exposed regions of the semiconductor wafer to singulate the integrated circuits. The patterned mask protects the integrated circuits during the plasma etching.
    Type: Grant
    Filed: December 6, 2013
    Date of Patent: April 12, 2016
    Assignee: Applied Materials, Inc.
    Inventors: Prabhat Kumar, Brad Eaton, Wei-Sheng Lei, James S. Papanu, Ajay Kumar
  • Patent number: 9275959
    Abstract: Semiconductor packages are provided. In some embodiments, the semiconductor package includes a substrate, a first ground line including a first internal ground line disposed along edges of the substrate and a plurality of first extended ground lines between the first internal ground line and sidewalls of the substrate, a chip on the substrate, a molding member disposed on the substrate to cover the chip, and an electromagnetic interference (EMI) shielding layer covering the molding member, the EMI shielding layer extending along the sidewalls of the substrate and contacting the end portions of the plurality of first extended ground lines. The plurality of first extended ground lines include end portions that are exposed at the sidewalls of the substrate.
    Type: Grant
    Filed: October 6, 2015
    Date of Patent: March 1, 2016
    Assignee: SK HYNIX INC.
    Inventors: Hyung Ju Choi, Jong Hyun Kim
  • Patent number: 9276199
    Abstract: Some implementations provide a die that includes a magnetoresistive random access memory (MRAM) cell array that includes several MRAM cells. The die also includes a first ferromagnetic layer positioned above the MRAM cell array, a second ferromagnetic layer positioned below the MRAM cell array, and several vias positioned around at least one MRAM cell. The via comprising a ferromagnetic material. In some implementations, the first ferromagnetic layer, the second ferromagnetic layer and the several vias define a magnetic shield for the MRAM cell array. The MRAM cell may include a magnetic tunnel junction (MTJ). In some implementations, the several vias traverse at least a metal layer and a dielectric layer of the die. In some implementations, the vias are through substrate vias. In some implementations, the ferromagnetic material has high permeability and high B saturation.
    Type: Grant
    Filed: September 26, 2014
    Date of Patent: March 1, 2016
    Assignee: QUALCOMM Incorporated
    Inventors: Shiqun Gu, Rongtian Zhang, Vidhya Ramachandran, Dong Wook Kim
  • Patent number: 9263381
    Abstract: A semiconductor module according to one embodiment includes a semiconductor chip, a wiring substrate, a mounting plate provided with the wiring substrate thereon, a frame body defining a case for the wiring substrate, together with the mounting plate, a bus bar extending from the case and being inserted into a side wall of the frame. The side wall has a projection. The bus bar includes a first region in the side wall, a second region extending from a first end of the first region outward from the frame, a third region extending from a second end of the first region into the frame. The third region is bent based on the shape being close to the wiring substrate of the projection. The mounting plate with the wiring substrate is attached to the frame such that the third region is in press-contact with the wiring pattern.
    Type: Grant
    Filed: May 23, 2013
    Date of Patent: February 16, 2016
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventor: Jiro Shinkai
  • Patent number: 9236356
    Abstract: A semiconductor package includes a substrate, a grounding layer, a chip, a package body, and a shielding layer. The substrate includes a lateral surface and a bottom surface. The grounding layer is buried in the substrate and extends horizontally in the substrate. The chip is arranged on the substrate. The package body envelops the chip and includes a lateral surface. The shielding layer covers the lateral surface of the package body and the lateral surface of the substrate, and is electrically connected to the grounding layer, where a bottom surface of the shielding layer is separated from a bottom surface of the substrate.
    Type: Grant
    Filed: July 30, 2014
    Date of Patent: January 12, 2016
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Jun-Young Yang, Sung-Mook Lim
  • Patent number: 9232686
    Abstract: An apparatus including a die including a device side with contact points and lateral sidewalls defining a thickness of the die; a build-up carrier coupled to the die, the build-up carrier including a plurality of alternating layers of patterned conductive material and insulating material, wherein at least one of the layers of patterned conductive material is coupled to one of the contact points of the die; and an interference shield including a conductive material disposed on the die and a portion of the build-up carrier. The apparatus may be connected to a printed circuit board. A method including forming a build-up carrier adjacent a device side of a die including a plurality of alternating layers of patterned conductive material and insulating material; and forming a interference shield on a portion of the build-up carrier.
    Type: Grant
    Filed: March 27, 2014
    Date of Patent: January 5, 2016
    Assignee: Intel Corporation
    Inventors: Digvijay A. Raorane, Kemal Aygun, Daniel N. Sobieski, Drew W. Delaney
  • Patent number: 9190341
    Abstract: A lid comprising a heat conductive substrate and a native silicon oxide layer connected to said substrate by at least one intermediate layer; a lidded integrated circuit package; and a method of providing a heat path through an integrated circuit package comprising providing a substrate with an exterior layer of native silicon oxide and interfacing the layer of native silicon oxide with a layer of thermal interface material.
    Type: Grant
    Filed: June 5, 2012
    Date of Patent: November 17, 2015
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Dwayne Richard Shirley
  • Patent number: 9156680
    Abstract: A three-dimensional printing technique can be used to form a microphone package. The microphone package can include a housing having a first side and a second side opposite the first side. A first electrical lead can be formed on an outer surface on the first side of the housing. A second electrical lead can be formed on an outer surface on the second side of the housing. The first electrical lead and the second electrical lead may be electrically shorted to one another. Further, vertical and horizontal conductors can be monolithically integrated within the housing.
    Type: Grant
    Filed: October 26, 2012
    Date of Patent: October 13, 2015
    Assignee: ANALOG DEVICES, INC.
    Inventors: Oliver J. Kierse, Christian Lillelund
  • Patent number: 9055682
    Abstract: There is provided a circuit module including a circuit substrate being a wiring substrate having a mount surface, a surface wiring layer disposed on the mount surface, and an inner wiring layer formed within the substrate, a first mount component mounted on the mount surface, a second mount component mounted on the mount surface, and electrically connected to the first mount component via the inner wiring layer, a sealing body formed on the mount surface, covering the first mount component and the second mount component and having a trench formed from a main surface of the sealing body to the surface wiring layer between the first mount component and the second mount component, and a shield having an inner shield section formed within the trench that abuts on the surface wiring layer and an outer shield section covering the sealing body and the inner shield section.
    Type: Grant
    Filed: November 21, 2013
    Date of Patent: June 9, 2015
    Assignee: Taiyo Yuden Co., Ltd
    Inventors: Eiji Mugiya, Kenzo Kitazaki, Masaya Shimamura
  • Patent number: 9041168
    Abstract: According to one exemplary embodiment, an overmolded package includes a component situated on a substrate. The overmolded package further includes an overmold situated over the component and the substrate. The overmolded package further includes a wirebond cage situated over the substrate and in the overmold, where the wirebond cage surrounds the component, and where the wirebond cage includes a number of wirebonds. The wirebond cage forms an EMI shield around the component. According to this exemplary embodiment, the overmolded package further includes a conductive layer situated on a top surface of the overmold and connected to the wirebond cage, where the conductive layer forms an EMI shield over the component.
    Type: Grant
    Filed: December 5, 2011
    Date of Patent: May 26, 2015
    Assignee: Skyworks Solutions, Inc.
    Inventors: Dinhphuoc V. Hoang, Thomas E. Noll, Anil K. Agarwal, Robert W. Warren, Matthew S. Read, Anthony LoBianco
  • Patent number: 9024416
    Abstract: A semiconductor structure is provided. The semiconductor structure includes an interposer structure. The interposer structure includes an interposer substrate, a ground, through vias, a dielectric layer, and an inductor. The through vias are formed in the interposer substrate and electrically connected to the ground. The dielectric layer is on the interposer substrate. The inductor is on the dielectric layer.
    Type: Grant
    Filed: August 12, 2013
    Date of Patent: May 5, 2015
    Assignee: United Microelectronics Corp.
    Inventors: Chun-Hung Chen, Ming-Tse Lin, Chien-Li Kuo, Kuei-Sheng Wu
  • Patent number: 9024366
    Abstract: A semiconductor device having a dummy active region for metal ion gathering, which is capable of preventing device failure due to metal ion contamination, and a method of fabricating the same are provided. The semiconductor device includes active regions defined by an isolation layer in a semiconductor substrate and ion-implanted with an impurity, and a dummy active region ion-implanted with an impurity having a concentration higher than that of the impurity in the active region and configured to gather metal ions.
    Type: Grant
    Filed: November 19, 2012
    Date of Patent: May 5, 2015
    Assignee: SK Hynix Inc.
    Inventor: Jong Il Kim
  • Patent number: 8994153
    Abstract: A semiconductor device (semiconductor module) includes a circuit board (module board) and a semiconductor element mounted on the circuit board. A shielding layer that blocks electromagnetic waves is disposed on the upper surface of the semiconductor element, and an antenna element is disposed over the shielding layer. The semiconductor element and the antenna element are electrically connected to each other by a connecting portion. This structure enables the semiconductor device to be reduced in size and to have both an electromagnetic-wave blocking function and an antenna function.
    Type: Grant
    Filed: June 12, 2012
    Date of Patent: March 31, 2015
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Hirohisa Matsuki, Masao Sakuma
  • Patent number: 8987872
    Abstract: One feature pertains to a multi-chip package that includes a substrate and an electromagnetic interference (EMI) shield coupled to the substrate. At least one integrated circuit is coupled to a first surface of the substrate. The EMI shield includes a metal casing configured to shield the package from radio frequency radiation, a dielectric layer coupled to at least a portion of an inner surface of the metal casing, and a plurality of signal lines. The signal lines are coupled to the dielectric layer and electrically isolated from the metal casing by the dielectric layer. At least one other integrated circuit is coupled to an inner surface of the EMI shield, and at least a portion of the inner surface of the EMI shield faces the first surface of the substrate. The signal lines are configured to provide electrical signals to the second circuit component.
    Type: Grant
    Filed: March 11, 2013
    Date of Patent: March 24, 2015
    Assignee: QUALCOMM Incorporated
    Inventors: Kyu-Pyung Hwang, Young Kyu Song, Dong Wook Kim, Changhan Hobie Yun
  • Patent number: 8981537
    Abstract: A semiconductor device has a base substrate having a plurality of metal traces and a plurality of base vias. An opening is formed through the base substrate. At least one die is attached to the first surface of the substrate and positioned over the opening. A cover substrate has a plurality of metal traces. A cavity in the cover substrate forms side wall sections around the cavity. The cover substrate is attached to the base substrate so the at least one die is positioned in the interior of the cavity. Ground planes in the base substrate are coupled to ground planes in the cover substrate to form an RF shield around the at least one die.
    Type: Grant
    Filed: January 11, 2012
    Date of Patent: March 17, 2015
    Assignee: Amkor Technology, Inc.
    Inventors: David Bolognia, Bob Shih-Wei Kuo, Bud Troche
  • Publication number: 20150069588
    Abstract: A novel radiation hardened chip package technology protects microelectronic chips and systems in aviation/space or terrestrial devices against high energy radiation. The proposed technology of a radiation hardened chip package using rare earth elements and mulitlayered structure provides protection against radiation bombardment from alpha and beta particles to neutrons and high energy electromagnetic radiation.
    Type: Application
    Filed: May 16, 2014
    Publication date: March 12, 2015
    Inventors: Jin Ho Kang, Godfrey Sauti, Cheol Park, Luke Gibbons, Sheila A. Thibeault, Sharon E. Lowther, Robert G. Bryant
  • Patent number: 8952504
    Abstract: Some implementations provide a die that includes a magnetoresistive random access memory (MRAM) cell array that includes several MRAM cells. The die also includes a first ferromagnetic layer positioned above the MRAM cell array, a second ferromagnetic layer positioned below the MRAM cell array, and several vias positioned around at least one MRAM cell. The via comprising a ferromagnetic material. In some implementations, the first ferromagnetic layer, the second ferromagnetic layer and the several vias define a magnetic shield for the MRAM cell array. The MRAM cell may include a magnetic tunnel junction (MTJ). In some implementations, the several vias traverse at least a metal layer and a dielectric layer of the die. In some implementations, the vias are through substrate vias. In some implementations, the ferromagnetic material has high permeability and high B saturation.
    Type: Grant
    Filed: February 26, 2013
    Date of Patent: February 10, 2015
    Assignee: QUALCOMM Incorporated
    Inventors: Shiqun Gu, Rongtian Zhang, Vidhya Ramachandran, Dong Wook Kim
  • Patent number: 8952503
    Abstract: Apparatus and methods for an electronic package incorporating shielding against emissions of electromagnetic interference (EMI). According to an integrated circuit structure, a substrate is on a printed circuit board. An integrated circuit chip is on the substrate. The integrated circuit chip is electrically connected to the substrate. An electromagnetic interference (EMI) shielding unit is on the integrated circuit chip and the substrate. The EMI shielding unit comprises a lid covering the integrated circuit chip and portions of the substrate outside the integrated circuit chip. A fill material can be deposited within a cavity formed between the lid and the substrate. The fill material comprises an EMI absorbing material. A periphery of the lid comprises a side skirt, the side skirt circumscribing the integrated circuit chip and the substrate. EMI absorbing material is on the printed circuit board, and a portion of the side skirt is embedded in the EMI absorbing material.
    Type: Grant
    Filed: January 29, 2013
    Date of Patent: February 10, 2015
    Assignee: International Business Machines Corporation
    Inventors: William L. Brodsky, Timothy W. Budell, Samuel R. Connor, Mark Curtis Hayes Lamorey, Janak G. Patel, Peter Slota, Jr., David B. Stone
  • Patent number: 8946874
    Abstract: Integrated Circuits and methods for reducing thermal neutron soft error rate (SER) of a digital circuit are provided by doping a protection layer on top of the metal layer and in physical contact with the metal layer of the digital circuit, wherein the protection layer is doped with additional thermal neutron absorbing material. The thermal neutron absorbing material can be selected from the group consisting of Gd, Sm, Cd, B, and combinations thereof. The protection layer may comprise a plurality of sub-layers among which a plurality of them containing additional thermal neutron absorbing material.
    Type: Grant
    Filed: January 25, 2011
    Date of Patent: February 3, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yung-Huei Lee, Chou-Jie Tsai, Chia-Fang Wu, Wei-Cheng Chu
  • Patent number: 8946873
    Abstract: Microfeature dies with redistribution structures that reduce or eliminate line interference are disclosed. The microfeature dies can include a substrate having a bond site and integrated circuitry electrically connected to the bond site. The microfeature dies can also include and a redistribution structure coupled to the substrate. The redistribution structure can include an external contact site configured to receive an electric coupler, a conductive line that is electrically connected to the external contact site and the bond site, and a conductive shield that at least partially surrounds the conductive line.
    Type: Grant
    Filed: August 28, 2007
    Date of Patent: February 3, 2015
    Assignee: Micron Technology, Inc.
    Inventor: Mark S. Johnson