With Means To Shield Device Contained In Housing Or Package From Charged Particles (e.g., Alpha Particles) Or Highly Ionizing Radiation (i.e., Hard X-rays Or Shorter Wavelength) Patents (Class 257/660)
  • Patent number: 10950556
    Abstract: A method includes forming a metal post over a first dielectric layer, attaching a second dielectric layer over the first dielectric layer, encapsulating a device die, the second dielectric layer, a shielding structure, and the metal post in an encapsulating material, planarizing the encapsulating material to reveal the device die, the shielding structure, and the metal post, and forming an antenna electrically coupling to the device die. The antenna has a portion vertically aligned to a portion of the device die.
    Type: Grant
    Filed: September 13, 2019
    Date of Patent: March 16, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kai-Chiang Wu, Chen-Hua Yu, Ching-Feng Yang, Meng-Tse Chen
  • Patent number: 10903088
    Abstract: An electronic package and a method for fabrication the same are provided. The method includes: disposing an electronic component on a substrate; forming an encapsulant layer on the substrate to encapsulate the electronic component; and forming a shielding layer made of metal on the encapsulant layer. The shielding layer has an extending portion extending to a lateral side of the substrate along a corner of the encapsulant layer, without extending to a lower side of the substrate. Therefore, the present disclosure prevents the shielding layer from coming into contact with conductive pads disposed on the lower side of the substrate and thereby avoids a short circuit from occurrence.
    Type: Grant
    Filed: June 20, 2017
    Date of Patent: January 26, 2021
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Shu-Chi Chang, Wei Ping Wang, Hsien-Lung Hsiao, Kaun-I Cheng
  • Patent number: 10879142
    Abstract: An electronic component includes a board, a surface mount device, a nonmagnetic resin layer, a metal shield layer, and a magnetic shield layer. The board includes first and second principal surfaces facing each other, and a magnetic body layer. The surface mount device is mounted on the first principal surface of the board. The nonmagnetic resin layer covers the surface mount device. The metal shield layer covers the nonmagnetic resin layer. The magnetic shield layer covers an entire or substantially an entire surface of the metal shield layer.
    Type: Grant
    Filed: May 9, 2019
    Date of Patent: December 29, 2020
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Hirokazu Yazaki
  • Patent number: 10867936
    Abstract: A semiconductor device includes a first die embedded in a molding material, where contact pads of the first die are proximate a first side of the molding material. The semiconductor device further includes a redistribution structure over the first side of the molding material, a first metal coating along sidewalls of the first die and between the first die and the molding material, and a second metal coating along sidewalls of the molding material and on a second side of the molding material opposing the first side.
    Type: Grant
    Filed: December 11, 2019
    Date of Patent: December 15, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chuei-Tang Wang, Chen-Hua Yu, Wei-Ting Chen, Chieh-Yen Chen
  • Patent number: 10834858
    Abstract: A method for shielding a system-in-package (SIP) assembly from electromagnetic interference (EMI) includes laminating a pre-form EMI shielding film onto the assembly in a single lamination process. The EMI shielding film may be moldable in a vacuum lamination process to cover the SIP assembly and to substantially fill trenches formed in the assembly between adjacent component modules. The SIP assembly is accordingly shielded from EMI through the application of a single EMI shielding film.
    Type: Grant
    Filed: November 12, 2019
    Date of Patent: November 10, 2020
    Assignee: HENKEL IP & HOLDING GMBH
    Inventors: Xuan Hong, Daniel Maslyk, Qizhuo Zhuo, Juliet Grace Sanchez
  • Patent number: 10825780
    Abstract: A method includes forming a first semiconductor device, wherein the first semiconductor device includes a top surface and a bottom surface, and wherein the first semiconductor device includes a metal layer having an exposed first surface. The method also includes forming a Electromagnetic Interference (EMI) layer over the top surface and sidewalls of the first semiconductor device, wherein the EMI layer electrically contacts the exposed first surface of the metal layer. The method also includes forming a molding compound over the EMI layer.
    Type: Grant
    Filed: November 29, 2016
    Date of Patent: November 3, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chi-Hsi Wu, Hsien-Wei Chen, Li-Hsien Huang, Tien-Chung Yang
  • Patent number: 10793419
    Abstract: A MEMS assembly includes a housing having an internal volume V, wherein the housing has a sound opening to the internal volume V, a MEMS component in the housing adjacent to the sound opening, and a layer element arranged at least regionally at a surface region of the housing that faces the internal volume V, wherein the layer element includes a layer material having a lower thermal conductivity and a higher heat capacity than the housing material of the housing that adjoins the layer element.
    Type: Grant
    Filed: February 7, 2019
    Date of Patent: October 6, 2020
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Marc Fueldner, Niccolo De Milleri, Bernd Goller, Ulrich Krumbein, Gerhard Lohninger, Giordano Tosolini, Andreas Wiesbauer
  • Patent number: 10790216
    Abstract: The present disclosure relates to a thermally enhanced semiconductor package, which includes a module substrate, a thinned flip chip die over the module substrate, a mold compound component, a thermally conductive film, and a thermally enhanced mold compound component. The mold compound component resides over the module substrate, surrounds the thinned flip chip die, and extends above an upper surface of the thinned flip chip die to form a cavity over the upper surface of the thinned flip chip die. The thermally conductive film resides over at least the upper surface of the thinned flip chip at the bottom of the cavity. The thermally enhanced mold compound component resides over at least a portion of the thermally conductive film to fill the cavity.
    Type: Grant
    Filed: July 18, 2018
    Date of Patent: September 29, 2020
    Assignee: Qorvo US, Inc.
    Inventors: Julio C. Costa, Robert Aigner
  • Patent number: 10784200
    Abstract: Methods of blocking ionizing radiation to reduce soft errors and resulting IC chips are disclosed. One embodiment includes forming a front end of line (FEOL) for an integrated circuit (IC) chip; and forming at least one back end of line (BEOL) dielectric layer including ionizing radiation blocking material therein. Another embodiment includes forming a front end of line (FEOL) for an integrated circuit (IC) chip; and forming an ionizing radiation blocking layer positioned in a back end of line (BEOL) of the IC chip. The ionizing radiation blocking material or layer absorbs ionizing radiation and reduces soft errors within the IC chip.
    Type: Grant
    Filed: March 1, 2012
    Date of Patent: September 22, 2020
    Assignee: International Business Machines Corporation
    Inventors: Mukta G. Farooq, Ian D. Melville, Kevin S. Petrarca, Kenneth P. Rodbell
  • Patent number: 10777482
    Abstract: A multipart lid is provided. The multipart lid may include a formed upper lid designed for maximum heat dissipation, a coined lower lid joined to the formed upper lid, where the coined lower lid comprises a coefficient of thermal expansion (CTE) substantially equal to a CTE of a first semiconductor component. A structure is provided. The structure may include a substrate, a first semiconductor component electrically connected and mounted on the substrate, one or more discrete components electrically connected and mounted on the substrate, a substrate mounted multipart lid covering both the semiconductor component and the one or more discrete components, where the multipart lid comprises a heat dissipating upper lid and a lower lid, where a coefficient of thermal expansion (CTE) of the lower lid substantially matches a CTE of the first semiconductor component.
    Type: Grant
    Filed: May 7, 2019
    Date of Patent: September 15, 2020
    Assignee: ELPIS TECHNOLOGIES INC.
    Inventors: Charles L. Arvin, Steven P. Ostrander, Krishna R. Tunga
  • Patent number: 10756026
    Abstract: A semiconductor device functioning properly by maintaining an electromagnetic shielding structure by a conductor layer is provided. A semiconductor device includes a wiring board having a surface, a semiconductor element, an insulating layer, and a conductor layer. The semiconductor element is arranged on the surface of the wiring board. The insulating layer is located on the surface of the wiring board and arranged to surround the semiconductor element. The conductor layer covers an outer peripheral surface of the insulating layer, and is connected to the wiring board. The outer peripheral surface of the insulating layer includes an upper surface located over the semiconductor element, and a side surface connecting the upper surface and the wiring board. The side surface includes a reverse tapered portion. The conductor layer is in contact with a surface of the reverse tapered portion.
    Type: Grant
    Filed: May 29, 2017
    Date of Patent: August 25, 2020
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Kiyoshi Ishida, Yukinobu Tarui
  • Patent number: 10727221
    Abstract: An ESD protection device for protecting an integrated circuit against an ESD event includes a first terminal coupled to an input/output pad of the IC, a second terminal coupled to a reference or ground voltage, a silicon-controlled rectifier device having an anode connected to the first terminal and a cathode connected to the reference or ground voltage, and a pnp transistor coupled in parallel with the SCR device. The pnp transistor has an emitter coupled to the first terminal, a collector coupled to the second terminal, and a base coupled to a gate of the SCR. The pnp transistor includes a contact region formed at a first side of a substrate, the first contact region being surrounded by an STI layer formed at the first side of the substrate. An insulation structure is formed at an intersection of the first contact region and the STI layer.
    Type: Grant
    Filed: February 27, 2019
    Date of Patent: July 28, 2020
    Assignee: NXP USA, Inc.
    Inventors: Rouying Zhan, Jean-Philippe Laine, Evgueniy Nikolov Stefanov, Alain Salles, Patrice Besse
  • Patent number: 10718825
    Abstract: A magnetic field sensor includes a magnetic sense element and a shield structure formed on a substrate. The shield structure fully encircles the magnetic sense element for suppressing stray magnetic fields along a first axis and a second axis, both of which are parallel to a surface of the substrate and perpendicular to one another. A magnetic field is oriented along a third axis perpendicular to the surface of the substrate, and the magnetic sense element is configured to sense a magnetic field along the first axis. A magnetic field deflection element, formed on the substrate proximate the magnetic sense element, redirects the magnetic field from the third axis into the first axis to be sensed as a measurement magnetic field by the magnetic sense element. At least two magnetic field sensors, each fully encircled by a shield structure, form a gradient unit for determining a magnetic field gradient.
    Type: Grant
    Filed: September 13, 2017
    Date of Patent: July 21, 2020
    Assignee: NXP B.V.
    Inventors: Stephan Marauska, Jörg Kock, Hartmut Matz, Mark Isler, Dennis Helmboldt
  • Patent number: 10665566
    Abstract: An electronic component includes: a substrate; a device chip including a functional element located on a lower surface thereof and mounted on an upper surface of the substrate so that the functional element faces the upper surface of the substrate across an air gap; a ring-shaped metal layer located on the upper surface of the substrate and surrounding the device chip in plan view, a side surface of the ring-shaped metal layer being located further in than a side surface of the substrate; a metal sealing portion surrounding the device chip in plan view and bonding with an upper surface of the ring-shaped metal layer, a side surface of the metal sealing portion being located further out than the side surface of the ring-shaped metal layer; and a metal film located on the side surface of the metal sealing portion and the side surface of the ring-shaped metal layer.
    Type: Grant
    Filed: November 3, 2017
    Date of Patent: May 26, 2020
    Assignee: TAIYO YUDEN CO., LTD.
    Inventor: Takuma Kuroyanagi
  • Patent number: 10659003
    Abstract: An electronic component includes: a first substrate; a second substrate that includes a functional element formed on a lower surface of the second substrate, the second substrate being mounted on the first substrate so that the functional element faces an upper surface of the first substrate across an air gap; and an insulating film that is located on the upper surface of the first substrate, overlaps with at least a part of the functional element in plan view, faces the functional element across the air gap, and has a film thickness that is more than half of a distance between a lower surface of the functional element and the upper surface of the first substrate.
    Type: Grant
    Filed: November 3, 2017
    Date of Patent: May 19, 2020
    Assignee: TAIYO YUDEN CO., LTD.
    Inventors: Hidetaro Nakazawa, Takashi Matsuda
  • Patent number: 10658303
    Abstract: A packaged semiconductor device includes: a substrate; an semiconductor die attached to a top surface of the substrate; a mold body surrounding the semiconductor die; a tiered through mold via (TMV) comprising: a first recess having a recessed surface within the mold body at a first depth, and a second recess from the recessed surface to a second depth that exposes a ground contact area on a bonding area on the top surface of the substrate, wherein the first depth is greater than the second depth; and a metal shielding layer formed on a top surface of the mold body to form a shielded mold body, wherein the metal shielding layer makes direct contact with at least one sidewall of the first recess, with at least a portion of the recessed surface, with at least one sidewall of the second recess, and with the ground contact area.
    Type: Grant
    Filed: November 8, 2018
    Date of Patent: May 19, 2020
    Assignee: NXP USA, Inc.
    Inventors: Michael B. Vincent, Stephen Ryan Hooper, Dwight Lee Daniels
  • Patent number: 10629542
    Abstract: An electronic device module includes a substrate, at least one first component and at least one second component disposed on one surface of the substrate, a shielding wall disposed between the at least one first component and the at least one second component, and disposed on the substrate, and a sealing portion having the at least one first component, the at least one second component and the shielding wall embedded therein, and disposed on the substrate. The shielding wall includes at least one insulating layer and at least one conductive layer disposed on the insulating layer.
    Type: Grant
    Filed: November 6, 2018
    Date of Patent: April 21, 2020
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Suk Youn Hong, Jang Hyun Kim, Hye Kyung Kim, Seung Hyun Hong, Jong In Ryu
  • Patent number: 10600743
    Abstract: A method to fabricate an electronic package is described and includes the steps of: connecting a plurality of semiconductor chips to at least one surface of a substrate using a connect pad; encapsulating the semiconductor chips with a non-conductive material; and forming an electro-magnetic interference shield layer over the encapsulated semiconductor chip.
    Type: Grant
    Filed: September 12, 2018
    Date of Patent: March 24, 2020
    Assignee: Inari Semiconductor Labs Sdn Bhd
    Inventors: Ching-Fong Lee, Heap-Hooi Nyeo, Chin-Chooi Ch'ng, Ooi-Lin Cheng
  • Patent number: 10600723
    Abstract: The present disclosure relates to a thermally enhanced semiconductor package, which includes a module substrate, a thinned flip chip die over the module substrate, a mold compound component, a thermally conductive film, and a thermally enhanced mold compound component. The mold compound component resides over the module substrate, surrounds the thinned flip chip die, and extends above an upper surface of the thinned flip chip die to form a cavity over the upper surface of the thinned flip chip die. The thermally conductive film resides over at least the upper surface of the thinned flip chip at the bottom of the cavity. The thermally enhanced mold compound component resides over at least a portion of the thermally conductive film to fill the cavity.
    Type: Grant
    Filed: July 18, 2018
    Date of Patent: March 24, 2020
    Assignee: Qorvo US, Inc.
    Inventors: Julio C. Costa, Robert Aigner
  • Patent number: 10593630
    Abstract: A semiconductor package includes a semiconductor die, a plurality of conductive bumps, a shielding layer, an encapsulant and a redistribution layer. The semiconductor die has an active surface, a backside surface and a lateral surface. The conductive bumps are disposed on the active surface of the semiconductor die. The shielding layer is disposed on the lateral surface of the semiconductor die. The encapsulant covers the shielding layer, and has a first surface and a second surface opposite to the first surface. The redistribution layer is disposed on the first surface of the encapsulant and electrically connected to the semiconductor die through the conductive bumps. The shielding layer is electrically connected to the redistribution layer.
    Type: Grant
    Filed: May 11, 2018
    Date of Patent: March 17, 2020
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Hsu-Nan Fang, Chun-Jun Zhuang, Yung I. Yeh
  • Patent number: 10573590
    Abstract: Device and method of forming the device are disclosed. A device includes a buildup package substrate with top and bottom surfaces and a plurality of interlevel dielectric (ILD) layers with interconnect structures printed layer by layer and includes a die region and a non-die region on the top surface. A semiconductor die is disposed in the die and non-die regions of the package substrate and is electrically connected to the plurality of interconnect structures via a plurality of wire bonds. A plurality of conductive elements are disposed on the bottom surface of the package substrate and a dielectric layer encapsulates the semiconductor die, the wire bonds and the top surface of the buildup package substrate.
    Type: Grant
    Filed: October 19, 2017
    Date of Patent: February 25, 2020
    Assignee: UTAC Headquarters Pte. Ltd.
    Inventors: Antonio Bambalan Dimaano, Jr., Roel Adeva Robles
  • Patent number: 10553521
    Abstract: The present disclosure relates to a thermally enhanced semiconductor package, which includes a module substrate, a thinned flip chip die over the module substrate, a mold compound component, a thermally conductive film, and a thermally enhanced mold compound component. The mold compound component resides over the module substrate, surrounds the thinned flip chip die, and extends above an upper surface of the thinned flip chip die to form a cavity over the upper surface of the thinned flip chip die. The thermally conductive film resides over at least the upper surface of the thinned flip chip at the bottom of the cavity. The thermally enhanced mold compound component resides over at least a portion of the thermally conductive film to fill the cavity.
    Type: Grant
    Filed: July 18, 2018
    Date of Patent: February 4, 2020
    Assignee: Qorvo US, Inc.
    Inventors: Julio C. Costa, Robert Aigner
  • Patent number: 10531558
    Abstract: An electronic module having an electromagnetic shielding structure and its manufacturing method are provided. At first, a first substrate and a second substrate are separately provided. At least one electronic element and at least one connection pad are formed on a surface of the first substrate. The second substrate includes a conductive film and at least one conductive bump is formed on a surface of the conductive film. The first substrate and the second substrate are laminated together wherein the conductive bump is aligned with and connected to the connection pad to obtain the electronic module.
    Type: Grant
    Filed: December 15, 2015
    Date of Patent: January 7, 2020
    Assignee: CYNTEC CO., LTD.
    Inventor: Ming-Che Wu
  • Patent number: 10529670
    Abstract: A semiconductor structure includes a packaged semiconductor device having at least one device, a conductive pillar, an encapsulant over the at least one device and surrounding the conductive pillar, wherein the conductive pillar extends from a first major surface to a second major surface of the encapsulant, and is exposed at the second major surface and the at least one device is exposed at the first major surface. The packaged device also includes a conductive shield layer on the second major surface of the encapsulant and on minor surfaces of the encapsulant and an isolation region at the second major surface of the encapsulant between the encapsulant and the conductive pillar such that the conductive shield layer is electrically isolated from the conductive pillar. The semiconductor structure also includes a radio-frequency connection structure over and in electrical contact with the conductive pillar at the second major surface of the encapsulant.
    Type: Grant
    Filed: January 28, 2019
    Date of Patent: January 7, 2020
    Assignee: NXP USA, Inc.
    Inventors: Michael B. Vincent, Gregory J. Durnan
  • Patent number: 10515887
    Abstract: A semiconductor package structure is provided. The semiconductor package structure includes a first carrier substrate having a first surface and an opposing second surface. A second carrier substrate is stacked on the first carrier substrate and has a first surface and an opposing second surface that faces the first surface of the first carrier substrate. A semiconductor die is mounted on the first surface of the second carrier substrate. A heat spreader is disposed on the first surface of the first carrier substrate to cover and surround the second carrier substrate and the semiconductor die. A method for forming the semiconductor package structure is also provided.
    Type: Grant
    Filed: September 11, 2017
    Date of Patent: December 24, 2019
    Assignee: MediaTek Inc.
    Inventors: Shih-Yi Syu, Chia-Yu Jin, Che-Ya Chou, Wen-Sung Hsu, Nan-Cheng Chen
  • Patent number: 10510632
    Abstract: A semiconductor device has a carrier and a semiconductor die disposed over the carrier. A dummy die is disposed over the carrier as well. A first encapsulant is deposited over the semiconductor die and dummy die. The dummy die and a first portion of the first encapsulant is backgrinded while a second portion of the first encapsulant remains covering the semiconductor die. Backgrinding the dummy die fully removes the dummy die while the second portion of the first encapsulant remains covering the semiconductor die. A second encapsulant is optionally deposited over the dummy die prior to disposing the dummy die over the carrier. A conductive pillar is optionally formed over the dummy die prior to depositing the second encapsulant. The carrier is removed to expose an active surface of the semiconductor die. A build-up interconnect structure is formed over the active surface after removing the carrier.
    Type: Grant
    Filed: March 13, 2018
    Date of Patent: December 17, 2019
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: Won Kyoung Choi, Pandi Chelvam Marimuthu
  • Patent number: 10510682
    Abstract: A semiconductor device includes a first die embedded in a molding material, where contact pads of the first die are proximate a first side of the molding material. The semiconductor device further includes a redistribution structure over the first side of the molding material, a first metal coating along sidewalls of the first die and between the first die and the molding material, and a second metal coating along sidewalls of the molding material and on a second side of the molding material opposing the first side.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: December 17, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chuei-Tang Wang, Chen-Hua Yu, Wei-Ting Chen, Chieh-Yen Chen
  • Patent number: 10510679
    Abstract: A semiconductor device includes a first die embedded in a molding material, where contact pads of the first die are proximate a first side of the molding material. The semiconductor device further includes a redistribution structure over the first side of the molding material, a first metal coating along sidewalls of the first die and between the first die and the molding material, and a second metal coating along sidewalls of the molding material and on a second side of the molding material opposing the first side.
    Type: Grant
    Filed: November 1, 2017
    Date of Patent: December 17, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chuei-Tang Wang, Chen-Hua Yu, Wei-Ting Chen, Chieh-Yen Chen
  • Patent number: 10504818
    Abstract: The present disclosure relates to a thermally enhanced semiconductor package, which includes a module substrate, a thinned flip chip die over the module substrate, a mold compound component, a thermally conductive film, and a thermally enhanced mold compound component. The mold compound component resides over the module substrate, surrounds the thinned flip chip die, and extends above an upper surface of the thinned flip chip die to form a cavity over the upper surface of the thinned flip chip die. The thermally conductive film resides over at least the upper surface of the thinned flip chip at the bottom of the cavity. The thermally enhanced mold compound component resides over at least a portion of the thermally conductive film to fill the cavity.
    Type: Grant
    Filed: July 18, 2018
    Date of Patent: December 10, 2019
    Assignee: Qorvo US, Inc.
    Inventors: Julio C. Costa, Robert Aigner
  • Patent number: 10453762
    Abstract: Several aspects of the present technology are directed toward fan-out packaged semiconductor devices having an integrated shield to protect against electromagnetic interference and methods of manufacturing such devices. The shield can be constructed by forming a conductive wall on a redistribution structure and disposing a conductive cap on an upper surface of an encapsulant. The conductive wall and the conductive cap are electrically connected to each other. By forming the conductive wall directly on the redistribution structure and separately disposing the conductive cap onto an upper surface of the encapsulant, an electromagnetic shield can be readily formed using wafer-level or panel-level processing techniques that are efficient and cost-effective. Several embodiments of semiconductor devices in accordance with the present technology accordingly shield the integrated circuitry of semiconductor dies from electromagnetic interference.
    Type: Grant
    Filed: July 28, 2017
    Date of Patent: October 22, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Fumitomo Watanabe, Keiyo Kusanagi
  • Patent number: 10446503
    Abstract: Shielded radio-frequency (RF) module having reduced area. In some embodiments, a method for fabricating a radio-frequency module includes forming or providing a packaging substrate configured to receive a plurality of components. The method may include mounting one or more devices on the packaging substrate such that the packaging substrate includes a first area associated with mounting of each of the one or more devices. In some embodiments, the method further includes forming a plurality of shielding wirebonds on the packaging substrate to provide RF shielding functionality for one or more regions on the packaging substrate, such that the packaging substrate includes a second area associated with formation of each shielding wirebond, the mounting of each device implemented with respect to a corresponding shielding wirebond such that a portion of the first area associated with the device overlaps at least partially with a portion of the second area associated with the corresponding shielding wirebond.
    Type: Grant
    Filed: September 12, 2017
    Date of Patent: October 15, 2019
    Assignee: Skyworks Solutions, Inc.
    Inventors: Howard E. Chen, Matthew Sean Read
  • Patent number: 10446470
    Abstract: The present disclosure relates to a thermally enhanced semiconductor package, which includes a module substrate, a thinned flip chip die over the module substrate, a mold compound component, a thermally conductive film, and a thermally enhanced mold compound component. The mold compound component resides over the module substrate, surrounds the thinned flip chip die, and extends above an upper surface of the thinned flip chip die to form a cavity over the upper surface of the thinned flip chip die. The thermally conductive film resides over at least the upper surface of the thinned flip chip at the bottom of the cavity. The thermally enhanced mold compound component resides over at least a portion of the thermally conductive film to fill the cavity.
    Type: Grant
    Filed: July 18, 2018
    Date of Patent: October 15, 2019
    Assignee: Qorvo US, Inc.
    Inventors: Julio C. Costa, Robert Aigner
  • Patent number: 10410975
    Abstract: A processed semiconductor wafer has layered elements that define electrical circuits and a double-seal ring surrounding each individual electrical circuit. The layered elements further define another double-seal ring that surrounds at least two electrical circuits. The processed semiconductor wafer can have additional layered elements that extend each of the double-seal rings that surround individual circuits or, that can extend the other double-seal ring. A method of fabricating such a processed semiconductor wafer. A device comprising two such electrical circuits.
    Type: Grant
    Filed: September 4, 2015
    Date of Patent: September 10, 2019
    Assignee: MICROSEMI SOLUTIONS (U.S.), INC.
    Inventors: Bruce Scatchard, Peter Onufryk, Chunfang Xie
  • Patent number: 10403587
    Abstract: A radio frequency circuit includes, a multilayer substrate having a grounded base metal and a plurality of insulating layers and wiring layers formed over the grounded base metal and having a recess surrounded by the plurality of insulating layers and wiring layers over the grounded base metal, an upper substrate having a through-hole penetrating the upper substrate, a first semiconductor chip mounted on the upper surface of the upper substrate and electrically coupled to a metal film formed on the lower surface of the upper substrate, a metal pillar formed on the upper surface of the grounded base metal in the recess, and a solder buried in the through-hole and bonded to the metal film and the upper surface of the metal pillar. The metal film is bonded to a ground wiring layer electrically coupled to the grounded base metal among the plurality of wiring layers.
    Type: Grant
    Filed: April 5, 2018
    Date of Patent: September 3, 2019
    Assignee: FUJITSU LIMITED
    Inventors: Masaru Sato, Yukiyasu Furukawa
  • Patent number: 10396011
    Abstract: The present disclosure relates to a thermally enhanced semiconductor package, which includes a module substrate, a thinned flip chip die over the module substrate, a mold compound component, a thermally conductive film, and a thermally enhanced mold compound component. The mold compound component resides over the module substrate, surrounds the thinned flip chip die, and extends above an upper surface of the thinned flip chip die to form a cavity over the upper surface of the thinned flip chip die. The thermally conductive film resides over at least the upper surface of the thinned flip chip at the bottom of the cavity. The thermally enhanced mold compound component resides over at least a portion of the thermally conductive film to fill the cavity.
    Type: Grant
    Filed: July 18, 2018
    Date of Patent: August 27, 2019
    Assignee: Qorvo US, Inc.
    Inventors: Julio C. Costa, Robert Aigner
  • Patent number: 10347560
    Abstract: The present disclosure relates to a thermally enhanced semiconductor package, which includes a module substrate, a thinned flip chip die over the module substrate, a mold compound component, a thermally conductive film, and a thermally enhanced mold compound component. The mold compound component resides over the module substrate, surrounds the thinned flip chip die, and extends above an upper surface of the thinned flip chip die to form a cavity over the upper surface of the thinned flip chip die. The thermally conductive film resides over at least the upper surface of the thinned flip chip at the bottom of the cavity. The thermally enhanced mold compound component resides over at least a portion of the thermally conductive film to fill the cavity.
    Type: Grant
    Filed: July 18, 2018
    Date of Patent: July 9, 2019
    Assignee: Qorvo US, Inc.
    Inventors: Julio C. Costa, Robert Aigner
  • Patent number: 10325830
    Abstract: A multipart lid is provided. The multipart lid may include a formed upper lid designed for maximum heat dissipation, a coined lower lid joined to the formed upper lid, where the coined lower lid comprises a coefficient of thermal expansion (CTE) substantially equal to a CTE of a first semiconductor component. A structure is provided. The structure may include a substrate, a first semiconductor component electrically connected and mounted on the substrate, one or more discrete components electrically connected and mounted on the substrate, a substrate mounted multipart lid covering both the semiconductor component and the one or more discrete components, where the multipart lid comprises a heat dissipating upper lid and a lower lid, where a coefficient of thermal expansion (CTE) of the lower lid substantially matches a CTE of the first semiconductor component.
    Type: Grant
    Filed: November 30, 2017
    Date of Patent: June 18, 2019
    Assignee: International Business Machines Corporation
    Inventors: Charles L. Arvin, Steven P. Ostrander, Krishna R. Tunga
  • Patent number: 10319686
    Abstract: A radiation-hard electronic device including a package structure, a semiconductor chip in a cavity within the package structure, an integrated circuit in the semiconductor chip, and structures for protection from radiation for protecting the integrated circuit from ionizing radiation. The structures for protection from radiation include a protective layer of gel, which occupies at least in part the cavity and coats the semiconductor chip.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: June 11, 2019
    Assignee: STMicroelectronics S.r.l.
    Inventor: Ignazio Bruno Mirabella
  • Patent number: 10297529
    Abstract: The present disclosure relates to a thermally enhanced semiconductor package, which includes a module substrate, a thinned flip chip die over the module substrate, a mold compound component, a thermally conductive film, and a thermally enhanced mold compound component. The mold compound component resides over the module substrate, surrounds the thinned flip chip die, and extends above an upper surface of the thinned flip chip die to form a cavity over the upper surface of the thinned flip chip die. The thermally conductive film resides over at least the upper surface of the thinned flip chip at the bottom of the cavity. The thermally enhanced mold compound component resides over at least a portion of the thermally conductive film to fill the cavity.
    Type: Grant
    Filed: July 18, 2018
    Date of Patent: May 21, 2019
    Assignee: Qorvo US, Inc.
    Inventors: Julio C. Costa, Robert Aigner
  • Patent number: 10269673
    Abstract: Packaged semiconductor devices and methods of packaging semiconductor devices are disclosed. In some embodiments, a packaged semiconductor device includes an integrated circuit die, a molding compound disposed around the integrated circuit die, and an interconnect structure disposed over the integrated circuit die and the molding compound. The molding compound is thicker than the integrated circuit die.
    Type: Grant
    Filed: February 27, 2018
    Date of Patent: April 23, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Chen-Hua Yu, Chung-Shi Liu, Chih-Fan Huang, Chih-Wei Lin, Wei-Hung Lin, Ming-Da Cheng
  • Patent number: 10269718
    Abstract: A rectangular semiconductor package and a method manufacturing the same described in the present disclosure features no carrier installed on a die cut from a wafer. In an embodiment, a first die on a top surface of a conductive routing layer is electrically connected to the conductive routing layer through a plurality of first metal wires, a plurality of conductive balls is installed on a bottom surface of the conductive routing layer, and a molding compound is used to encase the first die on the conductive routing layer. In another embodiment, a second die is added in the above rectangular semiconductor package and encased in the molding compound, as is the first die. Alternatively, the molding compound is processed such that the second die encapsulated in a package is stacked on the molding compound and electrically connected to the conductive routing layer.
    Type: Grant
    Filed: July 18, 2017
    Date of Patent: April 23, 2019
    Assignee: WALTON ADVANCED ENGINEERING INC.
    Inventors: Hong Chi Yu, Chun Jung Lin
  • Patent number: 10153253
    Abstract: A system-in-package apparatus includes a package substrate configured to carry at least one semiconductive device on a die side and a through-mold via package bottom interposer disposed on the package substrate on a land side. A land side board mates with the through-mold via package bottom interposer, and enough vertical space is created by the through-mold via package bottom interposer to allow space for at least one device disposed on the package substrate on the land side.
    Type: Grant
    Filed: November 21, 2016
    Date of Patent: December 11, 2018
    Assignee: Intel Corporation
    Inventors: Howe Yin Loo, Eng Huat Goh, Min Suet Lim, Bok Eng Cheah, Jackson Chung Peng Kong, Khang Choong Yong
  • Patent number: 10128203
    Abstract: A fan-out package structure is disclosed. The fan-out package structure includes an antenna main body; a redistribution layer (RDL); and an antenna auxiliary body in the RDL. An antenna system is also disclosed. The antenna system includes: an antenna main body, arranged to provide a first resonance; and an antenna auxiliary body, arranged to provide a second resonance through parasitic coupling to the antenna main body; wherein a dimension of the antenna main body is greater than a dimension of the antenna auxiliary body. An associated semiconductor packaging method is also disclosed.
    Type: Grant
    Filed: February 2, 2016
    Date of Patent: November 13, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Wei-Ting Chen, Tzu-Chun Tang, Ming Hung Tseng, In-Tsang Lin, Vincent Chen, Chuei-Tang Wang, Hung-Yi Kuo
  • Patent number: 10068831
    Abstract: The present disclosure relates to a thermally enhanced semiconductor package, which includes a module substrate, a thinned flip chip die over the module substrate, a mold compound component, a thermally conductive film, and a thermally enhanced mold compound component. The mold compound component resides over the module substrate, surrounds the thinned flip chip die, and extends above an upper surface of the thinned flip chip die to form a cavity over the upper surface of the thinned flip chip die. The thermally conductive film resides over at least the upper surface of the thinned flip chip at the bottom of the cavity. The thermally enhanced mold compound component resides over at least a portion of the thermally conductive film to fill the cavity.
    Type: Grant
    Filed: April 19, 2017
    Date of Patent: September 4, 2018
    Assignee: Qorvo US, Inc.
    Inventors: Julio C. Costa, Robert Aigner
  • Patent number: 10014260
    Abstract: Package structures and methods for forming the same are provided. A method for forming a package structure includes providing a carrier substrate. The method also includes forming a conductive layer over the carrier substrate. The method further includes forming a passivation layer over the conductive layer. The passivation layer includes openings that expose portions of the conductive layer. In addition, the method includes bonding integrated circuit dies to the portions of the conductive layer through bumps. There is a space between the integrated circuit dies and the passivation layer. The method also includes filling the space with a first molding compound. The first molding compound surrounds the bumps and the integrated circuit dies. The method further includes forming a second molding compound capping the first molding compound and the integrated circuit dies. The passivation layer has a sidewall that is covered by the second molding compound.
    Type: Grant
    Filed: November 10, 2016
    Date of Patent: July 3, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yi-Da Tsai, Cheng-Ping Lin, Wei-Hung Lin, Chih-Wei Lin, Ming-Da Cheng, Ching-Hua Hsieh, Chung-Shi Liu
  • Patent number: 9991194
    Abstract: A method of manufacture and a substrate for sensor packages is provided. The method involves premolding a lead frame with strips having V-grooves; cutting the substrate partially, and plating the exposed surfaces of the lead frame. The method subsequently involves attaching a die to a dies pad and connecting wires between the die and leads to form a sensor package. The sensor package is separated from the substrate by snapping along the score line. The substrate for assembly of sensor packages as well as substrate of sensor packages is manufactured using at least part of the method of manufacture.
    Type: Grant
    Filed: April 18, 2017
    Date of Patent: June 5, 2018
    Assignee: UBOTIC COMPANY LIMITED
    Inventors: Ming-Wa Tam, Ken Lik Hang Wan, Wa San Leung
  • Patent number: 9947624
    Abstract: The invention provides a semiconductor package assembly with a TSV interconnect. The semiconductor package assembly includes a first semiconductor package mounted on a base, having: a semiconductor die, a semiconductor substrate, and a first array of TSV interconnects and a second array of TSV interconnects formed through the semiconductor substrate, wherein the first array and second array of TSV interconnects are separated by an interval region. The assembly further includes a second semiconductor die mounted on the first semiconductor package, having a ground pad thereon. One of the TSV interconnects of the first semiconductor package has a first terminal coupled to the ground pad of the second semiconductor die and a second terminal coupled to an interconnection structure disposed on a front side of the semiconductor substrate.
    Type: Grant
    Filed: December 29, 2016
    Date of Patent: April 17, 2018
    Assignee: MediaTek Inc.
    Inventors: Ming-Tzong Yang, Cheng-Chou Hung, Wei-Che Huang, Yu-Hua Huang, Tzu-Hung Lin, Kuei-Ti Chan, Ruey-Beei Wu, Kai-Bin Wu
  • Patent number: 9924594
    Abstract: A printed circuit board (PCB) has a first, structured metalization arranged on its top side and at least one second metalization arranged below the first metalization in a vertical direction, parallel to the first metalization and insulated therefrom. Also on the PCB top side is a bare semiconductor chip having contact electrodes connected by bonding wires to corresponding contact pads of the first metalization on the PCB top side. A first portion of the contact electrodes and corresponding contact pads carry high voltage during operation. All high-voltage-carrying contact pads are conductively connected to the second metalization via plated-through holes. An insulation layer completely covers the chip and a delimited region of the PCB around the chip, and all high-voltage-carrying contact pads and the plated-through holes are completely covered by the insulation layer. A second portion of the contact electrodes and corresponding contact pads are under low voltages during operation.
    Type: Grant
    Filed: September 29, 2014
    Date of Patent: March 20, 2018
    Assignee: Infineon Technologies AG
    Inventors: Andre Arens, Juergen Hoegerl, Magdalena Hoier
  • Patent number: 9905546
    Abstract: A method for fabricating a package on package (PoP) structure is provided, which includes: providing a first packaging substrate having at least a first electronic element and a plurality of first support portions, wherein the first electronic element is electrically connected to the first packaging substrate; forming an encapsulant on the first packaging substrate for encapsulating the first electronic element and the first support portions; forming a plurality of openings in the encapsulant for exposing portions of surfaces of the first support portions; and providing a second packaging substrate having a plurality of second support portions and stacking the second packaging substrate on the first packaging substrate with the second support portions positioned in the openings of the encapsulant and bonded with the first support portions. As such, the encapsulant effectively separates the first support portions or the second support portions from one another to prevent bridging from occurring therebetween.
    Type: Grant
    Filed: March 14, 2014
    Date of Patent: February 27, 2018
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Shih-Hao Tung, Chang-Yi Lan, Lung-Yuan Wang, Cheng-Chia Chiang, Chu-Huei Huang
  • Patent number: 9842826
    Abstract: An integrated fan out package on package architecture is utilized along with a reference via in order to provide a reference voltage that extends through the InFO-POP architecture. If desired, the reference via may be exposed and then connected to a shield coating that can be used to shield the InFO-POP architecture. The reference via may be exposed by exposing either a top surface or a sidewall of the reference via using one or more singulation processes.
    Type: Grant
    Filed: July 15, 2015
    Date of Patent: December 12, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jing-Cheng Lin, Chen-Hua Yu, Po-Hao Tsai