With Means To Shield Device Contained In Housing Or Package From Charged Particles (e.g., Alpha Particles) Or Highly Ionizing Radiation (i.e., Hard X-rays Or Shorter Wavelength) Patents (Class 257/660)
  • Patent number: 11387190
    Abstract: The present disclosure relates to a shielded electronic module, which includes a module substrate, an electronic component attached to a top surface of the module substrate and encapsulated by a first mold compound, a second mold compound over a bottom surface of the module substrate, and a shielding structure. The second mold compound includes a recess extending inwardly from a bottom periphery of the second mold compound. The shielding structure completely covers a top surface of the module and extends over the side surface of the module until reaching the recess. Herein, the shielding structure is electrically grounded.
    Type: Grant
    Filed: October 7, 2020
    Date of Patent: July 12, 2022
    Assignee: QORVO US, INC.
    Inventors: Thomas Scott Morris, Stephen Craig Parker, Jerry Holt, John Davisson, Rommel Quintero Nevarez
  • Patent number: 11380624
    Abstract: A device package and a method of forming the device package are described. The device package includes a substrate having a ground plane and dies disposed on the substrate. The dies are electrically coupled to the substrate with solder balls or bumps surrounded by an underfill layer. The device package has a mold layer disposed over and around the dies, the underfill layer, and the substrate. The device package further includes an additively manufactured electromagnetic interference (EMI) shield layer disposed on an outer surface of the mold layer. The additively manufactured EMI shield layer is electrically coupled to the ground plane of the substrate. The outer surface of the mold layer may include a topmost surface and one or more sidewalls that are covered with the additively manufactured EMI shield layer. The additively manufactured EMI shield may include a first and second additively manufactured EMI shield layers and an additively manufactured EMI shield frame.
    Type: Grant
    Filed: September 30, 2017
    Date of Patent: July 5, 2022
    Assignee: Intel Corporation
    Inventors: Feras Eid, Henning Braunisch, Shawna M. Liff, Georgios C. Dogiamis, Johanna M. Swan
  • Patent number: 11357105
    Abstract: A method for producing a printed circuit board is disclosed, In the method, a slot is formed in a substrate having at least three layers with the slot extending through at least two of the layers. The slot has a length and a width with the length being greater than the width. The sidewall of the substrate surrounding the slot is coated with a conductive layer. Then, the conductive layer is separated into at least two segments that are electrically isolated along the side wall of the substrate.
    Type: Grant
    Filed: August 21, 2017
    Date of Patent: June 7, 2022
    Assignee: NextGin Technology BV
    Inventor: J. A. A. M. Tourne
  • Patent number: 11335651
    Abstract: Embodiments of the invention include a microelectronic device that includes a first silicon based substrate having compound semiconductor components. The microelectronic device also includes a second substrate coupled to the first substrate. The second substrate includes an antenna unit for transmitting and receiving communications at a frequency of approximately 4 GHz or higher.
    Type: Grant
    Filed: December 22, 2015
    Date of Patent: May 17, 2022
    Assignee: Intel Corporation
    Inventors: Telesphor Kamgaing, Georgios C. Dogiamis, Vijay K. Nair, Javier A. Falcon, Shawna M. Liff, Yoshihiro Tomita
  • Patent number: 11296037
    Abstract: A semiconductor package including a first semiconductor chip having an upper surface, a lower surface that is opposite to the upper surface, and a sidewall between the upper surface and the lower surface; a capping insulation layer covering the upper surface and the sidewall of the first semiconductor chip; and a shielding layer on the capping insulation layer, wherein a lower portion of the capping insulation layer includes a laterally protruding capping protrusion contacting a lower surface of the shielding layer.
    Type: Grant
    Filed: October 30, 2019
    Date of Patent: April 5, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Byoung-Gug Min, Younhee Kang, Min-Woo Song
  • Patent number: 11270953
    Abstract: Structures and formation methods of a chip package are provided. The method includes forming multiple conductive structures over a carrier substrate. The method also includes disposing a semiconductor die over the carrier substrate such that the conductive structures surround the semiconductor die. The method further includes forming a protective layer to surround the conductive structures and the semiconductor die. In addition, the method includes disposing a shielding element over the semiconductor die and the conductive structures. The shielding element is electrically connected to the conductive structures.
    Type: Grant
    Filed: February 25, 2019
    Date of Patent: March 8, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Po-Yao Chuang, Po-Hao Tsai, Shin-Puu Jeng, Shuo-Mao Chen, Ming-Chih Yew
  • Patent number: 11266010
    Abstract: A portable electronic device packaged into a System-in-Package assembly is disclosed. The portable electronic device can include a substrate and a plurality of components mounted on the substrate and included in one or more subsystems. Interference between subsystems or from external sources can be reduced or eliminated by disposing an insulating layer over the components, forming narrow trenches between subsystems, and depositing one or more layers of a multi-layer thin film stack on the insulating layer and filling the trenches. In some examples, the multi-layer thin film stack can include an adhesion layer, a shielding layer, a protection layer, and a cosmetic layer. In some examples, the multi-layer thin film stack can include multi-functional layers such as a protection and cosmetic layer.
    Type: Grant
    Filed: December 19, 2019
    Date of Patent: March 1, 2022
    Assignee: Apple Inc.
    Inventors: Yanfeng Chen, Shankar S. Pennathur
  • Patent number: 11227840
    Abstract: A module includes a substrate having a main surface, a first component mounted on the main surface, and a first wire group constituted of three or more wires in parallel with each other that are bonded to the main surface so as to straddle the first component while extending in a first direction. When sections are defined along a second direction perpendicular to the first direction, the first wire group includes a first section in which a distance between wires adjacent to each other is a first length and a second section in which a distance between wires adjacent to each other is a second length longer than the first length.
    Type: Grant
    Filed: July 29, 2019
    Date of Patent: January 18, 2022
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Yoshihito Otsubo, Motohiko Kusunoki
  • Patent number: 11211340
    Abstract: A semiconductor package includes a substrate having a semiconductor chip disposed on a top surface of the substrate, a ground ring surrounding the semiconductor chip on the top surface of the substrate, a metal-post reinforced glue wall disposed on the ground ring to surround the semiconductor chip, and a molding compound disposed only inside the metal-post reinforced glue wall and covering the semiconductor chip. The metal-post reinforced glue wall comprises a magnetic or magnetizable filler so as to form an active electro-magnetic compatibility (EMC) shielding.
    Type: Grant
    Filed: December 17, 2019
    Date of Patent: December 28, 2021
    Inventors: Shiann-Tsong Tsai, Hsien-Chou Tsai, Hsien-Wei Tsai, Yen-Mei Tsai Huang
  • Patent number: 11205602
    Abstract: A semiconductor device and a method of manufacturing a semiconductor device. As a non-limiting example, various aspects of this disclosure provide a stackable semiconductor device with small size and fine pitch and a method of manufacturing thereof.
    Type: Grant
    Filed: August 28, 2018
    Date of Patent: December 21, 2021
    Assignee: Amkor Technology Singapore Holding Pte. Ltd.
    Inventors: Jin Young Khim, Ji Young Chung, Ju Hoon Yoon, Kwang Woong Ahn, Ho Jeong Lim, Tae Yong Lee, Jae Min Bae
  • Patent number: 11184977
    Abstract: A method for producing a printed circuit board is disclosed, In the method, a slot is formed in a substrate having at least three layers with the slot extending through at least two of the layers. The slot has a length and a width with the length being greater than the width. The sidewall of the substrate surrounding the slot is coated with a conductive layer. Then, the conductive layer is separated into at least two segments that are electrically isolated along the side wall of the substrate.
    Type: Grant
    Filed: August 21, 2017
    Date of Patent: November 23, 2021
    Assignee: NextGin Technology BV
    Inventor: J. A. A. M. Tourne
  • Patent number: 11183477
    Abstract: Embodiments include a mixed hybrid bonding structure comprising a composite dielectric layer, where the composite dielectric layer comprises an organic dielectric material having a plurality of inorganic filler material. One or more conductive substrate interconnect structures are within the composite dielectric layer. A die is on the composite dielectric layer, the die having one or more conductive die interconnect structures within a die dielectric material. The one or more conductive die interconnect structures are directly bonded to the one or more conductive substrate interconnect structures, and the inorganic filler material of the composite dielectric layer is bonded to the die dielectric material.
    Type: Grant
    Filed: September 26, 2019
    Date of Patent: November 23, 2021
    Assignee: Intel Corporation
    Inventors: Shawna Liff, Adel Elsherbini, Johanna Swan, Nagatoshi Tsunoda, Jimin Yao
  • Patent number: 11158554
    Abstract: Several aspects of the present technology are directed toward fan-out packaged semiconductor devices having an integrated shield to protect against electromagnetic interference and methods of manufacturing such devices. The shield can be constructed by forming a conductive wall on a redistribution structure and disposing a conductive cap on an upper surface of an encapsulant. The conductive wall and the conductive cap are electrically connected to each other. By forming the conductive wall directly on the redistribution structure and separately disposing the conductive cap onto an upper surface of the encapsulant, an electromagnetic shield can be readily formed using wafer-level or panel-level processing techniques that are efficient and cost-effective. Several embodiments of semiconductor devices in accordance with the present technology accordingly shield the integrated circuitry of semiconductor dies from electromagnetic interference.
    Type: Grant
    Filed: October 18, 2019
    Date of Patent: October 26, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Fumitomo Watanabe, Keiyo Kusanagi
  • Patent number: 11116083
    Abstract: A component carrier includes a core having a recess, an electronic component arranged in the recess, a laminated electrically insulating sheet covering at least part of the core and of the electronic component and filling a gap between a lateral surface of the electronic component and a lateral surface of the core in the recess, and a further electrically insulating layer structure laminated on top of the sheet.
    Type: Grant
    Filed: March 28, 2017
    Date of Patent: September 7, 2021
    Assignee: AT&S (China) Co. Ltd.
    Inventors: Annie Tay, Mikael Tuominen
  • Patent number: 11081434
    Abstract: The present disclosure is directed to systems and methods for improving the impedance matching of semiconductor package substrates by incorporating one or more magnetic build-up layers proximate relatively large diameter, relatively high capacitance, conductive pads formed on the lower surface of the semiconductor package substrate. The one or more magnetic layers may be formed using a magnetic build-up material deposited on the lower surface of the semiconductor package substrate. Vias conductively coupling the conductive pads to bump pads on the upper surface of the semiconductor package substrate pass through and are at least partially surrounded by the magnetic build-up material.
    Type: Grant
    Filed: August 13, 2020
    Date of Patent: August 3, 2021
    Assignee: Intel Corporation
    Inventors: Zhiguo Qian, Kaladhar Radhakrishnan, Kemal Aygun
  • Patent number: 11075170
    Abstract: A semiconductor device with EMI shield and a fabricating method thereof are provided. In one embodiment, the semiconductor device includes EMI shield on all six surfaces of the semiconductor device without the use of a discrete EMI lid.
    Type: Grant
    Filed: January 30, 2020
    Date of Patent: July 27, 2021
    Assignee: AMKOR TECHNOLOGY SINGAPORE HOLDING PTE. LTD.
    Inventors: Doo Soub Shin, Tae Yong Lee, Kyoung Yeon Lee, Sung Gyu Kim
  • Patent number: 10998489
    Abstract: Embodiments are provided for a packaged semiconductor device including: a semiconductor die having an active side and an opposite back side, the semiconductor die including a magnetoresistive random access memory (MRAM) cell array formed within an MRAM area on the active side of the semiconductor die; and a top cover including a soft-magnetic material positioned on the back side of the semiconductor die, wherein the top cover includes a recess formed in a first major surface of the top cover, the first major surface faces the back side of the semiconductor die, and the recess is positioned over the MRAM cell array.
    Type: Grant
    Filed: January 14, 2019
    Date of Patent: May 4, 2021
    Assignee: NXP B.V.
    Inventors: Franciscus Petrus Widdershoven, Antonius Hendrikus Jozef Kamphuis
  • Patent number: 10950556
    Abstract: A method includes forming a metal post over a first dielectric layer, attaching a second dielectric layer over the first dielectric layer, encapsulating a device die, the second dielectric layer, a shielding structure, and the metal post in an encapsulating material, planarizing the encapsulating material to reveal the device die, the shielding structure, and the metal post, and forming an antenna electrically coupling to the device die. The antenna has a portion vertically aligned to a portion of the device die.
    Type: Grant
    Filed: September 13, 2019
    Date of Patent: March 16, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kai-Chiang Wu, Chen-Hua Yu, Ching-Feng Yang, Meng-Tse Chen
  • Patent number: 10903088
    Abstract: An electronic package and a method for fabrication the same are provided. The method includes: disposing an electronic component on a substrate; forming an encapsulant layer on the substrate to encapsulate the electronic component; and forming a shielding layer made of metal on the encapsulant layer. The shielding layer has an extending portion extending to a lateral side of the substrate along a corner of the encapsulant layer, without extending to a lower side of the substrate. Therefore, the present disclosure prevents the shielding layer from coming into contact with conductive pads disposed on the lower side of the substrate and thereby avoids a short circuit from occurrence.
    Type: Grant
    Filed: June 20, 2017
    Date of Patent: January 26, 2021
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Shu-Chi Chang, Wei Ping Wang, Hsien-Lung Hsiao, Kaun-I Cheng
  • Patent number: 10879142
    Abstract: An electronic component includes a board, a surface mount device, a nonmagnetic resin layer, a metal shield layer, and a magnetic shield layer. The board includes first and second principal surfaces facing each other, and a magnetic body layer. The surface mount device is mounted on the first principal surface of the board. The nonmagnetic resin layer covers the surface mount device. The metal shield layer covers the nonmagnetic resin layer. The magnetic shield layer covers an entire or substantially an entire surface of the metal shield layer.
    Type: Grant
    Filed: May 9, 2019
    Date of Patent: December 29, 2020
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Hirokazu Yazaki
  • Patent number: 10867936
    Abstract: A semiconductor device includes a first die embedded in a molding material, where contact pads of the first die are proximate a first side of the molding material. The semiconductor device further includes a redistribution structure over the first side of the molding material, a first metal coating along sidewalls of the first die and between the first die and the molding material, and a second metal coating along sidewalls of the molding material and on a second side of the molding material opposing the first side.
    Type: Grant
    Filed: December 11, 2019
    Date of Patent: December 15, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chuei-Tang Wang, Chen-Hua Yu, Wei-Ting Chen, Chieh-Yen Chen
  • Patent number: 10834858
    Abstract: A method for shielding a system-in-package (SIP) assembly from electromagnetic interference (EMI) includes laminating a pre-form EMI shielding film onto the assembly in a single lamination process. The EMI shielding film may be moldable in a vacuum lamination process to cover the SIP assembly and to substantially fill trenches formed in the assembly between adjacent component modules. The SIP assembly is accordingly shielded from EMI through the application of a single EMI shielding film.
    Type: Grant
    Filed: November 12, 2019
    Date of Patent: November 10, 2020
    Assignee: HENKEL IP & HOLDING GMBH
    Inventors: Xuan Hong, Daniel Maslyk, Qizhuo Zhuo, Juliet Grace Sanchez
  • Patent number: 10825780
    Abstract: A method includes forming a first semiconductor device, wherein the first semiconductor device includes a top surface and a bottom surface, and wherein the first semiconductor device includes a metal layer having an exposed first surface. The method also includes forming a Electromagnetic Interference (EMI) layer over the top surface and sidewalls of the first semiconductor device, wherein the EMI layer electrically contacts the exposed first surface of the metal layer. The method also includes forming a molding compound over the EMI layer.
    Type: Grant
    Filed: November 29, 2016
    Date of Patent: November 3, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chi-Hsi Wu, Hsien-Wei Chen, Li-Hsien Huang, Tien-Chung Yang
  • Patent number: 10793419
    Abstract: A MEMS assembly includes a housing having an internal volume V, wherein the housing has a sound opening to the internal volume V, a MEMS component in the housing adjacent to the sound opening, and a layer element arranged at least regionally at a surface region of the housing that faces the internal volume V, wherein the layer element includes a layer material having a lower thermal conductivity and a higher heat capacity than the housing material of the housing that adjoins the layer element.
    Type: Grant
    Filed: February 7, 2019
    Date of Patent: October 6, 2020
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Marc Fueldner, Niccolo De Milleri, Bernd Goller, Ulrich Krumbein, Gerhard Lohninger, Giordano Tosolini, Andreas Wiesbauer
  • Patent number: 10790216
    Abstract: The present disclosure relates to a thermally enhanced semiconductor package, which includes a module substrate, a thinned flip chip die over the module substrate, a mold compound component, a thermally conductive film, and a thermally enhanced mold compound component. The mold compound component resides over the module substrate, surrounds the thinned flip chip die, and extends above an upper surface of the thinned flip chip die to form a cavity over the upper surface of the thinned flip chip die. The thermally conductive film resides over at least the upper surface of the thinned flip chip at the bottom of the cavity. The thermally enhanced mold compound component resides over at least a portion of the thermally conductive film to fill the cavity.
    Type: Grant
    Filed: July 18, 2018
    Date of Patent: September 29, 2020
    Assignee: Qorvo US, Inc.
    Inventors: Julio C. Costa, Robert Aigner
  • Patent number: 10784200
    Abstract: Methods of blocking ionizing radiation to reduce soft errors and resulting IC chips are disclosed. One embodiment includes forming a front end of line (FEOL) for an integrated circuit (IC) chip; and forming at least one back end of line (BEOL) dielectric layer including ionizing radiation blocking material therein. Another embodiment includes forming a front end of line (FEOL) for an integrated circuit (IC) chip; and forming an ionizing radiation blocking layer positioned in a back end of line (BEOL) of the IC chip. The ionizing radiation blocking material or layer absorbs ionizing radiation and reduces soft errors within the IC chip.
    Type: Grant
    Filed: March 1, 2012
    Date of Patent: September 22, 2020
    Assignee: International Business Machines Corporation
    Inventors: Mukta G. Farooq, Ian D. Melville, Kevin S. Petrarca, Kenneth P. Rodbell
  • Patent number: 10777482
    Abstract: A multipart lid is provided. The multipart lid may include a formed upper lid designed for maximum heat dissipation, a coined lower lid joined to the formed upper lid, where the coined lower lid comprises a coefficient of thermal expansion (CTE) substantially equal to a CTE of a first semiconductor component. A structure is provided. The structure may include a substrate, a first semiconductor component electrically connected and mounted on the substrate, one or more discrete components electrically connected and mounted on the substrate, a substrate mounted multipart lid covering both the semiconductor component and the one or more discrete components, where the multipart lid comprises a heat dissipating upper lid and a lower lid, where a coefficient of thermal expansion (CTE) of the lower lid substantially matches a CTE of the first semiconductor component.
    Type: Grant
    Filed: May 7, 2019
    Date of Patent: September 15, 2020
    Assignee: ELPIS TECHNOLOGIES INC.
    Inventors: Charles L. Arvin, Steven P. Ostrander, Krishna R. Tunga
  • Patent number: 10756026
    Abstract: A semiconductor device functioning properly by maintaining an electromagnetic shielding structure by a conductor layer is provided. A semiconductor device includes a wiring board having a surface, a semiconductor element, an insulating layer, and a conductor layer. The semiconductor element is arranged on the surface of the wiring board. The insulating layer is located on the surface of the wiring board and arranged to surround the semiconductor element. The conductor layer covers an outer peripheral surface of the insulating layer, and is connected to the wiring board. The outer peripheral surface of the insulating layer includes an upper surface located over the semiconductor element, and a side surface connecting the upper surface and the wiring board. The side surface includes a reverse tapered portion. The conductor layer is in contact with a surface of the reverse tapered portion.
    Type: Grant
    Filed: May 29, 2017
    Date of Patent: August 25, 2020
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Kiyoshi Ishida, Yukinobu Tarui
  • Patent number: 10727221
    Abstract: An ESD protection device for protecting an integrated circuit against an ESD event includes a first terminal coupled to an input/output pad of the IC, a second terminal coupled to a reference or ground voltage, a silicon-controlled rectifier device having an anode connected to the first terminal and a cathode connected to the reference or ground voltage, and a pnp transistor coupled in parallel with the SCR device. The pnp transistor has an emitter coupled to the first terminal, a collector coupled to the second terminal, and a base coupled to a gate of the SCR. The pnp transistor includes a contact region formed at a first side of a substrate, the first contact region being surrounded by an STI layer formed at the first side of the substrate. An insulation structure is formed at an intersection of the first contact region and the STI layer.
    Type: Grant
    Filed: February 27, 2019
    Date of Patent: July 28, 2020
    Assignee: NXP USA, Inc.
    Inventors: Rouying Zhan, Jean-Philippe Laine, Evgueniy Nikolov Stefanov, Alain Salles, Patrice Besse
  • Patent number: 10718825
    Abstract: A magnetic field sensor includes a magnetic sense element and a shield structure formed on a substrate. The shield structure fully encircles the magnetic sense element for suppressing stray magnetic fields along a first axis and a second axis, both of which are parallel to a surface of the substrate and perpendicular to one another. A magnetic field is oriented along a third axis perpendicular to the surface of the substrate, and the magnetic sense element is configured to sense a magnetic field along the first axis. A magnetic field deflection element, formed on the substrate proximate the magnetic sense element, redirects the magnetic field from the third axis into the first axis to be sensed as a measurement magnetic field by the magnetic sense element. At least two magnetic field sensors, each fully encircled by a shield structure, form a gradient unit for determining a magnetic field gradient.
    Type: Grant
    Filed: September 13, 2017
    Date of Patent: July 21, 2020
    Assignee: NXP B.V.
    Inventors: Stephan Marauska, Jörg Kock, Hartmut Matz, Mark Isler, Dennis Helmboldt
  • Patent number: 10665566
    Abstract: An electronic component includes: a substrate; a device chip including a functional element located on a lower surface thereof and mounted on an upper surface of the substrate so that the functional element faces the upper surface of the substrate across an air gap; a ring-shaped metal layer located on the upper surface of the substrate and surrounding the device chip in plan view, a side surface of the ring-shaped metal layer being located further in than a side surface of the substrate; a metal sealing portion surrounding the device chip in plan view and bonding with an upper surface of the ring-shaped metal layer, a side surface of the metal sealing portion being located further out than the side surface of the ring-shaped metal layer; and a metal film located on the side surface of the metal sealing portion and the side surface of the ring-shaped metal layer.
    Type: Grant
    Filed: November 3, 2017
    Date of Patent: May 26, 2020
    Assignee: TAIYO YUDEN CO., LTD.
    Inventor: Takuma Kuroyanagi
  • Patent number: 10659003
    Abstract: An electronic component includes: a first substrate; a second substrate that includes a functional element formed on a lower surface of the second substrate, the second substrate being mounted on the first substrate so that the functional element faces an upper surface of the first substrate across an air gap; and an insulating film that is located on the upper surface of the first substrate, overlaps with at least a part of the functional element in plan view, faces the functional element across the air gap, and has a film thickness that is more than half of a distance between a lower surface of the functional element and the upper surface of the first substrate.
    Type: Grant
    Filed: November 3, 2017
    Date of Patent: May 19, 2020
    Assignee: TAIYO YUDEN CO., LTD.
    Inventors: Hidetaro Nakazawa, Takashi Matsuda
  • Patent number: 10658303
    Abstract: A packaged semiconductor device includes: a substrate; an semiconductor die attached to a top surface of the substrate; a mold body surrounding the semiconductor die; a tiered through mold via (TMV) comprising: a first recess having a recessed surface within the mold body at a first depth, and a second recess from the recessed surface to a second depth that exposes a ground contact area on a bonding area on the top surface of the substrate, wherein the first depth is greater than the second depth; and a metal shielding layer formed on a top surface of the mold body to form a shielded mold body, wherein the metal shielding layer makes direct contact with at least one sidewall of the first recess, with at least a portion of the recessed surface, with at least one sidewall of the second recess, and with the ground contact area.
    Type: Grant
    Filed: November 8, 2018
    Date of Patent: May 19, 2020
    Assignee: NXP USA, Inc.
    Inventors: Michael B. Vincent, Stephen Ryan Hooper, Dwight Lee Daniels
  • Patent number: 10629542
    Abstract: An electronic device module includes a substrate, at least one first component and at least one second component disposed on one surface of the substrate, a shielding wall disposed between the at least one first component and the at least one second component, and disposed on the substrate, and a sealing portion having the at least one first component, the at least one second component and the shielding wall embedded therein, and disposed on the substrate. The shielding wall includes at least one insulating layer and at least one conductive layer disposed on the insulating layer.
    Type: Grant
    Filed: November 6, 2018
    Date of Patent: April 21, 2020
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Suk Youn Hong, Jang Hyun Kim, Hye Kyung Kim, Seung Hyun Hong, Jong In Ryu
  • Patent number: 10600743
    Abstract: A method to fabricate an electronic package is described and includes the steps of: connecting a plurality of semiconductor chips to at least one surface of a substrate using a connect pad; encapsulating the semiconductor chips with a non-conductive material; and forming an electro-magnetic interference shield layer over the encapsulated semiconductor chip.
    Type: Grant
    Filed: September 12, 2018
    Date of Patent: March 24, 2020
    Assignee: Inari Semiconductor Labs Sdn Bhd
    Inventors: Ching-Fong Lee, Heap-Hooi Nyeo, Chin-Chooi Ch'ng, Ooi-Lin Cheng
  • Patent number: 10600723
    Abstract: The present disclosure relates to a thermally enhanced semiconductor package, which includes a module substrate, a thinned flip chip die over the module substrate, a mold compound component, a thermally conductive film, and a thermally enhanced mold compound component. The mold compound component resides over the module substrate, surrounds the thinned flip chip die, and extends above an upper surface of the thinned flip chip die to form a cavity over the upper surface of the thinned flip chip die. The thermally conductive film resides over at least the upper surface of the thinned flip chip at the bottom of the cavity. The thermally enhanced mold compound component resides over at least a portion of the thermally conductive film to fill the cavity.
    Type: Grant
    Filed: July 18, 2018
    Date of Patent: March 24, 2020
    Assignee: Qorvo US, Inc.
    Inventors: Julio C. Costa, Robert Aigner
  • Patent number: 10593630
    Abstract: A semiconductor package includes a semiconductor die, a plurality of conductive bumps, a shielding layer, an encapsulant and a redistribution layer. The semiconductor die has an active surface, a backside surface and a lateral surface. The conductive bumps are disposed on the active surface of the semiconductor die. The shielding layer is disposed on the lateral surface of the semiconductor die. The encapsulant covers the shielding layer, and has a first surface and a second surface opposite to the first surface. The redistribution layer is disposed on the first surface of the encapsulant and electrically connected to the semiconductor die through the conductive bumps. The shielding layer is electrically connected to the redistribution layer.
    Type: Grant
    Filed: May 11, 2018
    Date of Patent: March 17, 2020
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Hsu-Nan Fang, Chun-Jun Zhuang, Yung I. Yeh
  • Patent number: 10573590
    Abstract: Device and method of forming the device are disclosed. A device includes a buildup package substrate with top and bottom surfaces and a plurality of interlevel dielectric (ILD) layers with interconnect structures printed layer by layer and includes a die region and a non-die region on the top surface. A semiconductor die is disposed in the die and non-die regions of the package substrate and is electrically connected to the plurality of interconnect structures via a plurality of wire bonds. A plurality of conductive elements are disposed on the bottom surface of the package substrate and a dielectric layer encapsulates the semiconductor die, the wire bonds and the top surface of the buildup package substrate.
    Type: Grant
    Filed: October 19, 2017
    Date of Patent: February 25, 2020
    Assignee: UTAC Headquarters Pte. Ltd.
    Inventors: Antonio Bambalan Dimaano, Jr., Roel Adeva Robles
  • Patent number: 10553521
    Abstract: The present disclosure relates to a thermally enhanced semiconductor package, which includes a module substrate, a thinned flip chip die over the module substrate, a mold compound component, a thermally conductive film, and a thermally enhanced mold compound component. The mold compound component resides over the module substrate, surrounds the thinned flip chip die, and extends above an upper surface of the thinned flip chip die to form a cavity over the upper surface of the thinned flip chip die. The thermally conductive film resides over at least the upper surface of the thinned flip chip at the bottom of the cavity. The thermally enhanced mold compound component resides over at least a portion of the thermally conductive film to fill the cavity.
    Type: Grant
    Filed: July 18, 2018
    Date of Patent: February 4, 2020
    Assignee: Qorvo US, Inc.
    Inventors: Julio C. Costa, Robert Aigner
  • Patent number: 10531558
    Abstract: An electronic module having an electromagnetic shielding structure and its manufacturing method are provided. At first, a first substrate and a second substrate are separately provided. At least one electronic element and at least one connection pad are formed on a surface of the first substrate. The second substrate includes a conductive film and at least one conductive bump is formed on a surface of the conductive film. The first substrate and the second substrate are laminated together wherein the conductive bump is aligned with and connected to the connection pad to obtain the electronic module.
    Type: Grant
    Filed: December 15, 2015
    Date of Patent: January 7, 2020
    Assignee: CYNTEC CO., LTD.
    Inventor: Ming-Che Wu
  • Patent number: 10529670
    Abstract: A semiconductor structure includes a packaged semiconductor device having at least one device, a conductive pillar, an encapsulant over the at least one device and surrounding the conductive pillar, wherein the conductive pillar extends from a first major surface to a second major surface of the encapsulant, and is exposed at the second major surface and the at least one device is exposed at the first major surface. The packaged device also includes a conductive shield layer on the second major surface of the encapsulant and on minor surfaces of the encapsulant and an isolation region at the second major surface of the encapsulant between the encapsulant and the conductive pillar such that the conductive shield layer is electrically isolated from the conductive pillar. The semiconductor structure also includes a radio-frequency connection structure over and in electrical contact with the conductive pillar at the second major surface of the encapsulant.
    Type: Grant
    Filed: January 28, 2019
    Date of Patent: January 7, 2020
    Assignee: NXP USA, Inc.
    Inventors: Michael B. Vincent, Gregory J. Durnan
  • Patent number: 10515887
    Abstract: A semiconductor package structure is provided. The semiconductor package structure includes a first carrier substrate having a first surface and an opposing second surface. A second carrier substrate is stacked on the first carrier substrate and has a first surface and an opposing second surface that faces the first surface of the first carrier substrate. A semiconductor die is mounted on the first surface of the second carrier substrate. A heat spreader is disposed on the first surface of the first carrier substrate to cover and surround the second carrier substrate and the semiconductor die. A method for forming the semiconductor package structure is also provided.
    Type: Grant
    Filed: September 11, 2017
    Date of Patent: December 24, 2019
    Assignee: MediaTek Inc.
    Inventors: Shih-Yi Syu, Chia-Yu Jin, Che-Ya Chou, Wen-Sung Hsu, Nan-Cheng Chen
  • Patent number: 10510679
    Abstract: A semiconductor device includes a first die embedded in a molding material, where contact pads of the first die are proximate a first side of the molding material. The semiconductor device further includes a redistribution structure over the first side of the molding material, a first metal coating along sidewalls of the first die and between the first die and the molding material, and a second metal coating along sidewalls of the molding material and on a second side of the molding material opposing the first side.
    Type: Grant
    Filed: November 1, 2017
    Date of Patent: December 17, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chuei-Tang Wang, Chen-Hua Yu, Wei-Ting Chen, Chieh-Yen Chen
  • Patent number: 10510682
    Abstract: A semiconductor device includes a first die embedded in a molding material, where contact pads of the first die are proximate a first side of the molding material. The semiconductor device further includes a redistribution structure over the first side of the molding material, a first metal coating along sidewalls of the first die and between the first die and the molding material, and a second metal coating along sidewalls of the molding material and on a second side of the molding material opposing the first side.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: December 17, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chuei-Tang Wang, Chen-Hua Yu, Wei-Ting Chen, Chieh-Yen Chen
  • Patent number: 10510632
    Abstract: A semiconductor device has a carrier and a semiconductor die disposed over the carrier. A dummy die is disposed over the carrier as well. A first encapsulant is deposited over the semiconductor die and dummy die. The dummy die and a first portion of the first encapsulant is backgrinded while a second portion of the first encapsulant remains covering the semiconductor die. Backgrinding the dummy die fully removes the dummy die while the second portion of the first encapsulant remains covering the semiconductor die. A second encapsulant is optionally deposited over the dummy die prior to disposing the dummy die over the carrier. A conductive pillar is optionally formed over the dummy die prior to depositing the second encapsulant. The carrier is removed to expose an active surface of the semiconductor die. A build-up interconnect structure is formed over the active surface after removing the carrier.
    Type: Grant
    Filed: March 13, 2018
    Date of Patent: December 17, 2019
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: Won Kyoung Choi, Pandi Chelvam Marimuthu
  • Patent number: 10504818
    Abstract: The present disclosure relates to a thermally enhanced semiconductor package, which includes a module substrate, a thinned flip chip die over the module substrate, a mold compound component, a thermally conductive film, and a thermally enhanced mold compound component. The mold compound component resides over the module substrate, surrounds the thinned flip chip die, and extends above an upper surface of the thinned flip chip die to form a cavity over the upper surface of the thinned flip chip die. The thermally conductive film resides over at least the upper surface of the thinned flip chip at the bottom of the cavity. The thermally enhanced mold compound component resides over at least a portion of the thermally conductive film to fill the cavity.
    Type: Grant
    Filed: July 18, 2018
    Date of Patent: December 10, 2019
    Assignee: Qorvo US, Inc.
    Inventors: Julio C. Costa, Robert Aigner
  • Patent number: 10453762
    Abstract: Several aspects of the present technology are directed toward fan-out packaged semiconductor devices having an integrated shield to protect against electromagnetic interference and methods of manufacturing such devices. The shield can be constructed by forming a conductive wall on a redistribution structure and disposing a conductive cap on an upper surface of an encapsulant. The conductive wall and the conductive cap are electrically connected to each other. By forming the conductive wall directly on the redistribution structure and separately disposing the conductive cap onto an upper surface of the encapsulant, an electromagnetic shield can be readily formed using wafer-level or panel-level processing techniques that are efficient and cost-effective. Several embodiments of semiconductor devices in accordance with the present technology accordingly shield the integrated circuitry of semiconductor dies from electromagnetic interference.
    Type: Grant
    Filed: July 28, 2017
    Date of Patent: October 22, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Fumitomo Watanabe, Keiyo Kusanagi
  • Patent number: 10446470
    Abstract: The present disclosure relates to a thermally enhanced semiconductor package, which includes a module substrate, a thinned flip chip die over the module substrate, a mold compound component, a thermally conductive film, and a thermally enhanced mold compound component. The mold compound component resides over the module substrate, surrounds the thinned flip chip die, and extends above an upper surface of the thinned flip chip die to form a cavity over the upper surface of the thinned flip chip die. The thermally conductive film resides over at least the upper surface of the thinned flip chip at the bottom of the cavity. The thermally enhanced mold compound component resides over at least a portion of the thermally conductive film to fill the cavity.
    Type: Grant
    Filed: July 18, 2018
    Date of Patent: October 15, 2019
    Assignee: Qorvo US, Inc.
    Inventors: Julio C. Costa, Robert Aigner
  • Patent number: 10446503
    Abstract: Shielded radio-frequency (RF) module having reduced area. In some embodiments, a method for fabricating a radio-frequency module includes forming or providing a packaging substrate configured to receive a plurality of components. The method may include mounting one or more devices on the packaging substrate such that the packaging substrate includes a first area associated with mounting of each of the one or more devices. In some embodiments, the method further includes forming a plurality of shielding wirebonds on the packaging substrate to provide RF shielding functionality for one or more regions on the packaging substrate, such that the packaging substrate includes a second area associated with formation of each shielding wirebond, the mounting of each device implemented with respect to a corresponding shielding wirebond such that a portion of the first area associated with the device overlaps at least partially with a portion of the second area associated with the corresponding shielding wirebond.
    Type: Grant
    Filed: September 12, 2017
    Date of Patent: October 15, 2019
    Assignee: Skyworks Solutions, Inc.
    Inventors: Howard E. Chen, Matthew Sean Read
  • Patent number: 10410975
    Abstract: A processed semiconductor wafer has layered elements that define electrical circuits and a double-seal ring surrounding each individual electrical circuit. The layered elements further define another double-seal ring that surrounds at least two electrical circuits. The processed semiconductor wafer can have additional layered elements that extend each of the double-seal rings that surround individual circuits or, that can extend the other double-seal ring. A method of fabricating such a processed semiconductor wafer. A device comprising two such electrical circuits.
    Type: Grant
    Filed: September 4, 2015
    Date of Patent: September 10, 2019
    Assignee: MICROSEMI SOLUTIONS (U.S.), INC.
    Inventors: Bruce Scatchard, Peter Onufryk, Chunfang Xie