Semiconductor package with EMI shield and fabricating method thereof

A semiconductor device with EMI shield and a fabricating method thereof are provided. In one embodiment, the semiconductor device includes EMI shield on all six surfaces of the semiconductor device without the use of a discrete EMI lid.

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Description
BACKGROUND

Certain embodiments of the disclosure relate to a semiconductor package with electromagnetic interference (EMI) shield and a fabricating method thereof.

A semiconductor package may emit EMI that may interfere with operation of other semiconductor packages. Accordingly, various semiconductor packages may comprise EMI shield to help reduce EMI from being emitted and to block EMI from other sources.

Further limitations and disadvantages of conventional and traditional approaches will become apparent to one of skill in the art, through comparison of such systems with some aspects of the present disclosure as set forth in the remainder of the present application with reference to the drawings.

BRIEF SUMMARY

The present disclosure provides a semiconductor package with EMI shield and a fabricating method thereof.

The above and other objects of the present disclosure will be described in or be apparent from the following description of the preferred embodiments.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is an illustration of devices that may interfere with each other.

FIG. 2 is a cross-sectional view illustrating a semiconductor package according to an exemplary embodiment of the present disclosure.

FIGS. 3-9 are cross-sectional views illustrating various stages in shielding a semiconductor device according to an exemplary embodiment of the present disclosure.

FIG. 10 is an example of a flow diagram for shielding a semiconductor device according to an exemplary embodiment of the present disclosure.

FIG. 11 is a cross-sectional view illustrating a semiconductor package according to an exemplary embodiment of the present disclosure.

 DETAILED DESCRIPTION

Various example embodiments of the disclosure will be described in detail with reference to the accompanying drawings such that they can be made and used by those skilled in the art.

Various aspects of the present disclosure may be embodied in many different forms and should not be construed as being limited to the example embodiments set forth herein. Rather, these example embodiments of the disclosure are provided so that this disclosure will be thorough and complete and will convey various aspects of the disclosure to those skilled in the art.

The terminology used here is for the purpose of describing particular embodiments only and is not intended to limit the disclosure. In the drawings, the thickness of layers and regions may be exaggerated for clarity. Like reference numerals refer to like elements throughout.

As utilized herein, “and/or” means any one or more of the items in the list joined by “and/or.” As an example, “x and/or y” means any element of the three-element set {(x), (y), (x, y)}. In other words, “x and/or y” means “one or both of x and y”. As another example, “x, y, and/or z” means any element of the seven-element set {(x), (y), (z), (x, y), (x, z), (y, z), (x, y, z)}. In other words, “x, y and/or z” means “one or more of x, y and z.” As utilized herein, the term “exemplary” means serving as a non-limiting example, instance, or illustration. As utilized herein, the terms “e.g.” and “for example” set off lists of one or more non-limiting examples, instances, or illustrations.

Also, the singular forms are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises,” “comprising,” “includes,” and/or “including,” when used in this specification, specify the presence of stated features, numbers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, numbers, steps, operations, elements, components, and/or groups thereof.

In addition, it will be understood that when an element A is referred to as being “connected to” (or “coupled to”) an element B, the element A can be directly connected to (or coupled to) the element B, or an intervening element C may be present between the elements A and B so that the element A can be indirectly connected to the element B.

Furthermore, although the terms first, second, etc. may be used to describe various members, elements, regions, layers and/or sections, these members, elements, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one member, element, region, layer, and/or section from another. Thus, for example, a first member, a first element, a first region, a first layer, and/or a first section discussed below could be termed a second member, a second element, a second region, a second layer, and/or a second section without departing from the teachings of the present disclosure.

Spatially relative terms, such as “upper,” “lower,” “side,” and the like, may be used for ease of description to describe the relationship of one element or feature to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned upside-down, elements described as “below” or “beneath” other elements or features would then be oriented “above” the other elements or features. Thus, the exemplary term “below” can encompass both an orientation of above and below.

For ease of reference, a semiconductor device that is shielded on all sides in accordance with an embodiment of the disclosure may be referred to as a semiconductor package. However, the use of this term “semiconductor package” does not limit in any way the various embodiments of the disclosure.

The drawings and descriptions may leave out some parts of a semiconductor device/package in order to make the description/explanation clearer. Accordingly, it should be understood that various embodiments of the disclosure may include specific parts (for example, through vias, one or more layers of electrical connections, one or more layers of dielectrics/passivation/insulation, underfills, etc.) that are not described here.

FIG. 1 is an illustration of various devices that may interfere with each other. Referring to FIG. 1, there is shown a smartphone 100 and a laptop 102. In normal operation, the smartphone 100 and the laptop 102 may communicate wirelessly with each other. However, each of these devices may also emit electronic signals (noise) that are not useful to the other device. In some cases, the noise may be strong enough to interfere with operation of another device. Some entities may also want to reduce electronic signals emitted by a device for security purposes. For example, electronic signals emitted by a laptop may be picked up by a nearby party to recreate display images shown on the laptop.

To reduce noise emitted by a device, and to reduce susceptibility to noise from another device, a device manufacturer may provide electromagnetic interference (EMI) shielding for the device. The EMI shield may be at a system level such as for the entire smartphone 100 or the laptop 102, at a chip or electronic component level for a semiconductor package or semiconductor dies, or at different levels in between.

Accordingly, an exemplary embodiment of the disclosure may be a semiconductor package comprising one or more semiconductor devices, an electromagnetic interference (EMI) shield on all external surfaces of the semiconductor package, and an opening in which an electrical interconnect is placed to form electrical contact with a pad.

Another exemplary embodiment of the disclosure may be a method for shielding a semiconductor device, where the method comprises attaching, to the semiconductor device comprising a top encapsulant and a bottom encapsulant, a first carrier to a bottom surface of the bottom encapsulant, for example when the semiconductor device does not have a first carrier already attached. The method may comprise forming an external electromagnetic interference (EMI) shield on all external surfaces of the semiconductor device that are not covered by the first carrier. A second carrier may be attached to a top surface of the top encapsulant and the first carrier may be removed from the bottom encapsulant of the semiconductor device. An external bottom EMI shield may then be formed on a bottom surface of the bottom encapsulant.

A further exemplary embodiment of the disclosure may be a semiconductor package comprising semiconductor devices, where the semiconductor package also comprises a top encapsulant and a bottom encapsulant, and the top encapsulant may encapsulate at least two of the semiconductor devices. An electromagnetic interference (EMI) shield may be on all external surfaces of the semiconductor package, and an internal EMI shield may be between two of the semiconductor devices. Furthermore, an electrical interconnect may be electrically connected to at least one of the semiconductor devices via a pad, where the pad is located in the bottom encapsulant.

FIG. 2 is a cross-sectional view illustrating a semiconductor package according to an exemplary embodiment of the present disclosure. Referring to FIG. 2, there is shown a semiconductor package 200 that is EMI shielded on all six of its sides. The semiconductor package 200 comprises semiconductor dies 212, 214 covered by encapsulant 210 and semiconductor dies 222, 224 covered by encapsulant 220. The semiconductor dies 212, 214, 222, and 224 may be electrically connected to various conductive traces 204 (vias, redistribution layers (RDLs), pads, wires, electrical interconnects, etc.). The conductive traces 204 may be embedded, for example, in a substrate 201 (e.g., a cored or coreless substrate, printed circuit board, built-up signal distribution structure comprising one or more dielectric layers and/or conductive layers, etc.). An electronic device 232 may be connected to the conductive traces 204, which may be, for example, partially or fully embedded in the substrate 201. The conductive traces 204 and the electronic device 232 may be considered to be part of, for example, the substrate 201. An electronic device 234 may also be coupled to a lower surface of the substrate 201. Each of the electronic devices 232 and 234 may be a passive device, an active device, or a combination of passive and active devices.

The electrical connectors 206 (e.g., interconnection structures, such as conductive balls or bumps, conductive posts or pillars, etc.) may be coupled to the pads 208 on a lower side of the substrate 201. The electronic device 234, the electrical connectors 206, and the pads 208 may be covered by an encapsulant 230.

While the term “encapsulant” is used, it should be understood that any similar structure that covers or encapsulates the various semiconductor dies 212, 214, 222, and 224, the electronic devices 232 and 234, the conductive traces 204, the pads 208, etc. may also be referred to as “encapsulant.” Accordingly, molding may be an example of an encapsulant. An encapsulant may comprise an encapsulant material/layer, insulating material/layer, passivation material/layer, dielectric material/layer, etc.

Some examples of encapsulant material may be pre-preg, a build-up film, a polymer, polyimide (PI), benzocyclobutene (BCB), polybenzoxazole (PBO), bismaleimide triazine (BT), a molding material, a phenolic resin, an epoxy, silicone, acrylate polymer, combinations thereof, equivalents thereof, etc.

The inner shield 202′ may act to block electromagnetic signals from the devices covered by the encapsulant 210 to the devices covered by the encapsulant 220, and vice versa. The outer shield 202 on the top, the bottom, and the four sides of the semiconductor package 200 may act to block electromagnetic signals from the semiconductor package 200 from propagating outside the semiconductor package 200, as well as blocking electromagnetic signals from other semiconductor devices (not shown) from entering the semiconductor package 200. Since the semiconductor package 200 is EMI shielded on all six of its sides except for small areas at the bottom where the electrical connectors 206 are located, there should be minimal EMI to other electronic devices due to the semiconductor package 200. Similarly, there may be minimal EMI to the semiconductor package 200 due to other electronic devices external to the semiconductor package 200.

While semiconductor dies were specifically mentioned, various embodiments of the disclosure may also comprise blocking EMI to/from passive devices in the semiconductor package 200 such as, for example, resistors, capacitors, and inductors, as well as from signal traces. Additionally, a semiconductor die may be replaced with a semiconductor device that may comprise semiconductor die(s), discrete active device(s), and/or passive device(s).

FIGS. 3-9 are cross-sectional views illustrating various stages in shielding a semiconductor device according to an embodiment of the present disclosure.

FIG. 10 is an example flow diagram for shielding a semiconductor device according to an exemplary embodiment of the present disclosure. FIGS. 3-9 will be explained in more detail with respect to the exemplary flow diagram of FIG. 10.

At 1002, a semiconductor device 300 of FIG. 3 comprising a double-side molded device may be prepared for EMI shielding. Part of the preparation may be, for example, attaching the semiconductor device 300 to a carrier 310 if a carrier is not present. The carrier 310 may comprise a layer of material that is attached to the semiconductor device 300 to allow various operations and manipulations to be performed on the semiconductor device 300. The carrier 310 may comprise, for example, a metal plate, glass plate, semiconductor wafer or panel, etc. The carrier 310 may be attached to the semiconductor device 300 in any of a variety of manners, for example utilizing an adhesive (e.g., a thermally releasable adhesive, a chemically releasable adhesive, an ultraviolet light releasable adhesive, etc.), utilizing vacuum pressure, utilizing mechanical clamping, etc.).

The semiconductor device 300 may comprise, for example, semiconductor dies 312, 314, 322, and 324, and electronic devices 332 and 334 that may be passive devices or active devices, or a combination of passive and active devices. The semiconductor device 300 may also comprise conductive traces 302 (vias, RDLs, pads, wires, electrical interconnects, etc.). The conductive traces 302 may be embedded, for example, in a substrate 308. The semiconductor dies 312, 314, 322, and 324 may be covered by an encapsulant 306 (e.g., an upper encapsulant), and the conductive traces 302 and the electronic device 332 may be embedded in the substrate 308. The electronic device 334 may be covered by an encapsulant 304 (e.g., a lower encapsulant). Note that the encapsulant 306 and the encapsulant 304 may be, but need not be, formed of a same material.

While the term “encapsulant” is used, it should be understood that any similar structure that covers or encapsulates the various semiconductor dies 312, 314, 322, and 324, and the electronic device 334, etc. may also be referred to as “encapsulant.” Accordingly, an encapsulant may be any suitable encapsulant material/layer, insulating material/layer, passivation material/layer, dielectric material/layer, etc.

Some examples of encapsulant material may be pre-preg, a build-up film, a polymer, polyimide (PI), benzocyclobutene (BCB), polybenzoxazole (PBO), bismaleimide triazine (BT), a molding material, a phenolic resin, an epoxy, silicone, acrylate polymer, combinations thereof, equivalents thereof, and the like.

At block 1004, an internal shield is formed. This can be seen in the semiconductor device 300 of FIG. 4A where a space 401 is formed in the encapsulant 306, and the semiconductor device 300 of FIG. 4B where an internal shield 402 is formed in the space 401. The space 401 shown in FIG. 4A may be formed by removing a portion of the encapsulant 306 to form the separated encapsulants 410 and 420, where encapsulant 410 covers the semiconductor dies 312, 314 and encapsulant 420 covers the semiconductor dies 322, 324. The removal of a portion of the encapsulant 306 to form the space 401 may use any appropriate method, such as, for example, using a mechanical process such as sawing, using a chemical process, using a laser, using a jet of fluid or gas, etc. The space 401 may, for example extend completely between opposite sides of the device 300, but need not. The space 401 may, for example, be characterized as a gap, a trench, a hole, etc.

As shown in FIG. 4B, the space 401 may be filled with appropriate material for EMI shielding to form the internal shield 402. The internal shield 402 may be appropriate material that may block at least some EMI signals. For example, the internal shield 402 may comprise one or more suitable shielding materials such as copper, silver, gold, aluminum, tin, brass, bronze, steel, superpermalloy, mumetal, graphite, composite material, etc.

The material for the internal shield 402 may be deposited using a suitable deposition process depending on the dimensions of the internal shield 402 and/or the characteristics of the material, such as, for example, sputtering, electroplating, electroless plating, vacuum deposition, dipping, printing, injecting, flooding, etc.

At 1006, external EMI shielding is provided at five sides of the semiconductor device. For example, the semiconductor device 300 of FIG. 5 is shown with the addition of external shield 502 on the five sides that are exposed (i.e., not covered by the carrier 310). The external shield 502 may be formed of one or more suitable EMI shielding materials such as, for example, copper, silver, gold, aluminum, tin, brass, bronze, steel, superpermalloy, mumetal, graphite, composite material, etc. The material for the external shield 502 may be deposited using a suitable deposition process such as, for example, sputtering, electroplating, electroless plating, vacuum deposition, dipping, printing, injection, flooding, etc. Note that the external shield 502 may be, but need not be, formed of a same material as the internal shield 402. Also note that block 1006 and the forming of the shielding at block 1004 may be performed simultaneously utilizing a same forming (or deposition) process.

At 1008, a carrier 610 is added on top of the semiconductor device 300, as shown in FIG. 6A, and the carrier 310 is removed from the bottom of the semiconductor device 300, as shown in FIG. 6B. Referring to FIG. 6A, the carrier 610, which may be, for example, similar to the carrier 310, may be attached to the top of the semiconductor device 300. The carrier 610 may be, for example, attached to the top of the semiconductor device 300 in a manner similar to the manner in which the carrier 310 was attached to the bottom of the semiconductor device 300, or may be attached utilizing another suitable method.

Referring to FIG. 6B, after attaching the carrier 610, the carrier 310 may be removed using any of the various methods that may be suitable. For example, the carrier 310 may be pulled or peeled off; the adhesive (if used) may be dissolved or thermally released or UV released; the carrier 310 may be etched off or removed using laser, abrasion or grinding, jets of fluid or gas, etc. Accordingly, the bottom surface of the semiconductor device 300 may now be exposed.

At 1010, as shown in FIG. 7, the bottom surface may be deposited with EMI shielding material as, for example, the top surface and/or the vertical side surfaces were deposited with EMI shielding material. The semiconductor device 300 has now been processed to the semiconductor package 700 where all sides are EMI shielded. The EMI shielding material for the external bottom shield 702 for the bottom surface may be similar to the EMI shielding material for the external shield 502, although it need not necessarily be the same material. The process of forming the external bottom shield 702 may also be similar to the process of forming the external shield 502 for the top surface of the semiconductor package 700, although it need not be the same method. Note that the orientation of the device 700 as illustrated in FIG. 7 is kept consistent with other figures for illustrative clarity. During the forming of the external bottom shield 702 or during any processing step discussed herein, the orientation of the device 700 or any example device shown herein may be changed.

At 1012, the semiconductor package 700 of FIG. 8A may have portions of the EMI shielding material 702 and the encapsulant 304 removed to form openings 802 that provide access to pads 320. The EMI shielding material 702 may be removed by any of various suitable methods such as mechanical ablation, chemical etching, laser ablation, utilizing a jet of fluid or gas, etc. Once the encapsulant 304 is exposed, the process for exposing the pads 320 may be any method suitable. For example, portions of the encapsulant 304 may be removed using a suitable process such as, for example, laser ablation, although other processes such as chemical ablation, mechanical ablation, using a jet of fluid or gas for ablation of portions of the encapsulant 304, etc. may be used if suitable.

The ablation process may be a single step or multi-step process. For example, a two step ablation process is shown in FIGS. 8B to 8D. In the first step shown in FIGS. 8B and 8C, for example, a laser (or other material removal technique) may be used to remove the EMI shielding material 702 to start the opening 802, and the laser may be further used to remove a first desired portion of the encapsulant material 304 to form a first depression (or first portion of the opening 802). Then, in a second step shown in FIG. 8D, the laser (or other material removal technique) may be used to form a second depression (or second portion of the opening 802) to expose the pads 320. The second depression may be, for example, narrower than the first depression, but this need not be the case. Each of the respective depressions (or opening portions) may have respective vertical or sloped sides. As shown in FIG. 8D, in an example implementation in which the second depression is narrower than the first depression, there may be a shelf at the boundary of the first and second depressions. Such a shelf may, for example, provide a buffer space between an electrical connector (to be attached to the pad 320 later) and the external bottom shield 702.

Another process may be a three step process, for example, comprising first removing the EMI shielding material 702, then performing the first stage removal of the encapsulant material 304, then performing the second stage removal of the encapsulant material 304. Another process may allow, for example, multiple sweeps of the laser (or jets of gas or fluid) where the width of the depression is controlled for each sweep of the laser. Accordingly, various processes may be used to form different shapes of the opening 802 to expose the pads 320.

In yet another example implementation, a one step process may be utilized to form the opening 802. For example, a single laser ablation (or other material removal) step may be performed to form the opening 802. In such an implementation, the opening 802 may have continuous side walls (e.g., vertical side walls, sloped side walls, etc.).

At 1014, the semiconductor package 700 of FIG. 9 may have electrical interconnects 902 attached to the pads 320. The electrical interconnects 902 may be any suitable interconnect such as, for example, a conductive balls or conductive pillars. The conductive balls or pillars may be made of any suitable material. For example, the electrical interconnect 902 may be solder ball that may be heated (for example, using a solder reflow process) to melt at least some of the solder ball to form a connection to the pad 320 when the melted solder cools. Also for example, the electrical interconnect 902 may comprise a copper pillar or post that is plated on the pad 320 through the opening 802. Any appropriate method may be used for attaching the electrical interconnects 902 to the pads 320. The method of attaching the electrical interconnects 902 may depend on the type of interconnect.

When the EMI shielding of the semiconductor package 700 is finished, the carrier 610 may be removed with an appropriate method, which may be similar to the method described with respect to the carrier 310. The semiconductor package 700 may then be ready for assembly as part of, for example, a printed circuit board.

Various other processes can be followed for shielding all six sides of a semiconductor device. For example, some embodiments may form the internal shield 402 and the external shield 502 at the same time. Other embodiments may form the external shield 502 on only a portion of the vertical side surfaces of the semiconductor device 300 along with the external shield 502 on a top surface of the semiconductor device 300. Then, in a later step, the remainder of the external shield 502 may be formed on the vertical side surfaces of the semiconductor device 300 along with forming the external bottom shield 702 on the bottom surface of the semiconductor device 300.

In such a process, there may be another step to smooth out any overlap there may be of the external shield 502 on the vertical side surfaces of the semiconductor package 700. The overlap may be, for example, from overlapping that may occur on a given area of the vertical side surfaces from when the external shield 502 is formed on the top surface of the semiconductor device 300, and from when the external bottom shield 702 is formed on the bottom surface of the semiconductor device 300. The smoothing step may also be used with other embodiments as needed.

Additionally, various embodiments may also backfill the opening with a filler material, molding material, insulating material, or any other appropriate material. Furthermore, the internal shield 402, the external shield 502, and/or the external bottom shield 702 may be optionally connected to, for example, a ground path/plane of the semiconductor package 700 or to an electrical interconnect(s) that can be connected to a ground path/plane of a device/PCB to which the semiconductor 700 is mounted.

For example, referring to FIG. 9, the grounding of the internal shield 402, the external shield 502, and/or the external bottom shield 702 may be made, for example, by electrically connecting the internal shield 402 to a ground portion of the conductive trace 302, or by electrically connecting the external shield 502 to the ground portion of the conductive traces 302 at the sides of the semiconductor package 700.

FIG. 11 is a cross-sectional view illustrating a semiconductor package according to an embodiment of the present disclosure. Referring to FIG. 11, there is shown an embodiment where the internal shield 402, the external shield 502, and/or the external bottom shield 702 are electrically connected to a conductive interconnect 1102. In such cases, an electrical connection 1104 may be formed, for example, from the external bottom shield 702 to a conductive interconnect 1102. When such an electrical connection 1104 is made, the opening 802 into which the conductive interconnect 1102 was placed may be back filled to provide support for the electrical connection 1104 that will connect the external bottom shield 702 to the conductive interconnect 1102. The backfill 1106 may use any suitable material such as, for example, filler material, molding material, insulating material, and/or other appropriate material. The particular material used for backfilling may depend on, for example, the material that makes up the encapsulant 304. The pad 1108 may either be electrically isolated from other parts of the semiconductor package 700 or connected to ground trace/plane of the semiconductor package 700.

In another implementation, a first of the openings 802 (e.g., corresponding to a ground interconnect) may be formed to be narrower than others of the openings 802 (e.g., corresponding to general electronic signals). In such an implementation, when the interconnect is formed (e.g., solder reflowed), the interconnect may make electrical contact with the external bottom shield to provide a ground signal contact.

While a typical semiconductor device may have six sides, the disclosure also applies to a semiconductor device having a different number of sides. Additionally, the semiconductor device may have different number of semiconductor dies, different number of internal shields, different number of layers of semiconductor dies, etc. Additionally, while the various semiconductor devices/packages 200, 300, 700 are described as comprising semiconductor dies, it should be understood that a semiconductor device/package may comprise other semiconductor device(s)/package(s), semiconductor dies, passive devices, etc.

Additionally, while the electrical interconnects 902 are described as being electrically connected to the pads 320 that are covered by the encapsulant 304, various embodiments of the disclosure need not be so limited. For example, a pad 320 may be embedded in the encapsulant 304 with at least a bottom surface of the pad 320 exposed. However, it may be noted that if more than the bottom surface of the pad 320 is exposed from the encapsulant 304, then the exposed areas of the pad 320 may need to be insulated to protect from short circuiting to the external bottom shield 702 if an electrical connection between the external bottom shield 702 and the pad 320 is not desired. The insulation may be provided either during forming of the encapsulant 304 or by an additional step prior to forming the external bottom shield 702.

While the semiconductor package with EMI shield and the fabricating method thereof according to various aspects of the present disclosure have been described with reference to certain supporting embodiments, it will be understood by those skilled in the art that the present disclosure not be limited to the particular embodiments disclosed, but that the present disclosure will include all embodiments falling within the scope of the appended claims.

Claims

1. A semiconductor device, comprising:

a substrate comprising a substrate upper side, a substrate lower side, and substrate sidewalls between the substrate upper side and the substrate lower side;
one or more semiconductor dies coupled to the substrate upper side;
a first encapsulant comprising a first encapsulant upper side, a first encapsulant lower side, and first encapsulant sidewalls between the first encapsulant upper side and the first encapsulant lower side, wherein the first encapsulant encapsulates the one or more semiconductor dies and portions of the substrate upper side;
a second encapsulant comprising a second encapsulant upper side, a second encapsulant lower side, and second encapsulant sidewalls between the second encapsulant upper side and the second encapsulant lower side, wherein the second encapsulant encapsulates portions of the substrate lower side;
an electronic device below the substrate lower side and encapsulated by the second encapsulant;
an electromagnetic interference (EMI) shield comprising one or more EMI shield portions that cover at least a portion of the first encapsulant upper side, a portion of the first encapsulant sidewalls, a portion of the second encapsulant lower side, a portion of the second encapsulant sidewalls, and a portion of the substrate sidewalls, wherein: the one or more EMI shield portions comprise an EMI shield lower portion; the EMI shield lower portion covers the portion of the second encapsulant lower side; and the EMI shield lower portion completely covers an orthogonal projection of the electronic device upon the EMI shield lower portion;
a first opening that passes through the second encapsulant and to a first pad on the substrate lower side; and
a first electrical interconnect that extends through the first opening and is coupled to the first pad on the substrate lower side without contacting the EMI shield.

2. The semiconductor device of claim 1, wherein the EMI shield entirely covers the first encapsulant upper side, the first encapsulant sidewalls, the second encapsulant sidewalls, and the substrate sidewalls.

3. The semiconductor device of claim 1, wherein the EMI shield provides an external upper side, an external lower side, and external sidewalls of the semiconductor device.

4. The semiconductor device of claim 1, further comprising an internal EMI shield between two of the one or more semiconductor dies.

5. The semiconductor device of claim 4, wherein the internal EMI shield is coupled to the EMI shield.

6. The semiconductor device of claim 4, wherein the internal EMI shield couples the EMI shield to a ground portion of the substrate.

7. The semiconductor device of claim 1, wherein the EMI shield is coupled to a ground portion of the substrate at one of the substrate sidewalls.

8. The semiconductor device of claim 1, further comprising:

a second opening that passes: through a second portion of the EMI shield covering the second encapsulant lower side; through the second encapsulant; and to a second pad on the substrate lower side; and
a second electrical interconnect that: extends through the second opening of the EMI shield and the second encapsulant; is coupled to the second pad on the substrate lower side; and is in contact with the EMI shield.

9. The semiconductor device of claim 1, wherein the first electrical interconnect is coupled to the first pad via the first opening without contacting the second encapsulant.

10. The semiconductor device of claim 1, wherein:

the first opening comprises a volume of space not occupied by the first electrical interconnect; and
the volume of space is substantially filled with a backfill material that forms a substantially co-planar bottom surface with the second encapsulant lower side.

11. The semiconductor device of claim 10, wherein the EMI shield covers at least a portion of a lower surface of the backfill material.

12. The semiconductor device of claim 1, further comprising another electronic device embedded in the substrate.

13. The semiconductor device of claim 1, wherein the first opening comprises:

a first depression in the second encapsulant;
a second depression in the second encapsulant; and
a shelf at a boundary between the first depression and the second depression;
wherein the second depression is closer to the substrate lower side than the first depression; and
wherein a width of the second depression is narrower than a width of the first depression.

14. A semiconductor device, comprising:

a substrate comprising a substrate upper side, a substrate lower side, and substrate sidewalls between the substrate upper side and the substrate lower side;
a first semiconductor die coupled to the substrate upper side;
an encapsulant comprising an encapsulant upper side, an encapsulant lower side, and encapsulant sidewalls between the encapsulant upper side and the encapsulant lower side, wherein the encapsulant encapsulates the first semiconductor die and portions of the substrate upper side;
an electromagnetic interference (EMI) shield comprising: an EMI shield upper portion covering the encapsulant upper side, EMI shield sidewall portions covering the encapsulant sidewalls and the substrate sidewalls, an EMI shield lower portion covering the lower substrate side, interconnect openings that pass through the EMI shield lower portion; and
electrical interconnects that extend through the interconnect openings of the EMI shield lower portion to pads on the substrate lower side, wherein:
the EMI shield lower portion includes no openings other than the interconnect openings;
the electrical interconnects include an innermost left-side interconnect separated from an innermost right-side interconnect by a first distance; and
the EMI shield lower portion covers the lower substrate side along a majority of the first distance between the innermost left-side interconnect and the innermost right-side interconnect.

15. The semiconductor device of claim 14, further comprising:

a second semiconductor die coupled to the substrate upper side; and
an internal EMI shield between the first semiconductor die and the second semiconductor die; and
wherein the internal EMI shield couples the EMI shield to a ground portion of the substrate.

16. The semiconductor device of claim 14, further comprising:

a second semiconductor die coupled to the substrate upper side; and
an internal EMI shield between the first semiconductor die and the second semiconductor die; and
wherein the EMI shield couples the internal EMI shield to a ground portion of the substrate at one of the substrate sidewalls.

17. The semiconductor device of claim 14, further comprising:

a second semiconductor die coupled to the substrate upper side; and
an internal EMI shield between the first semiconductor die and the second semiconductor die;
wherein the internal EMI shield is coupled to the EMI shield;
wherein a first electrical interconnect of the electrical interconnects is coupled to the EMI shield and a first pad of the pads; and
wherein the first pad couples the first electrical interconnect to a ground portion of the substrate.

18. The semiconductor device of claim 14, further comprising an electronic device embedded in the substrate.

19. The semiconductor device of claim 14, wherein the EMI shield lower portion substantially the lower substrate side between the innermost left-side interconnect and the innermost right-side interconnect.

20. The semiconductor device of claim 14, wherein:

the electrical interconnects include first interconnects and one or more ground interconnects;
each ground interconnect extends through its respective interconnect opening and contacts the EMI shield at its respective interconnect opening; and
each first interconnect extends through its respective interconnect opening and is separated from the EMI shield lower portion by a respective gap that is less than a width of the respective first interconnect.

21. A method, comprising:

coupling one or more semiconductor dies to a substrate upper side of a substrate, the substrate comprising the substrate upper side, a substrate lower side, and substrate sidewalls between the substrate upper side and the substrate lower side;
coupling an electronic device to the substrate lower side;
encapsulating the one or more semiconductor dies and portions of the substrate upper side in encapsulating material to form a first encapsulant comprising a first encapsulant upper side, a first encapsulant lower side, and first encapsulant sidewalls between the first encapsulant upper side and the first encapsulant lower side;
encapsulating the electronic device and portions of the substrate lower side in encapsulating material to form a second encapsulant comprising a second encapsulant upper side, a second encapsulant lower side, and second encapsulant sidewalls between the second encapsulant upper side and the second encapsulant lower side;
covering at least a portion of the first encapsulant upper side, a portion of the first encapsulant sidewalls, a portion of the second encapsulant lower side, a portion of the second encapsulant sidewalls, and a portion of the substrate sidewalls in an electromagnetic interference (EMI) shielding material to form an EMI shield comprising an EMI shield lower portion that covers the portion of the second encapsulant lower side and completely covers an orthogonal projection of the electronic device upon the EMI shield lower portion;
forming a first opening that passes through the second encapsulant and to a first pad on the substrate lower side; and
connecting a first electrical interconnect to the first pad such that the first electrical interconnect extends through the first opening to the first pad on the substrate lower side without contacting the EMI shield.
Referenced Cited
U.S. Patent Documents
7851894 December 14, 2010 Scanlan
9343427 May 17, 2016 Kim et al.
9935083 April 3, 2018 Lee et al.
20090140419 June 4, 2009 Rhyner
20120008288 January 12, 2012 Tsukamoto et al.
20120228751 September 13, 2012 Song
20130223041 August 29, 2013 Arnold
20160351509 December 1, 2016 Dang
20170018531 January 19, 2017 Lin
20170118877 April 27, 2017 Kumbhat
20180096950 April 5, 2018 Chen
20180102345 April 12, 2018 Lin
Patent History
Patent number: 11075170
Type: Grant
Filed: Jan 30, 2020
Date of Patent: Jul 27, 2021
Patent Publication Number: 20200243459
Assignee: AMKOR TECHNOLOGY SINGAPORE HOLDING PTE. LTD. (Singapore)
Inventors: Doo Soub Shin (Seoul), Tae Yong Lee (Gyeonggi-do), Kyoung Yeon Lee (Seoul), Sung Gyu Kim (Seoul)
Primary Examiner: Matthew E. Gordon
Application Number: 16/777,519
Classifications
Current U.S. Class: With Means To Shield Device Contained In Housing Or Package From Charged Particles (e.g., Alpha Particles) Or Highly Ionizing Radiation (i.e., Hard X-rays Or Shorter Wavelength) (257/660)
International Classification: H01L 23/552 (20060101); H01L 23/31 (20060101); H01L 21/48 (20060101); H01L 23/00 (20060101); H01L 23/498 (20060101); H01L 21/56 (20060101); H01L 23/538 (20060101); H01L 25/065 (20060101);