Abstract: Disclosed is a substrate manufacturing method for realizing three-dimensional packaging, which includes: preparing a base plate, the base plate including a dielectric material layer, a first sidewall pad, a first through-hole pillar and a cavity, the cavity being filled with a first metal block; processing a first circuit layer and a second circuit layer, the first circuit layer including a first padding plate and a second metal block, and the second circuit layer including a second padding plate and a plurality of pin pads; processing and laminating interlayer through-hole pillars; processing a third circuit layer and a fourth circuit layer, the third circuit layer including a second sidewall pad and the fourth circuit layer including a routing circuit; and etching to expose the first sidewall pad, the second sidewall pad and the pin pads.

Abstract: An integrated circuit package is disclosed. The integrated circuit package includes a first integrated circuit die, a second integrated circuit die, an organic substrate, wherein both the first integrated circuit die and the second integrated circuit die are connected to the organic substrate, a multi-die interconnect bridge (EMIB) embedded within the organic substrate, and a termination resistor associated with a circuit in the first integrated circuit die, wherein the termination resistor is located within the multi-die interconnect bridge embedded within the organic substrate.

Abstract: Disclosed is a package for a semiconductor device including a semiconductor die. The package includes a base member, a side wall, first and second conductive films, and first and second conductive leads. The base member has a conductive main surface including a region that mounts the semiconductor die. The side wall surrounds the region and is made of a dielectric. The side wall includes first and second portions. The first and second conductive films are provided on the first and second portions, respectively and are electrically connected to the semiconductor die. The first and second conductive leads are conductively bonded to the first and second conductive films, respectively. At least one of the first and second portions includes a recess in its back surface facing the base member, and the recess defines a gap between the at least one of the first and second portions below the corresponding conductive film and the base member.

Abstract: Embodiments of the present disclosure are related to a display device, as a voltage line connection pattern electrically connecting a voltage line and a circuit element in a subpixel includes a first voltage line connection pattern, for example, disposed using an active layer and a second voltage line connection pattern, for example, disposed using a metal layer and not disposed in a part area on the first voltage line connection pattern, a damage of an electrode located at a periphery can be prevented or at least reduced when cutting by a laser for a repair. Furthermore, as the voltage line connection pattern which is easily cut and has a low resistance is disposed, a structure can be provided that is capable of responding to various types of repairs such as a disconnection defect of other signal lines.

Abstract: A semiconductor device includes a substrate comprising an antenna and a conductive feature; an integrated circuit (IC) die attached to the substrate and comprising a radio frequency (RF) circuit; and a flexible circuit integrated with the substrate, where the flexible circuit is electrically coupled to the IC die and the substrate, a first portion of the flexible circuit being disposed between opposing sidewalls of the substrate, a second portion of the flexible circuit extending beyond the opposing sidewalls of the substrate, the second portion of the flexible circuit comprising an electrical connector at a distal end.

Abstract: A chip testing board and a chip testing method are provided. The testing board includes a first conductive layer, a second conductive layer and a third conductive layer, wherein the first conductive layer is located on a substrate for electrical connection with a first power connection point of a chip, and one side of the first conductive layer leads to a first test point; the second conductive layer is located on the first conductive layer for electrical connection with a second power connection point of the chip, and one side of the second conductive layer leads to a second test point; and the third conductive layer is located on the second conductive layer for electrical connection with a third power connection point of the chip, and one side of the third conductive layer leads to a third test point.

Abstract: An electronic device may include one or more radios and one or more antennas. Radio-frequency transmission lines may couple a radio to a corresponding antenna. To more efficiently form a radio-frequency transmission line, the radio-frequency transmission line may be formed from interconnected conductive traces distributed between a plurality of printed circuits. By integrating transmission line structures onto printed circuits that also serve other functions, the device can require less space to implement a radio-frequency transmission line. While one or more of these printed circuits may individually be unsuitable to implement a radio-frequency transmission line with a particular impedance, the composite impedance of these transmission line structures across the printed circuits, when properly configured, may provide a radio-frequency transmission line with the particular impedance.

Abstract: A molded semiconductor package includes: a semiconductor die attached to a substrate, the semiconductor die having a bond pad at a first side of the semiconductor die which faces away from the substrate and an insulating layer covering the first side; an electrical conductor attached to a part of the bond pad exposed by an opening in the insulating layer; a mold compound encasing the semiconductor die; and an electrically insulative material filling the opening in the insulating layer and sealing the part of the bond pad exposed by the opening in the insulating layer. The electrically insulative material separates the mold compound from the part of the bond pad exposed by the opening in the insulating layer. A corresponding method of producing the molded semiconductor package also is described.

Abstract: Integrated chips include a dielectric layer that includes at least one trench and at least one plug region. A line is formed in the dielectric layer in the at least one trench and terminates at the plug region. A dielectric plug is formed in the plug region.

Abstract: System, apparatuses and methods are disclosed which relate to the use of substrate integrated waveguide technology in front-end modules. An example circuit card assembly for use as a cellular base station front-end is disclosed which includes at least one component printed circuit board (PCB) layer having front-end module hardware components and at least one filter PCB layer including at least one substrate integrated waveguide (SIW) filter.

Abstract: An open-ended hollow coaxial cable resonator probe configured to receive an aerosol sample for analysis. A metal post shorts the resonator's inner and outer conductors. A metal plate is spaced apart from an open end of the resonator by a dielectric layer that contains the received aerosol sample. Interrogator circuitry coupled to the resonator transmits an electromagnetic wave within the resonator and generates an electric field at the open end of the resonator. The interrogator circuitry is responsive to the generated electric field for determining a resonance frequency and an impedance of the resonator when the aerosol sample is present in the dielectric layer and is configured to identify virus particles in the aerosol sample as a function of the determined resonance frequency and impedance. A portable aerosol analyzer comprises the open-ended hollow coaxial cable resonator and a mouthpiece through which a subject expels a breath sample into the open end of the resonator.

Abstract: Embodiments disclosed herein include electronic packages with improved differential signaling architectures. In an embodiment, the electronic package comprises a package substrate, where the package substrate comprises alternating metal layers and dielectric layers. In an embodiment, a first trace is embedded in the package substrate, where the first trace has a first thickness that extends from a first metal layer to a second metal layer. In an embodiment, the electronic package further comprises a first ground plane laterally adjacent to a first side of the first trace, and a second ground plane laterally adjacent to a second side of the first trace.

Abstract: In an example, monitoring circuitry includes a first and a second coupling to electrically connect the monitoring circuitry to a monitored circuit having a resistance. The resistance of the monitored circuit may be indicative of a status, and the monitored circuit may be connected in series between the first and second coupling. The first coupling comprises a plurality of galvanically separated connection elements which are to form an electrical connection with a common connection element of the monitored circuit. The monitoring circuitry further comprises a monitoring apparatus to determine the resistance of the monitored circuit via the first coupling and the second coupling. The monitoring apparatus is to acquire a plurality of electrical values and to use the plurality of electrical values to determine a value of the resistance of the monitored circuit.

Abstract: The present disclosure provides a semiconductor device package including a first device, a second device, and a spacer. The first device includes a substrate having a first dielectric constant. The second device includes a dielectric element, an antenna, and a reinforcing element. The dielectric element has a second dielectric constant less than the first dielectric constant. The antenna is at least partially within the dielectric element. The reinforcing element is disposed on the dielectric element, and the reinforcing element has a third dielectric constant greater than the first dielectric constant. The spacer is disposed between the first device and the second device and configured to define a distance between the first device and the second device.

Abstract: Embodiments described herein provide an anisotropic conductive film (ACF) positioned on a semiconductor package and techniques of using the ACF to test semiconductor devices positioned in or on the semiconductor package. In one example, a semiconductor package comprises: a die stack comprising one or more dies; a molding compound encapsulating the die stack; a substrate on the molding compound; a contact pad on a surface of the substrate and coupled to the die stack; a test pad on the surface of the substrate; a conductive path between the contact pad and the test pad, where an electrical break is positioned along the conductive path; and an ACF over the electrical break. Compressing the ACF by a test pin creates an electrical path that replaces the electrical break. Data can be acquired by test pin and provided to a test apparatus, which determines whether the dies in the die stack are operating properly.

Abstract: A radar sensor. The radar sensor includes a high-frequency component situated on a circuit board and a waveguide structure, which is connected via a coupling structure to the high-frequency component. The waveguide structure is formed in a mold, which is injection molded to a part of the circuit board supporting the high-frequency component.

Abstract: A semiconductor packaging structure manufactured in a manner which does not leave the chip damaged or susceptible to damage upon the removal of temporary manufacturing supports includes at least one electrical conductor, at least one conductive layer, a chip, and a colloid. The chip is spaced from the conductive layer, the electrical conductor is disposed between the conductive layer and the chip and electrically connects the conductive layer to the chip. The colloid covers all outer surfaces of the chip. A method of fabricating such a semiconductor packaging structure is also provided.

Abstract: A semiconductor device is disclosed. The semiconductor device includes a first die on a first substrate, a second die on a second substrate separate from the first substrate, a transmission line in a redistribution layer on a wafer, and a magnetic structure surrounds the transmission line. The first transmission line electrically connects the first die and the second die. The magnetic structure is configured to increase the characteristic impedance of the transmission line, which can save the current and power consumption of a current mirror and amplifier in a 3D IC chip-on-wafer-on-substrate (CoWoS) semiconductor package.

Abstract: An electronic component includes a single-layer glass plate, an outer-surface conductor that is disposed above an outer surface of the single-layer glass plate and that is at least a part of an electrical element, and a terminal electrode that is a terminal of the electrical element. The terminal electrode is disposed above the outer surface of the single-layer glass plate and being electrically connected to the outer-surface conductor.

Abstract: Systems, devices, and methods related to generating and/or transmitting sensor measurement data are described. A device may include a first conductive pad positioned on a first surface of a substrate. The device may also include a second conductive pad positioned on a second, opposite surface of the substrate. Further, the device may include an inductive coil coupled between the first electrical pad and the second electrical pad. Also, the device may include a third conductive pad positioned on a third surface of the substrate and configured to couple to a sensor. The device may include a fourth conductive pad positioned on a fourth surface of the substrate and configured to couple to the sensor. The device may be configured to wirelessly transmit a signal.

Abstract: A semiconductor apparatus configured to decrease occurrence of exfoliation between a conductor layer and an insulator layer is provided. A first region containing silicon and copper is disposed between a first conductor portion and a first insulator portion. A second region containing silicon and copper is disposed between a second conductor portion and a second insulator portion. The first region has a maximum nitrogen concentration higher than that of the second region.

Abstract: A wiring substrate includes an insulating body; a first conductor including a first shield layer provided in a first layer inside the insulating body, and a second shield layer provided in a second layer at a different position from the first layer in a thickness direction of the insulating body; a second conductor including a first guard layer provided in a third layer positioned between the first layer and the second layer in the thickness direction, and a second guard layer provided in a fourth layer positioned between the second layer and the third layer in the thickness direction; and a third conductor provided in a fifth layer positioned between the third layer and the fourth layer in the thickness direction.

Abstract: A semiconductor device includes: a semiconductor substrate; an electrode pad disposed over a first face of the semiconductor substrate; a redistribution layer electrically connected to the electrode pad; a through hole disposed in the semiconductor substrate so as to extend from a second face opposite to the first face of the semiconductor substrate to the electrode pad; an electrically conductive film covering an inner wall of the through hole, and electrically connected to the electrode pad; an electrically conductive adhesive disposed on a side of the second face of the semiconductor substrate, and electrically connected to the electrode pad via the electrically conductive film; a heat radiating member bonded to the second face of the semiconductor substrate with the electrically conductive adhesive; and a filling member with which the through hole is filled, the filling member being lower in coefficient of thermal expansion than the electrically conductive adhesive.

Abstract: Electronic device package technology is disclosed. In one example, an electronic device includes a substrate having a bond finger, a die coupled to the substrate and having a bond pad, a first bond wire coupled between the bond pad and the bond finger, and a second bond wire coupled between the bond pad and the bond finger. The first bond wire is reverse bonded between a pad solder ball on the bond pad and a finger solder ball on the bond finger. The second bond wire is forward bonded between a supplemental pad solder ball on the pad solder and the bond finger adjacent the finger solder ball. Associated systems and methods are also disclosed.

Abstract: The present technology relates to a semiconductor chip that can ensure a low impedance current path in an I/O ring while suppressing attenuation of radio frequency signals. The semiconductor chip includes an I/O ring surrounding a core circuit, first and second pads serving as input/output terminals for radio frequency signals, and a radio frequency signal transmission line electrically connected to the first and second pads and the core circuit. The radio frequency signal transmission line is formed above the I/O ring. The present technology is applicable to a semiconductor chip that performs input and output of RF signals.

Abstract: A liquid ejecting apparatus includes a drive signal output circuit, a control signal output circuit, a differential signal output circuit, and a head unit, in which the head unit includes an integrated circuit that receives a first drive signal and outputs a second drive signal, and an ejector that ejects liquid from nozzle, and the integrated circuit includes a drive signal input terminal that inputs a first drive signal, a first signal input terminal that inputs a first signal, a second signal input terminal that inputs a second signal, a differential signal receiving circuit that receives the first signal and the second signal, and outputs the control signal, a drive signal selection circuit that outputs the second drive signal based on the control signal and the first drive signal, and a drive signal output terminal that outputs the second drive signal to the ejector.

Abstract: A semiconductor package according to an embodiment of the present invention includes: a heat sink board including an insulated board and a first metal layer formed on the insulated board; at least one semiconductor chip placed on the first metal layer; a plurality of lead frames connected to the semiconductor chips used to electrically connect the semiconductor chips to the outside; and a package housing partially covering the heat sink board, wherein both end parts of the insulated board are projected further than both end parts of the first metal layer.

Abstract: A first board includes a first ground plane, a first ground land, a first transmission line, and a first signal land connected to the first transmission line, wherein the first ground land and the first signal land are formed on the same surface. A second board includes a second ground plane, a second ground land, a second transmission line, and a second signal land connected to the second transmission line, wherein the second ground land and the second signal land are formed on a surface opposing the first board. The second ground land and the second signal land oppose the first ground land and the first signal land, respectively. A conduction member connects the first ground land and the second ground land. The first signal land and the second signal land are connected by capacitance coupling without using any conductor.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to partitioned substrates with interconnect bridge structures and methods of manufacture. The structure includes: a plurality of substrates; at least one chip bonded and electrically connected to each of the plurality of substrates; and an interconnect bridge that physically connects the plurality of substrates and electrically connects each of the plurality of chips bonded to each of the plurality of substrates.

Abstract: The semiconductor device includes: a semiconductor module including a plate-shaped semiconductor element, a conductor electrically connected to one surface of the semiconductor element, a heat dissipation plate of which one surface is thermally and electrically connected to another surface of the semiconductor element, a resin member sealing the semiconductor element, the conductor, and the heat dissipation plate, and an insulation heat dissipation member thermally connected to another surface of the heat dissipation plate exposed from the resin member; a heatsink thermally connected to the insulation heat dissipation member; and an electric field inhibiting plate including a plate-shaped thin part covering the one surface of the semiconductor element and opposed thereto so as to be separated therefrom, the thin part being sealed by the resin member, and a connection part extending from the thin part to the heatsink and thermally and electrically connected to the heatsink.

Abstract: A threaded cooling apparatus includes a head having a heat exchanger and a shaft having a threaded section configured to mechanically fasten the head to a structure. The heat exchanger is configured to exchange heat with a coolant flowing through the head. The shaft also includes first and second cooling channels. The first cooling channel is configured to deliver the coolant to the heat exchanger, and the second cooling channel is configured to exhaust the coolant from the heat exchanger. The apparatus may also include a first seal between the head and the structure that is configured to reduce or prevent coolant loss. The apparatus may further include a second seal that is configured to reduce or prevent coolant flow between the first and second cooling channels that bypasses the heat exchanger.

Abstract: Embodiments of the present disclosure provide an electronic device and an antenna. The antenna for includes a first component configured for high frequency feed; a second component configured for low frequency feed; a third component configured for high frequency signal transmission; and a fourth component configured for low frequency signal transmission. The first component is coupling a high frequency signal to the third component, and the second component is coupling a low frequency signal to the fourth component.

Abstract: An amplifier includes a transistor chip including a plurality of transistor cells, a gate pad, and a drain pad, a matching substrate having a surface on which a metal pattern is formed, a terminal with a width larger than a width of the transistor chip and than a width of the matching substrate, a plurality of terminal wires connecting the terminal to the metal pattern, and a plurality of chip wires connecting the metal pattern to the transistor chip. Inter-wire distances of portions of the plurality of terminal wires connected to the metal pattern are larger than inter-wire distances between portions of the plurality of terminal wires connected to the terminal.

Abstract: Disclosed herein is a thin film capacitor embedded substrate that includes a substrate and a plurality of thin film capacitors including at least first and second thin film capacitors embedded in the substrate. The first and second thin film capacitors are connected in parallel and have mutually different self-resonant frequencies.

Abstract: Method of manufacturing holding plate (11) including ceramic material of several chemical elements and configured for holding apparatus (10) for holding a component by electrostatic forces or vacuum, includes the steps of material removal from holding plate (11) by laser ablation, wherein by laser irradiation (1) protrusions (13) are formed on holding plate (11), end faces (13.1) of which span a carrier surface for the component, and surface modification of holding plate (11) by laser irradiation (1), wherein irradiation parameters of laser irradiation (1) are set such that at least one of the chemical elements of the ceramic material is enriched on the surface of holding plate (11). A method is also described of manufacturing holding apparatus (10) for holding a component by electrostatic forces or vacuum, holding plate (11) which is produced with the inventive method, and holding apparatus (10) with at least one holding plate (11).

Abstract: A microwave electronic component comprising a substrate having top and bottom substrate surfaces; the substrate comprising an aperture between the top and bottom substrate surfaces; a metallic heat sink filling the aperture; a microwave integrated circuit having a top circuit surface with at least one microwave signal port and a bottom circuit surface in contact with the metallic heat sink; a signal line comprising at least a metallic via between the top and bottom substrate surfaces, and a top signal conductor arranged between the microwave signal port and the metallic via; wherein the dimensions and location of the metallic via are chosen such that the metallic via forms, together with the metallic heat sink, a first impedance-matched non-coaxial transmission line.

Abstract: An antenna package structure comprises a substrate with a first surface and a second surface; a dielectric layer, disposed on the first surface of the substrate comprises at least a impedance matching structure and an interconnection structure; a molding layer, disposed on the dielectric layer comprises a plurality of chips wherein a control chip electrically connects to the impedance matching structure and a plurality of conducting structures; an antenna layer, disposed on the second surface of the substrate comprising at least an antenna electrically connects to the substrate; and a protection layer covers the antenna layer.

Abstract: A high-frequency transmission line is provided that improves a high-frequency characteristic. The high-frequency transmission line includes a first conductor line, a termination resistance connected to the first conductor line, a second conductor line connected to the termination resistance, and a ground line that is provided to be opposed to the first conductor line, the termination resistance, and the second conductor line to have a predetermined distance thereto and that is connected to the second conductor line. The first conductor line and the ground line are formed to have a line width decreasing toward the termination resistance, respectively.

Abstract: An integrated circuit includes a bottom substrate, a metal layer disposed over the bottom substrate and a hollow metal pillar disposed on the metal layer. The metal layer and the hollow metal pillar are electrically connected.

Abstract: A packaging structure (100) having a split-block assembly with a first and a second conducting block section (10A,20A) and at least one transition between a first planar transmission line (2A) and a second transmission line (11A), and one or more input/output ports. The first transmission line (2A) is arranged on a substrate disposed on the first conducting block section (10A) and has a coupling section (3A), a cavity (4A) with a cavity opening in an upper surface of the first conducting block section (10A), and the second transmission line (11A) being in line with the first transmission line (2A) and located on an opposite side of the opening of the cavity (4A).

Abstract: Traces on a PCB can be spaced closer together than in conventional layouts, which previously required the pair-to-pair spacing for the high-speed differential stripline signals to be at least 5H if the signals are originating from the same source and 7H when the signals on two pairs of transmission lines in the traces originate from different sources. Traces may be spaced closer together when, for example, a ratio of the core height to the prepreg height of the printed circuit board is approximately equal to one. Traces may be spaced closer together when, for example, a ratio of the trace spacing distance to the core height distance is less than approximately one.

Abstract: A highly reliable high-frequency ceramic board appropriately transmitting signals with high frequencies up to 50 GHz includes a flat ceramic substrate, a pair of ground lines bonded to a peripheral portion of a back surface of the ceramic substrate, a first lead pad electrode bonding the ground lines, at least one pair of signal lines between the ground lines, second lead pad electrodes attached where the signal lines are bonded, and a groove-like recess between the second lead pad electrodes. The pair of signal lines forms a differential transmission line. An interval LGS between a first edge of the first lead pad electrode and a second edge of a corresponding second lead pad electrode and an interval LSS between facing second edges satisfy LSS<2LGS.

Abstract: The invention relates to microwave technology and can be used in measuring technology and wireless communication. The technical result is a waveguide-to-microstrip transition which provides reduced signal transmission losses and increased working bandwidth together with a low wave reflection coefficient. A contacting metal layer is arranged on an upper surface of a dielectric circuit board around a micro-strip probe, without electrical contact with the micro-strip probe and a micro-strip transmission line and forming an internal area on the dielectric circuit boar being a waveguide channel area. A closed waveguide section having a slot in the area of the microstrip transmission line is arranged on the contacting metal layer. At least one metallized transition through-hole is formed along a perimeter around the area of the waveguide channel in the metal layers and in the dielectric circuit board, and at least one non-metallized through-hole is formed inside the waveguide channel area.

Abstract: An printed circuit board (PCB) assembly and method of assembling the same for a high-speed, short-reach communication link are described that provide a mechanism for transmitting radio frequency (RF) waves from one digital electronic component of the PCB assembly to another, where the second digital electronic component is located either on the same PCB assembly or on a second PCB assembly. The assembly includes a PCB having multiple layers and a digital electronic component supported by the PCB. At least one of the layers defines a channel that confines RF waves therein. An RF antenna in communication with the digital electronic component extends into the channel, and the RF antenna transmits RF signals generated by the digital electronic component into the channel as RF waves or receives RF waves via the channel and conveys corresponding RF signals to the digital electronic component.

Abstract: A device includes an enclosure cover; a chip carrier attachable to and removable from the enclosure cover; and a ridge gap waveguide (RGW) cover. The chip carrier includes at least two cavities disposed on one surface and located on opposite sides, and each cavity has a slot extending to an opposite surface of the chip carrier. The RGW cover includes a plurality of ridges and a plurality of pillars disposed on one surface. The enclosure cover and the RGW cover are configured to connect to each other with the chip carrier located therebetween, and the opposite surface of the chip carrier faces the one surface of the RGW cover when the enclosure cover and the RGW cover are connected.

Abstract: This electronic device is provided with: a resin molding; and a conductive cable including an electric wire. One end portion of the conductive cable is embedded in the resin molding. The surface of the resin molding exposes an end surface on the side of the one end portion of the conductive cable and includes a surface which is continuous to the end surface. The electronic device is further provided with wirings formed on the end surface and the surface so as to be connected to the electric wire in the end surface.

Abstract: A device includes an enclosure cover having a groove portion disposed on one surface, a chip carrier attachable to and removable from the enclosure cover in the groove portion, the chip carrier including at least two cavities disposed on one surface and located on opposite sides, each cavity has a slot extending to an opposite surface of the chip carrier. Also included is a ridge gap waveguide (RGW) cover with a plurality of pillars disposed on one surface, and a plurality of ridges are also disposed on the one surface. Each ridge includes a branching junction such that each ridge branches to at least two ridge portions. The enclosure cover and the RGW cover are configured to connect to each other with the chip carrier located therebetween, and the opposite surface of the chip carrier faces the one surface of the RGW cover.

Abstract: A device and a method for reducing an influence of interference between signals using an aperture array in chip-to-chip wireless communication are provided. The device includes a transmitter including at least one transmission antenna for transmitting a signal, a receiver including at least one reception antenna for receiving the signal, a guide structure including at least one opening for guiding a path of the signal, and the at least one transmission antenna, the at least one reception antenna, and the at least one opening are arranged to correspond to one another.

Abstract: A surface current suppression filter (1) is a bandstop filter that suppresses propagation of a surface current in a predetermined propagation direction on a dielectric substrate (2). The filter (1) is configured such that a plurality of electromagnetic band gap (EBG) rows (10, 20) are arrayed in an array direction. Each EBG row (10, 20) has at least one EBG (11, 21) that is arrayed in a perpendicular direction orthogonal to the array direction. Cutoff characteristics of a first EBG (11) in the first EBG row (10) differs from cutoff characteristics of a second EBG (12) in the second EBG row (20).

Abstract: An antenna semiconductor package device includes: (1) a waveguide cavity having a radiation opening; and (2) a first directing element outside of the waveguide cavity and separated from the waveguide cavity by a first gap.