Transmission Line Lead (e.g., Stripline, Coax, Etc.) Patents (Class 257/664)
  • Patent number: 10607953
    Abstract: A device includes an enclosure cover having a groove portion disposed on one surface, a chip carrier attachable to and removable from the enclosure cover in the groove portion, the chip carrier including at least two cavities disposed on one surface and located on opposite sides, each cavity has a slot extending to an opposite surface of the chip carrier. Also included is a ridge gap waveguide (RGW) cover with a plurality of pillars disposed on one surface, and a plurality of ridges are also disposed on the one surface. Each ridge includes a branching junction such that each ridge branches to at least two ridge portions. The enclosure cover and the RGW cover are configured to connect to each other with the chip carrier located therebetween, and the opposite surface of the chip carrier faces the one surface of the RGW cover.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: March 31, 2020
    Assignee: United States of America as represented by Secretary of the Navy
    Inventor: Jia-Chi S. Chieh
  • Patent number: 10581535
    Abstract: A device and a method for reducing an influence of interference between signals using an aperture array in chip-to-chip wireless communication are provided. The device includes a transmitter including at least one transmission antenna for transmitting a signal, a receiver including at least one reception antenna for receiving the signal, a guide structure including at least one opening for guiding a path of the signal, and the at least one transmission antenna, the at least one reception antenna, and the at least one opening are arranged to correspond to one another.
    Type: Grant
    Filed: December 27, 2016
    Date of Patent: March 3, 2020
    Assignees: Samsung Electronics Co., Ltd., Korea University Research and Business Foundation
    Inventors: Jae-Sung Rieh, Daekeun Yoon, Jungsoo Kim
  • Patent number: 10566704
    Abstract: A surface current suppression filter (1) is a bandstop filter that suppresses propagation of a surface current in a predetermined propagation direction on a dielectric substrate (2). The filter (1) is configured such that a plurality of electromagnetic band gap (EBG) rows (10, 20) are arrayed in an array direction. Each EBG row (10, 20) has at least one EBG (11, 21) that is arrayed in a perpendicular direction orthogonal to the array direction. Cutoff characteristics of a first EBG (11) in the first EBG row (10) differs from cutoff characteristics of a second EBG (12) in the second EBG row (20).
    Type: Grant
    Filed: July 14, 2015
    Date of Patent: February 18, 2020
    Assignee: DENSO CORPORATION
    Inventors: Kazushi Kawaguchi, Asahi Kondo
  • Patent number: 10546825
    Abstract: An antenna semiconductor package device includes: (1) a waveguide cavity having a radiation opening; and (2) a first directing element outside of the waveguide cavity and separated from the waveguide cavity by a first gap.
    Type: Grant
    Filed: January 30, 2019
    Date of Patent: January 28, 2020
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Shao-En Hsu, Huei-Shyong Cho, Shih-Wen Lu
  • Patent number: 10529642
    Abstract: The semiconductor device includes a first conductive layer, semiconductor elements bonded to the upper surface of the first conductive layer, a second conductive layer separated from the first conductive layer, a control terminal bonded to the second conductive layer, a control resistor bonded to the upper surface of the second conductive layer, a control-resistor pin bonded to the upper surface of the control resistor and a wiring board having a control-wiring layer for electrically connecting the semiconductor elements and the control-resistor pin.
    Type: Grant
    Filed: September 25, 2018
    Date of Patent: January 7, 2020
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Katsumi Taniguchi, Motohito Hori
  • Patent number: 10519426
    Abstract: The present invention provides methods for inducing regression of tumors in human subjects, the methods utilize a modified mesogenic strain of Newcastle disease virus (NDV) with modified F protein cleavage site, which is non-pathogenic to poultry (lentogenic), but exhibits oncolytic properties. The disclosed methods provide safe, effective and reliable means to induce regression of a tumor in an individual in need thereof. These methods overcome the drawbacks of using pathogenic strains of viruses for human therapy.
    Type: Grant
    Filed: September 2, 2014
    Date of Patent: December 31, 2019
    Assignee: MEDIMMUNE LIMITED
    Inventors: Xing Cheng, Danielle Carroll, Matthew McCourt, Mark Galinski, Hong Jin
  • Patent number: 10524347
    Abstract: The invention relates to a circuit board for populating with at least one electronic component, at least one heat conducting element being provided, connected to a surface of a sheet-like circuit board body by way of a boundary layer. The boundary layer consists in certain areas of an electrically non-conducting layer and in certain areas of an electrically conducting layer, the non-conducting layer combining with the circuit board body and the heat conducting element to provide at least one receiving space with a pocket-like volume for the conducting layer.
    Type: Grant
    Filed: October 24, 2013
    Date of Patent: December 31, 2019
    Assignee: Schoeller Electronics Systems GmbH
    Inventor: Jan Hendrik Berkel
  • Patent number: 10490509
    Abstract: A semiconductor package includes an integrated circuit mounted on a substrate, a first power line disposed on or above the substrate and configured to transmit an operating voltage to the integrated circuit, and a second power line disposed on or above the substrate and configured to transmit a ground voltage to the integrated circuit, in which each of the first power line and the second power line has a first width, the first power line is spaced apart from the second power line by a first distance, thicknesses of each of the first power line and the second power line are less than or equal to 20 ?m, and a ratio of the first width to the first distance is greater than 2.5.
    Type: Grant
    Filed: November 29, 2016
    Date of Patent: November 26, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sung Wook Moon, Min Sung Kim, Eun Seok Song, Kyoung Ho Kim, Dong Chul Kim, Jin Ho Kim, Ji Hyun Lee
  • Patent number: 10477674
    Abstract: A circuit substrate includes an insulating body, a wiring enclosed by the insulating body, a conductive layer formed within the insulating body on a same plane as the wiring, and electrically insulated from the wiring by the insulating body, and one or more conductive vias extending through an edge portion of the conductive layer in a thickness direction intersecting the plane. A first width of the insulating body between the wiring and the conductive layer at a first position in the plane direction that does not correspond to any of said one or more conductive vias is smaller than a second width of the insulating body between the wiring and the conductive layer at a second position in the plane direction that corresponds to one of said one or more conductive vias.
    Type: Grant
    Filed: August 30, 2017
    Date of Patent: November 12, 2019
    Assignee: Toshiba Memory Corporation
    Inventor: Satoru Fukuchi
  • Patent number: 10461034
    Abstract: A package structure and the method thereof are provided. At least one die is molded in a molding compound. A ground plate is located on a backside surface of the die, a first surface of the ground plate is exposed from the molding compound and a second surface of the ground plate is covered by the molding compound. The first surface of the ground plate is levelled and coplanar with a third surface of the molding compound. A connecting film is located between the backside surface of the die and the second surface of the ground plate. The die, the molding compound and the ground plate are in contact with the connecting film. Through interlayer vias (TIVs) are molded in the molding compound, and at least one of the TIVs is located on and physically contacts the second surface of the ground plate.
    Type: Grant
    Filed: September 6, 2017
    Date of Patent: October 29, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kai-Chiang Wu, Chen-Hua Yu, Kuo-Chung Yee
  • Patent number: 10460992
    Abstract: High-frequency thin film chip attenuators can include a substrate having a first side and a second side, a first portion coupled to the first side of the substrate, and a second portion coupled to the second side of the substrate. The first portion can include a ground section, an input contact section, and an output contact section. The second portion can include a ground section, an input section, an output section, and a plurality of resistive sections providing electrical communication between the input section, the output section, and the ground section. The resistive sections can be arranged in an attenuation configuration to attenuate a signal received at the input section and output via the output section. A plurality of through-holes extending through the substrate can provide electrical communication between sections on the first side of the substrate and associated sections on the second side of the substrate.
    Type: Grant
    Filed: November 6, 2018
    Date of Patent: October 29, 2019
    Assignee: THIN FILM TECHNOLOGY CORPORATION
    Inventors: Michael James Howieson, Mitchell Andrew Hansen, Mark Hamilton Broman
  • Patent number: 10438881
    Abstract: Embodiments provide a packaging arrangement that includes a high density interconnect bridge for interconnecting dies within the packaging arrangement. The packaging arrangement comprises one or more redistribution layers and an interconnect bridge embedded within the one or more redistribution layers. A first die is coupled to (i) a first portion of the one or more redistribution layers and (ii) a first portion of the interconnect bridge. A second die coupled to a (ii) a second portion of the one or more redistribution layers and (ii) a second portion of the interconnect bridge to electrically couple the first die and the second die via at least the first interconnect bridge.
    Type: Grant
    Filed: October 25, 2016
    Date of Patent: October 8, 2019
    Assignee: Marvell World Trade Ltd.
    Inventors: Long-Ching Wang, Lijuan Zhang, Ronen Sinai
  • Patent number: 10431526
    Abstract: A metal heat slug having an upper and lower surface is provided. First and second electrically conductive leads are provided. First and second electrically insulating fastening mechanisms are provided. The first and second fastening mechanisms are adhered to the upper surface of the heat slug in an outer peripheral region of the heat slug such that the first and second leads are vertically separated from and electrically insulated from the heat slug. The central die attach region is exposed from the first and second fastening mechanisms after adhering the first and second fastening mechanisms to the upper surface of the heat slug.
    Type: Grant
    Filed: October 9, 2017
    Date of Patent: October 1, 2019
    Assignee: Cree, Inc.
    Inventors: Kar Meng Ho, Chiew Li Tai, Jia Yi Wong, Sanjay Kumar Murugan
  • Patent number: 10418720
    Abstract: A signal line conversion structure of the antenna array is disposed between the antenna array and the circuit substrate, which includes a first dielectric substrate is disposed on the circuit substrate, a second dielectric substrate is vertically disposed on the first dielectric substrate and divided into a first region and a second region, and the second dielectric substrate is provided with the antenna array. At least one signal line is disposed on the first region and extends to the second dielectric substrate for connecting the circuit substrate and the antenna array. A metal connecting plate has at least three metal through holes pierced in the first dielectric substrate and connected to the second ground layer. The metal connecting plate is connected to the first ground layer of the first dielectric substrate and the second ground layer of the second dielectric substrate through the metal through holes.
    Type: Grant
    Filed: June 25, 2018
    Date of Patent: September 17, 2019
    Assignee: National Chiao Tung University
    Inventors: Jenn-Hwan Tarng, Chi-Yang Chang, Che-Hao Chang, Jing-Cheng Hong
  • Patent number: 10403604
    Abstract: Embodiments of the present disclosure are directed toward a stacked package assembly for embedded dies and associated techniques and configurations. In one embodiment, stacked package assembly may comprise a first die package and a second die package stacked one upon the other with plural interconnections between them; and a voltage reference plane embedded in at least one of the first and second die packages in proximity and generally parallel to the other of the first and second die packages.
    Type: Grant
    Filed: November 5, 2015
    Date of Patent: September 3, 2019
    Assignee: Intel Corporation
    Inventors: Bok Eng Cheah, Jackson Chung Peng Kong, Ping Ping Ooi, Kooi Chi Ooi, Shanggar Periaman
  • Patent number: 10396720
    Abstract: High-frequency amplifier apparatuses suitable for producing output powers of at least 1 kW at frequencies of at least 2 MHz for plasma excitation are disclosed. These high-frequency amplifiers include two transistors, the source or emitter connections of which are each connected to a ground connection point. The transistors can have an identical design and are arranged on a multilayer printed circuit board. The apparatus also includes a power transformer, the primary winding of which is connected to the drain or collector connections of the transistors. The primary winding and the secondary winding of the power transformer are each in the form of planar conductor tracks which are arranged in different upper layers of the multilayer printed circuit board.
    Type: Grant
    Filed: December 27, 2017
    Date of Patent: August 27, 2019
    Assignee: TRUMPF Huettinger GmbH + Co. KG
    Inventors: Andre Grede, Alexander Alt, Daniel Gruner, Anton Labanc
  • Patent number: 10361271
    Abstract: A semiconductor device comprises an active region and a passive region located outside the active region. The active region comprises a plurality of active region units. At least one pair of adjacent active region units do not completely overlap in a length direction of the semiconductor device.
    Type: Grant
    Filed: December 22, 2016
    Date of Patent: July 23, 2019
    Assignee: GPOWER SEMICONDUCTOR, INC.
    Inventors: Naiqian Zhang, Feihang Liu, Yi Pei
  • Patent number: 10340224
    Abstract: A package includes a conductor base plate having a element fixed to an upper surface thereof, a side wall provided on the conductor base plate to surround the element, the side wall having a conductor portion electrically connected to the conductor base plate, a dielectric cap disposed on the side wall, a front-side metal film provided on an outer surface of the dielectric cap, a first back-side metal film provided on an inner surface of the dielectric cap such that a center of the first back-side metal film approximately coincides with a center of a surface of the dielectric cap which faces the conductor base plate, and a plurality of vias passing through the dielectric cap to achieve electrical connection between the front-side metal film and the first back-side metal film and between the front-side metal film and the conductor portion oldie side wall.
    Type: Grant
    Filed: July 18, 2016
    Date of Patent: July 2, 2019
    Assignee: Mitsubishi Electric Corporation
    Inventors: Miyo Miyashita, Kazuya Yamamoto, Hiroaki Maehara
  • Patent number: 10256863
    Abstract: An integrated radio frequency (RF) circuit structure may include a resistive substrate material and a switch. The switch may be arranged in a silicon on insulator (SOI) layer supported by the resistive substrate material. The integrated RF circuit structure may also include an isolation layer coupled to the SOI layer. The integrated RF circuit structure may further include a filter, composed of inductors and capacitors. The filter may be arranged on a surface of the integrated RF circuit structure, opposite the resistive substrate material. In addition, the switch may be arranged on a first surface of the isolation layer.
    Type: Grant
    Filed: May 10, 2016
    Date of Patent: April 9, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Shiqun Gu, Chengjie Zuo, Steve Fanelli, Thomas Gee, Young Kyu Song
  • Patent number: 10242143
    Abstract: Aspects of the present disclosure relate to a racetrack that forms part of an RF isolation structure of a packaged module and wireless devices that include such a packaged module. The racetrack can be disposed in a substrate and around an RF component that is on the substrate. The racetrack can include at least one break and/or at least one narrowed section without significantly degrading the EMI performance of the RF isolation structure.
    Type: Grant
    Filed: February 17, 2016
    Date of Patent: March 26, 2019
    Assignee: Skyworks Solutions, Inc.
    Inventors: Howard E. Chen, Matthew Sean Read, Hoang Mong Nguyen, Anthony James LoBianco, Guohao Zhang, Dinhphuoc Vu Hoang
  • Patent number: 10224291
    Abstract: A high frequency semiconductor device package includes a metal plate, a frame body, a first lead part, a second lead part, a first conductive layer, and a second conductive layer. The frame body includes a first frame part made and a second frame part. The first frame part has a lower surface bonded to the metal plate. The first frame part has an upper surface including a first region and a second region. The first lead part protrudes outward along a line passing through a central part of the first region and a central part of the second region in plan view. The second lead part protrudes outward along the line in plan view. The first conductive layer includes a first stripe part and a first connection part. The second conductive layer includes a second stripe part and a second connection part.
    Type: Grant
    Filed: January 17, 2017
    Date of Patent: March 5, 2019
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Osamu Moriya, Tomohiro Senju
  • Patent number: 10194534
    Abstract: Provided herein is a printed wiring board that can desirably dissipate the heat of a heat-generating component. The printed wiring board includes one or more wires, and one or more heat-generating components. The one or more wires include a rolled copper foil, either partly or as a whole. The one or more heat-generating components and the one or more wires are directly or indirectly connected to each other.
    Type: Grant
    Filed: July 20, 2017
    Date of Patent: January 29, 2019
    Assignee: JX Nippon Mining & Metals Corporation
    Inventors: Hideta Arai, Atsushi Miki, Satoru Morioka
  • Patent number: 10153208
    Abstract: High-frequency thin film chip attenuators can include a substrate having a first side and a second side, a first portion coupled to the first side of the substrate, and a second portion coupled to the second side of the substrate. The first portion can include a ground section, an input contact section, and an output contact section. The second portion can include a ground section, an input section, an output section, and a plurality of resistive sections providing electrical communication between the input section, the output section, and the ground section. The resistive sections can be arranged in an attenuation configuration to attenuate a signal received at the input section and output via the output section. A plurality of through-holes extending through the substrate can provide electrical communication between sections on the first side of the substrate and associated sections on the second side of the substrate.
    Type: Grant
    Filed: January 9, 2018
    Date of Patent: December 11, 2018
    Assignee: THIN FILM TECHNOLOGY CORPORATION
    Inventors: Michael James Howieson, Mitchell Andrew Hansen, Mark Hamilton Broman
  • Patent number: 10122088
    Abstract: A collective lamination substrate N is provided with pattern layers having N number of layers, where N is an integer and 4 or more, a pseudo waveguide formed penetrating through the pattern layers in a lamination direction, a converter section formed in the pattern layers, mutually converting between an electrical signal and radio waves being transmitted and received via the pseudo waveguide, and ground patterns formed in the pattern layers, covering a periphery of a waveguide formation section. The collective lamination substrate further includes: antennas formed in the waveguide formation section; a first via group provided in a periphery of the waveguide formation section; and a second via group provided in a periphery of the waveguide formation section and positioned at a more outer portion than the first via group.
    Type: Grant
    Filed: January 21, 2015
    Date of Patent: November 6, 2018
    Assignee: DENSO CORPORATION
    Inventors: Kazuhiro Aoki, Shinichiro Matsuzawa
  • Patent number: 10108753
    Abstract: Method of designing a laminate substrate having upper laminate layers and an equal plurality of lower laminate layers including: dividing the laminate substrate into regions having corresponding laminate layer pairs consisting of an upper laminate layer and a lower laminate layer; calculating a net stretching value for each corresponding laminate layer pair in each region to result in net stretching values in each region; summing the net stretching values in each region to result in a net stretching value for each region proportional to a curvature of each local region; calculating a relative out-of-plane displacement for the laminate substrate from the curvature of each local region; calculating a predicted thermal warpage for the laminate substrate; and finalizing a design of the laminate substrate when the predicted thermal warpage is within a predetermined acceptable range.
    Type: Grant
    Filed: June 7, 2016
    Date of Patent: October 23, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Anson J. Call, Vijayeshwar D. Khanna, David J. Russell, Krishna R. Tunga
  • Patent number: 10020249
    Abstract: An electronic device is provided. In particular, the electronic device includes (i) an electronic integrated circuit (IC) chip, (ii) a chip mounting substrate for mounting the electronic IC chip on a chip side of the chip mounting substrate, (iii) a radio frequency (RF) interface component disposed on an opposing side of the chip mounting substrate, the opposing side opposing the chip side, and (iv) an RF bridge component penetrating a first opening in the chip mounting substrate and configured to operably connect the electronic IC chip and the RF interface component.
    Type: Grant
    Filed: October 21, 2016
    Date of Patent: July 10, 2018
    Assignee: Ciena Corporation
    Inventors: Jean-Frédéric Gagné, Mathieu Laliberté
  • Patent number: 9985680
    Abstract: Diversity modules for mobile devices are provided herein. In certain configurations, a diversity module includes a first antenna-side multi-throw switch, a second antenna-side multi-throw switch, a first transceiver-side multi-throw switch, a second transceiver-side multi-throw switch, a low band signal path between the first antenna-side multi-throw switch and the first transceiver-side multi-throw switch and configured to output a low band receive signal, a mid band signal path between the second antenna-side multi-throw switch and the second transceiver-side multi-throw switch and configured to output a mid band receive signal of higher frequency content than the low band receive signal, and a high band signal path between the second antenna-side multi-throw switch and the first transceiver-side multi-throw switch and configured to output a high band receive signal of higher frequency content than the mid band receive signal.
    Type: Grant
    Filed: February 9, 2017
    Date of Patent: May 29, 2018
    Assignee: SKYWORKS SOLUTIONS, INC.
    Inventor: Stephane Richard Marie Wloczysiak
  • Patent number: 9978676
    Abstract: An interconnect is described that comprises an interconnect channel, and two channel couplers coupled to the two ends of the interconnect channel through respective stoppers that provide a gap between the channel couplers and the interconnect channel. Each channel coupler can comprise a coplanar waveguide, a microstrip line, and a patch-antenna based coupler. The interconnect can enable communication between integrated circuits using signal waves having a frequency between 100 GHz and 3 THz.
    Type: Grant
    Filed: May 27, 2016
    Date of Patent: May 22, 2018
    Assignee: The Regents of the University of California
    Inventors: Qun Gu, Xiaoguang Liu, Neville C. Luhmann, Jr., Bo Yu
  • Patent number: 9978699
    Abstract: The invention discloses a three-dimensional complementary-conducting-strip (CCS) structure. Some two-dimensional mesh metal layers are stacked vertically and connected mutually via numerous vias to form a three-dimensional network structure, and one or more signal lines with three-dimensional trace style(s) are positioned inside and separated away the three-dimensional network structure. Moreover, each two-dimensional mesh metal layer is a planar metal layer with one or more empty areas. The three-dimensional network structure is grounded, the signal lines(s) is electrically connected to the device(s) and/or terminal(s) respectively, and the dielectric material(s) is used to electrically insulate the signal line(s) from the three-dimensional network structure.
    Type: Grant
    Filed: April 7, 2017
    Date of Patent: May 22, 2018
    Assignee: DR TECHNOLOGY CONSULTING COMPANY, LTD.
    Inventors: Gin-Lan Tzuang Yang, Lawrence Dah-Ching Tzuang
  • Patent number: 9941560
    Abstract: A broadband fully micromachined transition from rectangular waveguide to cavity-backed coplanar waveguide line for submillimeter-wave and terahertz application is presented. The cavity-backed coplanar waveguide line is a planar transmission line that is designed and optimized for minimum loss while providing 50 Ohm characteristic impedance. This line is shown to provide less than 0.12 dB/mm loss over the entire J-band. The transition from cavity-backed coplanar waveguide to a reduced-height waveguide is realized in three steps to achieve a broadband response with a topology amenable to silicon micromachining. A novel waveguide probe measurement setup is also introduced and utilized to evaluate the performance of the transitions.
    Type: Grant
    Filed: December 22, 2015
    Date of Patent: April 10, 2018
    Assignee: The Regents of The University of Michigan
    Inventors: Kamal Sarabandi, Meysam Moallem, Armin Jam
  • Patent number: 9941228
    Abstract: A millimeter wave integrated circuit (IC) chip. The IC chip comprises an IC die and a wire bond ball grid array package encapsulating the IC die. The wire bond ball grid array package comprises a solder ball array, a millimeter wave transmit channel, and a millimeter wave receive channel, wherein each millimeter wave transmit and receive channel electrically couples the IC die to a signal ball of the solder ball array and is configured to resonate at an operating frequency band of the millimeter wave IC chip.
    Type: Grant
    Filed: April 25, 2017
    Date of Patent: April 10, 2018
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Rajen Manicon Murugan, Minhong Mi, Gary Paul Morrison, Jie Chen, Kenneth Robert Rhyner, Stanley Craig Beddingfield, Chittranjan Mohan Gupta, Django Earl Trombley
  • Patent number: 9935063
    Abstract: Integrated circuit (IC) chip “on-die” inductor structures (systems and methods for their manufacture) may improve signaling from a data signal circuit to a surface contact of the chip. Such inductor structures may include a first data signal inductor having (1) a second end electrically coupled to an electrostatic discharge (ESD) circuit and a capacitance value of that circuit, and (2) a first end electrically coupled to a the data signal surface contact and to a capacitance value at that contact; and a second data signal inductor having (1) a second end electrically coupled to the data signal circuit and a capacitance value of that circuit, (2) a first end electrically coupled to the second end of the first data signal inductor, and to the capacitance value of the ESD circuit. Inductor values of the first and second inductors may be selected to cancel out the capacitance values to improve signaling.
    Type: Grant
    Filed: July 1, 2016
    Date of Patent: April 3, 2018
    Assignee: Intel Corporation
    Inventors: Yu Amos Zhang, Jihwan Kim, Ajay Balankutty, Anupriya Sriramulu, MD. Mohiuddin Mazumder, Frank O'Mahony, Zuoguo Wu, Kemal Aygun
  • Patent number: 9935025
    Abstract: An electronic component housing package includes a substrate having an upper surface including a mount region on which an electronic component is to be mounted; a frame body disposed on the upper surface of the substrate, the frame body being provided with a through-hole portion; and an input/output member disposed on the frame body so as to block the through-hole portion, the input/output member having wiring conductors which are to be electrically connected to the electronic component, the wiring conductors extending to an inside and outside of the frame body and also extending along a lower surface of the input/output member on the outside of the frame body. The input/output member is provided with a cutout portion which is cut out so as to extend from a gap between the wiring conductors on the lower surface along the wiring conductors to an outer side surface of the input/output member.
    Type: Grant
    Filed: March 13, 2015
    Date of Patent: April 3, 2018
    Assignee: Kyocera Corporation
    Inventor: Yoshiki Kawazu
  • Patent number: 9893026
    Abstract: Inter-substrate coupling and alignment using liquid droplets can include electrical and plasmon modalities. For example, a set of droplets can be placed on a bottom substrate. A top substrate can be placed upon the droplets, which uses the droplets to align the substrates. Using the droplets in a capacitive or plasmon coupling modality, information or power can be transferred between the substrates using the droplets.
    Type: Grant
    Filed: October 29, 2014
    Date of Patent: February 13, 2018
    Assignee: Elwha LLC
    Inventors: William David Duncan, Roderick A. Hyde, Jordin T. Kare, Thomas M. McWilliams, Thomas Allan Weaver, Lowell L. Wood, Jr.
  • Patent number: 9887177
    Abstract: Inter-substrate coupling and alignment using liquid droplets can include electrical and plasmon modalities. For example, a set of droplets can be placed on a bottom substrate. A top substrate can be placed upon the droplets, which uses the droplets to align the substrates. Using the droplets in a capacitive or plasmon coupling modality, information or power can be transferred between the substrates using the droplets.
    Type: Grant
    Filed: October 29, 2014
    Date of Patent: February 6, 2018
    Assignee: Elwha LLC
    Inventors: William David Duncan, Roderick A. Hyde, Jordin T. Kare, Thomas M. McWilliams, Thomas Allan Weaver, Lowell L. Wood, Jr.
  • Patent number: 9887676
    Abstract: A high frequency semiconductor amplifier includes a package base part, and a monolithic microwave integrated circuit. The package base part includes a metal plate provided with an attachment hole, a frame body bonded to the metal plate and provided with an opening, a first lead part, and a second lead part. The monolithic microwave integrated circuit is provided with a first amplification element and a second amplification element. An output electrode of the second amplification element is connected to the second lead part via an output combiner. Each finger electrode of the second amplification element is generally orthogonal to the first line. Each finger electrode of the first amplification element is generally parallel to the first line. The attachment hole of the metal plate is provided in a region lying along a second line generally orthogonal to the first line and protruding outside the frame body.
    Type: Grant
    Filed: January 17, 2017
    Date of Patent: February 6, 2018
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Osamu Moriya, Tomohiro Senju
  • Patent number: 9882258
    Abstract: An apparatus providing a direct chip to waveguide transition, comprising: one or more waveguides, a chip partially embedding each of the waveguides at a transition area positioned at a narrow side of each waveguide, and a transmitting element disposed at each of the transition areas, thereby providing one or more simultaneous, direct transitions between the chip and the waveguides.
    Type: Grant
    Filed: March 7, 2016
    Date of Patent: January 30, 2018
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Roi Carmon, Danny Elad, Noam Kaminski, Ofer Markish, Thomas Morf, Evgeny Shumaker
  • Patent number: 9871501
    Abstract: An RF circuit includes a first dielectric material, a signal line and a bias line over a first surface of the first dielectric material, a conductive layer over a second surface of the first dielectric material, and a second dielectric material over the conductive layer. The first and second dielectric materials have different dielectric constants. The conductive layer includes a ground plane over which the signal line is formed. A conductive material void, with which a section of the bias line is aligned, is present in the second conductive layer. The RF circuit further includes a mounting area for an RF device. First ends of the signal line and the section of the bias line are located proximate to the mounting area to enable the signal line and the bias line to be electrically coupled with one or more leads of the RF device.
    Type: Grant
    Filed: June 22, 2015
    Date of Patent: January 16, 2018
    Assignee: NXP USA, INC.
    Inventors: Travis A. Barbieri, Basim H. Noori
  • Patent number: 9852958
    Abstract: A container for housing an electronic component includes: a container body including a bottom plate and a polygonal side wall surrounding a central region of the bottom plate, the container body housing an electronic component inside a cavity defined by the bottom plate and the polygonal side wall; and an input-output terminal that penetrates through the polygonal side wall and is attached to two sides of the polygonal side wall, wherein a first side of the polygonal side wall is adjacent to a second side of the polygonal side wall, wherein the input-output terminal includes an insulator and a conductor, and wherein the conductor penetrates through the insulator and provides electrical continuity between an interior portion of the polygonal side wall and an exterior portion of the polygonal side wall.
    Type: Grant
    Filed: February 8, 2017
    Date of Patent: December 26, 2017
    Assignee: KYOCERA CORPORATION
    Inventors: Hiroshi Shibayama, Shigenori Takaya
  • Patent number: 9848488
    Abstract: A circuit board and package assembly electrically connecting a die to a circuit board. The circuit board has signal paths terminating in a signal pad located on an insulating layer. The circuit board also includes a ground pad on the insulating layer that has a concave shaped side forming a recess, the with a signal pad at least partially within the recess. A package has package ground pads aligned with the circuit board ground pads and package signal pads aligned with circuit board signal pads. The package ground pads extend through the package to connect to package ground paths, which extend toward the die. The package signal pads extend through the package to connect to package signal paths and the package signal paths extend toward the die, maintaining a consistent distance from the package ground paths. Multiple-tier bond wires connect the package bond locations to the die bond pads.
    Type: Grant
    Filed: June 17, 2016
    Date of Patent: December 19, 2017
    Assignee: MACOM Technology Solutions Holdings, Inc.
    Inventor: Alfredo Moncayo
  • Patent number: 9831168
    Abstract: According to example configurations herein, an apparatus comprises a die and a host substrate. The die can include a first transistor and a second transistor. A surface of the die includes multiple conductive elements disposed thereon. The multiple conductive elements on the surface are electrically coupled to respective nodes of the first transistor and the second transistor. Prior to assembly, the first transistor and second transistor are electrically isolated from each other. During assembly, the surface of the die including the respective conductive elements is mounted on a facing of the host substrate. Accordingly, a die including multiple independent transistors can be flipped and mounted to a respective host substrate such as printed circuit board, lead frame, etc.
    Type: Grant
    Filed: May 27, 2015
    Date of Patent: November 28, 2017
    Assignee: Infineon Technologies Americas Corp.
    Inventor: Robert T. Carroll
  • Patent number: 9768110
    Abstract: A method for fabricating an interconnect function array includes forming a first plurality of conductive lines on a substrate, forming an insulator layer over the first plurality of conductive lines and the substrate, removing portions of the insulator layer to define cavities in the insulator layer that expose portions of the substrate and the first plurality of conductive lines, wherein the removal of the portions of the insulator layer results in a substantially random arrangement of cavities exposing portions of the substrate and the first plurality of conductive lines, depositing a conductive material in the cavities, and forming a second plurality of conductive lines on portions of the conductive material in the cavities and the insulator layer.
    Type: Grant
    Filed: March 4, 2016
    Date of Patent: September 19, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kai D. Feng, Wai-Kin Li, Ping-Chuan Wang, Zhijian Yang
  • Patent number: 9721909
    Abstract: A radio frequency (RF) integrated circuit includes a first layer of semiconductor material in which a high electron mobility transfer (HEMT) device is formed. A semiconductor heat spreader substrate supports the first layer of semiconductor material. A pair of matching circuits are electrically connected to the HEMT device, wherein the pair of matching circuits are supported on a semiconductor substrate of a semiconductor material different than the semiconductor material of the first semiconductor heat spreader substrate. The first layer of semiconductor material and the first semiconductor heat spreader substrate have a thickness that is less than a second thickness of the semiconductor substrate supporting the pair of matching circuits.
    Type: Grant
    Filed: February 1, 2016
    Date of Patent: August 1, 2017
    Assignee: LOCKHEED MARTIN CORPORATION
    Inventor: Mahesh Kumar
  • Patent number: 9716049
    Abstract: A semiconductor device includes: a substrate; a semiconductor element disposed on the substrate; a plurality of electrodes disposed on the substrate separately from one another and arranged so as to surround the semiconductor element in a plan view; a lid that cover the semiconductor element, the lid including an inner portion and a periphery portion that is outer than the inner portion in a plan view, the lid including a plurality of first protruding members that is provided separately from one another, the first protruding members being disposed in the inner portion; and conductive members disposed between the plurality of electrodes and the plurality of protruding members disposed in positions opposed to the plurality of electrodes respectively, the conductive members being joined to the plurality of electrodes and the plurality of protruding members respectively.
    Type: Grant
    Filed: July 30, 2015
    Date of Patent: July 25, 2017
    Assignee: SOCIONEXT INC.
    Inventors: Kazuyuki Urago, Nobutaka Shimizu
  • Patent number: 9705173
    Abstract: A waveguide structure includes a signal line and two static lines. The signal line is disposed between the static lines in a first direction. The static lines and the signal line are disposed parallel to one another. Each static line includes a first conductive pattern, a second conductive pattern, and a third conductive pattern. The first conductive pattern and the signal line are disposed on an identical plane of a dielectric layer. A thickness of the first conductive pattern is substantially equal to a thickness of the signal line. The second conductive pattern is disposed on the first conductive pattern. A width of the first conductive pattern is larger than a width of the second conductive pattern in the first direction. The third conductive pattern is disposed on the second conductive pattern. A width of the third conductive pattern is larger than the width of the second conductive pattern.
    Type: Grant
    Filed: January 22, 2015
    Date of Patent: July 11, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Tzung-Lin Li, Chien-Yi Lee, Chieh-Pin Chang
  • Patent number: 9673134
    Abstract: A common mode filter coupled to a protection device. In accordance with an embodiment, the common mode filter has first and second coils, each coil having a spiral shape, a central region, an exterior region, a first terminal, and a second terminal, wherein the first terminal of the first coil is formed in a first portion of the central region, the first terminal of the second coil is formed in a second portion of the central region, and wherein the central region is laterally bounded by the first and second coils and the exterior region is not surrounded by the first and second coils. The protection device has a first terminal coupled to the first terminal of the first coil and a second terminal coupled to the first terminal of the second coil.
    Type: Grant
    Filed: December 11, 2013
    Date of Patent: June 6, 2017
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Rong Liu, Umesh Sharma, Phillip Holland
  • Patent number: 9669480
    Abstract: The invention relates to a semiconductor component with a chip, especially with a high-frequency switching circuit. The semiconductor component further comprises a metal body on the chip and a supplementary circuit board. The supplementary circuit board is provided on an underside facing away from the metal body for connection with a printed-circuit board by means of reflow soldering.
    Type: Grant
    Filed: December 19, 2014
    Date of Patent: June 6, 2017
    Assignee: Rohde & Schwarz GmbH & Co. KG
    Inventors: Daniel Hageneder, Martin Kappels
  • Patent number: 9666553
    Abstract: A millimeter wave integrated circuit (IC) chip. The IC chip comprises an IC die and a wire bond ball grid array package encapsulating the IC die. The wire bond ball grid array package comprises a solder ball array, a millimeter wave transmit channel, and a millimeter wave receive channel, wherein each millimeter wave transmit and receive channel electrically couples the IC die to a signal ball of the solder ball array and is configured to resonate at an operating frequency band of the millimeter wave IC chip.
    Type: Grant
    Filed: June 15, 2015
    Date of Patent: May 30, 2017
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Rajen Manicon Murugan, Minhong Mi, Gary Paul Morrison, Jie Chen, Kenneth Robert Rhyner, Stanley Craig Beddingfield, Chittranjan Mohan Gupta, Django Earl Trombley
  • Patent number: 9640857
    Abstract: A communication module includes a circuit board having electronic components thereon, an insulative molded member encapsulating the electronic components on the circuit board, and an antenna unit on the molded member. The circuit board is electrically connected to the antenna unit through a post terminal. The antenna unit and the molded member define a cavity therebetween.
    Type: Grant
    Filed: November 23, 2015
    Date of Patent: May 2, 2017
    Assignee: ALPS ELECTRIC CO., LTD.
    Inventors: Masashi Nakagawa, Kazuya Ishikawa, Yoshihisa Shibuya
  • Patent number: 9601439
    Abstract: A semiconductor structure includes a substrate, a die disposed over the substrate, and including a die pad disposed over the die and a seal ring disposed at a periphery of the die and electrically connected with the die pad, a polymeric layer disposed over the die, a via extending through the polymeric layer and electrically connected with the die pad, and a molding disposed over the substrate and surrounding the die and the polymeric layer, wherein the seal ring is configured for grounding.
    Type: Grant
    Filed: August 31, 2015
    Date of Patent: March 21, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Tzu-Chun Tang, Shou Zen Chang, Wei-Ting Chen, In-Tsang Lin, Vincent Chen, Chuei-Tang Wang, Kai-Chiang Wu, Chun-Lin Lu