Abstract: A stable electrical component includes a carrier substrate and a chip (2) mounted thereon. The component has a reactance element and a supporting element, which are at least partly arranged between the carrier substrate and the chip. The reactance element is at least partly realized by means of at least one conductor track. The reactance element includes a coil, a capacitor or a transmission line.

Abstract: A mmWave electronics package constructed from common Printed Circuit Board (PCB) technology and a metal cover. Assembly of the package uses standard pick and place technology and heat is dissipated directly to a pad on the package. Input/output of mmWave signal(s) is achieved through a rectangular waveguide. Mounting of the electronic package to an electrical printed circuit board (PCB) is performed using conventional reflow soldering processes and includes a waveguide I/O connected to an mmWave antenna. The electronic package provides for transmission of low frequency, dc and ground signals from the semiconductor chip inside the package to the PCB it is mounted on. An impedance matching scheme matches the chip to high frequency board transition by altering the ground plane within the chip. A ground plane on the high frequency board encircles the high frequency signal bump to confine the electromagnetic fields to the bump region reducing radiation loss.

Abstract: A mmWave electronics package constructed from common Printed Circuit Board (PCB) technology and a metal cover. Assembly of the package uses standard pick and place technology and heat is dissipated directly to a pad on the package. Input/output of mmWave signal(s) is achieved through a rectangular waveguide. Mounting of the electronic package to an electrical printed circuit board (PCB) is performed using conventional reflow soldering processes and includes a waveguide I/O connected to an mmWave antenna. The electronic package provides for transmission of low frequency, dc and ground signals from the semiconductor chip inside the package to the PCB it is mounted on. An impedance matching scheme matches the chip to high frequency board transition by altering the ground plane within the chip. A ground plane on the high frequency board encircles the high frequency signal bump to confine the electromagnetic fields to the bump region reducing radiation loss.

Abstract: A transmission line structure for semiconductor RF and wireless circuits, and method for forming the same. The transmission line structure includes embodiments having a first die including a first substrate, a first insulating layer, and a ground plane, and a second die including a second substrate, a second insulating layer, and a signal transmission line. The second die may be positioned above and spaced apart from the first die. An underfill is disposed between the ground plane of the first die and the signal transmission line of the second die. Collectively, the ground plane and transmission line of the first and second die and underfill forms a compact transmission line structure. In some embodiments, the transmission line structure may be used for microwave applications.

Abstract: Disclosed are systems, devices and methods for utilizing an interconnect conductor to inhibit or reduce the likelihood of de-lamination of a passivation layer of an integrated circuit die. In some implementations, a metal layer in ohmic contact with an intrinsic region of a semiconductor substrate can be partially covered by a passivation layer such as a dielectric layer. An interconnect conductor electrically connected to the metal layer can include an extension that covers an edge of the passivation layer to thereby inhibit the edge from lifting up. In some implementations, the metal layer in combination with a contact pad also in ohmic contact with the intrinsic region can yield a conduction path through the intrinsic region during an electrostatic discharge (ESD) event. In such a configuration, the interconnect conductor can route the ESD charge to a ground.

Abstract: A ground layer of a multilayer wiring board includes: a first clearance through which a first differential via is inserted without coming into contact with the ground layer; and a second clearance through which a second differential via is inserted without coming into contact with the ground layer. A distance between an outer edge of the first clearance on the side of the second differential via and the first differential via is set shorter than a distance between an outer edge of the first clearance on the side opposite from the second differential via and the first differential via. A distance between an outer edge of the second clearance on the side of the first differential via and the second differential via is set shorter than a distance between an outer edge of the second clearance on the side opposite from the first differential via and the second differential via.

Abstract: A semiconductor device (1) includes a wiring (10) and dummy conductor patterns (20). The wiring (10) is a wiring through which a current with a frequency of 5 GHz or higher flows. Near the wiring (10), the dummy conductor patterns (20) are formed. A planar shape of each of the dummy conductor patterns (20) is equivalent to a shape with an internal angle larger than 180°.

Abstract: Examples of high-speed ball grid array packages and a process of forming a package are provided. A package may include contact pads disposed on a bottom surface, conductive balls, and a signal via structure. The package may also include a first ground via structure arranged along one or more first semi-circular contours around the signal via structure and extending vertically and a second ground via structure arranged along one or more second semi-circular contours around the signal via structure and extending vertically. The package may include a ground interface plane disposed in separation from the signal contact pad by a distance. The distance may be determined based on at least a size of the signal contact pad, a dielectric constant of a transition layer between the ground interface plane and the signal contact pad, and a distance between the signal via structure and the second ground via structure.

Abstract: A high frequency circuit includes a first electronic device, a second electronic device, and a graphene interconnection unit, where at least one of a trench and a via is defined under the graphene interconnection unit.

Abstract: Transmission lines employing transmission line units or elements within integrated circuits (ICs) are well-known. Typically, different heights for these transmission line units can vary the characteristics of the cell (and transmission line), and there is typically a tradeoff between impedance and space (layout) specifications. Here, a transmission line is provided, which is generally comprised of elements of the same general width, but having differing or tapered heights that allow for impedance adjustments for high frequency applications (i.e., 160 GHz). For example, a transmission line that is coupled to a balun, with the transmission line units decreasing in height near the balun's center tap to adjust the impedance of the transmission line for the balun, is shown.

Abstract: A method for forming a semiconductor structure includes forming an isolation region in a semiconductor substrate; forming a conductive layer over the isolation region; forming a first dielectric layer over the conductive layer; forming a plurality of conductive vias extending through the first dielectric layer to the conductive layer and electrically contacting the conductive layer; forming a second dielectric layer over the first dielectric layer; and forming a conductive ground plane in the second dielectric layer. Each of the plurality of conductive vias is in electrical contact with the conductive ground plane, and the conductive ground plane includes an opening, wherein the opening is located directly over the conductive layer. At least one interconnect layer may be formed over the second dielectric layer and may include a transmission line which transmits a signal having a frequency of at least 30 gigahertz.

Abstract: In wireless communication devices, internally matching impedance in millimeter wave packaging enables better signal retention at high frequencies in the range of 15 GHz and above. Through the use of differential wire bond signal transmission, the inherent inductance of a millimeter wave package can be matched by the capacitance of the package wire bonds if the capacitance is tailored. The capacitance can be tailored by calculating a suitable distance between wire bonds and tuning the dielectric constant of the over-mold material. A differential set of wire bonds act like a differential transmission line whose characteristic impedance can be tuned by configuring the dielectric constant of the over-mold of the millimeter wave package.

Abstract: A printed circuit board and an electronic product are disclosed. In accordance with an embodiment of the present invention, the printed circuit board includes a first board, which has an electronic component mounted thereon, and a second board, which is positioned on an upper side of the first board and covers at least a portion of an upper surface of the first board and in which an EBG structure is inserted into the second board such that a noise radiating upwards from the first board is shielded. Thus, the printed circuit board can readily absorb various frequencies, be easily applied without any antenna effect and be cost-effective in manufacturing.

Abstract: A semiconductor device (1) includes a wiring (10) and dummy conductor patterns (20). The wiring (10) is a wiring through which a current with a frequency of 5 GHz or higher flows. Near the wiring (10), the dummy conductor patterns (20) are formed. A planar shape of each of the dummy conductor patterns (20) is equivalent to a shape with an internal angle larger than 180°.

Abstract: A security chip is disclosed. The security chip includes: a substrate; an integrated circuit disposed on the substrate, the integrated circuit including circuit elements, circuit interconnect layers connecting the circuit elements together, and interlayer contacts supporting the circuit interconnect layers; a shield to at least partially shield the integrated circuit; and at least one lightwell in the shield and the integrated circuit, wherein each lightwell has a closed shape formed from parts of the circuit interconnect layers and interlayer contacts, wherein no exploitable voltage can be measured on the parts of the circuit interconnect layers and interlayer contacts, and wherein each lightwell forms a path for light to penetrate to the substrate preventing the light from reaching the circuit elements. Related apparatus and methods are also disclosed.

Abstract: A multi-phase voltage regulator is disclosed where each phase is comprised of an array of high and low side transistors that are integrated onto a single substrate. Further, a system of mounting the voltage regulator onto a flip chip and lead frame is disclosed wherein the source and drain lines form an interdigital pattern.

Abstract: Described herein are wafer-level semiconductor device packages with EMI shielding and related methods. In one embodiment, a semiconductor device package includes: (1) a semiconductor device; (2) a package body covering lateral surfaces of the semiconductor device, a lower surface of the package body and a lower surface of the semiconductor device defining a front surface; (3) a set of redistribution layers disposed adjacent to the front surface, the set of redistribution layers including a grounding element that includes a connection surface electrically exposed adjacent to at least one lateral surface of the set of redistribution layers; and (4) an EMI shield disposed adjacent to the package body and electrically connected to the connection surface of the grounding element. The grounding element provides an electrical pathway to ground electromagnetic emissions incident upon the EMI shield.

Abstract: Antenna switch modules and methods of making the same are provided. In certain implementations, an antenna switch module includes a package substrate, an integrated filter, and a silicon on insulator (SOI) die attached to the package substrate. The SOI die includes a capacitor configured to operate in the integrated filter and a multi throw switch for selecting amongst the RF signal paths. In some implementations, a surface mount inductor is attached to the package substrate adjacent the SOI die and is configured to operate in the integrated filter with the capacitor. In certain implementations, the inductor is formed from a conductive layer of the package substrate disposed beneath a layer of the package substrate used to attach the SOI die.

Abstract: Described herein are semiconductor device packages with EMI shielding and related methods. In one embodiment, a semiconductor device package includes a circuit substrate, an electronic device, an encapsulant, and a conductive coating. The circuit substrate includes a carrying surface, a bottom surface, a lateral surface extending between the carrying surface and the bottom surface, a conductive layer, and a grounding ring. The grounding ring is in a substantially continuous pattern extending along a border of the circuit substrate, is exposed at a lateral surface of the circuit substrate, and is included in the conductive layer. The electronic device is disposed adjacent to the carrying surface and is electrically connected to the conductive layer of the circuit substrate. The encapsulant is disposed adjacent to the carrying surface and encapsulates the electronic device. The conductive coating is applied to the encapsulant and the grounding ring.

Abstract: An object of the present invention is providing a semiconductor device that is capable of improving the reliability of a semiconductor element and enhancing the mechanical strength without suppressing the scale of a circuit. The semiconductor device includes an integrated circuit sandwiched between first and second sealing films, an antenna electrically connected to the integrated circuit, the first sealing film sandwiched between a substrate and the integrated circuit, which includes a plurality of first insulating films and at least one second insulating film sandwiched therebetween, the second sealing film including a plurality of third insulating films and at least one fourth insulating film sandwiched therebetween. The second insulating film has lower stress than the first insulting film and the fourth insulating film has lower stress than the third insulating film. The first and third insulating films are inorganic insulating films.

Abstract: Manufacturing circuits with reference plane voids over vias with a strip segment interconnect permits routing critical signal paths over vias, while increasing via insertion capacitance only slightly. The transmission line reference plane defines voids above (or below) signal-bearing plated-through holes (PTHs) that pass through a rigid substrate core, so that the signals are not degraded by an impedance mismatch that would otherwise be caused by shunt capacitance from the top (or bottom) of the signal-bearing PTHs to the transmission line reference plane. In order to provide increased routing density, signal paths are routed over the voids, but disruption of the signal paths by the voids is prevented by including a conductive strip through the voids that reduces the coupling to the signal-bearing PTHs and maintains the impedance of the signal path conductor.

Abstract: A chip layout isolates Rx terminals and Rx ports from Tx terminals and Tx ports. Tx terminals are grouped contiguously to each other, and are segregated as a group to a given edge of the package, Rx terminals are similarly grouped and segregated to a different edge of the package. Tx and Rx data channels are disposed in a respective single layer of the package, or both are disposed in a same single layer of the package. Rx ports and Tx ports are located at an approximate center of the package, with Tx and Rx ports disposed on respective opposite sides of an axis bisecting the package. Data signals received by, and transmitted from, the chip flow in a same direction, from a first edge of the package to the center of the package and from the center of the package to a second edge of the package, respectively.

Abstract: A miniature component includes an MMIC microwave chip encapsulated in an individual package for surface-mounting capable of operating at a frequency F0 very much higher than 45 GHz; and at least one contactless microwave port, by electromagnetic coupling, ensuring the transmission of coupling signals at a working frequency F0.

Abstract: An integrated circuit structure includes an interconnect structure over a semiconductor substrate and a coaxial transmission line. The coaxial transmission line includes a signal line, a top plate over the signal line and electrically insulated from the signal line, and a bottom plate under the signal line and electrically insulated from the signal line. At least one of the top plate and the bottom plate includes metal strip shields and dielectric strips, with each of the dielectric strips being between two of the metal strip shields. The integrated circuit structure further includes a ground conductor electrically connecting the top plate and the bottom plate. The ground conductor is insulated from the signal line by a dielectric material.

Abstract: The present invention provides an antenna in that the adhesive intensity of a conductive body formed on a base film is increased, and a semiconductor device including the antenna. The invention further provides a semiconductor device with high reliability that is formed by attaching an element formation layer and an antenna, wherein the element formation layer is not damaged due to a structure of the antenna. The semiconductor device includes the element formation layer provided over a substrate and the antenna provided over the element formation layer. The element formation layer and the antenna are electrically connected. The antenna has a base film and a conductive body, wherein at least a part of the conductive body is embedded in the base film. As a method for embedding the conductive body in the base film, a depression is formed in the base film and the conductive body is formed therein.

Abstract: An integrated circuit structure includes a semiconductor substrate; an interconnect structure over the semiconductor substrate; a first dielectric layer over the semiconductor substrate and in the interconnect structure; a second dielectric layer in the interconnect structure and over the first dielectric layer; and a wave-guide. The wave-guide includes a first portion in the first dielectric layer and a second portion in the second dielectric layer. The first portion adjoins the second portion.

Abstract: To reduce the radio frequency (RF) losses associated with high RF loss plating, such as, for example, Nickel/Palladium/Gold (Ni/Pd/Au) plating, an on-die passive device, such as a capacitor, resistor, or inductor, associated with a radio frequency integrated circuit (RFIC) is placed in an RF upper signal path with respect to the RF signal output of the RFIC. By placing the on-die passive device in the RF upper signal path, the RF current does not directly pass through the high RF loss plating material of the passive device bonding pad.

Abstract: According to an embodiment of a method of manufacturing a power transistor module, the method includes mechanically fastening a first terminal, a second terminal and at least two different DC bias terminals to an electrically conductive flange; connecting the flange to a source of a power transistor device; electrically connecting the first terminal to a gate of the power transistor device; electrically connecting the second terminal to a drain of the power transistor device; mechanically fastening a bus bar to the flange which extends between and connects the DC bias terminals; and electrically connecting the bus bar to the drain via one or more RF grounded connections.

Abstract: An integrated circuit arrangement includes a substrate with a multiplicity of integrated semiconductor components arranged therein, the substrate having a wiring interconnect near to the substrate, a middle wiring interconnect and a wiring interconnect remote from the substrate, which are arranged in this order at increasing distance from the substrate.

Abstract: A high frequency flip chip package substrate of a polymer is a one-layer structure packaged by a high frequency flip chip package process to overcome the shortcomings of a conventional two-layer structure packaged by the high frequency flip chip package process. The conventional structure not only incurs additional insertion loss and return loss in its high frequency characteristic, but also brings out a reliability issue. Thus, the manufacturing process of a ceramic substrate in the conventional structure still has the disadvantages of a poor yield rate and a high cost.

Abstract: One aspect of the present invention relates to an integrated circuit package that includes multiple layers of a planarizing, photo-imageable epoxy that are formed over a substrate. In some designs, the substrate is a silicon wafer. An integrated circuit is embedded in the epoxy. An antenna, which is electrically coupled to the active face of the integrated circuit through an interconnect layer, is formed over one of the epoxy layers. In various embodiments, at least some of the epoxy layers are positioned between the substrate and the antenna such that there is a distance of at least approximately 100 microns between the substrate and the antenna.

Abstract: A printed circuit board (“PCB”) includes a first pattern structure, a second pattern structure, a third pattern structure, and a fourth pattern structure. The first pattern structure includes a first ground pattern. The second pattern structure includes a first line pattern overlapping the first ground pattern and a second ground pattern electrically insulated from the first line pattern. The third pattern structure includes a third ground pattern overlapping the first line pattern and a second line pattern overlapping the second ground pattern. The fourth pattern structure includes a fourth ground pattern overlapping the second line pattern. Therefore, the PCB may decrease noise.

Abstract: A transmission line includes two tapered lines having a tapered planar shape and arranged in parallel, opposite lines provided in opposition to the narrower width sides of the two tapered lines, and a bonding wire for connecting the narrower width sides of the two tapered lines and the opposite lines, wherein the width between two outer edges on the narrower width sides of the two tapered lines arranged in parallel is greater than the width between outer edges on the opposite side of the opposite lines in opposition to the narrower width sides of the two tapered lines.

Abstract: The present invention provides a thin semiconductor device in which its security such as prevention of counterfeit or information leakage is to be enhanced. One feature of the present invention is a thin semiconductor device in which a plurality of thin film integrated circuits are mounted and in which at least one integrated circuit is different from the other integrated circuits in any one of a specification, layout, frequency for transmission or reception, a memory, a communication means, a communication rule and the like. According to the present invention, a thin semiconductor device tag having the plurality of thin film integrated circuits communicates with a reader/writer and at least one of the thin film integrated circuits receives a signal to write information in a memory, and the information written in the memory determines which of the thin film integrated circuits communicates.

Abstract: An integrated circuit includes a conductive pad and a substrate. The conductive pad is used to transfer a first signal. The substrate blocks a second signal from a first region of the substrate to the conductive pad. A second region of the substrate insulates a third region of the substrate from the first region. The first and third regions include a first type of semiconductor and the second region includes a second type of semiconductor. In addition, a first shadow obtained by perpendicularly projecting the third region onto a surface of the substrate overlaps with a second shadow obtained by perpendicularly projecting the conductive pad onto the surface.

Abstract: A semiconductor device comprising a signal transmission line of a microstrip structure, capable of increasing the characteristic impedance of the signal transmission line and reducing coupling between a plurality of signal lines. In a signal transmission line of a microstrip structure composed of a signal line and a ground plate, the capacitance between wires is reduced and the characteristic impedance can be increased by forming holes in the signal line or in the ground plate. The coupling between a plurality of signal lines can also be reduced.

Abstract: A higher aspect ratio for upper level metal interconnects is described for use in higher frequency circuits. Because the skin effect reduces the effective cross-sectional area of conductors at higher frequencies, various approaches are described to reduce the effective RC delay in interconnects.

Abstract: A strip-line includes a ground plane extending through a plurality of dielectric layers over a substrate; a signal line over the substrate and on a side of the ground plane; a first plurality of metal strips under the signal line and in a first metal layer, wherein the first plurality of metal strips is parallel to each other, and is spaced apart from each other by spaces; and a second plurality of metal strips under the signal line and in a second metal layer over the first metal layer. The second plurality of metal strips vertically overlaps the spaces. The first plurality of metal strips is electrically coupled to the second plurality of metal strips through the ground plane, and no via physically contacts the first plurality of metal strips and the second plurality of metal strips.

Abstract: A vertical transmission structure for high frequency transmission lines includes a conductive axial core and a conductive structure surrounding the conductive axial core. The vertical transmission structure is applied to a high-frequency flip chip package for reducing the possibility of underfill from coming in contact with the conductive axial core.

Abstract: A coplanar waveguide includes a signal line formed on a major surface of a high-resistivity silicon substrate, a pair of ground conductors placed on opposite sides of the signal line, and a pair of trenches formed in the substrate between the signal line and the ground conductors. Because of the trenches, the attenuation characteristics of the coplanar waveguide are highly uniform, and are comparable to the attenuation characteristics of coplanar waveguides formed on compound semiconductor substrates.

Abstract: The present invention relates to a transition from a chip to a waveguide port (47, 47?, 11), the chip (1, 1?, 62) having a first main side (3, 3?, 66) and a second main side (4, 4?, 67), where the first main side (3, 3?, 66) comprises at least one input port (35, 36, 37, 38, 39), arranged to receive an input signal, at least one output port (44, 45; 72), arranged to output an output signal, and at least one electrical functionality. One port (44, 72) of said ports (44, 45; 72; 35, 36, 37, 38, 39) is electrically connected to an electrically conducting probe (48, 48?, 73) that is arranged to extend from said one port (44, 72) and at least partly over the waveguide port (47, 47?, 77) such that a signal may be transferred between said one port (44, 72) and the waveguide port (47, 47?, 77). The present invention also relates to a corresponding package.

Abstract: A radio-frequency package includes a radio-frequency device, a multilayer dielectric substrate, and an electromagnetic shield member. The multilayer dielectric substrate includes an internal conductor pad, a first signal via-hole connected to the internal conductor pad, an external conductor pad, a second signal via-hole connected to the external conductor pad, and an inner-layer signal line that connects between the first signal via-hole and the second signal via-hole. The internal conductor pad includes a leading-end open line having a length of substantially a quarter of a wavelength of a radio-frequency signal used in the radio-frequency device.

Abstract: A semiconductor device having a GaAsFET and input and output matching circuits connected to the FET is provided. In the semiconductor device, a line, including a wire connection portion connected to the input or output matching circuit and a lead connection portion connected to an input or output lead which is connected to an external circuit, is formed in such a manner that a line width at the wire connection portion is wider than that at the lead connection portion. With the semiconductor device, the number of wires connecting the input or output matching circuits with the wire connection portion can be increased.

Abstract: A semiconductor device and manufacturing method. One embodiment provides a device including a semiconductor chip. A first conductor line is placed over the semiconductor chip. An external contact pad is placed over the first conductor line. At least a portion of the first conductor line lies within a projection of the external contact pad on the semiconductor chip.

Abstract: In the present invention, a first circuit pattern 3 composing a semiconductor element is formed on the front side of a substrate 1, a first insulating layer 2 is formed on the first circuit pattern 3, solder electrodes 5 for external connection are formed on the first insulating layer 2, a second insulating layer 6 is formed on the backside of the substrate 1, a second circuit pattern 7 is formed on the second insulating layer 6, through vias 8 are formed to connect the first circuit pattern 3 and the second circuit pattern 7, chip passive components 9 are placed on the second circuit pattern 7, and the backside of the substrate is integrally molded with epoxy resin 10 such that the epoxy resin 10 covers the chip passive components 9.

Abstract: An integrated circuit structure includes a semiconductor substrate; an interconnect structure over the semiconductor substrate; a first dielectric layer over the semiconductor substrate and in the interconnect structure; a second dielectric layer in the interconnect structure and over the first dielectric layer; and a wave-guide. The wave-guide includes a first portion in the first dielectric layer and a second portion in the second dielectric layer. The first portion adjoins the second portion.

Abstract: A wiring board equipped with differential lines which compensate for differences in via lengths to minimize signal deterioration is disclosed. Two conductors are couple to different substrate levels through vias of different lengths. Compensation means are provided to correct for the phase difference caused by the different lengths.

Abstract: A method for forming a semiconductor structure includes forming an isolation region in a semiconductor substrate; forming a conductive layer over the isolation region; forming a first dielectric layer over the conductive layer; forming a plurality of conductive vias extending through the first dielectric layer to the conductive layer and electrically contacting the conductive layer; forming a second dielectric layer over the first dielectric layer; and forming a conductive ground plane in the second dielectric layer. Each of the plurality of conductive vias is in electrical contact with the conductive ground plane, and the conductive ground plane includes an opening, wherein the opening is located directly over the conductive layer. At least one interconnect layer may be formed over the second dielectric layer and may include a transmission line which transmits a signal having a frequency of at least 30 gigahertz.

Abstract: A microwave circuit package having a ball grid array, BGA, soldered on to a planar major surface of a metal housing of the package for the electrical connection of the ports of the microwave circuit through RF signal paths to an adjacent electrical device. Each of the RF signal paths comprises a pin electrically connected to a respective port of the microwave circuit package, projecting normally through an opening in the said major surface from which it is electrically insulated, and soldered to a ball of the BGA; the pin and the surrounding balls of the BGA, which are soldered to the metal housing, constituting a coaxial RF signal path.

Abstract: A multi-chip device which includes a plurality of integrated circuit die disposed one over another. Each integrated circuit die includes one or a plurality of bond pads. One or a plurality of conductors are disposed to electrically couple the bond pads of vertically adjacent integrated circuit die. Each conductor is designed, calculated, specified and/or predetermined to have a length so as to behave as a segment in a multi-drop transmission line. The multi-drop transmission line may be terminated at one end or utilized in a flow-through approach. In one embodiment, an integrated circuit die may be horizontally offset with respect to a vertically adjacent integrated circuit die to expose the periphery region. In another embodiment, each integrated circuit die may be stacked and aligned in a vertical column. In this embodiment, a spacer such as a thermally conductive spacer is disposed between each integrated circuit die in the stack.