Abstract: A semiconductor package for power transistors and the like has a heat sink flange with at least one die mounted thereon, a non-ceramic based window frame mounted thereon adjacent the die, and a plurality of leads mounted on the window frame and electrically coupled to the die by wire bonds. The non-ceramic based window frame is thermally matched to copper or other highly conductive material typically used for the flange, to facilitate assembly of the semiconductor package at high temperatures. The non-ceramic based window frame is flexible and is thermally matched to the highly conductive flange so as to expand and contract at a rate similar to the flange to prevent failure during assembly of the semiconductor package. The non-ceramic based material of the window frame includes a matrix of principally organic material, such as polytetrafluorethylene, filled with fibers which may be glass fibers or ceramic fibers.

Abstract: In wireless communication devices, internally matching impedance in millimeter wave packaging enables better signal retention at high frequencies in the range of 15 GHz and above. Through the use of differential wire bond signal transmission, the inherent inductance of a millimeter wave package can be matched by the capacitance of the package wire bonds if the capacitance is tailored. The capacitance can be tailored by calculating a suitable distance between wire bonds and tuning the dielectric constant of the over-mold material. A differential set of wire bonds act like a differential transmission line whose characteristic impedance can be tuned by configuring the dielectric constant of the over-mold of the millimeter wave package.

Abstract: Microelectronic assemblies interconnected using a separable network interface and electronic systems using the microelectronic assemblies to physically separate high performance signals and lower performance signals to enhance system performance are disclosed.

Abstract: An RF power circuit comprises a power transistor having a gate and drain, an output matching network coupled to the drain and an input matching network coupled to the gate. A closed-loop bias circuit is integrated with the power transistor on the same die and coupled to the gate for biasing the RF power transistor based on a reference voltage applied to the bias circuit.

Abstract: An explanation is given of an integrated interconnect arrangement having a plurality of interconnects that cross over one another at two crossover sections. By virtue of this measure, it is possible to achieve a uniform current flow in all three interconnects even at very high frequencies.

Abstract: An integrated circuit package having a multi-segment transmission line transformer for impedance matching a packaged integrated circuit, such as a driver or receiver, to a printed circuit board (PCB) transmission line to which the packaged chip is attached by, for example, solder balls. In one exemplary embodiment, a three-segment transmission line transformer provides improved broadband performance with the advantage of having a middle segment with a flexible length for easier routing. The length of each end segment of the three-segment transformer is adjusted to provide at least partial cancellation of reflections between the PCB and the transformer, and between the transformer and a circuit on the integrated circuit, respectively. Further, the inductive reactance of the solder balls and via wiring may be cancelled out by the transformed chip impedance to provide a non-inductive termination to the PCB transmission line at approximately one-half the highest data rate of the channel.

Abstract: An AC voltage signal is transmitted between a semiconductor substrate and a further semiconductor substrate arranged on the first semiconductor substrate by means of an electromagnetic field through one of the two semiconductor substrates by virtue of each semiconductor substrate having a circuit element that serves for transmission. Both circuit elements are directly electrically decoupled.

Abstract: An Al2O3 film for covering a ferroelectric capacitor is formed by a sputtering process. The thickness of the Al2O3 film is preferably optimized according to amount of remanent polarization and fatigue tolerance required for the ferroelectric capacitor, for example, 10 nm to 100 nm. Next, oxygen is supplied to a PZT film via the Al2O3 film by executing a heat treatment in an oxygen atmosphere. As a result, an oxygen deficit in the PZT film is made up for. At this time, evaporation of Pb in the PZT film is suppressed because of the Al2O3 film, and deterioration of the fatigue tolerance responsive to decrease of Pb amount is suppressed. Subsequently, another Al2O3 film is formed as a second protective film by the sputtering process for opposing the deterioration factor in later process. The thickness of the Al2O3 film is preferably the thickness which sufficiently protects the ferroelectric capacitor from the deterioration factor in later wiring process.

Abstract: A printed wiring board semiconductor package or PWB power core comprising singulated capacitors embedded on multiple layers of the printed wiring board semiconductor package wherein at least a part of each embedded capacitor lies within the die shadow and wherein the embedded, singulated capacitors comprise at least a first electrode and a second electrode. The first electrodes and second electrodes of the embedded singulated capacitors are interconnected to the Vcc (power) terminals and the Vss (ground) terminals respectively of a semiconductor device. The size of the embedded capacitors are varied to produce different self-resonant frequencies and their vertical placements within the PWB semiconductor package are used to control the inherent inductance of the capacitor-semiconductor electrical interconnections so that customized resonant frequencies of the embedded capacitors can be achieved with low impedance.

Abstract: A semiconductor package includes a base substrate on which semiconductor elements are disposed; a covering member which is provided to the base substrate, which covers the semiconductor elements, and which includes an opening at an end thereof at the side of the base substrate; and a connector substrate which is provided on the base substrate in a manner that the connector substrate closes the opening, which includes a first high-frequency signal line in an area located inside the covering member for a first surface, and which includes a second high-frequency signal line on a second surface being a surface on the opposite side of the first surface, the second high-frequency signal line being electrically connected to the first high-frequency signal line; wherein the base substrate is formed in a manner that the base substrate is located away from the second high-frequency signal line.

Abstract: A multi-layered integrated circuit chip package comprises a void layer that includes at least one void. The multi-layered integrated circuit chip package also includes an insulation layer that electrically insulates the void layer from a trace layer. At least one trace resides in the trace layer. The trace having a length in which a first section thereof is located an overlying relation to the at least one void, wherein the first section overlying the void has a width different from an adjacent section of the trace located on at least one opposing side of the void such that impedance mismatches and signal reflections along the trace are mitigated.

Abstract: A direct-connect signaling system including a printed circuit board and first and second integrated circuit packages disposed on the printed circuit board. A plurality of electric signal conductors extend between the first and second integrated circuit packages suspended above the printed circuit board.

Abstract: A microcircuit has a node thereon. A center conductor is electrically connected to the node and the center conductor has a length to minimum radius ratio of at least 50. A method of for providing electrical interconnections in a microcircuit, comprises the steps of depositing conductive bumps on the microcircuit; and aligning and bonding a center conductor to the conductive bumps, the center conductor having a first end and a second end, and the center conductor having a length to minimum radius ratio of at least 50.

Abstract: A semiconductor integrated circuit package, a printed circuit board, a semiconductor apparatus, and a power supply wiring structure that allow attainment of stable power source and ground wiring without causing resonance even in a high-frequency bandwidth are provided. In an interior portion of the package, a power source wiring and a ground wiring constitute a pair wiring structure in which the power source wiring and the ground wiring are juxtaposed at a predetermined interval so as to establish electromagnetic coupling therebetween. A plurality of pair wiring structures are combined in such a manner that, when viewed in a section perpendicular to a wiring extending direction, the pair wiring assembly assumes a staggered (checkered) configuration. It is preferable that, each of the silicon chip and the printed circuit board, like the package, has pair wiring structures disposed inside.

Abstract: A substrate including strip conductors with a wiring pattern that connects contact areas to one another. The strip conductors have a small strip conductor width. The contact areas and/or the strip conductors form a narrow connection pitch and include electrically conductive carbon nanotubes.

Abstract: A packaged semiconductor device includes an interconnect layer over a first side of a polymer layer, a semiconductor device surrounded on at least three sides by the polymer layer and coupled to the interconnect layer, a first conductive element over a second side of the polymer layer, wherein the second side is opposite the first side, and a connector block within the polymer layer. The connector block has at least one electrical path extending from a first surface of the connector block to a second surface of the connector block. The at least one electrical path electrically couples the interconnect layer to the first conductive element. A method of forming the packaged semiconductor device is also described.

Abstract: For a multi-terminal semiconductor package, such as a BGA or a CSP, that handles high-speed differential signals, a high-speed signal is assigned to the innermost located electrode pad on an interposer substrate, and the electrode pad is connected to the outermost located ball pad on the interposer substrate. With this arrangement, the length of a plating stub can be considerably reduced, and the adverse affect on a signal waveform can be minimized. This arrangement is especially effective for differential signal lines.

Abstract: The invention relates to an apparatus and method for improving AC coupling between adjacent signal traces and between plane splits and signals spanning plane splits on circuit boards. A circuit board includes adjacent conductive means and an oxide means interposed there between. The oxide means is a copper oxide, e.g., cupric or cuprous oxide. In one embodiment, the adjacent conductive means are adjacent voltage reference planes with a split interposed between the conductive means. The copper oxide fills the split. In another embodiment, the adjacent conductive means are differential signal traces. The copper oxide fills a gap between the differential signal traces. The copper oxide is a non-conductive material with an increased dielectric constant as compared to other common dielectric materials used as fillers. The increased dielectric constant increases capacitance, in turn, increasing AC coupling.

Abstract: A module for integrating peripheral circuit includes a silicon chip substrate, at least one peripheral circuit unit, and at least one main circuit unit. The peripheral circuit unit is integrated in the silicon chip substrate via a semiconductor manufacturing process. The main circuit unit is mounted on the surface of the silicon chip substrate and is electrically connected with the peripheral circuit unit for transmitting the signal. Thereby, the dimension of the module is reduced.

Abstract: Provided is a three-dimensional aluminum package module including: an aluminum substrate; an aluminum oxide layer formed on the aluminum substrate and having at least one first opening of which sidewalls are perpendicular to an upper surface of the aluminum substrate; a semiconductor device mounted in the first opening using an adhesive; an organic layer covering the aluminum oxide layer and the semiconductor device; and a first interconnection line and a passive device circuit formed on the organic layer and the aluminum oxide layer.

Abstract: A memory device is provided with a structure for improved transmission line operation on integrated circuits. The structure for transmission line operation includes a first layer of electrically conductive material on a substrate. A first layer of insulating material is formed on the first layer of the electrically conductive material. A number of high permeability metal lines are formed on the first layer of insulating material. The number of high permeability metal lines includes composite hexaferrite films. A number of transmission lines is formed on the first layer of insulating material and between and parallel with the number of high permeability metal lines. A second layer of insulating material is formed on the transmission lines and the high permeability metal lines. The structure for transmission line operation includes a second layer of electrically conductive material on the second layer of insulating material.

Abstract: An optical module comprises: a stem; a protruding portion on a surface of the stem; an optical semiconductor device mounted on the protruding portion; a power supply terminal penetrating through the stem, the power supply terminal being insulated from the stem; a first dielectric substrate mounted on the protruding portion; a first signal line on the first dielectric substrate and connected to a first end of the power supply terminal; a second dielectric substrate on a rear surface of the stem; and a second signal line on the second dielectric substrate and connected to a second end of the power supply terminal. The second signal line has an electrical length of 23.0-36.2 mm and an impedance of 21.5-24.5?.

Abstract: A method and apparatus for constructing, repairing and operating modular electronic systems utilizes peripheral half-capacitors (i.e., conductive plates on the outside of the modules) to communicate non-conductively between abutting modules. Such systems provide lower cost, improved testability/reparability and greater density than conventional modular packaging techniques, such as printed circuit boards and multi-chip modules. The non-conductive interconnection technique of the invention can be applied to all levels in the packaging hierarchy, from bare semiconductor dies to complete functional sub-units.

Abstract: A semiconductor device with micro connecting elements and method for producing the same disclosed. In one embodiment, the semiconductor device includes a number of micro connecting elements for the high-frequency coupling of components of the semiconductor device. The micro connecting elements have an at least three-layered structural form with a first layer of conducting material, a second layer of insulating material and a third layer of conducting material. In this configuration, the first and third layers and extend along a common center line and shield one another against electromagnetic interference fields. The first and third layers and are fixed on correspondingly adapted pairs of contact terminal areas of the components.

Abstract: A multi-layer heatsink module for effecting temperature control in a three-dimensional integrated chip is provided. The module includes a high thermal conductivity substrate having first and second opposing sides, and a gallium nitride (GaN) layer disposed on the first side of the substrate. An integrated array of passive and active elements defining electronic circuitry is formed in the GaN layer. A metal ground plane having first and second opposing sides is disposed on the second side of the substrate, with the first side of the ground plane being adjacent to the second side of the substrate. A dielectric layer of low thermal dielectric material is deposited on the back side of the ground plane, and a metal heatsink is bonded to the dielectric layer. A via extends through the dielectric layer from the metal heatsink to the metal ground plane.

Abstract: A semiconductor integrated circuit which is connected to a substrate by solder bumps wherein, when at least one solder bump is connected to a signal line of the semiconductor integrated circuit and the semiconductor integrated circuit is mounted on the substrate, the semiconductor integrated circuit is bonded to the substrate by the solder bump, and the interconnection to the substrate is made by dummy bumps forming wires at the substrate side.

Abstract: A multi-layer circuit substrate and method having improved transmission line integrity and increased routing density uses a selectively applied transmission line reference plane metal layer to achieve signal path shielding and isolation, while avoiding drops in impedance due to capacitance between large diameter vias and the transmission line reference plane metal layer. The transmission line reference plane defines voids above (or below) the signal-bearing plated-through holes (PTHs) that pass through a rigid substrate core, so that the signals are not degraded by an impedance mismatch that would otherwise be caused by shunt capacitance from the top (or bottom) of the signal-bearing PTHs to the transmission line reference plane. For voltage-plane bearing PTHs, no voids are introduced, so that signal path conductors can be routed above or adjacent to the voltage-plane bearing PTHs, with the transmission line reference plane preventing shunt capacitance between the signal path conductors and the PTHs.

Abstract: According to embodiments of the present invention, an optical transponder includes a transmitter optical subassembly (TOSA). In one embodiment, the electrical ground of the TOSA may be DC-isolated from chassis ground of the transponder using a blocking capacitor that couples the AC signal path to VDD and that allows the case of the TOSA to float. In an alternative embodiment, the electrical ground of the TOSA may be DC-isolated from chassis ground of the transponder using a blocking capacitor that couples the AC signal path to VDD and a resistor that couples the DC bias level path to internal electrical ground or transponder case ground.

Abstract: An integrated circuit includes N plane-like metal layers. A first plane-like metal layer includes M contact portions that communicate with the N plane-like metal layers, respectively. The first source region is arranged between first sides of the first and second drain regions and the second and third source regions are arranged adjacent to second sides of the first and second drain regions. A fourth source region is arranged adjacent to third sides of the first and second drain regions and a fifth source region is arranged adjacent to fourth sides of the first and second drain regions. First and second drain contacts are arranged in the first and second drain regions, respectively. At least two of the first, second, third, fourth and fifth source regions and the first and second drain regions communicate with at least two of the N plane-like metal layers.

Abstract: A method of manufacturing a coaxial trace (100) within a surrounding material (190) includes: providing a first substrate (191, 410) and a second substrate (192, 1010) composed of the surrounding material; forming a first portion (101, 601) of the coaxial trace in the first substrate; forming a second portion (102, 1001) of the coaxial trace in the second substrate; aligning the first portion of the coaxial trace with the second portion of the coaxial trace; and bonding the first portion of the coaxial trace to the second portion of the coaxial trace.

Abstract: A source mounted semiconductor device package is described which includes a semiconductor die having first and second opposing major surfaces, first and second major electrodes disposed on respective major surfaces and a control electrode disposed on the second major surface, and a thin metal clip electrically connected to the first major electrode of the die. The thin metal clip has a relatively large surface area, and package resistance which is caused by skin effect phenomenon is reduced thereby in high frequency applications.

Abstract: An integrated circuit includes N plane-like metal layers. A first plane-like metal layer includes M contact portions that communicate with the N plane-like metal layers, respectively. The first plane-like metal layer and the N plane-like metal layers are located separate planes. First and second drain regions have a symmetric shape across at least one of horizontal and vertical centerlines. First and second gate regions have a first shape that surrounds the first and second drain regions, respectively. First and second source regions are arranged adjacent to and on one side of the first gate region, the second gate region and the connecting region. The first source region, the second source region, the first drain region and the second drain region communicate with at least two of the N plane-like metal layers.

Abstract: A composite contact for a semiconductor device is provided. The composite contact includes a DC conducting electrode that is attached to a semiconductor layer in the device, and a capacitive electrode that is partially over the DC conducting electrode and extends beyond the DC conducting electrode. The composite contact provides a combined resistive-capacitive coupling to the semiconductor layer. As a result, a contact impedance is reduced when the corresponding semiconductor device is operated at high frequencies.

Abstract: A semiconductor package assembly and method for electrically isolating modules, having a capacitor within the semiconductor package assembly. The package assembly and method are suitable for electrically isolating modules according to IEEE 1394.

Abstract: An example of a circuit structure may include a first dielectric layer having first and second surfaces, and a channel extending at least partially between the first and second surfaces and along a length of the first dielectric layer. First and second conductive layers may be disposed on respective portions of the first and second surfaces. A first conductor, having an end, may be disposed on a surface of the first dielectric layer, including at least a first portion extending around at least a portion of the conductor end. The second conductive layer may line the channel extending around a portion of the conductor end. Some examples may include a stripline having a second conductor connected to the first conductor. Some examples may include a cover having a wall positioned on the first dielectric over the second conductor.

Abstract: A semiconductor device (1) includes a wiring (10) and dummy conductor patterns (20). The wiring (10) is a wiring through which a current with a frequency of 5 GHz or higher flows. Near the wiring (10), the dummy conductor patterns (20) are formed. A planar shape of each of the dummy conductor patterns (20) is equivalent to a shape with an internal angle larger than 180°.

Abstract: A semiconductor device may include a semiconductor chip including a signal terminating resistor coupled between a signal input pad and a first ground voltage pad, a semiconductor package including a signal input terminal and a first ground voltage terminal, the signal input terminal being electrically coupled to the signal input pad of the semiconductor chip and the first ground voltage terminal being electrically coupled to the first ground voltage pad of the semiconductor chip, a capacitor and a resistor that are coupled between the signal input terminal and the first ground voltage terminal, and a first inductor realized by coupling the signal input terminal and the signal input pad.

Abstract: A semiconductor device is mounted on a package substrate which has a power supply line and a signal line formed of a normal or predetermined resistance material layer on a dielectric layer. A resistance material layer has a high resistance as compared with the normal resistance material layer and is additionally provided on the surface of the normal resistance material layer of the peripheral face of the signal line closest to the power supply line.

Abstract: An integrated circuit comprises N plane-like metal layers, where N is an integer greater than one. A first plane-like metal layer includes M contact portions that communicate with the N plane-like metal layers, respectively, where M is an integer greater than one. The first plane-like metal layer and the N plane-like metal layers are located in separate planes. At least two of a first source, a first drain and a second source communicate with at least two of the N plane-like metal layers. A first gate is arranged between the first source and the first drain. A second gate is arranged between the first drain and the second source. The first and second gates define alternating first and second regions in the first drain, and wherein the first and second gates are arranged farther apart in the first regions than in the second regions.

Abstract: Provided are a semiconductor device with reduced power noise, which can be used in a high-speed device with an operating frequency of at or above about 1 GHz and does not have any spatial restriction due to signal patterns or other structures. The semiconductor device includes a power panel, an insulating layer, and a stub unit. The power panel has electrical devices formed thereon. The insulating layer covers the power panel. The stub unit is formed on the insulating layer and has one or more fan-shaped stubs electrically connected to the power panel through a via contact penetrating the insulating layer.

Abstract: Microwave generating and detection portions of a electronic circuit is improved in efficiency and reduced in size. A microwave generating element A comprises a lower electrode 1, a layer 3 formed on the lower electrode 1 in an island shape, forming a magnetoresistance element, an insulator 7 formed on the lower electrode 1 in such a manner as to surround the layer 3 forming the magnetoresistance element, and an upper electrode 5 formed on the insulator 7 and the layer 3 forming the magnetoresistance element. The layer 3 forming the magnetoresistance element includes, in order from the side of the lower electrode 1, a magnetization fixed layer 3a, an intermediate layer 3b, and a magnetization free layer 3c. The magnetization free layer 3c, which is required to produce resonance oscillation based on a current, preferably is dimensioned to be equal to or smaller than 200 nm square in a cross-sectional area and on the order of 1 to 5 nm in film thickness, for example.

Abstract: A high frequency substrate, on which a high frequency substrate transmission line for connecting a chip carrier transmission line and a package substrate transmission line is formed, is mounted while being inclined with respect to a package, so that each distance between the transmission lines can be reduced. Thereby, the lengths of wires for connecting the transmission lines can be reduced so as to improve frequency characteristics of an optical modulator module.

Abstract: A memory device is provided with a structure for improved transmission line operation on integrated circuits. The structure for transmission line operation includes a first layer of electrically conductive material on a substrate. A first layer of insulating material is formed on the first layer of the electrically conductive material. A number of high permeability metal lines are formed on the first layer of insulating material. The number of high permeability metal lines includes composite hexaferrite films. A number of transmission lines is formed on the first layer of insulating material and between and parallel with the number of high permeability metal lines. A second layer of insulating material is formed on the transmission lines and the high permeability metal lines. The structure for transmission line operation includes a second layer of electrically conductive material on the second layer of insulating material.

Abstract: A semiconductor device and fabricating method thereof are provided. A first substrate with an inductor cell and a through-electrode is connected to a second substrate having an RF device circuit unit. A connecting electrode can electrically connect the inductor cell to the RF device circuit unit.

Abstract: The disclosure relates to a semiconductor device and a method for producing a semiconductor device, in particular a semiconductor device having a circuit region having at least one active component for processing a high-frequency electromagnetic signal.

Abstract: For a multi-terminal semiconductor package, such as a BGA or a CSP, that handles high-speed differential signals, a high-speed signal is assigned to the innermost located electrode pad on an interposer substrate, and the electrode pad is connected to the outermost located ball pad on the interposer substrate. With this arrangement, the length of a plating stub can be considerably reduced, and the adverse affect on a signal waveform can be minimized. This arrangement is especially effective for differential signal lines.

Abstract: A vertical electrical device includes a region in a substrate extending from a surface of the substrate, the region having an inner wall and an outer wall circumscribing the inner wall. An inner electrically conductive layer is disposed on the inner wall and an outer electrically conductive layer is disposed on the outer wall, with an electrically insulative material disposed between the inner and outer layers. An electrical conductor in the substrate is bounded by the inner electrically conductive layer.

Abstract: This invention provides a structure and method for improved transmission line operation on integrated circuits. One method of the invention includes forming transmission lines in an integrated circuit. The method includes forming a first layer of electrically conductive material on a substrate. A first layer of insulating material is formed on the first layer of the electrically conductive material. A pair of layered high permeability shielding lines are formed on the first layer of insulating material. The pair of layered high permeability shielding lines include layered permalloy and/or Ni45Fe55 films. A transmission line is formed on the first layer of insulating material and between and parallel with the pair of layered high permeability shielding lines.

Abstract: Fundamental interconnect systems for connecting high-speed electronics elements are provided. Interconnect system has the means, which could reduce the microwave loss by reducing the effective dielectric loss and dielectric constant of the interconnect system, and increase the bandwidth of the interconnects and also reduce the signal propagation delay, respectively. Ideally, the speed of the electrical signal on the signal line can be reached to speed of the light in the air, and the bandwidth can be reached to closer to the optical fiber. The interconnect systems consists of the signal line, dielectric system with opened trench or slot filled up with the air or lower dielectric loss material, and the ground plan. The signal line proposed in this invention could be made any type of signal line configuration for example, microstripline, strip line or coplanar line. The signal line can also be made as single ended or differential pairs of any configurations.

Abstract: A semiconductor device has a mounting substrate and a semiconductor package mounted on the mounting substrate. The mounting substrate has a substrate body, input/output line conductors on the upper surface of the substrate body, a front-face grounding conductor on the upper surface of the substrate body, spaced from the input/output line conductors, and a lower surface grounding conductor formed on the lower surface of the substrate body and electrically connected to the front-face grounding conductor. The semiconductor package has input/output terminals electrically connected to end portions of the input/output line conductors, a grounding terminal electrically connected to the front-face grounding conductor, and a semiconductor element die-bonded on the grounding terminal and electrically connected to the input/output terminals.