Abstract: A semiconductor transistor which is burned in by a burn-in signal having a burn-in frequency higher than a thermal transient response frequency of a transistor used at an operating frequency in the microwave region, and supplying the burn-in signal to the transistor, wherein the burn-in signal has a frequency lower than the operating frequency of the transistor and higher than a response frequency of impurities included in the transistor, and the operating frequency is higher than 1 GHz.

Abstract: A kind of transient voltage suppressor structure that prevents the edge of the signal electrode from contacting with the variable impedance material by using an insulation layer to remove the point discharge existing on the edge of the signal electrode and increase the capability of the transient voltage suppressor to sustain higher transient voltage energy.

Abstract: A structure and method for a programming device or a fuse includes a capacitive circuit having a capacitance which is alterable. The capacitive circuit can include a first capacitor, a fuse link connected to the first capacitor and a second capacitor connected to the fuse link, wherein removing a portion of the fuse link changes the capacitance.

Abstract: A wiring board according to the present invention has a substrate, a plurality of lines provided on the substrate, an interference-preventive conductor layer provided between the lines to have open ends and prevent signal interference between the lines, and a via electrically connected to the interference-preventive conductor layer. The via is provided at a point at which a distance from each of the open ends of the interference-preventive conductor layer is less than one quarter of a wavelength corresponding to a maximum frequency component of harmonic components contained in the signal.

Abstract: Improved methods of packaging external fuses together with integrated circuit devices are described. A pair of frame strips are provided that each have an associated set of contact pads. A resistor paste is applied to one of the contact pad sets and the frame strips are laminated together by curing the resistor paste which is positioned between the contact pad sets. Dice are mounted to the opposite sides of the second contact pads to form integrated circuit devices having integrally packaged external fuses. The packaged devices are eventually singulated for use. In some embodiments, the contact pads each have downturned tabs that form wings on opposite sides of each die. When the dice are flip chips, a device may be attached to a substrate board by soldering both the bumps on the die and the tab wing tips to the substrate board. In a preferred embodiment, the resistor paste is a positive temperature coefficient resistor paste.

Abstract: The semiconductor device includes a semiconductor substrate, an insulating layer on the semiconductor substrate wherein a groove is patterned to a predetermined depth in an upper surface of the insulating layer, a fuse layer at sidewalls and on a bottom of the groove, and a wire connected electrically to the fuse layer.

Abstract: The present invention describes an apparatus and method for fabrication of a precision circuit elements. In particular, the circuit elements are fabricated as part of an integrated circuit assembly. The processing of the circuit elements is such to provide a nominal circuit element value close in value to the desired value. Additional trim circuit elements are joined to the nominal circuit element through links. The links are fusible links or antifuses. By selectively blowing the fusible links or fusing the antifuses, trim circuit elements are added or subtracted to personalize the value of the nominal circuit element. A capacitor is used in an illustrative example.

Abstract: A processor or a semiconductor integrated circuit which prevents a malfunction caused by noise on power supply nets. A noise detecting circuit which detects noise on power supply nets to a circuit block is arranged in each of a plurality of circuit blocks which performs signal processing, and which performs interruption for preventing a malfunction to the circuit block itself or other circuit blocks relating to this signal processing by a detection signal of each noise detecting circuit.

Abstract: A methodology of creating integrated circuits with improved noise isolation is presented. The circuitry of an integrated circuits is separated into noise generating circuit blocks and noise sensitive circuit blocks. N-type and P-type diffusion guard rings are placed around each of the circuit blocks. Substantially overlying the N-type and P-type diffusion guard rings are power supply meshes which are intimately in contract with the guard rings below through spaced apart vias. The power supply meshes not only supply power for the circuit blocks, but also reverse-bias the diffusion guard rings for improved noise isolation.

Abstract: A semiconductor antifuse device that utilizes a resistive heating element as both a heating source or fuse blowing and as part of the fuse link. The antifuse device may also be utilized as a fuse and the antifuse or fuse embodiment can be programmed and read with the same two electrodes. The antifuse or fuse is well suited for use and efficient fabrication in a printhead apparatus or other circuit arrangements.

Abstract: Outer leads extend outward from within a package that seals a semiconductor chip, and they are connected to the semiconductor chip inside the package. Depressions are formed at the distal end portions of the outer leads. The depressions are coated with a material which is one of: Sn—Pb, Sn—Ag, Sn—Bi, Sn—Zn, Sn—Cu, Pd, Au and Ag. The depressions are V-shaped, U-shaped, or rectangular. Each depression has a depth which is 30% to 75% with respect to the thickness which the outer lead has at the cut end face of distal end thereof. The outer leads are either a gull-wing type or a straight type.

Abstract: A semiconductor module having a first integrated circuit die having a planar surface. The first integrated circuit die has a first conductive pad disposed substantially on the planar surface and a redistributed conductive pad electrically connected to the first conductive pad. The redistributed conductive pad is disposed near a periphery of the planar surface. The semiconductor module has a second integrated circuit die stacked adjacent to the planar surface and offset from the periphery, such that a second conductive pad on the second integrated circuit die can be electrically connected to the redistributed conductive pad.

Abstract: A vertical fuse structure and methods for customization of integrated circuits include a substantially vertically-oriented interconnect structure or “fuse” which provides for a more densely packed and thus smaller programmable integrated circuit. In a preferred embodiment, a vertical interconnect structure is fabricated by forming a first interconnect layer, forming an insulating layer over the first interconnect layer in which substantially vertically-oriented vias are patterned in contact with the first interconnect layer, filling the vias with a conductive plug, and forming a second interconnect layer over the insulating layer in contact with the conductive plug. The vertical interconnect structure is preferably disconnected by forming a narrow, substantially vertical disconnect cavity through the second interconnect layer and a portion of the conductive plug, thereby removing the connection between the second interconnect layer and the plug.

Abstract: There is described a semiconductor device having a copper fuse which prevents damage to a silicon substrate beneath the copper fuse, which would otherwise be caused by a laser beam radiated to blow the copper fuse. A light absorbing layer is formed on the copper fuse layer from material whose light absorption coefficient is greater than that of a copper wiring layer. Light absorbed by the light absorbing layer is transmitted, through heat conduction, to the copper wiring layer beneath the light absorbing layer and further to a barrier metal layer beneath the copper wiring layer. Even when the widely-used conventional laser beam of infrared wavelength is used, the copper fuse can be blown. Since a guard layer is formed below the fuse layer, there can be prevented damage to the silicon substrate, which would otherwise be caused by exposure to the laser beam of visible wavelength.

Abstract: A ball grid array type semiconductor package includes a semiconductor chip formed with bonding pads, an elastomer bonded to the semiconductor chip, a flexible wiring substrate bonded to the elastomer and formed with wirings connected at one end of the bonding pads of the semiconductor chip, a solder resist formed on the main surface of the flexible wiring substrate and solder bump electrodes connected to the other ends of the wirings. The elastomer is bonded to the flexible wiring substrate on the side of the tape, the solder resist is formed on the side of the wirings, and the solder bump electrodes are connected with the wirings by way of through holes formed in the solder resist.

Abstract: A semiconductor device according to one embodiment may include protruding portions (2) formed on a periphery of a fuse pattern. Narrowed portions (3) are gaps between adjacent protruding portions (2), and may be filled with a first insulation layer (5), such as an oxide or the like. A silica layer (6) may then be deposited for enhancing the flatness of a semiconductor device surface. Excess silica layer (6) portions may be etched back and remaining silica layer (6) between fuses (1) may be planarized. A second insulation layer (7) may be formed that can contact portions of a first insulation layer (5) that fill narrowed portions (3). Consequently, the extents of a silica layer (6) may be interrupted along a periphery and between adjacent fuses by first insulation layer (5).

Abstract: A hemispherical grained (HSG) lower electrode, and its manufacturing method, are disclosed in which the yield is enhanced by suppressing the depletion due to insufficient diffusion of an impurity into the hemispherical grains (abbreviated also as HSGs) to reduce the deterioration in the capacity caused by the defect on the negative (lower) electrode side, and preventing the fracture of the HSGs. In a method of forming a capacitor composed of a polysilicon lower electrode, a dielectric film, and an upper electrode, the method of this invention includes at least a step of forming HSG silicon on the lower electrode, where each of its grains has a neck with decreased diameter on the side of the contact plane with the lower electrode, a step of depositing a silicon film covering the HSGs by filling the gaps between the lower electrode in the periphery of the necks and the HSGs while maintaining the rugged shape of the formed HSGs, a step of forming a dielectric film, and a step of forming an upper electrode.

Abstract: In order to program a programmable element, it is proposed in a semiconductor circuit configuration to connect a first and a second connecting terminal of a programmable element to first and/or second potential devices provided in the semiconductor circuit configuration. In this manner, the first and second potentials are intrinsically made available to form a burning voltage for programming the programmable element.

Abstract: A defect removable semiconductor element and the manufacturing method thereof are provided with a protective layer covering fuses exposed at a part of the redundancy memory cell region, the layer being thinner than the one covering the main memory cell region, so that a predetermined fuse is cut off for removing a defect without damaging adjacent fuses even if the amount of energy of laser beam to be applied is greater and the size of the spot to be focused is bigger, thereby improving operational conditions in the energy of the laser beam to be applied and the size of a spot to be focused and the operational reliability in removing a defect.

Abstract: A monolithically integrated semiconductor circuit apparatus includes circuit elements disposed on a semiconductor substrate. The circuit elements include at least one semiconductor memory device, drive circuits, and a digital logic component monolithically integrated on the semiconductor substrate. A first contact-making plane is provided which is closer to a main surface of the semiconductor substrate than a penultimate contact-making plane, which is closer to the main surface of the semiconductor substrate than a last contact-making plane. The first, penultimate, and last interconnect patterns electrically interconnect the plurality of circuit elements. A protection device is formed at least in a partial region of the penultimate interconnect pattern. The protection device includes at least a fuse or an antifuse and is assigned to a redundancy activation for defective memory cells and memory cell groups in the semiconductor memory device.

Abstract: A fusible link in an integrated semiconductor circuit and a process for producing the fusible link contemplate the disposition of a fusible link, which is constructed with a cross-sectional constriction as a desired fusing point for its conductor track, in a void. A surface of the void and/or a bare conductor track can be covered with a protection layer, to prevent corrosion. The advantages of such a fusible link are a lower ignition energy and increased reliability. The fusible link may be used as a memory element of a PROM.

Abstract: In the present invention, a semiconductor device includes a first insulation layer formed on a semiconductor substrate, an elevating pad formed on the first insulation layer, a second insulation layer covering the elevating pad, a plurality of fuses formed on the second insulation layer and over the elevating pad, a third insulation layer formed on the fuses, and an opening formed in a top portion of the third insulation layer and over the fuses. With this invention, the horizontal level of the fuses are elevated due to the existence of the elevating pad, which makes the distance between the fuse window and fuses be closer than that of the conventional and that reduces the step difference. Thus, a laser beam can reliably blow out all of the fuses reliably.

Abstract: A method is provided for etching fuse windows through a passivation layer and at least two inter-metal dielectric layers that are deposited on top of a fuse when the fuse is embedded in an insulating material including a top layer of silicon nitride on a semi-conducting substrate. The method can be carried out by a two-step etching process in which an opening is first etched for the fuse window through a passivation layer by a first etchant that has low selectivity to the passivation material, and then the opening is etched through the IMD layers in a second etching process by a second etchant which has high selectivity to the silicon nitride etch-stop layer. The two-step etching process can be easily controlled so that the quality and yield for the resulting fuse windows can be improved.

Abstract: A method for fabricating an improved metal-insulator-metal or metal-insulator-polysilicon capacitor having high capacitance density and low noise is achieved. An insulating layer is provided overlying a semiconductor substrate. A capacitor bottom plate electrode is formed overlying the insulating layer. A thin capacitor dielectric layer is deposited overlying the capacitor bottom plate electrode. An etch stop layer is deposited overlying the capacitor dielectric layer. A thick oxide layer is deposited overlying the etch stop layer. The oxide layer over the capacitor bottom plate electrode is etched away stopping at the etch stop layer whereby a recess is formed in the oxide layer overlying the bottom plate electrode wherein sidewalls of the oxide layer overlie the edges of the bottom plate electrode.

Abstract: The semiconductor device comprises a blocking layer 12 formed on a substrate 10, an insulation film 14 formed on the blocking layer 12, and a fuse 22 formed on the insulation film 14. The blocking layer 12 is formed below the fuse 22, whereby the fuse is disconnected by laser ablation, and the laser ablation can be stopped by the blocking layer 12 with good controllability without damaging the substrate. The fuses to be disconnected can be arranged at a very small pitch, which can improve integration of the fuse circuit.

Abstract: Improved methods of packaging external fuses together with integrated circuit devices are described. A pair of frame strips are provided that each have an associated set of contact pads. A resistor paste is applied to one of the contact pad sets and the frame strips are laminated together by curing the resistor paste which is positioned between the contact pad sets. Dice are mounted to the opposite sides of the second contact pads to form integrated circuit devices having integrally packaged external fuses. The packaged devices are eventually singulated for use. In some embodiments, the contact pads each have downturned tabs that form wings on opposite sides of each die. When the dice are flip chips, a device may be attached to a substrate board by soldering both the bumps on the die and the tab wing tips to the substrate board. In a preferred embodiment, the resistor paste is a positive temperature coefficient resistor paste.

Abstract: Fuses for integrated circuits and semiconductor devices, methods for making the same, methods of using the same, and semiconductor devices containing the same. The semiconductor fuse contains two conductive layers—an overlying and underlying layer—on an insulating substrate. The underlying layer comprises titanium nitride and the overlying layer comprises tungsten silicide. The semiconductor fuse may be fabricated during manufacture of a local interconnect structure containing the same materials. The fuse, which may be used to program redundant circuitry, is blown by electrical current rather than laser beams, thus allowing the fuse width to be smaller than prior art fuses blown by laser beams. The fuse may also be blown by less electrical current than the current required to blow conventional polysilicon fuses having similar dimensions.

Abstract: A battery system includes an electrical storage cell having a positive terminal and a negative terminal. The electrical storage cell is provided with a normally open bypass circuit path that is closed in the event of an open-circuit failure of the electrical storage cell. The bypass circuit path includes a first electrical conductor connected to the positive terminal of the electrical storage cell, a second electrical conductor connected to the negative terminal of the electrical storage cell, and a shorting gap between the first electrical conductor and the second electrical conductor. A mass of a fusible material is positioned at an initial mass location. A heat source is activatable upon the occurrence of an open-circuit condition of the electrical storage cell. The heat source is operable to melt at least a portion of the mass of the fusible material and thereby to close the shorting gap so that the first electrical conductor is in electrical communication with the second electrical conductor.

Abstract: Integrated circuitry fuse forming methods, integrated circuitry programming methods, and related integrated circuitry are described. In one implementation, a first layer comprising a first conductive material is formed over a substrate. A second layer comprising a second conductive material different from the first conductive material is formed over the first layer and in conductive connection therewith. A fuse area is formed by removing at least a portion of one of the first and second layers. In a preferred aspect, an assembly of layers comprising one layer disposed intermediate two conductive layers is provided. At least a portion of the one layer is removed from between the two layers to provide a void therebetween. In another aspect, programming circuitry is provided over a substrate upon which the assembly of layers is provided.

Abstract: A semiconductor device with a multi-level interconnection structure has a first conductive layer disposed below a fuse, and formed in the same layer as the first metal wire as a component of multi-level interconnects, and a second conductive layer disposed below the fuse and formed in the same layer as the second metal wire as a component of the multi-level interconnects. A laser beam control unit is configured with the first and second conductive layers. Thus, damage occurrence in a semiconductor substrate may be controlled during blowing the fuse, a quality deterioration and further a defective of the semiconductor device may be not only avoided, but also an integration degree thereof may be enhanced.

Abstract: Integrated circuitry fuse forming methods, integrated circuitry programming methods, and related integrated circuitry are described. In one implementation, a first layer comprising a first conductive material is formed over a substrate. A second layer comprising a second conductive material different from the first conductive material is formed over the first layer and in conductive connection therewith. A fuse area is formed by removing at least a portion of one of the first and second layers. In a preferred aspect, an assembly of layers comprising one layer disposed intermediate two conductive layers is provided. At least a portion of the one layer is removed from between the two layers to provide a void therebetween. In another aspect, programming circuitry is provided over a substrate upon which the assembly of layers is provided.

Abstract: A battery system includes an electrical storage cell having a positive terminal and a negative terminal. The electrical storage cell is provided with a normally open bypass circuit path that is closed in the event of an open-circuit failure of the electrical storage cell. The bypass circuit path includes a first electrical conductor connected to the positive terminal of the electrical storage cell, a second electrical conductor connected to the negative terminal of the electrical storage cell, and a shorting gap between the first electrical conductor and the second electrical conductor. A mass of a fusible material is positioned at an initial mass location. A spring is positioned to force the mass of the fusible material from the initial mass location, along the metal flow path, and into the shorting gap, when the mass of the fusible material is at least partially molten. A heat source is activatable upon the occurrence of an open-circuit condition of the electrical storage cell.

Abstract: A semiconductor fuse is positioned between conductors for connecting wiring lines. The fuse comprises spacers positioned on adjacent ones of the conductors, and a fuse element positioned between the spacers and connected to the wiring lines. A space between the conductors comprises a first width comprising a smallest possible photolithographic width and the fuse element has a second width smaller than the first width.

Abstract: A semiconductor memory device has a redundancy function using a fuse block arranged in a window. The fuse block includes a plurality of fuse elements selectively cut by a laser beam in the window for decoding the input address of a defective memory cell. Each fuse element has a pair of parallel lead sections, and a bridge section bridging the ends of the lead sections and disposed for laser cutting. The longer sides of the window can be reduced in size for reduction of the occupied area for the pitch of signal lines and thus the chip area.

Abstract: The invention relates to an overvoltage protection device and to a method for fabricating such a device. A substrate (1) is provided with a first electrode layer (2), above which extends a second electrode layer (3) which is separated from the first electrode layer (2) by a distance (d) determined by the thickness of a spacing layer (4). The spacing layer (4) has an opening (5) which forms a cavity (6) between the electrode layers (2, 3).

Abstract: An ion repulsion structure for a fuse window is provided. The ion repulsion structure includes multi-level metallic layers and a P-type silicon semiconductor substrate having a plurality of wells. The P-type silicon semiconductor substrate includes an N-type well, a P-type well formed in the N-type well and a plurality of P+ type diffusion regions formed in the P-type well. A fuse element is formed on the P-type silicon semiconductor substrate. A fuse window layer is formed over the fuse element. Multi-level metallic layers surrounding the fuse window are formed. A plurality of contact plugs is electrically connected between the P+ type diffusion regions of the semiconductor substrate and the lowest metallic layer. A plurality of via plugs electrically connect the multi-level metallic layers to each other.

Abstract: A semiconductor device has the following structure: a lead frame 2 is disposed on the center of a package 1, signal terminal electrodes 3 through 7 are disposed on edges of the package, a semiconductor chip 8 is mounted on the lead frame 2, a grounding electrode 16 having a grounding potential is disposed between the signal terminal electrodes 4 and 5, and a grounding electrode having a grounding potential is disposed between the signal terminal electrodes 5 and 6. This structure increases an electrical separation between the signal terminal electrodes.

Abstract: A silicon wafer is etched to form a first and second series of guidance features. The features of the first series are larger than and surround the features of the second series. The second series is clustered into groups and a hole is formed in the center of each group. The wafer is designed to integrate a silicon package having preformed contacts with a plurality of silicon-based chips. The package and each chip has a series of guidance recesses which correspond to the guidance features of the first and second series, respectively. One chip is placed on top of each group of the second series, and the package is placed on top of the first series. The recesses in the package and chips will precisely align with and slidingly engage the upper ends of the features. Since the features of the first series are larger than those of the second series, there is a clearance between the package and the chips.

Abstract: Electrostatic breakdown is avoided during fabrication of individual semiconductor devices using a semiconductor aggregate substrate. The semiconductor aggregate substrate is comprised of a large wafer. A plurality of sections are provided on the surface of the wafer, which are divided by division lines. A display active matrix circuit is integrally formed in each of the segments through normal IC production processing. Guard ring patterns are provided so that they surround the individual display active matrix circuits. A connection pattern is also provided for commonly connecting the guard ring patterns adjoining each other through the division lines. The connection pattern has opening structures for dealing with an external overcurrent on both sides of the division lines. The opening structures are constituted by, for example fuse patterns.

Abstract: A copper sputtering target is provided for producing copper films having reduced in-film defect densities. In addition to reducing dielectric inclusion content of the copper target material, the hardness of the copper target is maintained within a range greater than 45 Rockwell. Within this range defect generation from arc-induced mechanical failure is reduced. Preferably hardness is achieved by limiting grain size to less than 50 microns, and most preferably to less than 25 microns. The surface roughness preferably is limited to less than 20 micro inches, or more preferably, less than 5 micro inches to reduce defect generation from field-enhanced emission. This grain size range preferably is achieved by limiting the purity level of the copper target material to a level less than 99.9999%, preferably within a range between 99.995% to 99.9999%, while reducing particular impurity levels.

Abstract: Surface area of a semiconductor integrated circuit memory required by programmable fuse boxes is reduced, and the capacitive loading of a column address bus from the programmable fuse boxes is reduced by reducing the number of programmable boxes. Each programmable fuse box is connected through fuses to a plurality of redundant columns in memory arrays whereby any one or more of the redundant column lines can be addressed through the programmed fuse box in replacing a defective column line. An unprogrammed redundant column select line is connected to ground through the fuses connecting the unselected redundant column select lines to ground so that unprogrammed redundant columns are inactive.

Abstract: An integrated circuit and fabrication method for an antifuse structure that includes a shallow trench oxide isolation region disposed in a silicon substrate, the oxide in the trench having a top surface recessed below the surface of the substrate to form sharp corners at each side of the trench. The substrate includes diffusion regions adjacent to the sharp corners, electrical insulation layers over the diffusion regions, and an electrical conductor is disposed over the recessed oxide in the trench. When voltage is applied on the electrical conductor, a high field point is produced at the sharp corners causing the electrical insulation layer at the corners to break down and create a short circuit between the electrical conductor and the diffusions, thus providing a fuse function.

Abstract: An E-beam generator and detector arrangement sends an electron beam through a series of differentially evacuated vacuum chambers of small size to detect faulty circuitry in individual semiconductor devices. The vacuum chambers are open to one end and are sealed by the semiconductor device without contacting the vacuum chambers. A laser generator is operated by a control system with the E-beam generator and detector arrangement to provide a laser beam in a known physical relationship to the electron beam to correct detected faulty circuitry in the semiconductor devices. The E-beam generator and detector arrangement confirms the correction without further handling of the semiconductor device.

Abstract: A semiconductor device comprises a signal pin mounted on a base plate by adhesive. Parasitic capacitance exists between the pin and the base plate in the region of adhesive and may deleteriously affect the operation of circuitry in chip connected to pin by a bond wire. A bond wire connecting pin to the base plate has an inductance which forms a parallel resonant circuit with the parasitic capacitance, so that, at the resonant frequency, signals on pin at substantially the same frequency pass to or from the chip substantially unattenuated by the parasitic capacitance. Alternatively, the inductances of the signal pin and the bond wires may be such that, at the frequency of signals on the signal pin, an impedance transformation is provided between the input to the signal pin and the end of the first bond wire where it connects to the chip.

Abstract: A pad for input/output signals is formed on a first conductive type insulated island region interposing an insulating film therebetween. The insulated island region is electrically insulated and isolated from other semiconductor regions in a semiconductor substrate. A fixed potential is provided to the insulated island region through an n.sup.+ -type layer and an electrode. As a result, it is possible to prevent noise superimposed on the input/output signals from interfering in the operation of the other semiconductor regions, and to prevent noise produced in the other semiconductor regions from being superimposed on the input/output signals.

Abstract: A tailorable metallization level between a first set of pads connected to internal circuits of an electronic structure and a second set of pads for external connection provides for altering the configuration of the electronic structure. The second set of pads is kept invariant to facilitate external connection to the electronic structure. The reconfiguration scheme provides, in one embodiment, for sparing a stacked arrangement of chips. That is, it provides a way to disconnect a defective chip from a stack of chips and connect a spare chip so that, from the point of view of external circuitry, there is no change in the connection to or function of the stack. The invention also provides for changing the logical arrangement of circuits in a single chip, such as the organization of memory I/O.

Abstract: The integrated circuit is provided with capacitors for smoothing the supply voltage. The capacitors are disposed below the supply interconnects which supply the integrated circuit with the supply voltage. This enables the integrated circuit to be accommodated on a minimal area.

Abstract: A resettable fuse is connected in series with a bonding pad of an IC chip, In the presence of a high voltage surge, the resettable fuse breaks the connection temporary. After the surge is over, the resettable reset itself and the IC resumes operation.

Abstract: On a semiconductor substrate, a first circuit and a second circuit are provided with a space therebetween. The first circuit and the second circuit are connected to each other by a fuse portion. In the middle of the fuse portion, a connecting portion is interposed, which is made of a material highly resistant to corrosion. Accordingly, an improved semiconductor device with a corrosion-resisting fuse portion is accomplished, which ensures the layout to be designed much more freely.

Abstract: The large voltage required to program a conventional antifuse is substantially reduced by forming the antifuse with a diffusion region and an overlying layer of silicide. The silicide layer is contacted at opposite ends so that a current can flow in through contacts at one end, and out through contacts at the opposite end. When unprogrammed, a voltage is applied to the semiconductor material in which the diffusion region is formed to prevent the diffusion region to semiconductor material from being forward biased. The antifuse is programmed by heating the silicide layer until the silicide layer agglomerates. The silicide layer can be heated by passing a current through the silicide layer.