Abstract: A semiconductor integrated circuit device capable of reducing delay of wiring as far as possible is provided. The semiconductor integrated circuit device comprises at least two sets of pairs of signal lines having first polarity and second polarity opposite thereto, wherein the signal line of the first polarity of the signal lines of the second set is disposed at the portion adjacent to the signal line of the first polarity of the signal lines of the first set, the signal line of the second polarity of the first set is disposed at the portion adjacent to the signal line of the first polarity of the second set, and the signal line of the second polarity of the second set is disposed at the portion adjacent to the signal line of the second polarity of the first set.

Abstract: In an integrated circuit where one desires the most compact arrangement of fuses and active circuitry, an insulating layer is deposited over active circuitry which includes the associated interconnect layers. A protective layer made with a reflective material may be used as a conductive layer above the lower layers of the integrated circuit containing active circuitry which includes interconnect layers of any desired number. This protective layer is patterned below the areas that will later contain fuses (or antifuses or both). Above this protective layer another insulating layer is deposited. A fuse layer which may be metal or another conductive film is then deposited. This conductive layer is patterned to provide the desired fuses (and/or antifuses) as required, with some or all of the fuses aligned with the protective layer deposited underneath.

Abstract: Integrated circuitry fuse forming methods, integrated circuitry programming methods, and related integrated circuitry are described. In one implementation, a first layer comprising a first conductive material is formed over a substrate. A second layer comprising a second conductive material different from the first conductive material is formed over the first layer and in conductive connection therewith. A fuse area is formed by removing at least a portion of one of the first and second layers. In a preferred aspect, an assembly of layers comprising one layer disposed intermediate two conductive layers is provided. At least a portion of the one layer is removed from between the two layers to provide a void therebetween. In another aspect, programming circuitry is provided over a substrate upon which the assembly of layers is provided.

Abstract: A multilayered structure, such as a printed circuit board, includes a first conductive layer and a second conductive layer that are separated from each other by a dielectric layer. The dielectric layer is formed of a first material, such as a photoimagible polyimide and epoxy resin. The dielectric layer has a number of via holes that extend from the first conductive layer to the second conductive layer. The via holes are filled with a second material having a breakdown voltage less than a breakdown voltage of the first material included in the dielectric layer to form an antifuse. The second material in the via holes can be, for example, a conductive epoxy resin or a polymer loaded with conductive particles (also referred to as "conductive paste").

Abstract: A sharp transition or step is first formed on the surface of a semiconductor material. A layer of interconnect metal is deposited by conformal CVD and substantially the same thickness of the metal as deposited is removed by anisotropic etching, leaving a narrow line of the interconnect metal at the step portion to serve as an interconnect line. Interconnect lines of 0.5 micron or below can be achieved since the process is not limited by photostepper resolution.

Abstract: The present invention is a method and apparatus for programming a stack of segments wherein each segment includes a plurality of die which are interconnected through metal interconnects patterned on the surface of each segment. Once the segments are arranged into a stack, the stack is connected to external circuits and each segment is addressed through control lines. Electrically conductive fuses on the segments are used as an interface between the control lines and the die. Segment level programming is performed on each segment by opening the conductive fuses on the segments in a predetermined pattern in order to route the control lines to each segment such that segments are uniquely addressed. After segment level programming, circuit board programming is performed so that any defective die found in the stack is logically replaced with replacement die in the stack.

Abstract: A packaged integrated circuit configured for interconnection to an external component comprises a die (1) having a high frequency contact (8), the die (1) being disposed on a lead frame (3). The lead frame (3) comprises a plurality of leads (9). At least two of the leads are first and second RF port leads (9a, 9b) which are electrically connected to the RF port. When mounted to a printed circuit board substrate, there is a capacitor (12) connected between the first and second high frequency contact (8) leads (9a, 9b) to achieve frequency specific signal attenuation at an unwanted frequency with minimal contribution of insertion loss at a desired frequency.

Abstract: A semiconductor device has a semiconductor substrate on which are formed semiconductor devices. A wiring is provided to make electrical connection between the devices. First fuse elements are formed on the substrate and connected to the wiring. A second fuse element is also formed on the same plane as the first fuse elements on the substrate and provided in proximity to a portion of each first fuse element to be blown. Both the first and second fuse elements may be formed by a composite layer of titanium nitride film and a titanium film formed over the titanium nitride film, and a tungsten or aluminium film formed over the composite layer. The first and second fuse elements may have the same width. The first fuse elements may be linearly arranged and two of the first fuse elements adjacent to each other may share the second fuse element, or a flow catchment, provided in proximity to both fuse elements.

Abstract: A semiconductor wafer is arranged so that a burn-in test, which is performed to remove latent defects, can be conducted while the semiconductor chips are still on the semiconductor wafer. Sets of pad electrodes necessary for the burn-in test of the semiconductor chips are provided on each of the semiconductor wafers and are connected to external pad electrodes formed at a peripheral portion of the semiconductor wafer, by way of metal film wiring lines. High resistance polycrystalline silicone thin film wiring line portions which acts as fuses, and low resistance polycrystalline silicon wiring line portions which are cleanly cut upon dicing, are provided at a suitable intermediate location in the metal thin filming lines.

Abstract: An integrated circuit assembly is formed with an integral power supply decoupling capacitor for monolithic circuitry in a semiconductor substrate by using the substrate itself as one plate of the capacitor. A dielectric is formed on the "back" side, or surface, of the substrate (i.e., the surface opposite the surface in which component structures are formed) such as by growing a native oxide thereon. Using a conductive epoxy, the back side of the substrate (actually, the dielectric layer thereon) is then attached to a conductive foundation member, which forms the other plate of the capacitor when a potential is applied across the substrate and the foundation member. The conductive foundation member also may be connected to a heat sink structure integral with the package. The heat sink may extend through a window in the package, providing a path and surface via which heat may be transferred to an external heat sink if a larger heat sink mass is needed.

Abstract: A semiconductor device according to the present invention is formed on a semiconductor chip and has a common module and a plurality of selectable modules. Each selectable module on the semiconductor chip performs a defined function and has a separate input power terminal. The device also has a voltage pad for connecting to a first voltage source having a first voltage level, so that the voltage pad supplies power to the input power terminal of each selectable module. The output of each selectable module may be connected to one common output pad, or alternatively, may be connected to a dedicated output pad. Also connected to each selectable module is a die/sort pad used for disconnecting a corresponding selectable module from the first voltage source. In the wiring between the first voltage source and the selectable modules, there is provided a plurality of fuses, each fuse having first and second terminals.

Abstract: A semiconductor device according to the present invention comprises a fuse provided on a substrate, a first insulating layer formed on the substrate and the first insulating layer, a first wiring formed on the first insulating layer, a second insulating layer formed on the first wiring, the second insulating layer including a plurality of insulating films including a water absorptive overcoat, a second wiring formed on the second insulating layer, an opening portion formed in a portion of the second insulating layer corresponding to the fuse by selectively removing the portion and having a side face formed by an exposed portion of the second insulating layer and a bottom face formed by the exposed first insulating layer, a side wall film formed of the same material as that of the second wiring and covering the exposed side face of the opening portion and a passivation film formed on the second insulating layer, the second insulating layer and the side wall film.

Abstract: Resilient contact structures are mounted directly to bond pads on semiconductor dies, prior to the dies being singulated (separated) from a semiconductor wafer. This enables the semiconductor dies to be exercised (e.g., tested and/or burned-in) by connecting to the semiconductor dies with a circuit board or the like having a plurality of terminals disposed on a surface thereof. Subsequently, the semiconductor dies may be singulated from the semiconductor wafer, whereupon the same resilient contact structures can be used to effect interconnections between the semiconductor dies and other electronic components (such as wiring substrates, semiconductor packages, etc.). Using the all-metallic composite interconnection elements of the present invention as the resilient contact structures, burn-in can be performed at temperatures of at least 150.degree. C., and can be completed in less than 60 minutes.

Abstract: A fuse window structure and method for forming the same for a semiconductor device with a fuse and a cutting site on the fuse, the structure having (1) a first oxide region substantially in register with the cutting site, the first oxide region having a first thickness, (2) a second oxide region substantially in register with a first land generally surrounding the cutting site, the first land generally in register with the fuse, the second region having a second thickness, and (3) a third oxide region substantially in register with a second land generally surrounding the fuse, the third region having a third thickness different than the first thickness. Different fuse window structures are formed by using etch stops with different configurations, each configuration differing with regard to coverage of the three oxide regions.

Abstract: For the suppression of radio frequency emissions from an electrical drive comprising an electric motor supplied with electrical power via an electronic controller having a high speed switching device which generates high frequency energy, an electrical screen is provided to receive the radio frequency energy and is connected back to the input side of the high speed switching device.

Abstract: A stackable semiconductor package is described which has external contact points (pins, pads, solder-bumps, etc.), which are arranged in arrays on the top and bottom surfaces of the package. This package also has internal contact points (bond pads) for connection to an integrated circuit die. The external and internal connection points are connected by a programmable interconnection matrix, which may be manufactured separately from the package body and then assembled within the package. The internal contact points can each be selectively connected to the external contact points, and selective connections can also be made linking pairs of the external contact points. Stacks of such packages, containing different dice, may be formed, creating large, tightly-coupled circuit blocks. A presently-preferred embodiment of the programmable package is described in which the package body and programmable matrix are manufactured as a unit.

Abstract: A novel antifuse includes a composite of conductive particles dispersed throughout a nonconductive matrix, which composite is located inside an antifuse via. The antifuse via is defined by a dielectric layer that separates two electrodes. The electrodes can be located in the same conductive layer plane (typically parallel to and isolated from one another) or in two different conductive planes (typically formed transverse to one another and separated by a dielectric with an antifuse via formed therein). The electrodes can be coupled to, for example, active or passive regions of the integrated circuit. One embodiment of an antifuse (also called "composite antifuse") has only the composite in an antifuse via between the two conductive layers. Another embodiment of an antifuse (also called "hybrid antifuse") includes in addition to the composite, one or more thin dielectric layers also located in the antifuse via between the two conductive layers.

Abstract: Resilient contact structures are mounted directly to bond pads on semiconductor dies, prior to the dies being singulated (separated) from a semiconductor wafer. This enables the semiconductor dies to be exercised (e.g., tested and/or burned-in) by connecting to the semiconductor dies with a circuit board or the like having a plurality of terminals disposed on a surface thereof. Subsequently, the semiconductor dies may be singulated from the semiconductor wafer, whereupon the same resilient contact structures can be used to effect interconnections between the semiconductor dies and other electronic components (such as wiring substrates, semiconductor packages, etc.). Using the all-metallic composite interconnection elements of the present invention as the resilient contact structures, burn-in can be performed at temperatures of at least 150.degree. C., and can be completed in less than 60 minutes.

Abstract: An inductive structure for an integrated circuit. The inductor has a first turn that shields the other turns of the inductor from a proximate ground plane. Multiple turns are disposed one above another in respective metalization layers of the integrated circuit. The turns are partial loops and are electrically coupled end-to-end with vias. Predetermined ones of the turns have additional portions in different layers. An additional portion of a turn is an electrically conductive strip deposited above the turn in a higher metalization layer and electrically coupled to the turn, thereby increasing the surface area of the turn and decreasing resistance of the turn. A buried n-type loop disposed below the first turn and below the surface of the substrate shields the first turn from the capacitive effects of the substrate.

Abstract: Arrangement for the protection of electrical and electronic components against electrostatic discharge, where a printed circuit board on which the components are mounted is physically connected to a metal plate via an insulating layer with the insulating layer having at least one conductor track of the printed circuit board opening over which at least one track is placed to form a first spark gap between the track and the metal plate and with the metal plate being connected to a fixed potential.

Abstract: Two types of programmable elements, fuses and antifuses, are disclosed for forming an electrically programmable burn-in board in one embodiment and an electrically programmable device-under-test (DUT) card in another embodiment. Both types of programmable elements can also be used in a reconfiguration device for interconnecting electrical contacts in a first configuration to electrical contacts in a second configuration. The various embodiments of this invention include, for example, a component socket, a socket adapter, a cable, a cable adapter, a scrambler card for a burn-in board and a device-under-test card for a burn-in board. A method for forming a fuse is also disclosed.

Abstract: There is provided a tape automated bonding (TAB) tape including, a first film having a first open space therewithin, a second film having a second open space therewithin, the first film being located in the second open space, a third film located in the first open space of the first film, a first closed-loop wiring formed on the second film, a second closed-loop wiring formed on the third film, at least one signal wiring formed on the first film, and at least one ground wiring formed on the first film, the ground wiring inwardly and outwardly extending from the first film to connect the first and second closed-loop wirings to each other. The TAB tape makes it possible to increase the number of the ground wirings by providing the closed-loop wirings. As a result, it is possible to reduce effective inductance and ground bounce noises of the ground wirings, and further possible to reduce mutual capacities among the signal wirings with the result of reduced cross-talk noises.

Abstract: In a package including a substrate, a conductive layer formed within the substrate, an internal lead element connected via a first throughhole to the conductive layer, and an external lead element connected via a second throughhole to the conductive layer, notches are formed in the conductive layer in close proximity to the first and second throughholes.

Abstract: A lead frame of a DRAM chip includes a base end portion to which an external power supply potential ext.cndot.VCC is applied, and two branch portions branching away from the base end portion. A tip portion of one of these two branch portions is connected to an output buffer, and a tip portion of the other is connected to another circuit. Power supply noise generated at the output buffer passes through one of the branch portions to the outside, and will never reach another circuit through the other branch portion. Accordingly, a DRAM which is less susceptible to power supply noise can be provided.

Abstract: Several inventions are disclosed. A cell architecture using hexagonal shaped cells is disclose. The architecture is not limited to hexagonal shaped cells. Cells may be defined by clusters of two or more hexagons by triangles, by parallelograms, and by other polygons enabling a variety of cell shapes to be accommodated. Polydirectional non-orthogonal three layer metal routing is disclosed. The architecture may be combined with the tri-directional routing for a particularly advantageous design. In the tri-directional routing arraingement, electrical conductors for interconnecting terminals of microelectronic cells of an integrated circuit preferrably extend in three directions that are angularly displaced from each other by 60.degree.. The conductors that extend in the three directions are preferrably formed in three different layers. A method of minimizing wire length in a semiconductor device is disclosed. A method of minimizing intermetal capacitance in a semiconductor device is disclosed.

Abstract: A simplified method of manufacturing an electrothermal fuse includes the steps of screening conductive epoxy onto fuse link termination pads, placing a metal alloy fuse link into the conductive epoxy on the termination pads, curing the conductive epoxy, applying deoxidant, applying encapsulant, and curing the encapsulant. The resultant fuse of the preferred embodiment comprises a substrate, termination pads, conductive epoxy interconnects, a solder type fuse link, liquid deoxidant and encapsulant.

Abstract: A polysilicon interconnect is formed on a microelectronic circuit substrate for conducting signals from a driver to a non-polycrystalline silicon contact which has higher impedance than the interconnect. A plurality of electronic "speed bumps" are spaced along the interconnect for disturbing or disrupting signals propagating along the interconnect toward the contact and thereby reducing undesirable back reflection and ringing. The speed bumps can include capacitance altering elements in the form of dielectric strips, or resistance altering elements in the form of low resistance doped areas or high resistance amorphous areas. The speed bumps can include first and second elements having different values of capacitance or resistance which are spaced along the interconnect in alternating relation.

Abstract: A lead frame having protection against electrostatic discharge is disclosed. The lead frame having protection against electrostatic discharge includes a multiplicity of leads and an electrostatic discharge protection device. The electrostatic discharge protection device includes a conductive layer and a protection layer. The protection layer is arranged to contact a plurality of leads and is formed from an electrostatic discharge protection material, which insulates the leads from the conductive layer at voltages below a predefined threshold voltage and establishes an electrical connection between the leads and the conductive layer at voltages above the threshold voltage.

Abstract: A semiconductor device has a semiconductor chip with a plurality of pads, an inner lead which is connected to a plurality of pads by a plurality of bonding wires and which has a broken part portion, and a bonding wire which electrically connects broken ends of the broken portion of the inner lead and which has a fusing current smaller than that of the inner lead.

Abstract: An improved laser fusible link structure for semiconductor devices (200) and method of manufacturing thereof (10) is disclosed. A first conductive layer is patterned to create a laser fuse (202) and then covered with a first dielectric layer (212). An etch mask layer, in the preferred embodiment a second layer of polysilicon, is deposited and patterned to form a fuse etch mask (214) directly over the laser fuse (202). The fuse etch mask (214) has a width that is smaller than a minimum laser spot size, but large enough to protect the laser fuse (202) from fuse window over-etch, taking into account any potential misalignment between the laser fuse (202) and the fuse etch mask (214).

Abstract: An integrated circuit includes a conductive fusible link that may be blown by heating with laser irradiation, The integrate circuit comprises a silicon substrate; a first insulating layer; a fusible link on the first layer; a second insulating layer overlying the first layer and the fusible link; an opening through the second layer exposing the fuse; and a protective layer over the surfaces of the opening. A laser beam is irradiated through the opening and the protective layer to melt the fusible link. The protective layer is highly transparent to a laser beam and does not interfere with the laser melting (trimming) operation.

Abstract: A CMOS IC device operating at a frequency of 300 MHz or higher includes a power supply wiring for interconnecting one of circuit elements and a power supply pad, and a phase-shifting split wiring connected to the power supply wiring and not directly connected to any circuit elements, only for producing a noise phase difference between noises on the power supply wiring and the phase-shifting split wiring. A signal entering from the phase-shifting split wiring has a phase different from the phase of a signal transmitted on the power supply wiring to thereby reduce spike noises.

Abstract: The present disclosure sets forth an improved integrated circuit in which circuit elements, adjacent to a fuse, are protected by barriers positioned adjacent the fuse. In the improved integrated circuit the barriers are non-frangible, high melting point structures buried in the passivating layer, covering a wiring layer containing a fuse, and are between the fuse and adjacent circuit elements in the wiring layer structures. Also taught is a method of protecting circuit elements adjacent a fuse comprising the steps of depositing an insulating layer on the surface of a semiconductor device having active regions therein, forming a plurality of fuses and circuit elements in said layer, coating said fuses and elements with a second insulating layer, patterning said second insulating layer to form grooves between each of said fuses and any adjacent fuse or circuit element, and depositing a high melting point and non-frangible material in said grooves.

Abstract: A fusible link device disposed on a semiconductor substrate for providing discretionary electrical connections. The fusible link device of the invention includes a silicide layer and a polysilicon layer formed on the silicide layer and has a first un-programmed resistance. The silicide layer agglomerates to form an electrical discontinuity in response to a predetermined programming potential being applied across the silicide layer, such that the resistance of the fusible link device can be selectively increased to a second programmed resistance.

Abstract: A passivation structure is formed using two passivation layers and a protective overcoat layer using two masking steps. The first passivation layer is formed over the wafer and openings are provided to expose portions of the pads for testing the device and fusible links. After testing and laser repair, a second passivation layer is formed over the wafer followed a deposit of the protective overcoat. The protective overcoat is patterned and etched, exposing the pads. The remaining portions of the protective overcoat are used as a mask to remove portions of the second passivation layer overlying the pads. Leads are then attached to pads and the devices are encapsulated for packaging.

Abstract: The present invention is a method and apparatus for programming a stack of segments wherein each segment includes a plurality of die which are interconnected through metal interconnects patterned on the surface of each segment Once the segments are arranged into a stack, the stack is connected to external circuits and each segment is addressed through control lines. Electrically conductive fuses on the segments are used as an interface between the control lines and the die. Segment level programming is performed on each segment by opening the conductive fuses on the segments in a predetermined pattern in order to route the control lines to each segment such that segments are uniquely addressed. After segment level programming, circuit board programming is performed so that any defective die found in the stack is logically replaced with replacement die in the stack.

Abstract: An electrical connection is provided between a 3-wire transmission line buried in a dielectric substrate and corresponding first, second and third conductive pads formed on a substrate surface. The 3-wire line includes first, second and third wires having a wire cross-sectional dimension. A tapered section connects each wire of the 3-wire line to a corresponding pad. Each tapered section increases in cross-sectional dimension from a first end connected to an end of the wire and a second end connected to a pad. The tapered sections provide a smooth transition of electromagnetic fields between the 3-wire line and the pads.

Abstract: A semiconductor fuse and method for fabricating the same An insulating layer is provided and a trench formed therein. A fusible link is then formed across the insulating layer and trench and conformal therewith. The link has a break region of minimum thickness and width at an intersection of a sidewall and bottom surface of the trench.

Abstract: A layout portion (20) has a first portion (25), and a second portion (55). In the first portion (25), a reference voltage line (27) is disposed between two V.sub.DD power supply lines (26, 30) for a first predetermined length, for providing capacitive coupling between V.sub.DD and a reference voltage. In the second portion (55), the reference voltage line (27) is disposed between two V.sub.SS power supply lines (28, 41) for a second predetermined length, for providing capacitive coupling between V.sub.SS and the reference voltage. The capacitive coupling stabilizes the reference voltage with respect to the power supply voltage, and reduces power supply noise due to lead inductance and changing current demand. In addition, the power supply lines (26, 28, 30, 41) are disposed half above an N-type region (22) and half above a P-type substrate (21) for reducing local transistor switching noise.

Abstract: A process and resulting product are described for forming an integrated circuit structure with horizontal fuses on an insulation layer formed over other portions of the integrated circuit structure by forming rectangular recesses in the insulation layer which are subsequently filled during a subsequent metal deposition step which also serves to fill with the same metal vias or contact openings which have been etched through the insulation layer. Subsequent planarization of the deposited metal layer down to the vias or contact openings, i.e. to remove the portions of the metal layer over the insulation layer, leaves the metal in the vias or contact openings and also leaves metal stringers on the sidewalls of the rectangular recess which then serve as fusible links (fuses) which are then connected to one or more metal lines thereafter formed on the insulation layer.

Abstract: An improved structure and method for forming an integrated circuit guard ring which prevents contamination/moisture from diffusing through a fuse opening, in the insulating layer(s), to device areas, is described. A first insulating layer is formed over portions of the substrate. A gate insulating layer is formed surrounding the first insulating layer. The first ring surrounds a fuse area--including the area where the fuse will be cut by a laser or burned by a current. A first dielectric layer is formed over the substrate surface. A first passivation layer is then formed over the first insulating layer. A first opening is formed through the first passivation layer and first dielectric layer over the first ring. A fuse is formed over the first passivation layer over the fuse area and a second ring of water impervious material is formed on the first ring through the first opening. The first and second rings form a moisture impervious seal.

Abstract: Unsingulated dies on a wafer may be individually electronically selected using various "electronic mechanisms" on the wafer. Conductive lines extend on the wafer from the electronic mechanism to the individual dies. The conductive lines may be provided in sets of two or more, such as for providing discrete power and ground connections from the external equipment to the individual dies. Redundant conductive lines may be provided to ensure against "open" faults. Diode and/or fuses may also be provided in conjunction with the conductive lines to ensure against leakages and shorts. Redundant electronic selection mechanisms may also be provided.

Abstract: Method and apparatus for interconnecting integrated circuits (ICs) are described. The invented lattice preferably is formed in a plural-layer structure whereby each required interconnect signal has one or more dedicated layers of a planar, thin-film conductor that is coextensive with the substrate. Thousands of such horizontal layers are vertically stacked in the structure, each being shielded by voltage or ground planes and each being insulated by layers of insulative dielectric material. A regular array of vertical pillars is provided in the substrate, each pillar effectively providing an inner conductor either electrically connected with a conductive layer or electrically insulated therefrom by an insulative region. The columns extend from the top of the substrate on which the ICs are mounted through to the bottom surface of the bottom layer.

Abstract: A method for creating a MOS-type capacitor structure in function blocks or integrated circuits. Each block or cell is provided with capacitors for decoupling purposes under the board metal supply lines without requiring any extra silicon surface. The buried capacitors can be designed under any board conductor path or on a chip made of a semiconductor material.

Abstract: Ground lines 2 are disposed so as to sandwich a power supply line 1. A gate oxide film 3 and a gate 4 are formed below the power supply line 1. An n-type area 8 is formed adjacent to the end of the gate oxide film to set the ground potential thereto. A p-type area 9 is formed at most of the remaining part below the ground line to make it contact the substrate. Since the potential of the gate equals that of the power source, an inversion layer is formed below the oxide film, where the ground potential results through the n-type area. By sandwiching the gate oxide film between the gate and the inversion layer, a capacitor is formed.

Abstract: A programmable integrated circuit for forming conductive links includes a heat-generating programming structure through which current flows upon application of a programming voltage to heat the region around the programming structure. A programmable link structure including two conductors separated by a transformable insulator is in thermal communication with the programming circuit. When current flows through the programming circuit, the programmable link structure is heated. The heat causes the transformable insulator to break down such that a permanent conductive link is formed between the two conductors of the programmable link structure. During programming, a programming conductor is cut symmetrically about the programming structure.

Abstract: A polysilicon interconnect is formed on a microelectronic circuit substrate for conducting signals from a driver to a non-polycrystalline silicon contact which has higher impedance than the interconnect. A plurality of electronic "speed bumps" are spaced along the interconnect for disturbing or disrupting signals propagating along the interconnect toward the contact and thereby reducing undesirable back reflection and ringing. The speed bumps can include capacitance altering elements in the form of dielectric strips, or resistance altering elements in the form of low resistance doped areas or high resistance amorphous areas. The speed bumps can include first and second elements having different values of capacitance or resistance which are spaced along the interconnect in alternating relation.

Abstract: The conductor 15 to be connected to the doped region 12 of the substrate 11 has an edge 15a at which the laser beam 20 is aimed, regulated such as to definitively create a zone of low electrical resistance 19 in the dielectric layer 13 that separates the conductor from the doped region. The invention is particularly applicable to programming by laser of read only memories and defective integrated circuits with a view to correcting them.

Abstract: A power source noise suppressing type semiconductor device has: a semiconductor chip formed therein with a first circuit and a second circuit, the semiconductor chip having a plurality of pads on the surface thereof, the pads including at least a first circuit pad electrically connected to the first circuit and a second circuit pad electrically connected to the second circuit; a plurality of leads including at least one power source lead, each of the plurality of leads having an inner lead and an outer lead; and a plurality of bonding wires for electrically connecting the pad to the inner lead of the lead, the first circuit pad being connected to a first connection point of the inner lead of the power source lead by a bonding wire, the second circuit pad being connected to a second connection point of the inner lead of the power source lead by a bonding wire, and the first and second connection points being spaced apart by a distance which allows the mutual inductance between the first and second connection p

Abstract: The size of a fusible link (22 C.sub.F) created from part of a metal layer (22) is controlled by an oxidation performed in a deposition chamber that is also used for depositing a dielectric layer (30) over the fuse structure. The metal layer serves as a diffusion barrier between semiconductor material (14 and 16) and another metal layer (24).