Abstract: A field programmable gate array, comprises: a plurality of circuit blocks each having logic circuits; at least one spare circuit block having logic circuits; a set of interconnections including at least one interconnection for connecting at least one of the circuit blocks and the at least one spare circuit programmably; and at least one connecting element disposed on the interconnection of the set of interconnections which turns its status from a turned-on state to a turned-off state or vice versa when programmed. When any one of the circuit blocks is defective, since the defective circuit block can be replaced with the spare circuit block, it is possible to retain any desired functions of the logic circuits by programming the connecting means, thus improving the production yield of the field programmable gate array and thereby reducing the manufacturing cost thereof.

Abstract: The present disclosure sets forth an improved integrated circuit in which circuit elements, adjacent to a fuse, are protected by barriers positioned adjacent the fuse. In the improved integrated circuit the barriers are non-frangible, high melting point structures buried in the passivating layer, covering a wiring layer containing a fuse, and are between the fuse and adjacent circuit elements in the wiring layer structures.Also taught is a method of protecting circuit elements adjacent a fuse comprising the steps of depositing an insulating layer on the surface of a semiconductor device having active regions therein, forming a plurality of fuses and circuit elements in said layer, coating said fuses and elements with a second insulating layer, patterning said second insulating layer to form grooves between each of said fuses and any adjacent fuse or circuit element, and depositing a high melting point and non-frangible material in said grooves.

Abstract: A monitor circuit provided in a chip in which a semiconductor integrated circuit is formed. Connection mechanisms and disconnection mechanisms are connected in series in wirings connected to the monitor circuit. Before using the semiconductor integrated circuit, in the state that the connection mechanisms are opened, the monitor circuit is tested without conducting the monitor circuit to the semiconductor integrated circuit. In the case of using the semiconductor integrated circuit, the connection mechanisms are written to close them, so that the monitor circuit is connected to the semiconductor circuit main body and is thus driven. Further, after using the semiconductor integrated circuit, the monitor circuit is separated from the semiconductor integrated circuit by writing the disconnection mechanisms, to be investigated for the characteristic.

Abstract: An electrically blowable fuse structure usable with organic insulators in microelectronic parts is provided. The fuse structure is made of a first heat resistant member, a fusing element and a second heat resistant member. The heat resistant members are in substantial contact with the fuse and thermally insulate the fuse from the organic insulator. The ends of each fuse are electrically connected to a pair conductors.

Abstract: Disclosed are a semiconductor integrated circuit device and methods for production thereof. An embodiment of the invention is a semiconductor chip that comprises fuses constituting part of redundancy circuits formed therein, the fuses being made of the same ingredients as those of a CCB bump substrate metal. The fuses are patterned simultaneously during the patterning of the CCB bump substrate metal. This involves forming the fuses using at least part of the ingredients of an electrode conductor pattern in the chip. The cutting regions of the fuses are made of only one of the metal layers constituting the substrate. The principal plane of the semiconductor chip has a fuse protective film formed over at least the cutting regions of the fuses for protection of the latter. In operation, a switch MOSFET under switching control of a redundancy signal is used to select one of two transmission paths, one carrying an address signal or a decode signal, the other carrying a reference voltage.

Abstract: At least one fusing electrode charging electrode portion is connected to an intermediate portion of a fuse body of a fuse that has the fuse body and connecting end electrode portions provided at both ends thereof. A fusing voltage for fusing the fuse is charged through this fusing voltage charging electrode portion. It allows the concentration of a current at a specific portion of the fuse body to assure fusing of the fuse body at the specified portion. In addition, it is not necessary to increase the overall resistance of the fuse, no problem will arise even when the fuse, and is used in the circuit.

Abstract: A programmable integrated circuit for prototyping applications including a first patterned metal layer, an insulation layer formed over the first metal layer and a second patterned metal layer formed over the insulation layer, the first and second patterned metal layers being formed with selectably removable regions, the insulation layer being formed with apertures overlying at least some of the selectably removable regions, and there being formed over the selectably removable regions a coating comprising a layer of a dielectric material of high laser radiation absorption coefficient.

Abstract: The present invention provides a multilayer ceramic package, which comprises a conductive layer, formed like a square layer, applying a power voltage V.sub.DD or a ground voltage V.sub.SS to a semiconductor device, and having a square hole in its central portion, a plurality of inner leads connected to the conductive layer at the inner portion of the conductive layer, and a plurality of outer leads connected to the conductive layer at the outer portion of the conductive layer, wherein if a first contact point between the inner lead and the conductive layer, a second contact point between the outer lead and conductive layer, a distance between adjacent two first contact points is C.sub.1, a distance between adjacent two second contact points is C.sub.2, a shortest distance from the first contact point to the second contact point is h, both C.sub.1 /h and C.sub.2 /h are 3/8 or less.

Abstract: In an external lead terminal 5 of a transistor module, an intermediate terminal portion 6 and an external lead terminal 8 are conductively connected to each other via a U-shaped intermediate terminal portion 7 having a curved portion 7b. Connected in parallel with this intermediate terminal portion 7 is a shortcircuit wire 9 having a larger electric resistance and a smaller inductance than the same. For this reason, even if a current is reduced suddenly in a state in which the current is flowing from the external terminal portion 8 to the intermediate terminal portion 6 via the intermediate terminal portion 7, the current shifts to the shortcircuit wire 9 side, so that a transient voltage is low. Consequently, it is provided a transistor module capable of reducing a transient voltage without being subjected to restrictions in the size of an external lead terminal while maintaining a high level of reliability.

Abstract: An easily circuit-programmable semiconductor device which comprises a dynamic random access memory (DRAM) unit, a redundancy circuit and a connection between them, the DRAM unit having as a capacitor a dielectric film made of a silicon oxide/silicon nitride/silicon oxide composite layer and the connection having, as a member for programming the redundancy circuit, an electrically breakable dielectric film made of a silicon oxide/silicon nitride/silicon oxide composite layer.

Abstract: A method is provided for writing into a semiconductor memory which includes a MOS transistor formed on a semiconductor substrate and an anti-fuse formed of an insulating film and an upper electrode on a drain of the MOS transistor. The method includes the steps of applying a first voltage between the upper electrode of the anti-fuse and a source of the MOS transistor to cause dielectric breakdown of the insulating film of the anti-fuse, with the MOS transistor turned on; and applying a second voltage between the upper electrode of the anti-fuse and the semiconductor substrate so that a larger amount of current flows than the amount of current required for breaking down the insulating film of the anti-fuse.

Abstract: A submicron-width fuse element is disclosed that protects peripheral DRAM chip devices from low current failures below the range of metal fuse elements. In a specific application, the fuse elements are used to protect a DRAM chip from dielectric failure of voltage supply filtering capacitors. A low cross-section and length allows minimum space for the element.

Abstract: A selectably customizable semiconductor device including a first metal layer disposed in a first plane and including first elongate strips extending parallel to a first axis, a second metal layer disposed in a second plane generally parallel to and electrically insulated from said first plane and including second elongate strips extending parallel to a second axis, the second axis being generally perpendicular to the first axis, whereby a multiplicity of elongate strip overlap locations are defined at which the elongate strips of the first and second metal layers overlap in electrical insulating relationship;the second metal layer comprising a plurality of fusible conductive bridges joining adjacent pairs of the second elongate strips, each of the fusible conductive bridges including first and second fusible links;a via being defined between the first and second metal layers at a location along each of the fusible conductive strips intermediate the first and second fusible links;the fusible conductive bridges

Abstract: A fuse link includes a fuse portion and a exothermic charge adjacent the fuse portion for blowing the fuse portion upon application of a triggering current to the fuse link.

Abstract: An integrated circuit device is disclosed. The device includes a first leadframe power supply bus and a second leadframe power supply bus that each have portions separate from and adjacent to one another that lie between a first plurality of leadfingers and a second plurality of leadfingers. An electronic device is connected to the first leadframe power supply bus and to the second leadframe power supply bus. Another electronic device can be connected to the first leadframe power supply bus and to the second leadframe bus. Exemplary of the electronic devices are a de-coupling capacitor and a capacitor for high frequency noise suppression. A semiconductor die is attached to the power supply busses. A substance encapsulates the components so that an integrated semiconductor chip is formed. A method of making an integrated circuit device is also disclosed.