Abstract: A method of making a semiconductor device is provided. The method includes the following steps. First, a semiconductor chip is mounted on a lower conductor, with first solder material applied between the chip and the lower conductor. Then, an upper conductor is placed on the chip, with second solder material applied between the chip and the upper conductor. Then, the first and the second solder materials are heated up beyond their respective melting points. Finally, the first and the second solder materials are allowed to cool down, so that the first solder material solidifies earlier than the second solder material.

Abstract: A semiconductor integrated circuit device, and method of manufacturing the same, having a conventional-type lead frame with the die paddle removed. In particular, the die paddle is replaced with a section of tape that is supported by the ends of the lead fingers. The semiconductor die is attached to the tape so that it may be wire bonded to the lead fingers. The tape contains at least one slot to allow for expansion and/or contraction of the tape due to various temperatures experienced during the manufacturing process so that the tape does not wrinkle or warp to alter the position of the die.

Abstract: A semiconductor device enabling word lines to be arranged at close intervals, comprising a plurality of memory transistors arranged in an array and a plurality of word lines serving also as gate electrodes of memory transistors in a same row, extending in a row direction, and repeating in a column direction, where insulating films are formed between the plurality of word lines to insulate and isolate the word lines from each other and where a dimension of separation of word lines is defined by the thickness of the insulating films.

Abstract: A semiconductor die package is disclosed. In one embodiment, the die package includes a semiconductor die including a first surface and a second surface, and a leadframe structure having a die attach region and a plurality of leads extending away from the die attach region. The die attach region includes one or more apertures. A molding material is around at least portions of the die attach region of the leadframe structure and the semiconductor die. The molding material is also within the one or more apertures.

Abstract: In a leadframe for an LGA package, a lead member is pressed downward to form a land lead with a half-cut portion and a land portion. The land portion, whose bottom will be a land electrode, is inclined at a predetermined angle and the bottom of the land portion is made lower than that of a lead. Thus, in a resin molding process using a seal sheet, the land electrode is forced into, and strongly adhered to, the seal sheet when pressure is applied through dies, and no resin encapsulant reaches the land electrode. As a result, no resin bur will be left on the land electrode of the land lead.

Abstract: In a lead frame which has second tie bars in the vicinity of plastic packages first notches are formed along first edges of the second tie bars (in areas defined on both sides of the inner leads and to come into contact with a punch during the tie bar cutting step). The first notches prevent troubles associated with close arrangement of the second tie bars and the plastic packages. In addition, second notches are provided along second edges of the second tie bars. These second notches are designed to receive the tips of outer leads which extend from neighboring plastic packages of the lead frames.

Abstract: A lead frame for semiconductor electronic parts with a landed semiconductor chip has a body part formed with a molding resin by landing the semiconductor chip on an island, connecting a plurality of leads to respective electrode pads of the semiconductor chip via conductors and sealing the semiconductor chip with the molding resin and a junction to a mounted board formed by exposing the lower faces of the leads to the lower face of the body. Recessed mold resin engaging cavities are provided at both side faces of each of the leads. Otherwise, each of the leads is formed in inverted trapezoidal cross section, with its upper face being wider than its lower face. Protruded thrust extension members which make the lower faces of the leads extend to the extending direction of the leads and which are thinner than the leads are provided at the end of each of the leads.

Abstract: A semiconductor package comprising a leadframe which includes a die paddle having an opening formed therein. In addition to the die paddle, the leadframe includes a plurality of leads, at least one of which is disposed in spaced relation to the die paddle. The remaining leads are attached to the die paddle and extend therefrom. Electrically connected to the die paddle is the source terminal of a semiconductor die which also includes a gate terminal and a drain terminal. The gate terminal is itself electrically connected to the at least one of the leads disposed in spaced relation to the die paddle. A package body at least partially encapsulates the die paddle, the leads, and the semiconductor die such that portions of the leads and the drain terminal of the semiconductor die are exposed in the package body.

Abstract: A resin-encapsulated package includes a semiconductor IC chip, in which the ratio of the size of the semiconductor IC chip to the package size of the resin-encapsulated package including the semiconductor IC chip is large to miniaturize the resin-encapsulated package. The resin-encapsulated package is capable of dealing with increase in the operating speed of the semiconductor IC chip. The resin-encapsulated package includes a semiconductor IC chip (110) sealed in a resin molding, and a lead member (130B) having an arrangement of a plurality of discrete terminal sections (130A). Each of the terminal sections has inner terminal parts (131) to be electrically connected to terminals (115) of the semiconductor IC chip, outer terminal parts (132) to be connected to external circuits, and connecting parts (133) interconnecting the inner and the outer terminal parts.

Abstract: A semiconductor device for supplying a signal to an electro-optical device which displays a two-dimensional image, includes first terminals which are formed along a first side of the semiconductor device in a longitudinal direction and have a length L1 in a direction intersecting the longitudinal direction at right angles; and second terminals which are formed along a second side intersecting the first side at right angles and have a length L2 which is greater than the length L1 in the longitudinal direction.

Abstract: A leadless leadframe semiconductor package includes a plurality of contacts, at least some of which have integrally formed stems that extend to the peripheral surface of the package. These stems have heights and widths less than the heights and widths of their corresponding contacts. A molded cap encapsulates the stems and the contacts to leave contact surfaces of the contacts exposed on the bottom surface of the package. Another aspect of the invention pertains to a leadless leadframe panel assembly having a conductive substrate panel that has at least one array of device areas, which has a plurality of tie bars and a plurality of contacts. The contacts have integrally formed stems that extend towards and connect to one of the tie bars. The stems have widths and heights that are less than the widths and heights of their corresponding contacts.

Abstract: A semiconductor device assembly package includes a semiconductor device having components thereon which are generic to a variety of applications by manipulation of the pinout configuration. The lead frame includes redundant leads for connection to the semiconductor device, as desired. The semiconductor device may include redundant wire bond pads, each redundant pair including one pad on a lateral edge and one pad on a non-lateral edge of the die. In applications requiring less than all of the available leads, the pinout configuration of the leadframe is adjusted to use the extra space from unused NC leads and missing pins for providing wider, shorter leads with reduced inductance, and wider paddle arms for reduced bending and breakage.

Abstract: Electrically, mechanically, and thermally enhanced ball grid array (BGA) packages are described. An IC die is mounted in a centrally located cavity of a substantially planar first surface of a stiffener. The first surface of a substrate is attached to a substantially planar second surface of the stiffener. The second surface of the stiffener is opposed to the first surface of the stiffener. A centrally located protruding portion on the second surface of the stiffener is opposed to the centrally located cavity. The protruding portion extends through an opening in the substrate. A wire bond is coupled from a bond pad of the IC die to a contact pad on the first surface of the substrate through a through-pattern in the stiffener. The through-pattern in the stiffener is one of an opening through the stiffener, a recessed portion in an edge of the stiffener, a notch in an edge of the recessed portion, and a notch in an edge of the opening.

Abstract: Two dice may be provided within a single package so that one pin and associated leadfinger may be coupled to bond pads on different dice. This may mean that two different bond pads on different dice are coupled, for example by wirebonding, to the same leadfinger. An adhesive tape may be secured so as to bridge the two dice. One or more conductive traces are formed on the upper side of the adhesive tape and adhesive is provided on the other side to secure the tape to the two dice. As a result, wire bonds may be made from a pad on one die to a trace and then from the opposite side of the trace to a leadfinger. At the same time, a wire bond may be made from a pad on the other die to the same leadfinger. In another embodiment, an adhesive tape with a conductive trace on it may be used as a wire bond bridge to join spaced bond pads on a single chip.

Abstract: Prepackaged chips, such a memory chips, are vertically stacked and bonded together with their terminals aligned. The exterior lead frames are removed including that portion which extends into the packaging. The bonding wires are now exposed on the collective lateral surface of the stack. In those areas where no bonding wire was connected to the lead frame, a bare insulative surface is left. A contact layer is disposed on top of the stack and vertical metallizations defined on the stack to connect the ends of the wires to the contact layer and hence to contact pads on the top surface of the contact layer. The vertical metallizations are arranged and configured to connect all commonly shared terminals of the chips, while the control and data input/output signals of each chip are separately connected to metallizations, which are disposed in part on the bare insulative surface.

Abstract: A dual gauge lead frame 36 is provided, including at least one mating surface 14 and a plurality of terminal arms 16 formed into a flat circuit surface 12 having a first gauge 32. Each of the plurality of terminal arms 16 includes a fold over terminal arm portion 28 folded over and coined into a base terminal arm portion 26 to form a plurality of end posts 30. The plurality of end posts 30 form a second gauge 34.

Abstract: A semiconductor package includes a chip mounting pad having a peripheral edge. The package further includes a semiconductor chip attached to the chip mounting pad. The package further includes a plurality of leads. Each lead includes an inner end and an opposing distal end. Each inner end is disposed adjacent the peripheral edge in spaced relation thereto and vertically downset with respect to each respective distal end. The package further includes at least one isolated ring structure disposed along the peripheral edge between the peripheral edge and the inner ends of the leads in spaced relation thereto. The ring structure is electrically connected to the semiconductor chip and an inner end of at least one of the leads.

Abstract: A first semiconductor chip 102 includes an integrated circuit formed on a face which is shown upwards in FIG. 2. A second semiconductor chip 103 includes an integrated circuit formed on a face which is shown downwards in FIG. 2. Between the first semiconductor chip 102 and the second semiconductor chip 103, a non-conductive die pad 107 is interposed. The die pad 107 is provided with connection members 110 protruding from the first semiconductor chip 102 and the second semiconductor chip 103. The connection members 110 are plated on their surfaces so as to be electrically conductive. The integrated circuit on the first semiconductor chip 102 and the integrated circuit on the second semiconductor chip 103 are interconnected by two inter-chip connection wires 104a and 104b, via the connection members 110.

Abstract: Two dice may be provided within a single package so that one pin and associated leadfinger may be coupled to bond pads on different dice. This may mean that two different bond pads on different dice are coupled, for example by wirebonding, to the same leadfinger. An adhesive tape may be secured so as to bridge the two dice. One or more conductive traces are formed on the upper side of the adhesive tape and adhesive is provided on the other side to secure the tape to the two dice. As a result, wire bonds may be made from a pad on one die to a trace and then from the opposite side of the trace to a leadfinger. At the same time, a wire bond may be made from a pad on the other die to the same leadfinger. In another embodiment, an adhesive tape with a conductive trace on it may be used as a wire bond bridge to join spaced bond pads on a single chip.

Abstract: A semiconductor element provided in a semiconductor device includes a built-in contact-type sensor having a sensor area formed on a circuit formation surface. Connection terminals are provided in an area other than the sensor area. A wiring board is connected to the connection terminals of the semiconductor element so that an end surface of the wiring board is positioned on the circuit formation surface. A protective resin part covers a part extending from the end surface of the wiring board to the circuit formation surface so as to protect a connection portion between the semiconductor element and the wiring board.

Abstract: A surface-mountable light emitting diode structural element in which an optoelectronic chip is attached to a chip carrier part of a lead frame, is described. The lead frame has a connection part disposed at a distance from the chip carrier part, and which is electrically conductively connected with an electrical contact of the optoelectronic chip. The chip carrier part presents a number of external connections for improved conduction of heat away from the chip. The external connections project from a casing and at a distance from each other.

Abstract: A semiconductor integrated circuit for driving an LCD. The circuit has a shift register circuit portion (3) and a driver circuit portion (7). All the stages of the shift register circuit portion are formed adjacently to the outer fringe of a chip (30). All the stages of the driver circuit portion are formed along the central line (L1) of the chip. Signal electrodes (81-8n) for individual bits are formed in a belt-like region (33) extending in the X-direction along the central line (L1) and adjacently to the driver circuit portion. Output electrodes are arranged in a zigzag fashion. Since the output electrodes overlap with each other in the Y-direction, the width of the chip can be suppressed. Power supply voltages (VH, V0, V2, V3, V5) are applied to the driver circuit portion (7) through leads (36-40). These leads are connected so as to form a closed loop making one revolution around the output electrodes (81-8N) located in the center of the chip.

Abstract: A leadframe configuration for a semiconductor device that has a die attach paddle with paddle support bars. In addition, clamp tabs extend outwardly from lesser supported locations of the paddle to underlie a conventional lead clamp. The clamp tabs are formed as an integral part of the paddle. Normal clamping during die attach and wire bonding operations prevents paddle movement and enhances integrity of the die bond and wire bonds.

Abstract: A semiconductor die mounted between an X-lead frame and a support structure without bonding wires or straps. A power enhancement mode junction field effect transistor (JFET) die having a top surface defining a drain, and a bottom surface having a first metalized region defining a source and a second metalized region defining a gate, is positioned on a support structure. An X-lead frame is bonded to the support structure such that electrical contact is made with an external lead. Angular projections from the X-lead frame make contact with the top surface of the JFET, hold the die in place on the support structure, and form electrical continuity between the JFET drain and the external lead. A construction on the surface of the support structure is positioned directly under the source region on the bottom of the JFET die and forms electrical continuity between the JFET source and a second external lead.

Abstract: A flexible interconnect substrate (1) comprises a tape-shaped base substrate (10) and a plurality of interconnect patterns (20) formed on the base substrate (10). The base substrate (10) bas a plurality of first regions (44) met to be punched out, and second regions (45) between those first regions (44). Each of the second regions (45) has the material that forms the base substrate (10) is present in a central portion in the widthwise direction of the base substrate (10), and a low-bending-resistance portion (40) for ensuring that the second region (45) bends more readily than the adjacent first regions (44) in a direction in which the longitudinal axis of the base substrate (10) bends.

Abstract: A stackable ball grid array (BGA) or fine ball grid array (FBGA) semiconductor package particularly suitable for board-on-chip or chip-on-board applications in which a low profile BGA or FBGA semiconductor package is needed. Exemplary BGA or FBGA semiconductor packages generally comprise a substrate having a semiconductor device attached to a selected surface thereof; Burn in and testing of the semiconductor chip may be performed by electrically contacting selected test pads by complementary arranged test probes in lieu of directly contacting and perhaps harming the connective elements. Upon burning in and testing of the semiconductor device, the test pads may be disassociated from the substrate to decrease the foot print of the semiconductor package.

Abstract: A stackable ball grid array (BGA) or fine ball grid array (FBGA) semiconductor package particularly suitable for board-on-chip or chip-on-board applications in which a low-profile BGA or FBGA semiconductor package is needed. The stackable ball grid array (BGA) or fine ball grid array (FBGA) provides a semiconductor package that is capable of being burned-in and tested in a more efficient and cost-effective manner than prior known BGA or FBGA semiconductor packages. A high-density, low-profile memory module incorporating a plurality of the disclosed BGA or FBGA semiconductor packages in a stacked arrangement is further disclosed.

Abstract: A micro leadframe package employing an oblique etching method is disclosed. The micro leadframe package includes a semiconductor chip, an oblique-etched micro leadframe (MLF) having a die pad on which the semiconductor chip is mounted via adhesive means, leads formed along outer sides of the die pad, and tie bars for supporting four corners of the die pad, wires for connecting the semiconductor chip with the leads of the MLF, and an epoxy molding compound (EMC) for encapsulating the semiconductor chip, the MLF, and the wires.

Abstract: A lead frame including a first set of leads in a first plane and a second set of leads in a second plane offset vertically from the second plane. The leads in the first and second planes are offset from each other by a lead width.

Abstract: In a non-leaded type semiconductor device, a tab, tab suspension leads, and other leads are exposed to one surface of a seal member. A semiconductor element is positioned within the seal member and fixed to a surface of the tab with an adhesive. The tab is formed larger than the semiconductor element so that outer peripheral edges of the tab are positioned outside outer peripheral edges of the semiconductor element. A groove is formed in the tab surface portion positioned between the area to which the semiconductor element is fixed and wire connection areas to which the wires are connected, the groove being formed so as to surround the semiconductor element fixing area, thereby preventing peeling-off between the tab to which the semiconductor element is fixed and the resin which constitutes the package.

Abstract: A leadframe for use with integrated circuit chips comprising a base metal having a plated layer of nickel fully covering said base metal; a plated layer of pure tin on said nickel layer, selectively covering areas of said leadframe intended for attachment to other parts; and a plated layer of palladium on said nickel layer, selectively covering areas of said leadframe intended for bonding wire attachment.

Abstract: In a leadframe packaging structure, a leadframe includes a plurality of first leads, a plurality of second leads, and a die pad. The first leads define a chip-bonding region in which is arranged the die pad. The second leads extend and terminate into a plurality of contact pads in the chip-bonding region. An adhesive tape further is bonded on bottom surfaces of the contact pads. A chip is bonded on the die pad. At least a passive device is mounted between and electrically connects the contact pads. A plurality of bonding wires respectively connect the chip, the passive device, and the first and second leads. An encapsulant material encapsulates the chip, the passive device, and the bonding wires.

Abstract: A resin-encapsulated semiconductor device includes a die pad, a semiconductor chip mounted on the die pad, and a group of leads. The group of leads include at least three kinds of leads, including first, second and third leads. While the first lead and the third lead are connected to each other upon production of the lead frame, the first lead and the third lead are separated from each other in a subsequent step. Moreover, a thin metal wire for connecting an electrode of the semiconductor chip to the bonding pad of each lead, and an encapsulation resin for encapsulating the semiconductor chip, the leads, the thin metal wire, etc., are provided. The pad of each lead is exposed on a surface of the encapsulation resin so that the pad can function as an external terminal.

Abstract: The semiconductor integrated circuit device comprises a planar leadframe having lead segments arranged in alternating order into first and second pluralities, the segments having their inner tips near the chip mount pad and their outer tips remote from the mount pad. The outer tips have a solderable surface. All outer tips are bent away from the leadframe plane into the direction towards the intended attachment locations on an outside substrate such that the first segment plurality forms an angle of about 70±1° from the plane and the second segment plurality forms an angle of about 75±1° (see FIG. 4). Consequently, the outer tips create a staggered lead pattern suitable for solder attachment to an outside substrate.

Abstract: A semiconductor package is comprised of a semiconductor device 4 mounted on a die-pad 3, a wire 6 for electrically connecting some electrodes of the semiconductor device 4 and terminals 5 of lead frame, wires 8 for bonding the other electrodes of semiconductor device to the surface of die-pad for grounding, and molding compound 7 for encapsulating the outer area of semiconductor device 4 under a state where the back face of die-pad 3. The lower face and side face of terminals 5 are exposed, wherein portions plated with silver for connecting of wires on the surface of the die-pad are formed at points positioned between a peripheral edge of the die-pad and an outer edge of the semiconductor device while leaving spaces from both the edges. The adhesion of die-pad 3 to bonding compound 7 is improved to avoid the occurrence of wires coming-off even if heat is applied to the contact points of die-pad 3 to wires 8 when mounting semiconductor package on a printed circuit board.

Abstract: The semiconductor device is composed of a semiconductor die 1, and a lead frame 7 equipped with a die paddle 2 for mounting the semiconductor die and lead terminals 3, 4, 5, 6 for external connections, with the die paddle 2 and die paddle-side ends of the lead terminals 3, 4, 5, 6 being encapsulated together in a plastic package. The die paddle 2 is provided with links 14, 15, 16 which extend one by one between the lead terminals 3, 4, 5, 6. The extreme end of each link 14, 15, 16 is joined with adjacent lead terminals. The semiconductor die 1 is electrically connected with some of the lead terminals which correspond to a wiring pattern of an external circuit. Any of the links 14, 15, 16 uninvolved in the electrical connections is cut off.

Abstract: A lead frame for a semiconductor device. The semiconductor device has a sheet with oppositely facing sides and a thickness between the oppositely facing sides. The sheet has first and second unit lead frames. Each unit lead frame has a support for a semiconductor chip and at least one lead space from the support. The sheet has a tie bar network which connects a) the support to the at least one lead on each of the first and second lead frames and b) the first and second lead frames, each to the other. The sheet has a dividing line along which the sheet can be cut to separate the first and second lead frames from each other. The tie bar network consists of at least one tie bar extending along a substantial length of the dividing line. The support has a first thickness between the oppositely facing sides of the sheet. The at least one tie bar has a second thickness between the oppositely facing sides of the sheet over a substantial length of the dividing line that is less than the first thickness.

Abstract: A method of making a Fe-Ni strip whose chemical composition comprises, by weight: 36% ≦Ni+Co≦43%; 0%≦Co≦3%; 0.05%≦C≦0.4%; 0.2%≦Cr≦1.5%; 0.4%≦Mo≦3%; Cu≦3%; Si≦0.3%, Mn≦0.3%; the rest being iron and impurities, the alloy having an elastic limit Rp0.2 more than 750 Mpa and a distributed elongation Ar more than 5%. The alloy is optionally recast under slag. The strip is obtained by hot-rolling above 950° C., then cold-rolling and carrying out a hardening treatment between 450° C. and 850° C., the hardening heat treatment being preceded by a reduction of at least 40%. The invention is useful for making integrated circuit support grids and electronic gun grids.

Abstract: A stackable ball grid array (BGA) or fine ball grid array (FBGA) semiconductor package particularly suitable for board-on-chip or chip-on-board applications in which a low-profile BGA or FBGA semiconductor package is needed. The stackable ball grid array (BGA) or fine ball grid array (FBGA) provides a semiconductor package that is capable of being burned-in and tested in a more efficient and cost-effective manner than prior known BGA or FBGA semiconductor packages. A high-density, low-profile memory module incorporating a plurality of the disclosed BGA or FBGA semiconductor packages in a stacked arrangement is further disclosed.

Abstract: A semiconductor plastic package, more particularly a preferred package structure and method for making a BGA package. A resin sealed BGA package where a supporting frame which fixedly supports semiconductor parts; i.e., an IC chip, a circuit board, or a circuit film, is sealed with resin, using a mold, which is composed of an upper mold half and a lower mold half with the lower mold half having a plurality of projections, one at a position corresponding to each of the external terminals. The mold has a divisional structure which has an air vent between the divisional elements thereof.

Abstract: A semiconductor component includes a non-leaded leadframe (100, 200, 300) having at least one interior electrical contact (110) and a plurality of exterior electrical contacts (120), a semiconductor chip (410) mounted onto the leadframe, a mold compound (510) disposed around the semiconductor chip, a cavity (520) in the mold compound exposing a portion of the at least one interior electrical contact, an electronic chip (710) mounted in the cavity, and a cover (810) disposed over the cavity. In one embodiment, the leadframe is part of an array including a plurality of leadframes spaced apart from each other by a plurality of dam bars.

Abstract: A leadless leadframe semiconductor package comprising a plurality of contacts, which have contact surfaces on the bottom surface of the package. At least some of the contacts have integrally formed stems that extend outward to the peripheral surface of the package. These stems have heights and widths less than the heights and widths of their corresponding contacts. A molded cap encapsulates at least a portion of the die, the stems and the contacts. The molded cap leaves the contact surfaces of the contacts exposed on the bottom surface of the package, leaves a peripheral surface of the stems exposed on the peripheral surface of the package, and covers a bottom surface of each of the stems. Another aspect of the invention pertains to a leadless leadframe panel assembly having a conductive substrate panel that has at least one array of device areas, each array of device areas having a plurality of tie bars and a plurality of contacts.

Abstract: A lead end grid array semiconductor package comprises a leadframe having a plurality of leads. The leads extend outwardly from a chip paddle and have an outer end that defines an outer perimeter of the leadframe. A plurality of inner protrusions and outer protrusions are located on a lower surface of the leads. The outer protrusions communicate with the outer perimeter of the leadframe. An encapsulating material encapsulates the semiconductor chip and the conductive wires to form the semiconductor package. Solder balls are attached to a lower surface of the protrusions. The protrusions on the perimeter of the leadframe enable the semiconductor package to be positioned on a flat heat block when affixing the conductive wires to bond pads in the semiconductor chip. A ball of conductive material is affixed to the lower end of the protrusions to form a ball grid array.

Abstract: A lead frame includes a pair of guide rails separated at a predetermined space; at least one dam bar for connecting the pair of guide rails; a die paddle for mounting a semiconductor chip between the dam bar; a tie bar for supporting the die paddle; a plurality of leads each consisting of a first lead having a predetermined length extended from the dam bar between the dam bar and the die paddle, a second lead connected electrically to the first lead and formed bent in a first direction, and a third lead connected electrically to the second lead and formed bent in a second direction.

Abstract: The resin-sealed semiconductor device includes a die pad portion, a semiconductor element mounted on the die pad portion and having electrodes, a plurality of lead portions arranged with their respective tips facing the die pad portion, thin metal wires for connecting the electrodes of the semiconductor element to the lead portions, and a sealing resin for sealing the die pad portion, the semiconductor element, the lead portions and connection regions of the thin metal wires except a bottom surface of the die pad portion and respective bottom surfaces and terminal ends of the lead portions. The terminal ends of the lead portions are approximately flush with a side surface of the sealing resin. The die pad portion has a first recess formed in an outer periphery of the bottom surface thereof.

Abstract: In a leadframe for an LGA package, a lead member is pressed downward to form a land lead with a half-cut portion and a land portion. The land portion, whose bottom will be a land electrode, is inclined at a predetermined angle and the bottom of the land portion is made lower than that of a lead. Thus, in a resin molding process using a seal sheet, the land electrode is forced into, and strongly adhered to, the seal sheet when pressure is applied through dies, and no resin encapsulant reaches the land electrode. As a result, no resin bur will be left on the land electrode of the land lead.

Abstract: A device and method for increasing input/output from a die by making electrically conductive microvias connecting the integrated circuit with a backside of the die. The backside electrically conductive microvias connect an integrated circuit in the die to pads on the backside of the die. A superstrate is situated on top of the die and connects to the microvias using controlled collapse chip connections (C4) with a thermal interface material (TIM) surrounding the electrical connections. A superstrate lead system electrically connects the backside pads to wirebonds that connect with either the substrate or directly to the motherboard. Heat dissipates from the die via the TIM to the superstrate to a heat sink situated on top of the superstate.

Abstract: Memory chips containing multiple-bank memory devices are arranged to be mounted in a memory package with the major axis of the memory chip aligned substantially parallel with the major axis of its memory package. Memory devices of various embodiments contain banks of non-volatile flash memory cells and have access commands synchronized to a system clock. Data chip bond pads for coupling to data pins of a memory package are located in a first quadrant of the memory chip. Address chip bond pads for coupling to address pins of a memory package are located in an opposite quadrant of the memory chip.

Abstract: An image pickup device and a portable telephone reduced in planar dimension and thickness are provided. The image pickup device includes a circuit board provided with an opening portion and having an interconnection pattern formed of interconnections and an interface region disposed therein, and an image pickup element placed on the circuit board and having a light receiving portion. The interconnection pattern is placed in an outer frame portion on the lateral side of the opening portion, together with land portions as terminals of the respective interconnections, and extends to reach the interface region. At least one of the interconnections is placed between the land portions and the opening portion.

Abstract: In a lead frame which has second tie bars 4a2, 4b2 in the vicinity of plastic packages 15, first notches 1 are formed along first edges of the second tie bars 4a2, 4b2 (in areas defined on both sides of the inner leads 12a, 12b and to come into contact with a punch during the tie bar cutting step). The first notches 1 prevent troubles associated with close arrangement of the second tie bars 4a2, 4b2 and the plastic packages 15. In addition, second notches 2 are provided along second edges of the second tie bars 4a2, 4b2. These second notches 2 are designed to receive the tips of outer leads 13a, 13b which extend from neighboring plastic packages 15 of the lead frames 100a, 100b.