With Heat Sink Means Patents (Class 257/675)
  • Patent number: 10917972
    Abstract: According to one embodiment, a switching device includes a first switching element, a second switching element, and a holder. The first switching element includes a plurality of terminals. The second switching element includes a plurality of terminals and is provided apart from the first switching element in a thickness direction of the first switching element. The holder includes a holding member, a connection portion, and a conductor. The holding member is provided with a cavity to contain the first switching element. The cavity includes a bottom portion between the first switching element and the second switching element. The connection portion is provided on the holding member to face the cavity and is electrically connected to the second switching element. The conductor connects the connection portion and the terminals of the first switching element. The first switching element and the second switching element are connected in parallel.
    Type: Grant
    Filed: September 4, 2019
    Date of Patent: February 9, 2021
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventors: Hiroshi Ota, Hirofumi Omote
  • Patent number: 10910746
    Abstract: Sleds for operation in racks of data centers are disclosed herein. A sled includes a circuit board substrate, one or more physical resources, and one or more memory devices. The circuit board substrate has a top side and a bottom side arranged opposite the top side. The one or more physical resources are coupled to the top side of the circuit board substrate. The one or more memory devices are coupled to the bottom side of the circuit board substrate. Additionally, the sled includes a connector to electrically couple the one or more physical resources to the one or more memory devices.
    Type: Grant
    Filed: December 3, 2018
    Date of Patent: February 2, 2021
    Assignee: Intel Corporation
    Inventors: Russell Aoki, Aaron Gorius, Michael T. Crocker, Matthew J. Adiletta
  • Patent number: 10910297
    Abstract: In a general aspect, a method can include forming a first conductive metal layer including a common gate conductor, and coupling a plurality of semiconductor die to the common gate conductor of the first conductive metal layer where the plurality of semiconductor die include a first silicon carbide die and a second silicon carbide die. The method can include encapsulating at least a portion of the first conductive metal layer and the semiconductor die within an insulator where the first conductive metal layer includes a first conductive path between the common gate conductor and a die gate conductor of the first silicon carbide die, and a second conductive path between the common gate conductor and a die gate conductor of the second silicon carbide die. The first conductive path can have a length substantially equal to a length of the second conductive path.
    Type: Grant
    Filed: June 3, 2019
    Date of Patent: February 2, 2021
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Jerome Teysseyre, Maria Cristina Estacio, Seungwon Im
  • Patent number: 10896882
    Abstract: An electronic package and a method for fabricating the same are provided. The method includes bonding a portion of an inactive surface of an electronic component to a thermal conductive layer of a heat dissipating element, encapsulating the electronic component and the thermal conductive layer with an encapsulant, and forming a circuit structure on the encapsulant and electrically connecting the circuit structure to the electronic component. Since the heat dissipating element is bonded to the electronic component through the thermal conductive layer, the heat dissipating effect of the electronic package is improved.
    Type: Grant
    Filed: March 15, 2019
    Date of Patent: January 19, 2021
    Assignee: PHOENIX & CORPORATION
    Inventors: Shih-Ping Hsu, Che-Wei Hsu, Chih-Kuai Yang
  • Patent number: 10832995
    Abstract: A power module (10) having a leadframe (20), a power semiconductor (30) arranged on the leadframe (20), a base plate (40) for dispersing heat generated by the power semiconductor (30) and a potting compound (50) surrounding the leadframe (20) and the power semiconductor (30), that physically connects the power semiconductor (30) and/or the leadframe (20) to the base plate(40).
    Type: Grant
    Filed: July 17, 2019
    Date of Patent: November 10, 2020
    Assignee: Danfoss Silicon Power GmbH
    Inventors: Ronald Eisele, Frank Osterwald
  • Patent number: 10825748
    Abstract: Implementations of a semiconductor package may include: a substrate, a case coupled to the substrate, and a plurality of press-fit pins. The plurality of press-fit pins may be fixedly coupled with the case. The plurality of press-fit pins may have at least one locking portion that extends from a side of the plurality of press-fit pins into the case and the plurality of press-fit pins may be electrically and mechanically coupled to the substrate.
    Type: Grant
    Filed: November 2, 2016
    Date of Patent: November 3, 2020
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Yushuang Yao, Chee Hiong Chew, Atapol Prajuckamol
  • Patent number: 10825747
    Abstract: A method of manufacturing a packaged semiconductor device includes forming an assembly by placing a semiconductor die over a substrate with a die attach material between the semiconductor die and the substrate. A conformal structure which includes a pressure transmissive material contacts at least a portion of a top surface of the semiconductor die. A pressure is applied to the conformal structure and in turn, the pressure is transmitted to the top surface of the semiconductor die by the pressure transmissive material. While the pressure is applied, concurrently encapsulating the assembly with a molding compound and exposing the assembly to a temperature that is sufficient to cause the die attach material to sinter.
    Type: Grant
    Filed: September 20, 2017
    Date of Patent: November 3, 2020
    Assignee: NXP USA, INC.
    Inventors: Li Li, Jaynal A. Molla, Lakshminarayan Viswanathan
  • Patent number: 10811345
    Abstract: Assembly of the semiconductor device includes the following steps: (a) mounting a semiconductor chip on the bottom electrode 40; (b) mounting the top electrode 30 on the semiconductor chip; (c) forming a sealing body 70 made of resin and provided with a convex portion 74 so as to cover the semiconductor chip; and (d) exposing the electrode surface 31 of the top electrode 30 on the top surface of the sealing body 70 and exposing the electrode surface 41 of the bottom electrode 40 on the back surface of the sealing body 70. In the step (d), at least one of the electrode surface 31 and the electrode surface 41 is exposed from the sealing body 70 by irradiating at least one of the front surface and the back surface of the sealing body 70 with the laser 110.
    Type: Grant
    Filed: May 13, 2019
    Date of Patent: October 20, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Kuniharu Muto, Hideyuki Nishikawa
  • Patent number: 10804254
    Abstract: Structures and methods of forming fan-out packages are provided. The packages described herein may include a cavity substrate, one or more semiconductor devices located in a cavity of the cavity substrate, and one or more redistribution structures. Embodiments include a cavity preformed in a cavity substrate. Various devices, such as integrated circuit dies, packages, or the like, may be placed in the cavity. Redistribution structures may also be formed.
    Type: Grant
    Filed: November 16, 2018
    Date of Patent: October 13, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Po-Hao Tsai, Techi Wong, Po-Yao Chuang, Shin-Puu Jeng, Meng-Wei Chou, Meng-Liang Lin
  • Patent number: 10790163
    Abstract: In a method for manufacturing a semiconductor sensor, an upper mold has a pair of projections on a wall surface opposing to side surfaces of a semiconductor chip in a first cavity and at positions closest to a second cavity. The projections project so as to reduce the space between the side surfaces of the semiconductor chip and the upper mold, so that a flow of a resin material from a first cavity to a second cavity is delayed. The resin material is filled in the first cavity prior to the second cavity. After a portion of a film corresponding to the first cavity is entirely brought into close contact with the upper mold, the resin material is filled in the second cavity.
    Type: Grant
    Filed: January 17, 2019
    Date of Patent: September 29, 2020
    Assignee: DENSO CORPORATION
    Inventor: Masaaki Tanaka
  • Patent number: 10779446
    Abstract: Device (1) for cooling at least one power electronics circuit (4), including: a liquid-cooled heatsink (2); and an interface plate (3) that is in thermal contact with the heatsink (2) and to which the one or more power electronics circuits (4) are attached, the interface plate (3), including at least one thermosiphon (6), being removably mounted on the heatsink (2) so as to be capable of being separated therefrom with the one or more electronic circuits (4) attached thereto.
    Type: Grant
    Filed: July 10, 2017
    Date of Patent: September 15, 2020
    Assignee: MOTEURS LEROY-SOMER
    Inventors: Ludovic Bourlier, Aurelien Courage, Thierry Crespo
  • Patent number: 10777476
    Abstract: This semiconductor device includes: a first insulation resin portion formed on the mounting surface side of a lead frame; a second insulation resin portion formed on the heat dissipation surface side of the lead frame; and a heatsink fixed to the heat dissipation surface of the second insulation resin portion, wherein the second insulation resin portion has a second skirt portion formed at an end of a thin molded portion, the first insulation resin portion has a first skirt portion covering the second skirt portion, and an outer peripheral surface part of the second skirt portion has a first end connected to the lead frame and the first skirt portion, a second end connected to the heatsink, and at least one bent portion formed between the first end and the second end.
    Type: Grant
    Filed: June 9, 2017
    Date of Patent: September 15, 2020
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Yuki Okabe, Takanobu Kajihara, Junya Suzuki, Muneaki Mukuda, Hiroyuki Miyanishi
  • Patent number: 10770376
    Abstract: A semiconductor chip (2a) is bonded to an upper surface of the conductive substrate (1a). A control terminal (11a) is disposed outside the semiconductor chip (2a) and connected to a control electrode of the semiconductor chip (2a) via a lead (12a). A case (10) surrounds the semiconductor chip (2a). A sealing material (13) seals the semiconductor chip (2a). The lead frame (4) includes a bonded part (4a) joined to the semiconductor chip (2a), and an upright part (4b) embedded in the case (10), extending from the bonded part (4a) to an outer side of the control terminal (11a), and standing upright vertically relative to an upper surface of the semiconductor chip (2a).
    Type: Grant
    Filed: November 11, 2016
    Date of Patent: September 8, 2020
    Assignee: Mitsubishi Electric Corporation
    Inventors: Yosuke Nakata, Yuji Imoto, Taishi Sasaki, Tatsuya Kawase
  • Patent number: 10770444
    Abstract: An electronics package includes an insulating substrate, a first electrical component coupled to a first surface of the insulating substrate, and a first conductor layer formed on the first surface of the insulating substrate. A second conductor layer is formed on a second surface of the insulating substrate, opposite the first surface, the second conductor layer extending through vias in the insulating substrate to contact at least one contact pad of the first electrical component and couple with the first conductor layer. The electronics package also includes a second electrical component having at least one contact pad coupled to the first conductor layer. The first conductor layer has a thickness greater than a thickness of the second conductor layer.
    Type: Grant
    Filed: April 26, 2018
    Date of Patent: September 8, 2020
    Assignee: General Electric Company
    Inventors: Risto Ilkka Tuominen, Arun Virupaksha Gowda
  • Patent number: 10763240
    Abstract: A semiconductor device may include a first semiconductor chip, a second semiconductor chip, an encapsulant encapsulating the first and second semiconductor chips, a first signal terminal extending over inside and outside of the encapsulant and connected to the first semiconductor chip inside the encapsulant, and a second signal terminal extending over the inside and the outside of the encapsulant and connected to the second semiconductor chip inside the encapsulant. The first and second signal terminals may protrude from the encapsulant in a same direction. The first signal terminal may include, inside the encapsulant, a section where the first signal terminal extends farther away from the second signal terminal along a direction toward the first semiconductor chip. The second signal terminal may include, inside the encapsulant, a section where the second signal terminal extends farther away from the first signal terminal along a direction toward the second semiconductor chip.
    Type: Grant
    Filed: February 6, 2019
    Date of Patent: September 1, 2020
    Assignee: DENSO CORPORATION
    Inventors: Shingo Iwasaki, Kaisei Satou, Yuri Imai
  • Patent number: 10763225
    Abstract: An antenna module includes a fan-out semiconductor package including an IC, an encapsulant encapsulating at least a portion of the IC, a core member having a first side surface facing the IC or the encapsulant, and a connection member including at least one wiring layer electrically connected to the IC and the core member and at least one insulating layer; and an antenna package including a plurality of first directional antenna members configured to transmit or receive a first RF signal. The fan-out semiconductor package further includes at least one second directional antenna member disposed on a second side surface of the core member opposing the first side surface of the core member, stood up from a position electrically connected to at least one wiring layer, and configured to transmit or receive a second RF signal.
    Type: Grant
    Filed: April 10, 2018
    Date of Patent: September 1, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Doo Il Kim, Yong Ho Baek, Jin Seon Park, Young Sik Hur
  • Patent number: 10742169
    Abstract: An oscillator includes a resonator and an integrated circuit element. The resonator includes a resonator element and a resonator element container accommodating the resonator element. The integrated circuit element includes an inductor. The resonator and the integrated circuit element are stacked on each other. The resonator includes a metal member, and the metal member does not overlap the inductor when viewed in a plan view.
    Type: Grant
    Filed: November 26, 2018
    Date of Patent: August 11, 2020
    Assignee: SEIKO EPSON CORPORATION
    Inventors: Hisahiro Ito, Tetsuya Otsuki, Shoichiro Kasahara
  • Patent number: 10727163
    Abstract: A semiconductor device includes a semiconductor element having a front electrode, an electrode plate having an area larger than the front electrode of the semiconductor element in a two-dimensional view and made of aluminum or aluminum alloy, and a metal member having a joint surface joined to the front electrode of the semiconductor element with solder, having an area smaller than the front electrode of the semiconductor element in a two-dimensional view, made of a metal different from the electrode plate, and fastened to the electrode plate to electrically connect the front electrode of the semiconductor element to the electrode plate.
    Type: Grant
    Filed: July 25, 2017
    Date of Patent: July 28, 2020
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Junji Fujino, Yuji Imoto, Shohei Ogawa, Mikio Ishihara
  • Patent number: 10720383
    Abstract: In a semiconductor device, a first semiconductor chip and a second semiconductor chip are aligned in a direction orthogonal to a plate thickness direction of the first semiconductor chip. A pair of first heat sinks is disposed on opposite sides of the first semiconductor chip in the first direction, and a pair of second heat sinks disposed on opposite sides of the second semiconductor chip in the first direction. The semiconductor chips and the heat sinks are sealed in a resin molded body. A plurality of main terminals are aligned in the second direction and project from a same side surface of a resin molded body. The main terminals includes a positive electrode terminal, a negative electrode terminal, an output terminal, and an auxiliary terminal. The first relay members are disposed in the resin molded body, and electrically connecting the main terminals and the corresponding heat sinks.
    Type: Grant
    Filed: July 9, 2019
    Date of Patent: July 21, 2020
    Assignee: DENSO CORPORATION
    Inventor: Shinji Hiramitsu
  • Patent number: 10720372
    Abstract: Disclosed is a cooling assembly for circuit boards. In one embodiment, the assembly includes a circuit board that is thermally and physically coupled to a heat spreader by a thermal interface. In one configuration, the circuit board is formed from a semiconductor material and includes a first board surface on which integrated circuits are mounted and a second board surface opposite the first board surface. The heat spreader is formed from a thermally conductive material and includes a plurality of vanes that are spaced apart from one another. The thermal interface is coupled between at least one area of the second board surface of the circuit board and a contact area of each of the plurality of vanes. Heat generated by the integrated circuits is conducted from at least one integrated circuit to the plurality of vanes of the heat spreader through the circuit board and the thermal interface.
    Type: Grant
    Filed: October 26, 2018
    Date of Patent: July 21, 2020
    Assignee: Microsoft Technology Licensing, LLC
    Inventor: Douglas Patrick Kelley
  • Patent number: 10699986
    Abstract: An electronics package includes an electrically conducting support layer; at least one electrically conducting outer layer; at least two power electronics components arranged on different sides of the support layer and electrically interconnected with the support layer and with the at least one outer layer; and isolation material, in which the support layer and the at least two power electronics components are embedded, the support layer and the at least one outer layer are laminated together with the isolation material; and a cooling channel for conducting a cooling fluid through the electronics package, the cooling channel runs between the at least two power electronics components through the support layer.
    Type: Grant
    Filed: December 27, 2018
    Date of Patent: June 30, 2020
    Assignee: ABB Schweiz AG
    Inventors: Daniel Kearney, Jürgen Schuderer, Slavo Kicin, Liliana Duarte
  • Patent number: 10686404
    Abstract: A method for testing the die-attach quality of a photovoltaic cell assembly, in particular, for electrical inline monitoring of a photovoltaic cell die-attach quality during the manufacturing of a concentrator photovoltaic module, comprises the steps of providing a photovoltaic cell assembly comprising at least one photovoltaic cell, in particular, a concentrator photovoltaic cell, attached to a heat sink, injecting a current into the photovoltaic cell assembly, measuring the voltage across the photovoltaic cell during the current injection, and determining the relative voltage drop over the duration of the current injection, whereby insufficiently bonded photovoltaic cell assemblies can be identified and screened.
    Type: Grant
    Filed: May 17, 2016
    Date of Patent: June 16, 2020
    Assignee: Saint-Augustin Canada Electric Inc.
    Inventors: Eckart Gerster, Hannes Meyer-Schönbohm
  • Patent number: 10658277
    Abstract: Embodiments of the present invention are directed to a semiconductor package with improved thermal performance. The semiconductor package includes a package substrate comprising a top substrate surface and a bottom substrate surface. The package substrate comprises a thickness extending from the top substrate surface to the bottom substrate surface. A heat spreader is disposed on the top substrate surface. The heat spreader comprises a thickness extending from a top planar surface to a bottom planar surface of the heat spreader. The top planar surface of the heat spreader is defined with a die region and a non-die region surrounding the die region. A semiconductor die is directly disposed on the top planar surface of the heat spreader in the die region. The thickness of the heat spreader is greater relative to the thickness of the package substrate.
    Type: Grant
    Filed: August 7, 2018
    Date of Patent: May 19, 2020
    Assignee: UTAC Headquarters Pte. Ltd.
    Inventors: Antonio Bambalan Dimaano, Jr., Nataporn Charusabha, Saravuth Sirinorakul, Preecha Joymak, Roel Adeva Robles
  • Patent number: 10658264
    Abstract: The disclosed technology generally relates to integrated circuit (IC) packages, and more particularly to integrated circuit packages comprising perforated diamond-based heat spreading substrates. In one aspect, a heat spreading substrate for an IC die is configured to be attached to an IC die and to spread heat away therefrom. The diamond-based heat spreading substrate can have an electrically conductive surface and an array of vias formed therethrough. At least one of the vias is configured to overlap an edge of the IC die when attached to the diamond-based heat spreading substrate.
    Type: Grant
    Filed: December 28, 2017
    Date of Patent: May 19, 2020
    Assignee: Analog Devices, Inc.
    Inventors: Jin Zou, Gary T. Wenger
  • Patent number: 10638595
    Abstract: The disclosure relates to an electric device. The electric device has a housing, at least one printed circuit board, and at least one heat sink. The housing encloses a cavity, and the printed circuit board is received in the cavity. The printed circuit board is connected to the heat sink so as to conduct heat. According to the disclosure, the housing has a housing cover, and the housing cover has at least one, two, or three pressing elements, in particular pressing bolts or pressing pins, which are mounted in a movable manner along the longitudinal axis transversely to an areal extension of the housing cover. The pressing element is designed to be inserted into the cavity and to be pressed against the printed circuit board directly or at least indirectly and thus press the printed circuit board against the heat sink.
    Type: Grant
    Filed: July 13, 2017
    Date of Patent: April 28, 2020
    Assignee: Robert Bosch GmbH
    Inventor: Andreas Falkenburger
  • Patent number: 10615108
    Abstract: A semiconductor device includes: an oscillator including external terminals disposed on a first face with a specific distance along a first direction; an integrated circuit including a first region formed with first electrode pads along one side, and a second region formed with second electrode pads on two opposing sides of the first region; a lead frame that includes terminals at a peripheral portion, and on which the oscillator and the integrated circuit are mounted such that the external terminals, the first and second electrode pads face in a substantially same direction and such that one side of the integrated circuit is substantially parallel to the first direction; a first bonding wire that connects one external terminal to one first electrode pad; a second bonding wire that connects one terminal of one lead frame to one second electrode pad; and a sealing member that seals all of the components.
    Type: Grant
    Filed: January 18, 2016
    Date of Patent: April 7, 2020
    Assignee: LAPIS SEMICONDUCTOR CO., LTD.
    Inventors: Toshihisa Sone, Kazuya Yamada, Akihiro Takei, Yuichi Yoshida, Kengo Takemasa
  • Patent number: 10615055
    Abstract: A package structure is provided, which includes: a frame having a cavity penetrating therethrough; a semiconductor chip received in the cavity of the frame, wherein the semiconductor chip has opposite active and inactive surfaces exposed from the cavity of the frame; a dielectric layer formed in the cavity to contact and fix in position the semiconductor chip, wherein a surface of the dielectric layer is flush with a first surface of the frame toward which the active surface of the semiconductor chip faces; and a circuit structure formed on the surface of the dielectric layer flush with the first surface of the frame and electrically connected to the active surface of the semiconductor chip, thereby saving the fabrication cost and reducing the thickness of the package structure.
    Type: Grant
    Filed: December 19, 2018
    Date of Patent: April 7, 2020
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Chi-Hsin Chiu, Shih-Kuang Chiu
  • Patent number: 10600671
    Abstract: In certain embodiments, a method of making a semiconductor structure suitable for transfer printing (e.g., micro-transfer printing) includes providing a support substrate and disposing and processing one or more semiconductor layers on the support substrate to make a completed semiconductor device. A patterned release layer and, optionally, a capping layer are disposed on or over the completed semiconductor device and the patterned release layer or capping layer, if present, are bonded to a handle substrate with a bonding layer. The support substrate is removed to expose the completed semiconductor device and, in some embodiments, a portion of the patterned release layer. In some embodiments, an entry path is formed to expose a portion of the patterned release layer. In some embodiments, the release layer is etched and the completed semiconductor devices transfer printed (e.g., micro-transfer printed) from the handle substrate to a destination substrate.
    Type: Grant
    Filed: July 3, 2019
    Date of Patent: March 24, 2020
    Inventors: Christopher Bower, Matthew Meitl, António José Marques Trindade, Ronald S. Cok, Brook Raymond, Carl Prevatte
  • Patent number: 10541354
    Abstract: A light source device includes an electronic component and a substrate. The electronic component includes first and second electrodes exposed at a lower surface. The first electrode includes first and second parts separated from each other by a separation region on the lower surface of the electronic component. The substrate includes a basal member and a first and second wiring layers disposed on an upper surface of the basal member. The electronic component is mounted to the substrate so that upper surfaces of the first and second wiring layers respectively face the first and second electrodes. The substrate includes a first region at a position overlapping the separation region as seen in a top view. Solder wettability of the substrate in the first region is lower than solder wettability of the substrate in at least regions of the first wiring layer facing the first and second parts of the first electrode.
    Type: Grant
    Filed: April 20, 2018
    Date of Patent: January 21, 2020
    Assignee: NICHIA CORPORATION
    Inventors: Takeshi Aki, Ryosuke Wakaki
  • Patent number: 10541190
    Abstract: An apparatus is described that includes a first semiconductor die. A second semiconductor die is stacked on the first semiconductor die. The first semiconductor die has a larger surface area than the second semiconductor die such that there exists a peripheral region of the first semiconductor die that is not covered by the second semiconductor die. The apparatus includes thermally conductive material above the second semiconductor die. The apparatus includes a compound mold between the thermally conductive material and both the second semiconductor die and the peripheral region of the first semiconductor die. The apparatus includes a thermally conductive structure extending through the compound mold that thermally couples the peripheral region to the thermally conductive material.
    Type: Grant
    Filed: November 30, 2015
    Date of Patent: January 21, 2020
    Assignee: Intel Corporation
    Inventors: Chandra Jha, Eric Li
  • Patent number: 10535587
    Abstract: Packaged semiconductor device having a frame, of conductive material; a body of semiconductor material, fixed to the frame through a first adhesive layer; a heat-sink element, fixed to the body through a second adhesive layer; and a packaging mass surrounding the body and, at least partially, the frame and the heat-sink element. The heat-sink element is formed by a heat-sink die facing, and coplanar to, a main face of the device and by a spacer structure, which includes a pair of pedestals projecting from the perimeter of the heat-sink die towards the body and rest on the body.
    Type: Grant
    Filed: December 7, 2015
    Date of Patent: January 14, 2020
    Assignee: STMICROELECTRONICS S.R.L.
    Inventors: Concetto Privitera, Maurizio Maria Ferrara, Fabio Vito Coppone
  • Patent number: 10511196
    Abstract: An antenna for receiving electromagnetic waves having different polarizations that comprises a plurality of slots defined by a piece of metal, and each of the plurality of slots includes at least two continuous segments. In addition, for each of the plurality of slots: a first segment of the at least two continuous segments is: (i) defined by the piece of metal in a first dimension, and (ii) configured to receive radio frequency (RF) power transmission waves having a first polarization, and a second segment of the at least two continuous segments is: (i) defined by the piece of metal in a second dimension, distinct from the first dimension, and (ii) configured to receive RF power transmission waves having a second polarization different from the first polarization.
    Type: Grant
    Filed: July 17, 2018
    Date of Patent: December 17, 2019
    Assignee: Energous Corporation
    Inventor: Alister Hosseini
  • Patent number: 10510557
    Abstract: An electronic part mounting substrate includes: a metal plate 10 (for mounting thereon electronic parts) of aluminum or an aluminum alloy having a substantially rectangular planar shape, one major surface of the metal plate 10 being surface-processed so as to have a surface roughness of not less than 0.2 micrometers; a plating film 20 of nickel or a nickel alloy formed on the one major surface of the metal plate 10; an electronic part 14 bonded to the plating film 20 by a silver bonding layer 12 (containing a sintered body of silver); a ceramic substrate 16 having a substantially rectangular planar shape, one major surface of the ceramic substrate 16 being bonded to the other major surface of the metal plate 10; and a radiating metal plate (metal base plate) 18 bonded to the other major surface of the ceramic substrate 16.
    Type: Grant
    Filed: November 22, 2013
    Date of Patent: December 17, 2019
    Assignee: DOWA METALTECH CO., LTD.
    Inventors: Naoya Sunachi, Hideyo Osanai, Satoru Kurita
  • Patent number: 10511137
    Abstract: A laser module with a flattened structure is installed on a mobile device for a camera program installed in the mobile device to operate photo-taking and image measurement. The laser module includes a printed circuit board (PCB), a photodiode embedded on the PCB, an automatic power control integrated circuit embedded on the PCB, and a laser diode chip electrically connected to the PCB. The flattened structure has a top surface of the PCB, a detection surface of a photodiode chip, a first surface of the automatic power control integrated circuit, a connecting surface of the laser diode chip sharing a common plane surface for operation.
    Type: Grant
    Filed: April 12, 2018
    Date of Patent: December 17, 2019
    Assignee: Conary Enterprise Co., Ltd.
    Inventor: Hsien-Cheng Yen
  • Patent number: 10510638
    Abstract: There is provided an electronic component-embedded board. The electronic component-embedded board includes: a first insulating layer; a metal layer formed on the first insulating layer; a first electronic component disposed on the metal layer; a second insulating layer formed on the first insulating layer and the metal layer such that the first electronic component is buried in the second insulating layer; a second electronic component disposed above the second insulating layer; and a heat radiating member thermally connected to the metal layer exposed from the second insulating layer and thermally connected to the second electronic component.
    Type: Grant
    Filed: September 21, 2018
    Date of Patent: December 17, 2019
    Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventors: Shigeru Mizuno, Tomoya Kubo, Katsuya Fukase
  • Patent number: 10490490
    Abstract: A semiconductor device of the present invention includes: a plurality of wiring boards disposed separately from one another; a plurality of semiconductor elements disposed on first main surfaces of the wiring boards and electrically connected to the wiring boards; a plurality of terminals electrically connected to the wiring boards; a sealing resin sealing the wiring boards and the semiconductor elements so that second main surfaces of the wiring boards are exposed.
    Type: Grant
    Filed: March 11, 2016
    Date of Patent: November 26, 2019
    Assignee: SHINDENGEN ELECTRIC MANUFACTURING CO., LTD.
    Inventor: Yoshihiro Kamiyama
  • Patent number: 10483178
    Abstract: A semiconductor device includes a first contact element, a second contact element, a semiconductor chip, and an encapsulation material. The first contact element is on a first side of the semiconductor device. The second contact element is on a second side of the semiconductor device opposite to the first side. The semiconductor chip is electrically coupled to the first contact element and the second contact element. The encapsulation material encapsulates the semiconductor chip and portions of the first contact element and the second contact element. The encapsulation material defines at least two notches on a third side of the semiconductor device extending between the first side and the second side.
    Type: Grant
    Filed: January 3, 2017
    Date of Patent: November 19, 2019
    Assignee: Infineon Technologies AG
    Inventors: Upendra Balehithlu Manjappaiah, Kok Kiat Koo, Khai Seen Yong
  • Patent number: 10446297
    Abstract: A power resistor has paired harness electric wires that have one end parts connected to a resistor substrate, and other end parts pass through an exterior material made of insulating resin and extend outward. Crimp terminals, which are means for reinforcing affinity between the coating material of the harness electric wires and the insulating resin, i.e., the exterior material and for maintaining adhesion, are formed on predetermined portions of the harness electric wires. As a result, a short and small power resistor suitable for an in-vehicle environment is provided.
    Type: Grant
    Filed: February 20, 2017
    Date of Patent: October 15, 2019
    Assignee: KOA Corporation
    Inventors: Masaki Miyagawa, Kyohei Miyashita, Hiroshi Sakai
  • Patent number: 10446462
    Abstract: A power semiconductor device module includes, among other parts, a DMB structure. The DMB structure includes a ceramic sheet, a top metal plate that is directly bonded to the top of the ceramic, and a bottom metal plate that is directly bonded to the bottom of the ceramic. A power semiconductor device die is attached to the top metal plate. The bottom surface of the bottom metal plate has a plurality small cavities. When the bottom metal plate is attached to another metal member, a material between the plate and the member (for example, thermal grease or a PCM or solder) is forced into the cavities. This results in an improvement in thermal transfer between the plate and the member. Such cavities can alternatively, or in addition, be included on a metal surface other than a DMB, such as the bottom surface of a baseplate of the module.
    Type: Grant
    Filed: April 29, 2019
    Date of Patent: October 15, 2019
    Assignee: LITTELFUSE, INC.
    Inventor: Thomas Spann
  • Patent number: 10431575
    Abstract: Embodiments are provided that include a method for fabricating a multi-die package including: placing a plurality of flip chip dies and splitter dies on the sacrificial carrier; performing solder reflow to join solder bumps of each flip chip die and each splitter die to the sacrificial carrier that includes test probe circuitry; testing the flip chip and splitter dies; replacing any faulty dies; overmolding the flip chip and splitter dies on the sacrificial carrier to form a panel of embedded dies; planarizing the panel of embedded dies to expose back surfaces of the embedded dies; forming a metallization layer across the back surface of the panel of embedded dies; and removing the sacrificial carrier to expose a front surface of the panel of embedded dies, wherein a contact surface of each solder bump of each flip chip die and splitter die is exposed in the front surface.
    Type: Grant
    Filed: December 19, 2017
    Date of Patent: October 1, 2019
    Assignee: NXP B.V.
    Inventors: Antonius Hendrikus Jozef Kamphuis, Jeroen Johannes Maria Zaal, Johannes Henricus Johanna Janssen, Amar Ashok Mavinkurve
  • Patent number: 10424526
    Abstract: A chip package structure includes a redistribution layer, at least one chip, a reinforcing frame, an encapsulant and a plurality of solder balls. The redistribution layer includes a first surface and a second surface opposite to each other. The chip is disposed on the first surface and electrically connected to the redistribution layer. The reinforcing frame is disposed on the first surface and includes at least one through cavity. The chip is disposed in the through cavity and a stiffness of the reinforcing frame is greater than a stiffness of the redistribution layer. The encapsulant encapsulates the chip, the reinforcing frame and covering the first surface. The solder balls are disposed on the second surface and electrically connected to the redistribution layer.
    Type: Grant
    Filed: October 13, 2017
    Date of Patent: September 24, 2019
    Assignee: Powertech Technology Inc.
    Inventors: Chi-An Wang, Hung-Hsin Hsu, Wen-Hsiung Chang
  • Patent number: 10410947
    Abstract: A semiconductor package may include a first semiconductor chip, a second semiconductor chip, and a thermal redistribution pattern which are disposed on a package substrate. The thermal redistribution pattern may include a first end portion disposed in a high temperature region adjacent to the first semiconductor chip, a second end portion disposed in a low temperature region adjacent to the second semiconductor chip, and an extension portion connecting the first end portion to the second end portion.
    Type: Grant
    Filed: July 16, 2018
    Date of Patent: September 10, 2019
    Assignee: SK hynix Inc.
    Inventor: Dae Woong Lee
  • Patent number: 10395946
    Abstract: A method for manufacturing an electronic package includes: forming a middle patterned conductive layer having a first surface, a second surface opposite to the first surface, and a plurality of middle conductive pads; forming a first redistribution circuitry on the first surface, wherein the first redistribution circuitry includes a first patterned conductive layer having a plurality of first conductive elements, each first conductive element has a first conductive via and pad that form a T-shaped section, and each first conductive via connects the corresponding middle conductive pad and is tapering; and forming a second redistribution circuitry on the second surface, wherein the second redistribution circuitry includes a second patterned conductive layer having a plurality of second conductive elements, each second conductive element has a second conductive via and pad that form an inversed T-shaped section, and each second conductive via connects the corresponding middle conductive pad and is tapering.
    Type: Grant
    Filed: November 1, 2018
    Date of Patent: August 27, 2019
    Inventor: Dyi-Chung Hu
  • Patent number: 10373899
    Abstract: A semiconductor module includes: a semiconductor chip; a package sealing the semiconductor chip; and a plurality of terminals connected to the semiconductor chip and protruding from the package, wherein the plurality of terminals includes a plurality of first terminals arranged side by side at a first pitch, and a plurality of second terminals arranged side by side at a second pitch, each terminal has a base portion, a tip portion narrower than the base portion, and a connection portion connecting the base portion and the tip portion, the connection portions of the plurality of first terminals are right-angled, and the connection portions of the plurality of second terminals are arc-shaped.
    Type: Grant
    Filed: May 3, 2018
    Date of Patent: August 6, 2019
    Assignee: Mitsubishi Electric Corporation
    Inventors: Hongbo Zhang, Shogo Shibata
  • Patent number: 10373895
    Abstract: A semiconductor device includes a first lead frame, a second lead frame, a first semiconductor chip, and an encapsulation material. The first lead frame includes a first die pad having a first surface and a second surface opposite to the first surface. The second lead frame includes a second die pad having a first surface and a second surface opposite to the first surface. The first surface of the second die pad faces the first surface of the first die pad. The first semiconductor chip is attached to the first surface of the first die pad. The encapsulation material encapsulates the first semiconductor chip and portions of the first lead frame and the second lead frame. The encapsulation material has a first surface aligned with the second surface of the first die pad and a second surface aligned with the second surface of the second die pad.
    Type: Grant
    Filed: December 12, 2016
    Date of Patent: August 6, 2019
    Assignee: Infineon Technologies Austria AG
    Inventors: Edward Fuergut, Martin Gruber, Wolfgang Scholz, Ralf Otremba
  • Patent number: 10373896
    Abstract: Provided is a semiconductor module having an integrated insulating sheet structure, wherein detachment of the insulating sheet can be suppressed and improved reliability of the semiconductor module is achieved, by adopting a structure in which at least one location of the insulating sheet is sunken inside a mold, and a sealing resin body and the insulating sheet of the semiconductor module form a protrusion.
    Type: Grant
    Filed: March 28, 2014
    Date of Patent: August 6, 2019
    Assignee: Mitsubishi Electric Corporation
    Inventors: Shunsuke Fushie, Yu Kawano, Yoshihito Asao, Akihiko Mori
  • Patent number: 10348214
    Abstract: A power converter device includes a double-sided electrode module in which an electrical wiring board and a power semiconductor element are molded with a resin material. The power converter device also includes a heat dissipating base disposed on both sides of the double-sided electrode module and directly contacting cooling medium. The power converter device also includes a module fixture which presses the heat dissipating base in a state of contact with the heat dissipating base. The module fixture is configured to support a circuit board.
    Type: Grant
    Filed: June 28, 2017
    Date of Patent: July 9, 2019
    Assignee: Hitachi Automotive Systems, Ltd.
    Inventors: Kinya Nakatsu, Hiroshi Hozoji, Takeshi Tokuyama, Yusuke Takagi, Toshiya Satoh, Taku Oyama, Takanori Ninomiya
  • Patent number: 10325784
    Abstract: A method for manufacturing a cover for an electronic package includes placing an insert having opposite faces between opposite faces of a cavity of a mold. A coating material is injected in the mold cavity around the insert. The coating material is then set to form a substrate that is overmolded around the insert and produce the cover.
    Type: Grant
    Filed: August 24, 2017
    Date of Patent: June 18, 2019
    Assignee: STMicroelectronics (Grenoble 2) SAS
    Inventors: Benoit Besancon, Alexandre Mas, Karine Saxod
  • Patent number: RE47530
    Abstract: An LED apparatus includes a base having thermal conductivity, an insulative substrate provided on one surface of the base and including electrodes provided on a surface of the substrate, at least one base-mounting area that is an exposed part of the base, exposed within a pass-through hole provided in the substrate, a plurality of LED elements mounted on the base in the base-mounting area and some of the LED elements in a unit electrically connected to the electrodes in series, a plurality of the units are electrically connected in parallel, and a frame disposed to surround the base-mounting area and configured to form a light-emitting area.
    Type: Grant
    Filed: October 27, 2016
    Date of Patent: July 23, 2019
    Assignees: CITIZEN ELECTRONICS CO., LTD., CITIZEN WATCH CO., LTD.
    Inventors: Norikazu Kadotani, Koichi Fukasawa, Sadato Imai
  • Patent number: RE47923
    Abstract: A PiP semiconductor device has an inner known good semiconductor package. In the semiconductor package, a first via is formed in a temporary carrier. A first conductive layer is formed over the carrier and into the first via. The first conductive layer in the first via forms a conductive bump. A first semiconductor die is mounted to the first conductive layer. A first encapsulant is deposited over the first die and carrier. The semiconductor package is mounted to a substrate. A second semiconductor die is mounted to the first conductive layer opposite the first die. A second encapsulant is deposited over the second die and semiconductor package. A second via is formed in the second encapsulant to expose the conductive bump. A second conductive layer is formed over the second encapsulant and into the second via. The second conductive layer is electrically connected to the second die.
    Type: Grant
    Filed: March 1, 2016
    Date of Patent: March 31, 2020
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: Zigmund R. Camacho, Frederick R. Dahilig, Lionel Chien Hui Tay, Arnel Senosa Trasporto, Henry Descalzo Bathan