Abstract: A light emitting device includes a substrate, a light emitting element, a first resin member and a second resin member. The substrate includes a base member, a plurality of wiring portions disposed on a surface of the base member, and a covering layer covering the wiring portions with an opening formed in a part of the covering layer. The light emitting element is arranged on the substrate in the opening of the covering layer and having an upper surface at a position higher than the covering layer. The first resin member is arranged at least in the opening of the covering layer and at periphery of the light emitting element. The second resin member seals the substrate and the light emitting element. The second resin member is disposed in contact with the first resin member.

Abstract: A printed circuit assembly includes a printed circuit board, a heat generating component coupled to the printed circuit board, and a conductive substrate extending parallel to the printed circuit board. The conductive substrate includes a flexing structure and a protrusion disposed on the flexing structure. The protrusion extends toward the printed circuit board opposite the heat generating component.

Abstract: A semiconductor device according to the present invention includes an insulating substrate having a circuit pattern, semiconductor elements bonded on the circuit pattern with a brazing material, and a wiring terminal bonded with a brazing material on an electrode provided on each of the semiconductor elements on an opposite side of the circuit pattern, in which a part of the wiring terminal is in contact with the insulating substrate, and insulated from the circuit pattern.

Abstract: The disclosure discloses a packaging module of a power converting circuit and a method for manufacturing the same. The packaging module of the power converting circuit includes a substrate, a molding layer and a plurality of pins. A power device is assembled at the substrate, a plurality of pins electrically are coupled to the power device, the molding layer covers the surface of the substrate with the power device, and at least a contact surface of the pins configured to electrically connect an external circuit is exposed. The molding layer includes a main hat-body part and a hat-brim part, the main hat-body part and the hat-brim part form a hat-shaped molding layer, and the hat-brim part is used to increase a creepage distance between the contact surfaces of the pins located at the top of the molding layer and the bottom of the substrate.

Abstract: A semiconductor package structure and forming method thereof; the semiconductor package structure includes a heat sink frame (2) and a lead frame (1), where the heat sink frame (2) is connected with a heat sink (4), a chip pad (21) of the lead frame (1) is adhered with a chip (3), and the heat sink (4) is connected to the chip (3) through a bonding material (5), and where the lead frame (1) is provided with a first lead (22), and the heat sink frame (2) is provided with a second lead (43) and a third lead (44).

Abstract: A semiconductor device is made by mounting a prefabricated heat spreader frame over a temporary substrate. The heat spreader frame includes vertical bodies over a flat plate. A semiconductor die is mounted to the heat spreader frame for thermal dissipation. An encapsulant is deposited around the vertical bodies and semiconductor die while leaving contact pads on the semiconductor die exposed. The encapsulant can be deposited using a wafer level direct/top gate molding process or wafer level film assist molding process. An interconnect structure is formed over the semiconductor die. The interconnect structure includes a first conductive layer formed over the semiconductor die, an insulating layer formed over the first conductive layer, and a second conductive layer formed over the first conductive layer and insulating layer. The temporary substrate is removed, dicing tape is applied to the heat spreader frame, and the semiconductor die is singulated.

Abstract: A semiconductor device includes two or more semiconductor elements, a lead with island portions on which the semiconductor elements are mounted, a heat dissipation member for dissipating heat from the island portions, a bonding layer bonding the island portions and the heat dissipation member, and a sealing resin covering the semiconductor elements, the island portions and a part of the heat dissipation member. The bonding layer includes mutually spaced individual regions provided for the island portions, respectively.

Abstract: A stacked semiconductor package and a manufacturing method thereof. For example and without limitation, various aspects of this disclosure provide a semiconductor package in which an upper interposer and/or package are electrically and mechanically coupled to a lower package utilizing an adhesive member comprising conductive particles.

Abstract: In accordance with an embodiment, a semiconductor component includes a support having a first device receiving structure, a second device receiving structure, a first lead and a second lead. A first semiconductor chip is coupled to the first device receiving structure and a second semiconductor chip is coupled to the first semiconductor chip and the second device receiving structure. The first semiconductor chip is configured from a silicon semiconductor material and has a gate bond pad, a source bond pad, and a drain bond pad, and the second semiconductor chip is configured from a gallium nitride semiconductor chip and has a gate bond pad, a source bond pad, and a drain bond pad. In accordance with another embodiment, a method for manufacturing a semiconductor component includes coupling a first semiconductor chip to a support and coupling a second semiconductor chip to the support.

Abstract: A method includes the steps of: preparing a lead frame including a plurality of die pads, and preparing a plurality of semiconductor chips; disposing each of the semiconductor chips on a respective one of the die pads; forming a sealing resin to cover the die pads and the semiconductor chips; and attaching a heat dissipation plate to the die pads by pressing the heat dissipation plate against the die pads via a resin sheet which is an adhesive layer after the sealing resin is formed.

Abstract: A power-module substrate includes first and second sets of circuit-layer metal-plates, a first ceramic substrate, a metal member connecting the first and second sets of circuit-layer metal-plates through a hole formed in the first ceramic substrate, a second ceramic substrate, a heat-radiation-layer metal-plate, and an electric component attached to a top surface of one of the first set of circuit-layer metal-plates above the metal member and the through hole. The power-module substrate is configured to conduct heat from the electric component through the through hole via the metal member, along the second set of circuit-layer metal-plates, and to the heat-radiation-layer metal-plate.

Abstract: A rigid-flex circuit connector is provided that includes a layered circuit board and an array of electrical contacts. The layered circuit board has a rigid board stacked above a flex board. The rigid board includes at least one rigid substrate and a rigid board circuit. The rigid board circuit includes a plurality of conductive vias extending into the rigid board from a top surface of the rigid board. The flex board includes at least one flexible substrate and a flex board circuit. The flex board circuit electrically connects to the conductive vias of the rigid board circuit. The array of electrical contacts is loaded in the conductive vias. The electrical contacts have mating ends that protrude from the top surface of the rigid board to mechanically engage and electrically connect to mating contacts of a mating electronic component.

Abstract: A semiconductor device package may include: a semiconductor chip element; and a supporting structure on which the semiconductor chip element is mounted and including an electrical connection element for connecting the semiconductor chip element to an external terminal. The supporting structure may include: a first lead frame including a heat dissipation element; a second lead frame coupled to the first lead frame; and/or an insulator configured to electrically insulate the first and second lead frames from each other. Each of the first and second lead frames may include a mounting region on which the semiconductor chip element is mounted. The first lead frame may include: a first portion; and/or a second portion formed on the first portion and having a smaller width than that of the first portion. The insulator may be on the first portion around the second portion. The second lead frame may be on the insulator.

Abstract: A semiconductor device includes a plurality of metal patterns formed on a ceramic substrate, and a semiconductor chip mounted on some of the plurality of metal patterns. Also, a plurality of hollow portions are formed in peripheral portions of the plurality of metal patterns. In addition, the plurality of hollow portions are not formed in a region overlapping the semiconductor chip in the plurality of metal patterns. Furthermore, the plurality of hollow portions are provided in a plurality of metal patterns arranged at a position closest to the peripheral portion of the top surface of the ceramic substrate among the plurality of metal patterns.

Abstract: The present invention relates to methods of making a semiconductor assembly having a semiconductor device embedded in a heat spreader and electrically connected to a dual-stage formed interconnect substrate. In a preferred embodiment, the interconnect substrate consists of first and second build-up circuitries and the methods are characterized by the step of attaching a semiconductor subassembly having a first build-up circuitry adhered to a sacrificial carrier to a heat spreader using an adhesive with the semiconductor device inserted into a cavity of the heat spreader and the step of detaching the sacrificial carrier from the first build-up circuitry. The heat spreader provides thermal dissipation, and the first and second build-up circuitries provide staged fan-out routing for the semiconductor device.

Abstract: A semiconductor device includes a semiconductor element having a front surface and a rear surface, a pair of heat sinks disposed facing each other so as to sandwich the semiconductor element, and attached respectively to the front surface and the rear surface, and a fastening screw fastening the pair of the heat sinks in the facing direction, the fastening screw having insulation property. Threads are arranged on at least a part of the fastening screw in an axis direction of the fastening screw between the pair of the heat sinks.

Abstract: A method of forming a molding layer includes the following operations: forming a substrate having at least one column structure thereon; flipping over the substrate having the column structure such that the column structure is beneath the substrate; dipping the column structure of the flipped substrate into a molding material fluid contained in a container; and separating the column structure of the flipped substrate from the container to form a molding layer covering and in contact with the column structure.

Abstract: On the assumption that a pair of hanging parts is provided in a lead frame and a clip includes a main body part and a pair of extension parts, the pair of the extension parts is mounted and supported on the pair of the hanging parts. Accordingly, the clip is mounted on a lead (one point) and the pair of the hanging parts (two points), and the clip is supported by the three points.

Abstract: An ultraviolet curing apparatus includes a chamber, a gas flow generator, and an ultraviolet lamp. The gas flow generator includes a top liner and a bottom liner coupled to each other. The top liner and the bottom liner are disposed in the chamber, and are made of low-coefficient of thermal expansion material. The ultraviolet lamp is disposed on the chamber and is configured for providing ultraviolet light.

Abstract: A method of forming a custom module lid. The method may include placing a multichip module (MCM) between a module base and a temporary lid, target components are exposed through viewing windows in the temporary lid, a top surface of the target components is measured and mapped to create a target profile, the target profile is used to form custom pockets in a custom lid, and the custom pockets correspond to the target components.

Abstract: Sealing force between a metal case and a power semiconductor module is improved. In a power semiconductor module 3, peripheral side surfaces of power semiconductor devices 31U and 31L and conductor plates 33 to 36 are integrated by being covered with a first sealing resin 6. An oxide layer (rough surface layer) 46 is formed on an inner surface of a metal case 40. A fluid resin material is injected into a space S between the oxide layer 46 provided to the metal case 40 and a power semiconductor module 30, and then a second sealing resin 52 is formed. The second sealing resin 52 fills dents of the oxide layer 46, and therefore sealing force improves.

Abstract: The semiconductor device includes a semiconductor element, a main lead and a resin package. The semiconductor element includes an obverse surface and a reverse surface spaced apart from each other in a thickness direction. The main lead supports the semiconductor element via the reverse surface of the semiconductor element. The resin package covers the entirety of the semiconductor element. The resin package covers the main lead in such a manner that a part of the main lead is exposed from the resin package. The semiconductor element includes a part that does not overlap the main lead as viewed in the thickness direction.

Abstract: An element housing package includes a base body having a rectangular shape, having a mounting region for mounting a semiconductor element, a frame body disposed so as to surround the mounting region, a connection conductor disposed from the upper surface to a lower surface of the base body, a circuit conductor disposed on the lower surface of the base body, one end of the circuit conductor being electrically connected to the connection conductor and an other end of the circuit conductor being drawn out laterally from a first side surface of the base body, and a metal plate bonded to the lower surface of the base body, having an attachment region and a ground conductor region. The metal plate has an outer peripheral region which is drawn out laterally from the base body, from the ground conductor region to the attachment region along an outer periphery of the base body.

Abstract: A test system, and a method of manufacture thereof, including: a thermal management head including a heat spreader; an electronic device in direct contact with the heat spreader; and an electrical current for transferring energy between the heat spreader and the electronic device.

Abstract: A laser component includes a carrier having a lens carrier surface and a chip carrier surface raised relative to the lens carrier surface, wherein an optical lens is arranged on the lens carrier surface, a laser chip is arranged on the chip carrier surface, the chip carrier surface and the lens carrier surface are formed by materially uniformly continuous sections of the carrier, the carrier includes a plastic material, and the laser component is configured as a surface-mountable SMD component.

Abstract: A semiconductor device incorporating a heat spreader and improved to inhibit dielectric breakdown is provided. The semiconductor device has an electrically conductive heat spreader having a bottom surface, a sheet member having a front surface and a back surface electrically insulated from each other, IGBTs and diodes fixed on the heat spreader and electrically connected thereto, and a molding resin. The front surface contacts with the bottom surface and has a peripheral portion jutting out from edges thereof. The molding resin encapsulates the front surface of the sheet member, the heat spreader and the semiconductor elements. At least part of the back surface of the sheet member is exposed out of the molding resin. The heat spreader has, at a corner of its bottom surface, corner portions having a beveled shape or a curved-surface shape as seen in plan and having a rectangular shape as seen in section.

Abstract: A stacked optoelectronic packaged device includes a bottom die having a top surface including bottom electrical traces and a light source die coupled to ?1 bottom electrical traces. A first cavity die is on the bottom die. An optics die is on the first cavity die and a second cavity die on the optics die. A mounting substrate is on the second cavity die including top electrical traces. A photodetector die is optically coupled to receive light from the light source. The bottom and top electrical traces are both positioned substantially symmetrically on sides of a mirror plane so that when conducting equal and opposite currents a first magnetic field emanating from the first side and a second magnetic field emanating from the second side cancel one another to provide a reduction in magnetic flux density by more than 50% at one or more die locations on the optics die.

Abstract: The present disclosure relates to a semiconductor package. In an embodiment, the semiconductor package includes a substrate, a semiconductor device, a thermal conductive element and a molding compound. The semiconductor device is mounted to the substrate. The thermal conductive element is disposed above the semiconductor device. The molding compound covers a side surface of the substrate and at least a part of a side surface of the semiconductor device.

Abstract: A surface-mount device (SMD) uses no conventional lead frame and contains a multi-function die module formed from either a single die or two or more dies electrically connected in series, in parallel, or in any combination of series and parallel, to provide such a SMD having one or more different functions including wave filtration, rectification, surge protection, sensing, current limiting, voltage regulation or prevention from voltage backflow, as compared to the prior art, the SMD disclosed is formed from fewer components, is simpler to manufacture and more effectively reduce layout wire length and noise.

Abstract: In the upper surface of a metallic substrate, a region near the central part of the metallic substrate is surrounded by a rectangle having dotted sides electrically separate the interior and exterior of the rectangle. Each dot of the sides is formed of a pillared insulating resin that penetrates from the upper surface to the lower surface of the metallic substrate. Oxide films are so formed as to fill in the spaces between adjacent cylinders of insulating resins and the surrounding of the cylinders. That is, a separation layer is formed of the pillared insulating resins and the oxide films that fill up the spaces between the pillared insulating resins as well as their vicinities.

Abstract: A semiconductor apparatus is provided. The semiconductor apparatus includes: a base having a main surface on which a terminal is disposed; a first semiconductor device retained on the main surface of the base and having a top surface on which an electrode is disposed and a bottom surface facing the main surface of the base; a connection member connecting the terminal and the electrode; an encapsulant disposed on the main surface of the base and covering the terminal, the first semiconductor device and the connection member; and a heat dissipating member disposed on the encapsulant and having a space that opens in a direction extending perpendicular to the main surface of the base. The encapsulant is disposed in the space and, in a side view of the base, a peak of the connection member is located inside the space.

Abstract: The present invention is directed to a semiconductor device including a semiconductor chip formed with an SiC-IGBT including an SiC semiconductor layer, a first conductive-type collector region formed such that the collector region is exposed on a second surface of the SiC semiconductor layer, a second conductive-type base region formed such that the base region is in contact with the collector region, a first conductive-type channel region formed such that the channel region is in contact with the base region, a second conductive-type emitter region formed such that the emitter region is in contact with the channel region to define a portion of a first surface of the SiC semiconductor layer, a collector electrode connected to the collector region, and an emitter electrode connected to the emitter region, and a MOSFET including a second conductive-type source region electrically connected to the emitter electrode and a second conductive-type drain region electrically connected to the collector electrode, the

Abstract: A method of forming a chip stack is provided and includes arraying solder pads along a plane of a major surface of a substrate forming walls of electrically insulating material between adjacent ones of the solder pads.

Abstract: First and second semiconductor die are mounted to first and second die pads of a lead frame disposed in a lead frame sheet. With a plurality of wire bonds, each post of a plurality of posts of the lead frame is connected to the first and second semiconductor die. Each post extends inward from opposite sides of the lead frame between the first and second die pads and is connected with a respective one of a plurality of leads of the lead frame. The first and second semiconductor die, the plurality of posts of the lead frame, and the plurality of wire bonds are encapsulated in a package. The lead frame sheet is sheared to define each lead of the plurality of leads. The plurality of posts includes first and second sets of posts extending inward from first and second opposite sides of the lead frame.

Abstract: A semiconductor package. Implementations may include a substrate including a metallic baseplate coupled with an electrically insulative layer and a plurality of metallic traces coupled to the electrically insulative layer on a surface of the electrically insulative layer opposing a surface of the electrically insulative layer coupled to the metallic baseplate. The plurality of metallic traces may include at least two different trace thicknesses, where the trace thicknesses are measured perpendicularly to the surface of the electrically insulative layer coupled with the metallic baseplate. The package may include at least one semiconductor device coupled to the substrate, a mold compound that encapsulates the power electronic device and at least a portion of the substrate, and at least one package electrical connector coupled with the substrate.

Abstract: There is provided a technology enabling the improvement of the reliability of a semiconductor device manufactured by physically fixing separately formed chip mounting portion and lead frame. A feature of an embodiment resides in that, a second junction portion formed in a suspension lead is fitted into a first junction portion formed in a chip mounting portion, thereby to physically fix the chip mounting portion and the suspension lead. Specifically, the first junction portion is formed of a concave part disposed in the surface of the chip mounting portion. The second junction portion forms a part of the suspension lead.

Abstract: Consistent with an example embodiment, a semiconductor device comprises a device die having bond pads providing connection to device die circuitry. The semiconductor device includes a QFN package (quad-flat-pack no-leads) built-up substrate lead frame having, a sub-structure of I/O terminals and a die attach area, the I/O terminals and die attach area enveloped in a molding compound; the die attach area has exposed areas to facilitate device die attachment thereon and the terminal I/O terminals provide connection to the device die bond pads. I/O terminals are electrically coupled with one another and to the die attach area with connection traces. The coupled I/O terminals and connection traces facilitate electroplating of exposed vertical surfaces of the I/O terminals during assembly, said connection traces being severed after assembly. Molding compound encapsulates the device die on the built-up substrate lead frame.

Abstract: Methods of fabricating multi-die assemblies including a wafer segment having no integrated circuitry thereon and having a plurality of vertically stacked dice thereon electrically interconnected by conductive through vias, resulting multi-die assemblies, and semiconductor devices comprising such multi-die assemblies. The wafer segment may function as a heat sink to enhance heat transfer from the stacked dice in the resulting multi-die assembly. The die stacks are fabricated at the wafer level on a base wafer, from which the wafer segment and die stacks are singulated after at least peripheral encapsulation.

Abstract: Semiconductor package devices and methods of forming the semiconductor package devices are provided. The semiconductor package devices may include a lower package including a lower semiconductor chip on a lower substrate, an upper package including an upper semiconductor chip on an upper substrate. The upper substrate may include a protruding part corresponding to the lower semiconductor chip and a connection part that has a bottom surface lower than a bottom surface of the protruding part and is disposed around the protruding part. The semiconductor package devices may also include a heat dissipation part in a space between the lower semiconductor chip and the protruding part on the upper substrate and a package connection pattern electrically connecting the lower package to the upper package.

Abstract: The invention is aimed at providing a bonding structure of a copper-based bonding wire, realizing low material cost, high productivity in a continuous bonding in reverse bonding for wedge bonding on bumps, as well as excellent reliability in high-temperature heating, thermal cycle test, reflow test, HAST test or the like. The bonding structure is for connecting the bonding wire onto a ball bump formed on an electrode of a semiconductor device, the bonding wire and the ball bump respectively containing copper as a major component thereof.

Abstract: A method, system, and apparatus for improved IC device packaging is described. In an aspect, an (IC) device package includes an IC die having at one or more contact pads, each contact pad located at a corresponding hotspot on a surface of the IC die. The package also includes a thermally conductive interposer which is thermally coupled to the IC die at the contact pads. In another aspect, an underfill material fills a space between the IC die and the interposer. The interposer may also be electrically coupled to the IC die. In an aspect, the interposer and the IC die are coupled through thermal interconnects or “nodules.

Abstract: The present invention discloses a high reliability semiconductor package structure, which includes a lower heat sink, a die, an upper heat sink, a lead frame and a package body. The lead frame and the upper heat sink contain separately a first bending unit and a second bending unit that are electrically connected. The upper and lower heat sinks are attached to two opposite surfaces of the die and sink the high power transient heat generated at the die. The lower heat sink also has an indentation that circles the die and contains extra solder that might otherwise contaminate the die. Package body contains and protects the die, the upper and lower heat sinks and the lead frame. With the implementation of the invention, the reliability of the semiconductor package structure is promoted and the EMC durability together with the operable power is enhanced.

Abstract: The present invention relates to a light emitting device package and a method of manufacturing the same. There is provided a light emitting device package including a metal core; an insulating layer formed on the metal core; a metal layer formed on the insulating layer; a first cavity formed by removing parts of the metal layer and the insulating layer to expose a top surface of the metal core; and a light emitting device directly mounted on the top surface of the metal core in the first cavity and further there is provided a method of manufacturing the light emitting device package.

Abstract: An encapsulated semiconductor device includes: a first conduction path formative plate; a second conduction path formative plate joined to the first conduction path formative plate; a power element bonded to the first conduction path formative plate; a heatsink held by the first conduction path formative plate with an insulation sheet interposed between the heatsink and the first conduction path formative plate; and an encapsulation resin configured to encapsulate the first and second conduction path formative plates. A through hole or a lead gap is formed in a region of the first conduction path formative plate in contact with the insulation sheet. The insulation sheet is press-fitted into the through hole or the lead gap.

Abstract: The semiconductor device includes a semiconductor element, a main lead and a resin package. The semiconductor element includes an obverse surface and a reverse surface spaced apart from each other in a thickness direction. The main lead supports the semiconductor element via the reverse surface of the semiconductor element. The resin package covers the entirety of the semiconductor element. The resin package covers the main lead in such a manner that a part of the main lead is exposed from the resin package. The semiconductor element includes a part that does not overlap the main lead as viewed in the thickness direction.

Abstract: Discoloration is suppressed in a wiring substrate including a conductive member including silver. A wiring substrate includes a ceramic layer and a conductive member including a conductive layer disposed on an upper surface of the ceramic layer. The conductive member includes silver and at least a portion of an upper surface of the conductive layer is covered with a covering layer. The covering layer includes an inorganic reflecting layer and a glass layer stacked on the inorganic reflecting layer.

Abstract: An integrated circuit (IC) package with a heat conductor is disclosed. The IC package has an IC disposed on a surface of a package substrate. A molding compound injected into the IC package surrounds the IC package and covers the perimeter of the top surface of the IC, exposing the center portion of the top surface of the IC. A heat conductor is disposed onto the top surface of the IC that is not covered by the molding compound. The heat conductor is placed such that the heat conductor lies adjacent to the center portion of the top surface of the IC and the edges of the heat conductor are surrounded by the molding compound.

Abstract: Disclosed is a method for fabricating a semiconductor package, including providing a package unit having an insulating layer and at least a semiconductor element embedded into the insulating layer, wherein the semiconductor element is exposed from the insulting layer and a plurality of recessed portions formed in the insulating layer; and electrically connecting a redistribution structure to the semiconductor element. The formation of the recessed portions release the stress of the insulating layer and prevent warpage of the insulating layer from taking place.

Abstract: In an electronic control device, semiconductor modules are disposed in a power region of a substrate, and on a surface of a substrate adjacent to a housing to radiate heat from rear surfaces to the housing through a heat radiation layer. Therefore, a heat radiation performance improves. Further, a first distance from an end surface of a power region corresponding part corresponding to the power region to the substrate is shorter than a second distance from an end surface of a control region corresponding part corresponding to a control region of the substrate to the substrate. Therefore, a closed circuit bridged by parasitic capacitances is formed mainly in an area of the power region and the power region corresponding part. A noise generated from the semiconductor modules is returned to noise sources through the closed circuit without affecting the control region.

Abstract: An LED apparatus includes a base having thermal conductivity, an insulative substrate provided on one surface of the base and including electrodes provided on a surface of the substrate, at least one base-mounting area that is an exposed part of the base, exposed within a pass-through hole provided in the substrate, a plurality of LED elements mounted on the base in the base-mounting area and some of the LED elements in a unit electrically connected to the electrodes in series, a plurality of the units are electrically connected in parallel, and a frame disposed to surround the base-mounting area and configured to form a light-emitting area.