Abstract: The present disclosure is directed to a leadframe package with a surface mounted semiconductor die coupled to leads of the leadframe package through wire bonding. The leads are partially exposed outside the package and configured to couple to another structure, like a printed circuit board (PCB). The exposed portions, namely outer segments, of the leads include a plating or coating layer of a material that enhances the solder wettability of the leads to the PCB through solder bonding. The enclosed portions, namely inner segments, of the leads do not include the plating layer of the outer segment and, thus, include a different surface material or surface finish.

Abstract: Manufacturing a semiconductor device, such as an integrated circuit, comprises: providing a leadframe having a die pad area, attaching onto the die pad area of the leadframe one or more semiconductor die or dice via soft-solder die attach material, and forming a device package by molding package material onto the semiconductor die or dice attached onto the die pad area of the leadframe. An enhancing layer, provided onto the leadframe to counter device package delamination, is selectively removed via laser beam ablation from the die pad area, and the semiconductor die or dice are attached onto the die pad area via soft-solder die attach material provided where the enhancing layer has been removed to promote wettability by the soft-solder material.

Abstract: A semiconductor device includes a leadframe, a semiconductor die attached to the leadframe, and an encapsulation material encapsulating the semiconductor die and a portion of the leadframe. The leadframe includes a first main face and a second main face opposite to the first main face. The leadframe includes leads wherein each lead includes a fully plated end face extending between an unplated first sidewall and an unplated second sidewall opposite to the first sidewall. The end face and the first and second sidewalls of each lead are perpendicular to the first and second main faces.

Abstract: The disclosure describes a magnetic circuit assembly that includes a magnet assembly and an excitation ring. The magnet assembly defines a central axis and includes a pole piece and a magnet underlying the pole piece. The excitation ring includes a base and an outer ring positioned around the magnet assembly. The base includes a platform layer underlying the magnet, an upper base layer underlying the platform layer, and a lower base layer underlying the upper base layer. The outer ring overlies the upper base layer and is configured to couple to an outer radial portion of a proof mass assembly. The platform layer and lower base layer are made from high coefficient of thermal expansion (CTE) materials, while the upper base layer and outer ring are made from low CTE materials. Each relatively high CTE material has a higher CTE than each relatively low CTE material.

Abstract: A lighting assembly is disclosed which includes a leadframe and at least one light-emitting diode (LED) element arranged on the leadframe. At least a portion of the leadframe is covered with a polyurethane coating arranged to electrically insulate the portion of the leadframe, and at least a portion of the polyurethane covered portion of the leadframe is further covered with a thermally conductive material. A method for manufacturing the lighting assembly is also disclosed.

Abstract: Methods of forming a semiconductor package. Implementations include providing a leadframe, coupling a semiconductor die or an electronic component to the leadframe, and encapsulating at least a portion of the semiconductor die or the electronic component using a mold compound leaving two or more leads of the leadframe exposed. The method may also include coating the two or more leads of the leadframe with an electrically conductive layer. The method may include fully electrically and physically singulating one or more tie bars between two or more leads of the leadframe, a lead of the two or more leads and a leadframe flag, or any combination thereof. The method may also include singulating the leadframe to form one or more semiconductor packages.

Abstract: A semiconductor device includes a leadframe, a semiconductor die attached to the leadframe, and an encapsulation material encapsulating the semiconductor die and a portion of the leadframe. The leadframe includes a first main face and a second main face opposite to the first main face. The leadframe includes leads wherein each lead includes a fully plated end face extending between an unplated first sidewall and an unplated second sidewall opposite to the first sidewall. The end face and the first and second sidewalls of each lead are perpendicular to the first and second main faces.

Abstract: In described examples, a terminal (e.g., a conductive terminal) includes a base material, a plating stack and a solder finish. The base material can be a metal, such as copper. The plating stack is arranged on a surface of the base material, and includes breaks in the plating stack. The breaks in the plating stack extend from a first surface of the plating stack to a second surface of the plating stack adjacent to the surface of the base material. The solder finish is coated over the breaks in the plating stack.

Abstract: A method for forming a pattern includes: forming a preliminary pattern having a plate portion and a plurality of pad portions that protrude from an end of the plate portion over a substrate; forming a first hard mask pattern that includes a blocking portion covering the pad portions and a plurality of line portions partially covering the plate portion; forming a spacer on a sidewall of each of the line portions; forming a second hard mask pattern that fills a space between the line portions by contacting the spacer; forming an opening that exposes the plate portion between the first hard mask pattern and the second hard mask pattern by removing the spacer; and forming a plurality of line pattern portions that are respectively coupled to the pad portions by etching an exposed portion of the plate portion through the opening.

Abstract: Reliability of a semiconductor module is improved. In a resin mold step of assembly of a semiconductor module, an IGBT chip, a diode chip, a control chip, a part of each of chip mounting portions are resin molded so that a back surface of each of the chip mounting portions is exposed from a back surface of a sealing body. After the resin molding, an insulating layer is bonded to the back surface of the sealing body so as to cover each back surface (exposed portion) of the chip mounting portions, and then, a TIM layer is bonded to an insulating layer. Here, a region of the TIM layer in a plan view is included in a region of the insulating layer.

Abstract: The present disclosure describes methods of soldering on printed circuits, and, more specifically, to methods of using a copper-containing layer or copper “ink” in low-temperature soldering using established solder processes on silver-containing layers in circuit boards. The present disclosure is also directed, in part, to a solder joint having a copper-containing layer acting as a bonding layer between a traditional solder and a silver-containing layer “ink” on a printed circuit board. The low-temperature forming of the solder joint occurs at or below a temperature of 300° C. and occurs via at least one of sintering, photosintering, lasersintering, local resistive heating, or electrochemical deposition. The methods disclosed can satisfy the growing demand for creating reliable interconnection joints that can be used in next generation electronics and printed electrical circuit boards.

Abstract: In the present invention, a lower arm control substrate, an insulation material and an upper arm control substrate are layered to be arranged in this order on a top surface of a small-sized power module. An upper arm main region and a lower arm main region are arranged to overlap the insulation material in plan view, and large parts of the upper arm main region and the lower arm main region overlap each other in plan view. The upper arm control substrate and the upper arm control substrate are configured with substrates of the same structure and the lower arm control substrate has a positional relation with the upper arm control substrate so as to be rotated by 180° from the upper arm control substrate in a horizontal direction.

Abstract: A method which comprises applying a common pressing force operative to interconnect an electronic chip with a connector body by an interconnect structure, and to contribute to a forming of the connector body.

Abstract: Methods of forming a semiconductor package. Implementations include providing a leadframe, coupling a semiconductor die or an electronic component to the leadframe, and encapsulating at least a portion of the semiconductor die or the electronic component using a mold compound leaving two or more leads of the leadframe exposed. The method may also include coating the two or more leads of the leadframe with an electrically conductive layer. The method may include fully electrically and physically singulating one or more tie bars between two or more leads of the leadframe, a lead of the two or more leads and a leadframe flag, or any combination thereof. The method may also include singulating the leadframe to form one or more semiconductor packages.

Abstract: A lead frame strip having a plurality of unit lead frames is provided. Each of the unit lead frames have a die paddle and a plurality of leads extending away from the die paddle. A first one of the unit lead frames is plated with an adhesion promoter plating material within a package outline area of the first unit lead frame. The package outline area includes one of the die paddles and interior portions of the leads. Wire bond sites are processed in the first unit lead frame before or after the plating of the first lead frame such that, after the plating of the first lead frame. The wire bond sites are substantially devoid of the adhesion promoter plating material. The wire bond sites are disposed within the package outline area at an end of the interior portions of the leads that is closest to the die paddle.

Abstract: An electronic device has structures that are assembled using attachment structures. The attachment structures change shape to help join the electronic device structures together. Structures that may be joined together can include electronic device housing structures, display structures, internal device components, electrical components, and other portions of an electronic device. The attachment structures can include heat-activated attachment structures, structures that are activated using other types of applied energy, and structures that change shape due the application of chemicals or other treatments.

Abstract: A semiconductor device includes a leadframe having a flag and a plurality of bond terminals. A semiconductor die is attached to the leadframe at the flag. A bond pad is formed on the semiconductor die. A top surface layer of the bond pad includes copper having a predetermined grain orientation. A bond wire includes a first end and a second end. The bond wire is attached to the bond pad at the first end and attached to one of the bond terminals in the plurality at the second end.

Abstract: According to an embodiment of the present disclosure, a chip package including at least one chip, a first encapsulation layer, a redistribution layer, and a second encapsulation layer is provided. The at least one chip has an active surface, a back surface opposite to the active surface, and sidewall surfaces connecting the active surface and the back surface. The first encapsulation layer covers the sidewall surfaces. The first encapsulation layer has a first surface and a second surface opposite to the first surface. The redistribution layer is disposed on the active surface and the first surface, and electrically connected to the at least one chip. The second encapsulation layer is disposed on the back surface and the second surface. A thermal expansion coefficient of the second encapsulation layer is less than a thermal expansion coefficient of the first encapsulation layer. Chip packaging methods are also provided.

Abstract: The present invention provides a structure and a method of reinforcing a conductor soldering point of a semiconductor device. The structure includes an inner frame lead, a soldering area arranged on the surface of the inner frame lead, a conductor soldered in the soldering area, and a locking card including a pressing part, a locking part overhangs outwards from the pressing part pressed on the conductor. The locking part penetrates through the inner frame lead and is clamped on the side of the inner frame lead deviating from the conductor. According to the present invention, the conductor soldered on the inner frame lead is firmly clamped on the inner frame lead through the locking card to effectively avoid the stripping condition of the conductor and the inner frame lead, reinforce the electrical connection of the conductor and the inner frame lead, and improve the reliability of the semiconductor device.

Abstract: A component comprises at least one support on which is fixed at least one electronic circuit, for example a circuit of MMIC type, one or more layers of organic materials stacked on the support according to a technique of printed circuit type and forming a pre-existing cavity containing the electronic circuit, the cavity being filled with a material of low permeability to water vapor such as LCP.

Abstract: Methods and associated structures of forming a package structure including forming a low melting point solder material on a solder resist opening location of an IHS keep out zone, forming a sealant in a non SRO keep out zone region; attaching the IHS to the sealant, and curing the sealant, wherein a solder joint is formed between the IHS and the low melting point solder material.

Abstract: A lead frame strip having a plurality of unit lead frames is provided. Each of the unit lead frames includes a die paddle, a plurality of leads extending away from the die paddle, and a peripheral ring delineating interior portions of the leads from exterior portions of the leads. An adhesion promoter plating material is selectively plated within a package outline area of a first unit lead frame. The die paddle and the interior portions of the leads are disposed within the package outline area and the exterior portions of the leads are disposed outside of the package outline area. Wire bond sides are processed such that, after selectively plating the adhesion promoter plating material, the wire bond sites are substantially devoid of the adhesion promoter plating material. The wire bond sites are disposed within the package outline area and are spaced apart from the peripheral ring.

Abstract: A resin-encapsulated semiconductor device comprises a semiconductor chip mounted on a die pad. A plurality of leads each having an inner lead and an outer lead are arranged in spaced relation from the die pad with the inner leads facing the die pad. A metal plating layer is formed on top surfaces of the inner leads, and the inner leads are connected by metal wires to the semiconductor chip. An encapsulation resin encapsulates the semiconductor chip, die pad, metal wires and inner leads leaving the outer leads exposed. The outer edge of the metal plating layer coincides with the outer surface of the encapsulation resin and with the outer edge of the metal plating layer.

Abstract: A power semiconductor package includes a first direct bonded copper (DBC) substrate having a plurality of connection traces on a first face of the first DBC substrate. A plurality of die are coupled to the connection traces, each die coupled to one of the connection traces at a first face of the die. A second DBC substrate includes connection traces on a first face of the second DBC substrate. A second face of each die is coupled to one of the connection traces of the first face of the second DBC substrate. A cavity between the first face of the first DBC substrate and the first face of the second DBC substrate is filled with an encapsulating compound. Terminal pins may be coupled to connection traces on the first face of the first DBC substrate. More than two DBC substrates may be stacked to form a stacked power semiconductor package.

Abstract: A patterned, non-conductive substrate for an integrated circuit (IC) package has a die side configured to receive a die and a lead side opposite the die side. A pattern formed in the substrate defines openings (e.g., holes, steps, grooves, and/or cavities) that extend between the die side and the lead side of the substrate. In the IC package, the openings are filled with conductive material (e.g., solder) that supports electrical connections between bond pads on the die and leads formed from the conductive material. The substrate can be used to form a relatively inexpensive, quad flat no-lead (QFN) IC package without using a metal lead frame and without bond wires.

Abstract: A method of forming an electronic component includes masking a lead frame to form a mask defining an exposed area, oxidizing the exposed area of the lead frame, wherein the mask inhibits oxidation of an unexposed area, and removing the mask from the lead frame following oxidizing. A lead frame can include a metal sheet patterned to define a pad region and leads. The metal sheet includes metal oxide in a select area. The pad region is substantially free of metal oxide.

Abstract: A die comprising a body of semiconductor material, said body configured to receive a solder layer of gold containing alloy for use in die bonding said die to a substrate, wherein the die includes an interface layer on a surface of the body for receiving the solder layer, the interface layer having a plurality of sub-layers of different metals.

Abstract: Methods and associated structures of forming a package structure including forming a low melting point solder material on a solder resist opening location of an IHS keep out zone, forming a sealant in a non SRO keep out zone region; attaching the IHS to the sealant, and curing the sealant, wherein a solder joint is formed between the IHS and the low melting point solder material.

Abstract: A universal lead frame for semiconductor packages includes a solid lead frame sheet comprising an electrically conductive material and a plurality of columns etched into the lead frame sheet and distributed with a predetermined lead pitch so that the universal lead frame has a solid first main side opposite the columns and a patterned second main side opposite the first main side. A method of manufacturing the universal lead frame includes providing a solid lead frame sheet of an electrically conductive material and etching a plurality of columns into the lead frame sheet so that the columns are distributed with a predetermined lead pitch and the universal lead frame has a solid first main side opposite the columns and a patterned second main side opposite the first main side. A method of manufacturing molded semiconductor packages using the universal lead frame is also provided.

Abstract: A method of manufacturing a resin-encapsulated semiconductor device capable of supporting finer pitches comprises forming a metal plating layer on an inner lead and an outer lead of a lead. A semiconductor chip is mounted on a die pad, and an electrode on a surface of the semiconductor chip is electrically connected to the inner lead via a thin metal wire. The semiconductor chip, the thin metal wire and the inner lead are encapsulated by an encapsulation resin so that the outer lead extends beyond the encapsulation resin and is exposed. Resin burrs formed during resin encapsulation are removed by a defocused laser, and any metal adhered on the lead is lifted off.

Abstract: A solar cell having a molded lead frame, and method of manufacture of same, is disclosed. Specifically, a plurality of solar cells is manufactured from a strip of lead-frames and soft solder techniques for die assembly and component assembly. After wire bonding, glass attachment and transfer molding, a trim and form process produces individual solar cells having a molded lead frame.

Abstract: A semiconductor device includes a semiconductor element, a lead, and a wire including a first bonding portion bonded to the semiconductor element and a second bonding portion bonded to the lead. The semiconductor element includes a first bonding surface which faces to a first side in a first direction and to which the first bonding portion is bonded. The lead includes a second bonding surface and a third bonding surface both facing to the first side in the first direction and forming an angle larger than 180° on the first side in the first direction. The semiconductor device further includes a ball bump extending onto both the second bonding surface and the third bonding surface. The second bonding portion is bonded to the lead via the ball bump.

Abstract: Some exemplary embodiments of a multi-chip module (MCM) power quad flat no-lead (PQFN) semiconductor package utilizing a leadframe for electrical interconnections have been disclosed. One exemplary embodiment comprises a PQFN semiconductor package comprising a leadframe, a driver integrated circuit (IC) coupled to the leadframe, a plurality of vertical conduction power devices coupled to the leadframe, and a plurality of wirebonds providing electrical interconnects, including at least one wirebond from a top surface electrode of one of the plurality of vertical conduction power devices to a portion of the leadframe, wherein the portion of the leadframe is electrically connected to a bottom surface electrode of another of the plurality of vertical conduction power devices. In this manner, efficient multi-chip circuit interconnections can be provided in a PQFN package using low cost leadframes.

Abstract: The present invention discloses an electronic package structure. The body has a top surface with a cavity thereon, the first conductive element is disposed in the cavity, and the second conductive element is disposed in the body. The first external electrode electrically connected to the first conductive element and the second external electrode electrically connected to the second conductive element are both disposed on the top surface of the body or a first surface formed by the top surface of the encapsulation compound and the exposed portions of the top surface of the body which are not covered by the encapsulation compound.

Abstract: The present invention is a package for optical semiconductor devices, and an optical semiconductor device using the package, which can prevent discoloration of a plating layer formed on a lead frame even when a silicone resin is used as a sealing resin for an optical semiconductor device, and which enables high luminous efficiency for a long time. Specifically, in the package for semiconductor devices, a plating laminate 15, wherein a pure Ag plating layer 4, a thin reflective plating layer 6 serving as the uppermost layer for improving the light reflection ratio, and a resistant plating layer 5 serving as an intermediate layer therebetween and having chemical resistance against at least either metal chlorides or metal sulfides are laminated, is formed on at least the surface of a lead electrode. The reflective plating layer 4 is composed of a pure Ag thin film, and the resistant plating layer 5 is composed of a complete solid solution Au—Ag alloy plating layer.

Abstract: The present invention relates to a multi-row leadframe for semiconductor packaging, characterized by: forming a plating pattern on a leadframe material (first step); forming a protective pattern on the plating pattern (second step); and forming a nano pattern by using the protective pattern as a mask (third step), whereby a protective pattern is formed on an upper surface of a plating pattern to increase reliability of a product by preventing damage to a plating layer caused by etching solution during pattern formation of leadframe and to thereby solve the problem of using the plating layer as an etching mask.

Abstract: Embodiments provide a method of forming a chip package. The method may include attaching at least one chip on a carrier, the chip including a plurality of chip pads on a surface of the chip opposite to the carrier; depositing a first adhesion layer on the carrier and on the chip pads of the chip, the first adhesion layer including tin or indium; depositing a second adhesion layer on the first adhesion layer, the second adhesion layer including a silane organic material; and depositing a lamination layer or an encapsulation layer on the second adhesion layer and the chip.

Abstract: A lead frame and a semiconductor package including the lead frame are provided. The lead frame includes: a base material; a first metal layer which is formed on at least one side of the base material, of which a surface is roughly formed, and which includes copper or nickel; a second metal layer which is formed on a surface of the first metal layer, of which a surface is roughly formed, and which includes palladium or a palladium alloy; a third metal layer which is formed on a surface of the second metal layer, of which a surface is roughly formed, and which includes gold or a gold alloy; and a fourth metal layer which is formed on a surface of the third metal layer, of which a surface is roughly formed, and which includes metal that includes silver.

Abstract: A semiconductor package and a method of manufacturing the same, and more particularly, to a package of a power module semiconductor and a method of manufacturing the same. The semiconductor package includes a substrate including a plurality of conductive patterns spaced apart from one another; a plurality of semiconductor chips disposed on the conductive patterns; a connecting member for electrically connecting the conductive patterns to each other, for electrically connecting the semiconductor chips to each other, or for electrically connecting the conductive pattern and the semiconductor chip; and a sealing member for covering the substrate, the semiconductor chips, and the connecting member, wherein a lower surface of the substrate and an upper surface of the connecting member are exposed to the outside by the sealing member.

Abstract: A packaged power device involves no soft solder and no wire bonds. The direct-bonded metal layers of two direct metal bonded ceramic substrate assemblies, such as Direct Bonded Aluminum (DBA) substrates, are provided with sintered silver pads. Silver nanoparticle paste is applied to pads on the frontside of a die and the paste is sintered to form silver pads. Silver formed by an evaporative process covers the backside of the die. The die is pressed between the two DBAs such that direct silver-to-silver bonds are formed between sintered silver pads on the frontside of the die and corresponding sintered silver pads of one of the DBAs, and such that a direct silver-to-silver bond is formed between the backside silver of the die and a sintered silver pad of the other DBA. After leadforming, leadtrimming and encapsulation, the finished device has exposed ceramic of both DBAs on outside package surfaces.

Abstract: A semiconductor device includes a first semiconductor chip; an extension formed at a side surface of the first semiconductor chip; a connection terminal formed on the first semiconductor chip; a re-distribution part formed over the first semiconductor chip and the extension and including an interconnect connected to the connection terminal and an insulating layer covering the interconnect; and an electrode formed above the extension on a surface of the re-distribution part and connected to the interconnect at an opening of the insulating layer. The electrode is mainly made of a material having an elastic modulus higher than that of the interconnect. The electrode includes a bonding region where the electrode is bonded to the interconnect at the opening, and an outer region closer to an end part of the extension. The interconnect is formed so as not to continuously extend to a position right below the outer region.

Abstract: Disclosed herein are a power module package and a method for manufacturing the same. The power module package includes: first and second lead frames arranged to face each other, both or either of the first and second frames being made of aluminum; anodized layers formed on portions of the lead frame(s) made of aluminum in the first and second lead frames; and semiconductor devices mounted on first surfaces of the first and second lead frames.

Abstract: Methods and apparatus for package on package structures. A structure includes a first integrated circuit package including at least one integrated circuit device mounted on a first substrate, a plurality of package on package connectors extending from a bottom surface and arranged in a pattern of one or more rows proximal to an outer periphery of the first substrate; and a second integrated circuit package including at least another integrated circuit device mounted on a second substrate and a plurality of lands on an upper surface coupled to the plurality of package on package connectors, and a plurality of external connectors extending from a bottom surface of the second substrate; wherein the pattern of the external connectors is staggered from the pattern of the package on package connectors so that the package on package connectors are not in vertical alignment with the external connectors. Methods for forming structures are disclosed.

Abstract: Techniques for providing high-capacity, re-workable connections in concentrated photovoltaic devices are provided. In one aspect, a lead frame package for a photovoltaic device is provided that includes a beam shield; and one or more lead frame connectors affixed to the beam shield, wherein the lead frame connectors are configured to provide connection to the photovoltaic device when the photovoltaic device is assembled to the lead frame package. A photovoltaic apparatus is also provided that includes a lead frame package assembled to a photovoltaic device. The lead frame package includes a beam shield and one or more lead frame connectors affixed to the beam shield, wherein the lead frame connectors are configured to provide connection to the photovoltaic device.

Abstract: Provided is a light emitting device package, which includes a ceramic body, an ultraviolet light emitting diode, a support member, and a glass film. The ceramic body defines a cavity. The ultraviolet light emitting diode is disposed within the cavity. The support member is disposed on the body, and surrounds the cavity. The glass film is coupled to the support member, and covers the cavity. Since the light emitting device package includes the ceramic body to efficiently dissipate heat, and the glass film is directly attached to the ceramic body to decrease the number of components, thereby simplifying the manufacturing process thereof, and reducing the manufacturing costs thereof.

Abstract: The invention provides advances in the arts with useful and novel integrated packaging having inductor elements and adjacent magnetic material enhancing the inductance characteristics of the packaged inductor. Preferably the integrated packages also contain one or more ICs operable coupled to the inductor(s).

Abstract: The present invention relates to a multi-row leadframe for semiconductor packaging, characterized by: forming a plating pattern on a leadframe material (first step); forming a protective pattern on the plating pattern (second step); and forming a nano pattern by using the protective pattern as a mask (third step), whereby a protective pattern is formed on an upper surface of a plating pattern to increase reliability of a product by preventing damage to a plating layer caused by etching solution during pattern formation of leadframe and to thereby solve the problem of using the plating layer as an etching mask.

Abstract: According to one embodiment, an LED package includes first and second lead frames, an LED chip and a resin body. The first and second lead frames are apart from each other. The LED chip is provided above the first and second lead frames, the LED chip includes a semiconductor layer which contains at least indium, gallium and aluminum, one terminal of the LED chip is connected to the first lead frame, and another terminal of the LED chip is connected to the second lead frame. The resin body covers the LED chip and an entire upper surface, a part of a lower surface, and parts of edge surfaces of each of the first and second lead frames, and the resin body exposes a rest of the lower surface and a rest of the edge surfaces. And, an appearance of the resin body is a part of an appearance of the LED package.

Abstract: An apparatus comprising a metallic leadframe including a pad and a plurality of leads. Each having a first and a parallel second surface and sidewalls normal to the surfaces. The pad and each lead having a core of a first metal and layers of a second metal different from the first metal on each surface. The first metal exposed at the sidewalls and at portions of the first surface of the pad. A semiconductor chip is assembled on the leadframe. Portions of the assembled chip and the leadframe are packaged in a polymeric encapsulation compound.

Abstract: A chip package is provided, the chip package including: a chip carrier; a chip disposed over and electrically connected to a chip carrier top side; an electrically insulating material disposed over and at least partially surrounding the chip; one or more electrically conductive contact regions formed over the electrically insulating material and in electrical connection with the chip; a further electrically insulating material disposed over a chip carrier bottom side; wherein an electrically conductive contact region on the chip carrier bottom side is released from the further electrically insulating material.