Abstract: A chip arrangement is provided. The chip arrangement including: a chip including at least one electrically conductive contact; a passivation material formed over the at least one electrically conductive contact; an encapsulation material formed over the passivation material; one or more holes formed through the encapsulation material and the passivation material, wherein the passivation material at least partially surrounds the one or more holes; and electrically conductive material provided within the one or more holes, wherein the electrically conductive material is electrically connected to the at least one electrically conductive contact.

Abstract: A method of manufacturing, at a reduced cost, a semiconductor device assembly and a semiconductor device, having a conductive support which is not eroded by an etchant for a lift-off layer even when the lift-off layer is made of a material for which no suitable selective etching solution has been found is provided. In the method of manufacturing the semiconductor device assembly, a plating step of forming a conductive support is carried out such that a first metal which is dissolved with an etchant is encapsulated in second metal which are not dissolved with the etchant, and through-holes for supplying etchant are formed in the second metal.

Abstract: Some exemplary embodiments of a multi-chip module (MCM) power quad flat no-lead (PQFN) semiconductor package utilizing a leadframe for electrical interconnections have been disclosed. One exemplary embodiment comprises a PQFN semiconductor package comprising a leadframe, a driver integrated circuit (IC) coupled to the leadframe, a plurality of vertical conduction power devices coupled to the leadframe, and a plurality of wirebonds providing electrical interconnects, including at least one wirebond from a top surface electrode of one of the plurality of vertical conduction power devices to a portion of the leadframe, wherein the portion of the leadframe is electrically connected to a bottom surface electrode of another of the plurality of vertical conduction power devices. In this manner, efficient multi-chip circuit interconnections can be provided in a PQFN package using low cost leadframes.

Abstract: A lead frame for a resin-seal type semiconductor device, which includes a semiconductor element having an electrode, a bonding wire connected to the electrode of the semiconductor element, and a sealing resin covering and sealing the semiconductor element and the bonding wire. The lead frame includes a substrate frame, a four-layer plating, and a three-layer plating. The substrate frame include leads, a connection region, which is sealed by the sealing resin and connected to the bonding wire, and an exposed region, which is not sealed by the sealing resin. A four-layer plating is applied to a portion of the substrate frame that is to be connected to the bonding wire and sealed by the sealing resin. A three-layer plating is applied to an exposed region of the substrate frame that is exposed from the sealing resin.

Abstract: The present invention is directed to a semiconductor packaging solution wherein a high K thermal material such as a grease or gel is placed in a controlled thin bond line between the semiconductor die of the package and a heat sink in a direct manner using a thermal tape window frame as a low cost mechanical attachment mechanism. As the main thermal dissipation path is between the backside of the semiconductor die and the heat sink, a high K TIM material can be used to maximize thermal dissipation in a manner that does not require expensive mechanical attachment methods.

Abstract: A lead frame comprises: a base metal layer; a copper plating layer, including one of a copper layer and an alloy layer including a copper, configured to plate the based metal layer to make a surface roughness; and an upper plating layer, including at least one plating layer including at least one selected from the group of a nickel, a palladium, a gold, a silver, a nickel alloy, a palladium alloy, a gold alloy, and a silver alloy, configured to plate the copper plating layer.

Abstract: A housing for an optoelectronic semiconductor component includes a housing body having a mounting plane and a leadframe with a first connection conductor and a second connection conductor. The housing body deforms the leadframe in some regions. The leadframe has a main extension plane which extends obliquely or perpendicularly with respect to the mounting plane. A semiconductor component having such a housing and a semiconductor chip and a method for producing a housing are also disclosed.

Abstract: Method for manufacturing a rigid power module with a layer that is electrically insulating and conducts well thermally and has been deposited as a coating, the structure having sprayed-on particles that are fused to each other, of at least one material that is electrically insulating and conducts well thermally, having the following steps: manufacturing a one-piece lead frame; populating the lead frame with semiconductor devices, possible passive components, and bonding corresponding connections, inserting the thus populated lead frame into a compression mold so that accessibility of part areas of the lead frame is ensured, pressing a thermosetting compression molding compound into the mold while enclosing the populated lead frame, coating the underside of the thus populated lead frame by thermal spraying in at least the electrically conducting areas and overlapping also the predominant areas of the spaces, filled with mold compound.

Abstract: A lead frame (100) for a semiconductor device is formed by applying nickel plating (102), palladium plating (103), and gold flash plating (104) substantially entirely to lead frame body (101) such as copper thin plate in this order, and further applying silver plating (105) selectively to part of an inner part that is to be enclosed with a package of the semiconductor device. The lead frame (100) may also include a base of the package. The silver plating contributes to an excellent light reflectance and wire bonding efficiency of the inner part, whereas the gold flash plating contributes to an excellent resistance to corrosion and soldering efficiency of an outer part that is outside the package.

Abstract: A semiconductor device includes a lead frame, a semiconductor element mounted on the lead frame, and a frame-like member formed on the lead frame, surrounding the semiconductor element, and covering a side surface of the lead frame and exposing a lower surface of the lead frame. The frame-like member has at least one concave portion in a side surface thereof. The concave portion has a ceiling portion located at the same height as or lower than an upper surface of the lead frame, and a bottom portion located higher than the lower surface of the lead frame.

Abstract: An integrated circuit assembly is fabricated on a metal substrate strip in an array format that has raised circuitry pattern formed by photolithographic and metal etching processes. The circuitry pattern is formed on one side of the metal substrate only. The raised circuitry's etch depth extends partially through the metal substrate. Die attachment can be performed using a non-conductive material applied directly onto and around the raised circuitry features directly under the die. After wirebond and molding processes, the molded metal substrate strip assembly is processed through a metal etching process to remove the metal substrate portion that is exposed beyond the mold cap. A solder mask coating can be applied to protect the metal circuitry and to define the package pad opening to form Land-Grid-Array (LGA) packages. Solder balls can also be attached to form Ball-Grid-Array (BGA) packages.

Abstract: Reliability is improved by improving adhesiveness, crack resistance, and moisture resistance of a metal member-resin jointed body by enhancing adhesiveness between the metal member and the resin. A jointed body of a metal member and a resin including: an intermediate layer and a silane coupling agent layer formed on the metal member at an interface between the metal member and the resin, wherein the silane coupling agent layer and the resin are contacted; the intermediate layer is any one of an oxide layer of the metal, a chelating agent layer, a composite layer made of the oxide layer and the chelating agent layer, and a mixed layer made of the oxide and the chelating agent; and the intermediate layer has an electrically non-insulating characteristic, and a method of manufacturing the same.

Abstract: An integrated circuit package system includes: connecting an integrated circuit die and external interconnects; forming an encapsulation over the integrated circuit die and a portion of the external interconnects; and forming an isolation hole between the external interconnects and into a side of the encapsulation exposing the external interconnects.

Abstract: The present invention provides a Quad Flat Non-leaded (QFN) package, which comprises a chip, a lead frame, a plurality of composite bumps and an encapsulant. The chip has a plurality of pads, and the lead frame has a plurality of leads. Each of the plurality of composite bumps has a first conductive layer and a second conductive layer. The first conductive layer is electrically connected between one of the pads and the second conductive layer, and the second conductive layer is electrically connected between the first conductive layer and one of the leads. The encapsulant encapsulates the chip, the leads and the composite bumps. Thereby, a QFN package with composite bumps and a semi-cured encapsulant is forming between the spaces of leads of lead frame before chip bonded to the lead frame are provided.

Abstract: Provided are a semiconductor device and a method of forming a semiconductor device in which a plurality of patterns are simultaneously formed to have different widths and the pattern densities of some regions are increased using a double patterning.

Abstract: A lead frame includes a lead frame body 21 having a die pad 24 to which a semiconductor chip 12 is bonded and a plurality of leads 25 arranged around the die pad 24 and made of Cu or an alloy containing Cu, and a metallic film formed on the lead frame body 21 and to connected to a metallic wire 15 connected to the electrode pad 36 of the semiconductor chip 12. The metallic film is an Ag-plated film 22 with nanoparticles 34 arranged in gaps 33 among Ag crystal grains 31.

Abstract: An electronic device is disclosed. In one embodiment, the electronic device includes a substrate, a plurality of conducting lines formed on a first conducting material that is disposed on the substrate, and a layer of a second conducting material disposed on the plurality of conducting lines. The conducting lines include a top face and a side face. The layer of the second conducting material includes a first thickness disposed on each of the top faces and a second thickness disposed on each of the side faces. To this end, the first thickness is greater than the second thickness.

Abstract: Some exemplary embodiments of a multi-chip module (MCM) power quad flat no-lead (PQFN) semiconductor package utilizing a leadframe for electrical interconnections have been disclosed. One exemplary embodiment comprises a PQFN semiconductor package comprising a leadframe, a driver integrated circuit (IC) coupled to the leadframe, a plurality of vertical conduction power devices coupled to the leadframe, and a plurality of wirebonds providing electrical interconnects, including at least one wirebond from a top surface electrode of one of the plurality of vertical conduction power devices to a portion of the leadframe, wherein the portion of the leadframe is electrically connected to a bottom surface electrode of another of the plurality of vertical conduction power devices. In this manner, efficient multi-chip circuit interconnections can be provided in a PQFN package using low cost leadframes.

Abstract: A leadframe for a QFN/SON semiconductor device comprising a strip of a first metal as the leadframe core with a plurality of leads and a pad. a layer of a second metal over both surfaces of the strip. There are sidewalls normal to the surfaces. The first metal exposed at the sidewalls and at portions of a surface of the pad.

Abstract: A semiconductor device includes a semiconductor element; a group of back-inner terminals coupled with the semiconductor element through bonding wires and arranged in an area array shape so as to be exposed inside of the bottom; a group of back-outer terminals arranged outside the group of back-inner terminals; a group of front-outer terminals located immediately above the back-outer terminals to be exposed from the front surface, which are electrically coupled with the back-outer terminals located immediately therebelow through coupling conductors, respectively; and a sealing resin which seals the semiconductor element and bonding wires and non-exposed portions of said back-inner terminals, back-outer terminals and front-outer terminals. On at least the respective terminal faces of said back-inner terminals, back-outer terminals and front-outer terminals, noble-metal plated layers are formed.

Abstract: A method and a system for improving reliability of a semiconductor device are provided. In one embodiment, a semiconductor device is provided comprising a semiconductor chip, a metallization layer comprising a metallic material disposed over a surface of the semiconductor chip, and an alloy layer comprising the metallic material disposed over the metallization layer.

Abstract: A leadframe includes a die paddle and leads, in which the back side of the die paddle has a fillister. The fillister defines a rim surrounding a recess, and the recess accommodates protrusion of fusible material. Also, a package includes such a leadframe. Also, a method for making a leadframe includes patterning a sheet of metal to form a die paddle and leads, and forming a fillister in the back side of the die paddle.

Abstract: An integrated circuit package system includes providing a leadframe that is coplanar with a bottom surface of the integrated circuit package system to which is attached a device with a thermally conductive coating that is coplanar with the bottom surface of the integrated circuit package system to the leadframe, the device having the characteristics of being singulated from a wafer and the thermally conductive coating having the characteristics of being singulated from a wafer level thermally conductive coating and encapsulating the device with an encapsulation material that leaves the thermally conductive coating exposed for thermal dissipation.

Abstract: A cost-effective, ultra-compact, hybrid power module packaging system and method for making allows device operation in conventional and high temperature ranges over 300° C. Double metal leadframes are directly bonded to the front- and backside of semiconductor chips, and injection-molded high temperature polymer materials encapsulate the module. The invention eliminates the use of unreliable metal wirebonds and solders joints, and expensive aluminum nitride ceramic substrates commonly used in conventional and high temperature hybrid power modules. Advantages of the new power modules include high current carrying capability, low package parasitic impedance, low thermo-mechanical stress under high temperature cycling, low package thermal resistance (double-side cooling), modularity for easy system-level integration, and low-cost manufacturing of devices compatible with current electronic packaging industry. A first embodiment uses molybdenum leadframes for operation in temperatures over 300° C.

Abstract: An optical semiconductor device can have a first lead for an optical semiconductor chip to be mounted on and a second lead for joining to a wire extending from the optical semiconductor chip. The device can be configured to be capable of reducing the possibility of a break of the wire even under a thermal shock and the like. The optical semiconductor device can include a first lead for an optical semiconductor chip to be mounted on, a second lead for joining to a wire (for example, gold wire) extending from the optical semiconductor chip mounted on the first lead; a holder part for supporting the first lead and the second lead at two locations each; a lens part; and a light-transmitting sealing part. The second lead can be separated into two lead pieces with a predetermined gap (?0) therebetween as seen in a plan view, or with certain bend configurations as shown in side views, within the inside space of the holder part by which the second lead is supported at two locations.

Abstract: The present invention relates to a multi-row leadframe for semiconductor packaging, characterized by: forming a plating pattern on a leadframe material (first step); forming a protective pattern on the plating pattern (second step); and forming a nano pattern by using the protective pattern as a mask (third step), whereby a protective pattern is formed on an upper surface of a plating pattern to increase reliability of a product by preventing damage to a plating layer caused by etching solution during pattern formation of leadframe and to thereby solve the problem of using the plating layer as an etching mask.

Abstract: Provided are a semiconductor device lead frame and a method of manufacturing of the same that improve adhesive properties between plating layers when a plurality of plating layers are laminated, that control deterioration in wire bonding properties during the manufacturing process of a semiconductor device and worsening of solderability during packaging, and that effectively reduce manufacturing cost. Specifically, the lead frame (2a, 2b) has a laminated structure that includes a lower plating layer (22) formed on a conductive base material (21) and an uppermost plating layer (23), with an organic film (22) that has metal-binding properties formed between the lower plating layer (21) and the uppermost plating layer (23). The organic film (22) is formed as a monomolecular film in which functional organic molecules (11) self assemble. Each of the organic molecules (11) has functional groups (A1, A1) with metal-binding properties on both ends of a main chain (B1).

Abstract: A carrying structure of semiconductor includes a carrier made of a plastic material with a heat conduction region, each surface of the carrier has an interface layer formed on, and an electrically insulation circuit and a metal layer are defined on the interface layer. The insulation circuit is located on the surface of the heat conduction region and on an encircling annular region extended from two surfaces of the heat conduction region, and at the same time exposing parts of the carrier surface thereby splitting the metal layer on the interface layer into at least two electrodes. A thermal conductor formed in the heat conduction region has a LED chip adhered on it which has at least a contact point connected with the corresponding metal layer with a metal wiring so as to dissipate the heat generated by the chip rapidly with the thermal conductor.

Abstract: A Cu—Fe—P alloy sheet that is provided with the high strength and with the improved resistance of peel off of oxidation film, in order to deal with problems such as package cracks and peeling, is provided. A copper alloy sheet for electric and electronic parts according to the present invention is a copper alloy sheet containing Fe: 0.01 to 0.50 mass % and P: 0.01 to 0.15 mass %, respectively, with the remainder of Cu and inevitable impurities. A centerline average roughness Ra is 0.2 ?m or less and a maximum height Rmax is 1.5 ?m or less, and Kurtosis (degree peakedness) Rku of roughness curve is 5.0 or less, in measurement of the surface roughness of the copper alloy sheet in accordance with JIS B0601.

Abstract: A resin-encapsulated semiconductor device having a semiconductor chip which is prevented from being damaged. The resin-encapsulated semiconductor device comprises a semiconductor chip including a silicon substrate, a die pad to which the semiconductor chip is secured through a first solder layer, a resin-encapsulating layer encapsulating the semiconductor chip, and lead terminals electrically connected to the semiconductor chip and including inner lead portion covered with the resin-encapsulating layer. The lead terminals are made of copper or a copper alloy. The die pad is made of 42 alloy or a cover alloy and has a thickness (about 0.125 mm) less than the thickness (about 0.15 mm) of the lead terminals.

Abstract: An electrical connection arrangement between a semiconductor circuit arrangement and an external contact device, and to a method for producing the connection arrangement is disclosed. In one embodiment, a metallic layer is deposited onto at least one contact terminal and/or the contacts and the wire, the metallic layer protecting the contact terminal or the electrical connection against ambient influences and ensuring a high reliability.

Abstract: Provided are a semiconductor device lead frame and a method of manufacturing of the same that improve adhesive properties between plating layers when a plurality of plating layers are laminated, that control deterioration in wire bonding properties during the manufacturing process of a semiconductor device and worsening of solderability during packaging, and that effectively reduce manufacturing cost. Specifically, the lead frame (2a, 2b) has a laminated structure that includes a lower plating layer (22) formed on a conductive base material (21) and an uppermost plating layer (23), with an organic film (22) that has metal-binding properties formed between the lower plating layer (21) and the uppermost plating layer (23). The organic film (22) is formed as a monomolecular film in which functional organic molecules (11) self assemble. Each of the organic molecules (11) has functional groups (A1, A1) with metal-binding properties on both ends of a main chain (B1).

Abstract: A method of manufacture of a thin package system with external terminals includes: providing a leadframe; providing a template for defining an external bond finger; forming external bond fingers in the template on the leadframe; forming land pad terminals by a first multi-layer plating; providing a die; attaching the die to the land pad terminals above the leadframe with an adhesive on the leadframe; covering an encapsulant over at least portions of the die and the external bond fingers; and removing the leadframe leaving a surface of the adhesive coplanar with a surface of the encapsulant.

Abstract: The present invention relates to a semiconductor package, comprising a carrier, a semiconductor device, a first wire and a second wire. The carrier has a first electrically connecting portion and a second electrically connecting portion. The semiconductor device has a plurality of pads. The first wire electrically connects one of the pads of the semiconductor device and the first electrically connecting portion of the carrier, and the first wire has a first length. The second wire electrically connects one of the pads of the semiconductor device and the second electrically connecting portion of the carrier, and the second wire has a second length. The second length is larger than the first length, and the diameter of the second wire is larger than that of the first wire. Thus, the material usage for the wire is reduced, and the manufacturing cost is reduced.

Abstract: A lead frame (100) for a semiconductor device is formed by applying nickel plating (102), palladium plating (103), and gold flash plating (104) substantially entirely to lead frame body (101) such as copper thin plate in this order, and further applying silver plating (105) selectively to part of an inner part that is to be enclosed with a package of the semiconductor device. The lead frame (100) may also include a base of the package. The silver plating contributes to an excellent light reflectance and wire bonding efficiency of the inner part, whereas the gold flash plating contributes to an excellent resistance to corrosion and soldering efficiency of an outer part that is outside the package.

Abstract: A method of packaging an integrated circuit, including providing a lead frame having lead fingers, where the lead frame has a gold layer thereon on a top surface and a bottom surface. An integrated circuit die is attached to the lead frame. The gold layer is substantially removed from portions of the top surface of the lead frame. The integrated circuit die is wire bonded to the lead fingers with a plurality of wire stitches subsequent to substantially removing the gold. The die is encapsulated in a mold compound to form a packaged integrated circuit.

Abstract: An integrated circuit package system is provided including: forming a plurality of leads with a predetermined thickness and a predetermined interval gap between each of the plurality of leads; configuring each one of the plurality of leads to include first terminal ends disposed adjacent an integrated circuit and second terminal ends disposed along a periphery of a package; and forming the second terminal ends of alternating leads disposed along the periphery of the package to form an etched lead-to-lead gap in excess of the predetermined interval gap.

Abstract: A lead frame includes a base material having a front surface for mounting of a semiconductor chip and a back surface for connection with an external board, and an Ni layer having a thick section and thin section. The thick section is formed on the back surface of the base material, whereas the thin section is formed on all or a part of the front surface of the base material. It is preferable that the thick section has a thickness ranging from 2.5 to 5 ?m, and the thin section is 0.5-2 ?m thinner than the thick section. The lead frame can be manufactured with improved productivity by forming an Ni layer on both front and back surfaces of the base material, and then etching only the Ni layer formed on the front surface of the base material.

Abstract: An integrated circuit package system includes: providing a die attach paddle with interconnection pads connected to a bottom surface of the die attach paddle; connecting a first device to the interconnection pads with a bond wire; connecting a lead to the interconnection pad or to the first device; encapsulating the first device and the die attach paddle with an encapsulation having a top surface; and etching the die attach paddle leaving a recess in the top surface of the encapsulation.

Abstract: A semiconductor device (7) has gold coatings (1 to 5) which are applied to metallic or ceramic components (6) of the semiconductor device (7). The gold coatings (1 to 4) have a multifunctional multilayer metal coating (8) with a minimal gold layer (9). The gold layer has a thickness dG where dG?0.5 ?m. Moreover, at least one metallic interlayer (10) is arranged between the gold layer (9) and the metallic or ceramic components (6).

Abstract: The present invention proposes a semiconductor device including a semiconductor chip having a plurality of electrodes, a plurality of leads electrically connected to the plurality of electrodes of the semiconductor chip by bonding wires, and a resin for implementing the semiconductor chip, wherein the plurality of leads are comprised of two or more kinds of leads having different rigidities.

Abstract: A packaging conductive structure for a semiconductor substrate and a method for forming the structure are provided. The dielectric layer of the packaging conductive structure partially overlays the metallic layer of the semiconductor substrate and has a receiving space. The lifting layer and conductive layer are formed in the receiving space, wherein the conductive layer extends for connection to a bump. The lifting layer is partially connected to the dielectric layer. As a result, the conductive layer can be stably deposited on the edge of the dielectric layer for enhancing the reliability of the packaging conductive structure.

Abstract: A multi-chip module suitable for use in a battery protection circuit. The multi-chip module includes an integrated circuit chip, a first power transistor, a second power transistor, a first connection structure electrically coupling the integrated circuit chip to the first power transistor, a second connection structure electrically coupling the integrated circuit chip to the second power transistor, and a leadframe structure comprising a first lead, a second lead, a third lead and a fourth lead, wherein the integrated circuit chip, the first power transistor, and the second power transistor are mounted on the leadframe structure. A molding material covers at least part of the integrated circuit chip, the first power transistor, the second power transistor, the first connection structure, and the second connection structure.

Abstract: While a semiconductor device is provided with a plurality of element electrodes 5 formed on a semiconductor element 4 and a plurality of lead terminal electrodes 6 formed on a lead frame, the semiconductor device is equipped with a coupling conductor which electrically connects at least one electrode among the above-described element electrodes 5 to at least one electrode among the above-described lead terminal electrodes 6; the above-described coupling conductor is manufactured by a first conductor 1 and a second conductor 2, the major components of which are metals; the first conductor 1 has been electrically connected to the second conductor 2; and the element electrodes 5 and the lead terminal electrodes 6 have been electrically connected to the second conductor 2 respectively.

Abstract: The semiconductor device according to the present invention includes a semiconductor chip, a solid plate to which the semiconductor chip is bonded, and a bonding member made of a BiSn-based material interposed between the semiconductor chip and the solid plate, while the bonding member has a heat conduction path made of Ag for improving heat conductivity between the semiconductor chip and the solid plate.

Abstract: To hermetically seal a cavity in a microelectronic component, a cap located in a sealing device is positioned above the orifice opening into the cavity. The cap plastically deforms to seal the cavity. The sealing device includes a cavity permitting the cavity of the microelectronic component to be filled. The sealing device slides along the component so as to be positioned opposite either the filling cavity, or the cap.

Abstract: A semiconductor device has a leadframe with a structure made of a base metal (105), wherein the structure consists of a chip mount pad (402) and a plurality of lead segments (403). Covering the base metal are, consecutively, a nickel layer (301) on the base metal, and a continuous layer of noble metal, which consists of a gold layer (201) on the nickel layer, and an outermost palladium layer (202) on the gold layer. A semiconductor chip (410) is attached to the chip mount pad and conductive connections (412) span from the chip to the lead segments. Polymeric encapsulation compound (420) covers the chip, the connections, and portions of the lead segments. In QFN devices with straight sides (501), the compound forms a surface (421) coplanar with the outermost palladium layer (202) on the un-encapsulated leadframe surfaces.

Abstract: Semiconductor die packages are disclosed. An exemplary semiconductor die package includes a premolded substrate. The premolded substrate can have a semiconductor die attached to it, and an encapsulating material may be disposed over the semiconductor die.

Abstract: Aspects of the invention are directed towards an integrated circuit package and method of forming the same, and more particularly to a redistributed chip packaging for an integrated circuit. The integrated circuit package includes an integrated circuit having a protective material on at least a portion of the integrated circuit. A lead frame is coupled to the integrated circuit and a conductive layer is also coupled to the interconnect. A solder ball is coupled to the conductive layer and a passivation layer is on the conductive layer. Active and passive components are electrically coupled to the integrated circuit.

Abstract: A composite ?-Ta/graded tantalum nitride/TaN barrier layer is formed in Cu interconnects with a controlled surface roughness for improved adhesion, electromigration resistance and reliability. Embodiments include lining a damascene opening, such as a dual damascene opening in a low-k interlayer dielectric, with an initial layer of TaN, forming a graded tantalum nitride layer on the initial TaN layer and then forming an ?-Ta layer on the graded TaN layer, the composite barrier layer having an average surface roughness (Ra) of about 25 ? to about 50 ?. Embodiments further include controlling the surface roughness of the composite barrier layer by varying the N2 flow rate and/or ratio of the thickness of the combined ?-Ta and graded tantalum nitride layers to the thickness of the initial TaN layer.