For Erasing Eprom Patents (Class 257/681)
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Patent number: 11282763Abstract: In one example, a semiconductor device, includes a substrate having a top side and a conductor on the top side of the substrate, an electronic device on the top side of the substrate connected to the conductor on the top side of the substrate via an internal interconnect, a lid covering a top side of the electronic device, and a thermal material between the top side of the electronic device and the lid, wherein the lid has a through-hole. Other examples and related methods are also disclosed herein.Type: GrantFiled: June 24, 2019Date of Patent: March 22, 2022Assignee: Amkor Technology Singapore Holding Pte. Ltd.Inventors: Keun Soo Kim, Young Ik Kwon, Yu Jin Jeon, Mi Kyoung Choi
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Patent number: 10636718Abstract: A packaging module includes a substrate, a chip firmly mounted on the substrate, a frame firmly connected to the substrate via a gold-to-gold bonding and a cover firmly connected to the frame via the same gold-to-gold bonding. With the inorganic bonding structure, the packaging module is able to endure high temperature and high pressure without the worry of bonding agent being damaged by environmental condition change.Type: GrantFiled: September 21, 2018Date of Patent: April 28, 2020Assignee: Chang Sheng Hsiang ChangInventor: Sheng Hsiang Chang
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Nanomaterial having tunable infrared absorption characteristics and associated method of manufacture
Patent number: 10358350Abstract: A quantum nanomaterial having a bandgap that may be tuned to enable the quantum nanomaterial to detect IR radiation in selected regions including throughout the MWIR region and into the LWIR region is provided. The quantum nanomaterials may include tin telluride (SnTe) nanomaterials and/or lead tin telluride (PbxSn1-xTe) nanomaterials. Additionally, a method of manufacturing nanomaterial that is tunable for detecting IR radiation in selected regions, such as throughout the MWIR region and into the LWIR region, is also provided.Type: GrantFiled: June 23, 2017Date of Patent: July 23, 2019Assignee: THE BOEING COMPANYInventors: Larken Elizabeth Cumberland, Adam Franklin Gross, Keith John Davis, Nicole L. Abueg -
Patent number: 10323979Abstract: Disclosed are an ultraviolet measuring device, a photodetector, an ultraviolet detector, an ultraviolet index calculation device, and an electronic device or portable terminal including the same. In one aspect, an ultraviolet measuring is provided to comprise: a substrate on which an electrode is formed; a readout integrated circuit (ROTC) unit electrically connected with the electrode; and an aluminum gallium nitride (AlGaN) based UVB sensor electrically connected with the readout integrated circuit unit and formed on an insulating substrate, wherein the read-out integrated circuit converts a photocurrent input from the UV sensor into a digital signal including UV data.Type: GrantFiled: May 3, 2016Date of Patent: June 18, 2019Assignee: SEOUL VIOSYS CO., LTD.Inventors: Ki Yon Park, Choong Min Lee, Hwa Mok Kim, Soo Hyun Lee, Gun Woo Han
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Patent number: 10270021Abstract: Provided is a light emitting device package. The light emitting device package comprises a body, a heat diffusing member, a light emitting diode (LED), and a buffer layer. A cavity with an opened topside is formed in the body. The heat dissipation member is disposed between a bottom surface of the cavity and a lower surface of the body. The LED is disposed on one of an electrode disposed on the bottom surface of the cavity. The buffer layer is disposed between the heat dissipation member and a pad and has a thickness thinner than a thickness of the heat dissipation member.Type: GrantFiled: May 11, 2012Date of Patent: April 23, 2019Assignee: LG INNOTEK CO., LTD.Inventors: Gun Kyo Lee, Su Jung Jung, Yu Dong Kim, Byung Mok Kim
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Patent number: 10167566Abstract: A substrate (5) in which a surface of an aluminum base (10) other than a surface on which an insulating thin film layer (17) is formed is covered with a protective layer (19) which is an aluminum anodic oxide film.Type: GrantFiled: July 25, 2014Date of Patent: January 1, 2019Assignee: SHARP KABUSHIKI KAISHAInventors: Masahiro Konishi, Shin Itoh
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Patent number: 9799637Abstract: The present disclosure relates to a semiconductor package with a lid that includes a lid conductive structure. The semiconductor package includes a substrate with a top surface, a lid over the top surface of the substrate, and at least one substrate-mounted component mounted on the top surface of the substrate. Herein, a cavity is defined within the lid and over the top surface of the substrate. The substrate includes a metal pad over the top surface of the substrate. The lid includes a lid conductive structure, a lid body, and a perimeter wall that extends from a perimeter of the lid body toward the top surface of the substrate. The lid conductive structure includes a body conductor that extends through a portion of the lid body and a wall conductor that is coupled to the body conductor, extends through the perimeter wall, and is electronically coupled to the metal pad.Type: GrantFiled: October 13, 2016Date of Patent: October 24, 2017Assignee: Qorvo US, Inc.Inventors: Brian P. Balut, Jonathan Fain, Kevin J. Anderson, Tarak A. Railkar
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Patent number: 9560757Abstract: A chip component includes external terminals on a mounting surface thereof at positions that are rotationally symmetric to each other by 180 degrees with respect to a center of the mounting surface. A substrate includes first and second mounting terminals on the mounting surface of the substrate at first diagonal positions of a square indicated by a two dot chain line, and third and fourth mounting terminals on the surface of the substrate at second diagonal positions of the square. The first and fourth mounting terminals are connected by a first terminal connecting portion, and the second and third mounting terminals are connected by a second terminal connecting portion. The chip component is configured to be mounted in any of four directions obtained by rotating the chip component every 90 degrees and achieves the same electrical characteristics.Type: GrantFiled: May 21, 2015Date of Patent: January 31, 2017Assignee: Murata Manufacturing Co., Ltd.Inventors: Hiromi Murayama, Kazuaki Higashibata, Noboru Kato
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Patent number: 9070695Abstract: An integrated circuit package for an integrated circuit having one or more sensor elements in a sensor element area of the circuit. An encapsulation covers bond wires but leaves an opening over the sensor element area. A protection layer is provided over the integrated circuit over which the encapsulation extends, and it has a channel around the sensor element area to act as a trap for any encapsulation material which has crept into the opening area.Type: GrantFiled: September 11, 2012Date of Patent: June 30, 2015Assignee: NXP, B.V.Inventors: Roel Daamen, Hendrik Bouman, Coenraad Cornelis Tak
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Patent number: 8624371Abstract: Packaging assemblies for optically interactive devices and methods of forming the packaging assemblies in an efficient manner that eliminates or reduces the occurrence of process contaminants. In a first embodiment, a transparent cover is attached to a wafer of semiconductor material containing a plurality of optically interactive devices. The wafer is singulated, and the optically interactive devices are mounted on an interposer and electrically connected with wire bonds. In a second embodiment, the optically interactive devices are electrically connected to the interposer with back side conductive elements. In a third embodiment, the optically interactive devices are mounted to the interposer prior to attaching a transparent cover. A layer of encapsulant material is formed over the interposer, and the interposer and encapsulant material are cut to provide individual packaging assemblies. In a fourth embodiment, the optically interactive devices are mounted in a preformed leadless chip carrier.Type: GrantFiled: April 19, 2013Date of Patent: January 7, 2014Assignee: Round Rock Research, LLCInventors: Todd O. Bolken, Chad A. Cobbley
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Patent number: 8526194Abstract: The invention provides an anti-UV electronic device and fabrication method thereof. The anti-ultraviolet (anti-UV) electronic device includes an integrated circuit die, wherein the integrated circuit die has an ultraviolet (UV) light erasable memory; and an anti-UV light layer is formed on and covers the ultraviolet (UV) light erasable memory.Type: GrantFiled: May 25, 2011Date of Patent: September 3, 2013Assignee: Princeton Technology CorporationInventor: Hwa-Hsiang Chang
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Patent number: 8426954Abstract: Packaging assemblies for optically interactive devices and methods of forming the packaging assemblies in an efficient manner that eliminates or reduces the occurrence of process contaminants. In a first embodiment, a transparent cover is attached to a wafer of semiconductor material containing a plurality of optically interactive devices. The wafer is singulated, and the optically interactive devices are mounted on an interposer and electrically connected with wire bonds. In a second embodiment, the optically interactive devices are electrically connected to the interposer with back side conductive elements. In a third embodiment, the optically interactive devices are mounted to the interposer prior to attaching a transparent cover. A layer of encapsulant material is formed over the interposer, and the interposer and encapsulant material are cut to provide individual packaging assemblies. In a fourth embodiment, the optically interactive devices are mounted in a preformed leadless chip carrier.Type: GrantFiled: August 18, 2011Date of Patent: April 23, 2013Assignee: Round Rock Research, LLCInventors: Todd O. Bolken, Chad A. Cobbley
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Patent number: 8022519Abstract: A system-in-a-package based flash memory card including an integrated circuit package occupying a small overall area within the card and cut to conform to the shape of a lid for the card. An integrated circuit may be cut from a panel into a shape that fits within and conforms to the shape of lids for a finished memory card, such as for example an SD Card. The integrated circuit package may be a system-in-a-package, a multi-chip module, or other arrangement where a complete electronic system is formed in a single package.Type: GrantFiled: May 19, 2005Date of Patent: September 20, 2011Assignee: SanDisk Technologies Inc.Inventors: Hem Takiar, Robert C. Miller, Warren Middlekauff, Michael W. Patterson, Shrikar Bhagath
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Patent number: 8008770Abstract: An integrated circuit package system includes an integrated circuit, and forming a patterned redistribution pad over the integrated circuit.Type: GrantFiled: November 2, 2006Date of Patent: August 30, 2011Assignee: Stats Chippac Ltd.Inventors: Yaojian Lin, Romeo Emmanuel P. Alvarez, Haijing Cao, Wan Lay Looi
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Patent number: 8008762Abstract: Packaging assemblies for optically interactive devices and methods of forming the packaging assemblies in an efficient manner that eliminates or reduces the occurrence of process contaminants. In a first embodiment, a transparent cover is attached to a wafer of semiconductor material containing a plurality of optically interactive devices. The wafer is singulated, and the optically interactive devices are mounted on an interposer and electrically connected with wire bonds. In a second embodiment, the optically interactive devices are electrically connected to the interposer with back side conductive elements. In a third embodiment, the optically interactive devices are mounted to the interposer prior to attaching a transparent cover. A layer of encapsulant material is formed over the interposer, and the interposer and encapsulant material are cut to provide individual packaging assemblies. In a fourth embodiment, the optically interactive devices are mounted in a preformed leadless chip carrier.Type: GrantFiled: December 28, 2006Date of Patent: August 30, 2011Assignee: Round Rock Research, LLCInventors: Todd O. Bolken, Chad A. Cobbley
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Patent number: 7964945Abstract: A glass cap molding package includes a substrate with an external connection terminal formed on a peripheral region of a top surface; an image sensor mounted on the top surface of the substrate; a transparent member installed on an upper part of the image sensor; and a molding unit formed to seal the image sensor and the transparent member. The mold unit exposes the external connection terminal of the substrate to a lateral surface of the substrate. The glass cap molding package and a manufacturing method thereof and a camera module including the same reduce a manufacturing cost and improve productivity by manufacturing a small module in comparison with a conventional module and simplifying a process.Type: GrantFiled: August 20, 2008Date of Patent: June 21, 2011Assignee: Samsung Electro-Mechanics Co., Ltd.Inventors: Jin Mun Ryu, Jung Seok Lee, Hyung Kyu Park, Bo Kyoung Kim, Yun Seok Woo, Jung Jin Kim
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Patent number: 7964954Abstract: An integrated circuit having a semiconductor sensor device including a sensor housing partly filled with a rubber-elastic composition is disclosed. One embodiment has a sensor chip with sensor region arranged in the interior of the housing. The sensor housing has an opening to the surroundings which is arranged in such a way that the sensor region faces the opening. The sensor chip is embedded into a rubber-elastic composition on all sides in the interior of the housing. The sensor housing has a sandwich-like framework having three regions arranged one above another, including an intermediate region with the rubber-elastic composition.Type: GrantFiled: March 19, 2007Date of Patent: June 21, 2011Assignee: Infineon Technologies AGInventor: Jean Schmitt
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Patent number: 7869279Abstract: A memory device including a plurality of memory cells, each with access and program PMOS transistors situated in a common N-Well formed in a P-substrate, and an n-erase pocket formed directly in the P-substrate. Each cell includes a program PMOS including gate, and first and second P+ regions formed in an N-Well, wherein the first P+ region is electrically connected to a corresponding bit line. Each cell further comprises an access PMOS including a gate, and first and second P+ regions formed within the same n-doped well as the first and second P+ regions of the program PMOS, wherein the first P+ region is electrically connected to the second P+ region of the program PMOS, and the gate is electrically connected to a corresponding word line. Each cell further includes an n-doped erase pocket including gate, and first and second N+ regions electrically connected to a corresponding erase line, and the gate is electrically connected to the gate of the program PMOS, forming the floating gate of the cell.Type: GrantFiled: July 18, 2008Date of Patent: January 11, 2011Assignee: Maxim Integrated Products, Inc.Inventor: Kola Nirmal Ratnakumar
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Patent number: 7683477Abstract: A semiconductor device is disclosed. One embodiment provides a device including a carrier, an electrically insulating layer arranged over the carrier and a first semiconductor chip arranged over the electrically insulating layer, wherein the first semiconductor chip has a first contact element on a first surface and a second contact element on a second surface.Type: GrantFiled: June 26, 2007Date of Patent: March 23, 2010Assignee: Infineon Technologies AGInventor: Ralf Otremba
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Patent number: 7605455Abstract: With this semiconductor device, the distortion and cracking of a thinned portion of a semiconductor substrate are prevented to enable high precision focusing with respect to a photodetecting unit and uniformity and stability of high sensitivity of the photodetecting unit to be maintained. A semiconductor device 1 has a semiconductor substrate 10, a wiring substrate 20, conductive bumps 30, and a resin 32. A CCD 12 and a thinned portion 14 are formed on semiconductor substrate 10. Electrodes 16 of semiconductor substrate 10 are connected via conductive bumps 30 to electrodes 22 of wiring substrate 20. Wiring substrate 20 has formed therein a groove portion 26a that surrounds a region opposing thinned portion 14 and groove portions 26b that extend to an exposed surface of wiring substrate 20 from groove portion 26a. Insulating resin 32 fills a gap between outer edge 15 of thinned portion 14 and wiring substrate 20 to reinforce the bonding strengths of conductive bumps 30.Type: GrantFiled: September 24, 2004Date of Patent: October 20, 2009Assignee: Hamamatsu Photonics K.K.Inventors: Hiroya Kobayashi, Masaharu Muramatsu
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Patent number: 7545036Abstract: A semiconductor device includes a semiconductor substrate having a main surface, the main surface including a first and second areas formed with a high-frequency circuit element, and a third area located around the first and second areas and formed with a low-frequency circuit element. The semiconductor device also includes a sealing resin which covers the main surface; a plurality of first external terminals which are formed above the third area and which are electrically connected to the high-frequency circuit element, the first external terminals protruding from the surface of the sealing resin. The semiconductor device further includes a plurality of second external terminals which are formed above the third area and which are electrically connected to the low-frequency circuit element, the second external terminals protruding from the surface of the sealing resin.Type: GrantFiled: September 28, 2006Date of Patent: June 9, 2009Assignee: Oki Semiconductor Co., Ltd.Inventors: Makoto Terui, Noritaka Anzai
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Patent number: 7535071Abstract: An apparatus and method of integrating optics into an IC package is for detecting light from at least one light source is disclosed. The apparatus has a housing, which has a predetermined spectral transmittance. A sensor is positioned within the housing. An opaque mask is applied to the housing, where the opaque mask has a hole aligned with the sensor such that the light's centroid is detected by the sensor. In one embodiment, the apparatus further comprises a substrate for positioning and stabilizing the sensor in the housing, an analog filter and amplification module (“AFA”) for filtering and amplifying signals from the sensor and generating a second signal, and a digital signal processor (“DSP”) for generating a coordinate system by extracting frequency components from the AFA output signal.Type: GrantFiled: March 25, 2005Date of Patent: May 19, 2009Assignee: Evolution Robotics, Inc.Inventors: Steve Schell, Robert Witman, Joe Brown
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Patent number: 7528473Abstract: An electronic circuit includes a first semiconductor device and a second semiconductor device on a mounting substrate. The mounting substrate lines have lengths which are made unequal for respective bits. Assembling lines which reach connecting electrodes of a semiconductor chip from the external terminals of the second semiconductor device have made lengths thereof unequal for respective bits. The unequal lengths of the mounting substrate lines have a relationship which offsets the unequal lengths of the assembling lines.Type: GrantFiled: March 19, 2004Date of Patent: May 5, 2009Assignee: Renesas Technology Corp.Inventors: Motoo Suwa, Yoshinori Miyaki, Toru Hayashi, Ryoichi Sano, Shigezumi Matsui, Takanobu Naruse, Takashi Sato, Hisashi Shiota
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Patent number: 7504670Abstract: A semiconductor device includes: a substrate; a semiconductor element mounted on the substrate; a sealing structure for sealing the semiconductor element, the sealing structure being mounted on the substrate; and an adhesive for bonding the sealing structure and the substrate, wherein the sealing structure has a groove for storing the adhesive.Type: GrantFiled: June 7, 2006Date of Patent: March 17, 2009Assignee: Shinko Electric Industries Co., Ltd.Inventors: Satoshi Shiraishi, Yoichi Kazama
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Publication number: 20090001497Abstract: A semiconductor integrated circuit device includes a substrate having a PROM formed thereon in which the data memory state of the PROM is changed by the irradiation of light, and a multilayer wiring structure formed on the same side of the substrate as the PROM is formed. The multilayer wiring structure includes a transparent area, a shield area, and a PAD portion. The transparent area is formed from transparent material at a position opposite to the PROM area where the PROM is formed, and used as a light guiding path from the outside of the multilayer wiring structure to the PROM. The shield area is formed continuously from shielding materials arranged in several layers in the periphery of the transparent area. The PAD portion is formed on the outside of the shield area in regard to the transparent area, and controls the memory state of the PROM.Type: ApplicationFiled: June 30, 2008Publication date: January 1, 2009Applicant: NEC ELECTRONICS CORPORATIONInventor: Hitoshi MITANI
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Patent number: 7468293Abstract: In a method for the production of window elements which can be soldered into a housing in a hermetically tight manner and of a window element sealing a housing, the object of the invention is to achieve an improved hermetic sealing between window and housing through increased adherence and homogeneity in the metal coating and to prevent penetration of scattered light and unwanted radiation. Optically transparent, flat substrate material whose size is sufficient for a plurality of window elements is provided on at least one surface with an optical coating from which frame-like portions on a coated surface which enclose optically active surfaces of the window elements are subsequently removed, whereupon a metal coating that is used for producing a solder connection to the housing is applied to the generated portions having no coating, and the window elements are separated from the substrate material.Type: GrantFiled: May 25, 2006Date of Patent: December 23, 2008Assignee: Jenoptik Laser, Optik, Systeme GmbHInventors: Thomas Weyh, Elvira Gittler, Wolfgang Brode
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Patent number: 7405470Abstract: A storage apparatus 10 is disclosed, that comprises a wiring substrate 11 having a first surface and a second surface, a flat type external connection terminal 12a disposed on the first surface of the wiring substrate 11, a semiconductor device 14 disposed on the second surface of the wiring substrate 11 and having a connection terminal 14a connected to the flat type external connection terminal 12a, a molding resin 15 for coating the semiconductor device 14 on the second surface of the wiring substrate 11, a card type supporting frame 10a having a concave portion or a hole portion fitting the wiring substrate 11, the semiconductor device 14, and the molding resin 15 in such a manner that the flat type external connection terminal 12a is exposed to the first surface of the wiring substrate 11, and adhesive resin a adhering integrally the flat type external connection terminal 12a, the wiring substrate 11, the semiconductor device 14, the molding resin 15, and the card type supporting frame 10a.Type: GrantFiled: March 29, 2005Date of Patent: July 29, 2008Assignee: Kabushiki Kaisha ToshibaInventor: Hiroshi Iwasaki
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Patent number: 7348241Abstract: Provided are a cell structure of an EPROM device and a method for fabricating the same. The cell structure includes a gate stack, which includes a first floating gate, an insulating pattern including a nitride layer, and a control gate that are sequentially stacked on a semiconductor substrate, and includes a window for exposing the top surface or both sidewalls of the first floating gate on both sides of the control gate, so that charges of the first floating gate can be erased by ultraviolet rays. The cell structure further includes a floating gate transistor, which includes a gate insulating layer formed on the semiconductor substrate, a second floating gate that is formed on the gate insulating layer and is connected to the first floating gate in the gate stack, and a source/drain that is formed in the semiconductor substrate so as to be aligned to the second floating gate. In the cell structure, the window is formed on the top surface or both sidewalls of the first floating gate of the gate stack.Type: GrantFiled: March 20, 2006Date of Patent: March 25, 2008Assignee: Samsung Electronics Co., Ltd.Inventors: Joon-hyung Lee, Byung-sun Kim, Tae-jung Lee
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Patent number: 7320738Abstract: Method for conditioning of an electronic microcircuit designed for the production of an electronic module which can be glued by means of a simple glue or by soldering. For this purpose the microchip has a geometric shape compatible with a recess in a card provided to accommodate it and has a means serving as a mask compatible with the card. Ultimately this mask also serves to prevent an outflow of a resin coating used to protect a chip included in this type of module. The mask is glued to a support having, on a first face, the contact area, and on a second face the mask and the chip. The mask includes a window determining the placement of the chip.Type: GrantFiled: April 16, 2003Date of Patent: January 22, 2008Assignee: FCIInventors: Jean-Pierre Radenne, Yannick De Maquille, Jean-Jacques Mischler, Christophe Mathieu
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Patent number: 7276413Abstract: An NROM flash memory cell is implemented in an ultra-thin silicon-on-insulator structure. In a planar device, the channel between the source/drain areas is normally fully depleted. An oxide layer provides an insulation layer between the source/drain areas and the gate insulator layer on top. A control gate is formed on top of the gate insulator layer. In a vertical device, an oxide pillar extends from the substrate with a source/drain area on either side of the pillar side. Epitaxial regrowth is used to form ultra-thin silicon body regions along the sidewalls of the oxide pillar. Second source/drain areas are formed on top of this structure. The gate insulator and control gate are formed on top.Type: GrantFiled: August 25, 2005Date of Patent: October 2, 2007Assignee: Micron Technology, Inc.Inventor: Leonard Forbes
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Patent number: 7274096Abstract: A light transmissive cover for a device comprising: a cover member of light transmissive material; and a junction member joined to the cover member, the junction member being a member used to be joined to the body of the device and having a light interrupting film on the inner surface thereof. A device provided with a light transmissive cover, the device being provided with a cover member of light transmissive material joined to the body of device via a junction member so as to cover at least a part of the device, and having a light interrupting film on the inner surface of the junction member is also disclosed. In addition, methods for manufacturing them disclosed.Type: GrantFiled: October 21, 2004Date of Patent: September 25, 2007Assignee: Shinko Electric Industries, Co., Ltd.Inventor: Akinori Shiraishi
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Patent number: 7262455Abstract: A nonvolatile semiconductor memory package includes a memory device having a memory cell array including a plurality of nonvolatile semiconductor memory cells, a control portion configured to control the memory device, a network interface connectable to a network, a file management portion connected to the network interface configured to manage a relationship between a data file given from the network and an address of the memory cell array, and a memory interface connected to the file management portion configured to convert a signal given from the network to a signal that is capable of being used at the control portion. The package is wrapped by an insulating material.Type: GrantFiled: April 14, 2004Date of Patent: August 28, 2007Assignee: Kabushiki Kaisha ToshibaInventors: Tomoharu Tanaka, Hiroshi Sukegawa
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Patent number: 7205643Abstract: A stray field shielding structure for die attaching onto a magnetic random access memory chip or to other chips to prevent loss of memory due to magnetic fields or radiation is made by a method which provides a thick layer of magnetic material which is precise in its dimensions and adapted for placement on individual die by existing pick and place machines and die attach bonders. The magnetic shielding material is cut to a desired size by etching to remove all burrs and debris and is then attached only to good die using a die attach film of thermoset plastic or a gob of epoxy adhesive.Type: GrantFiled: March 8, 2005Date of Patent: April 17, 2007Inventor: David Walter Smith
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Patent number: 7157794Abstract: A semiconductor device includes a semiconductor substrate having a main surface, the main surface including a first area formed with a high-frequency circuit element and a second area located around the first area and formed with a low-frequency circuit element. The semiconductor device also includes a sealing resin which covers the main surface; a plurality of first external terminals which are formed above the second area and which are electrically connected to the high-frequency circuit element, the first external terminals protruding from the surface of the sealing resin. The semiconductor device further includes a plurality of second external terminals which are formed above the second area and which are electrically connected to the low-frequency circuit element, the second external terminals protruding from the surface of the sealing resin.Type: GrantFiled: November 7, 2002Date of Patent: January 2, 2007Assignee: Oki Electric Industry Co., Ltd.Inventor: Hiroyuki Mori
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Patent number: 7157742Abstract: An integrally packaged optronic integrated circuit device (310) including an integrated circuit die (322) containing at least one of a radiation emitter and radiation receiver and having top and bottom surfaces formed of electrically insulative and mechanically protective material, at least one of the surfaces (317) being transparent to radiation, and electrically insulative edge surfaces (314) having pads.Type: GrantFiled: March 11, 2003Date of Patent: January 2, 2007Assignee: Tessera Technologies Hungary Kft.Inventor: Avner Badehi
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Patent number: 7154053Abstract: An optoelectronic package with a wire-protection lid is provided. An active surface of a silicon die includes a light working area. The silicon die is disposed on a substrate and electrically connected to the substrate through a plurality of bonding wires. A glass is disposed on the active surface of the silicon die. A silicon base lid with an opening is located above the substrate and connected to the glass by anodic bonding to mask the bonding wires. In addition, the opening of the silicon base lid is aligned with the light working area of the silicon die.Type: GrantFiled: February 22, 2006Date of Patent: December 26, 2006Assignee: Advanced Semiconductor Engineering Inc.Inventor: Chain-Hau Hsu
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Patent number: 7049690Abstract: An information card includes a ground plate that is connected to a ground conductor portion of a printed substrate and is integral with an external panel. Plural contacts are provided with the ground plate, and are exposed at the upper side out of windows provided in the external panel. Lead terminals are extended from the ground plate and are integral therewith, and the tips of the lead terminals are soldered to the ground conductor portion of the printed substrate.Type: GrantFiled: March 9, 2001Date of Patent: May 23, 2006Assignee: Murata Manufacturing Co., Ltd.Inventor: Wataru Kakinoki
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Patent number: 7015579Abstract: A semiconductor device is disclosed that performs fingerprint recognition on the electrostatic-capacity principle. A finger sweeping across a fingerprint recognition area of a semiconductor chip provides positive fingerprint recognition operations with improved reliability. The semiconductor device includes the semiconductor chip having a sensor unit that performs fingerprint recognition, and a substrate having an opening formed in the position corresponding to the sensor unit. The semiconductor chip is flip chip bonded to the substrate such that the sensor unit corresponds to the opening, and except for the formed position of the opening, an under-fill material is provided between the semiconductor chip and the substrate.Type: GrantFiled: January 29, 2004Date of Patent: March 21, 2006Assignee: Fujitsu LimitedInventors: Akira Okada, Mitsuru Sato
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Patent number: 6995462Abstract: Packaging assemblies for optically interactive devices and methods of forming the packaging assemblies in an efficient manner that eliminates or reduces the occurrence of process contaminants. In a first embodiment, a transparent cover is attached to a wafer of semiconductor material containing a plurality of optically interactive devices. The wafer is singulated, and the optically interactive devices are mounted on an interposer and electrically connected with wire bonds. In a second embodiment, the optically interactive devices are electrically connected to the interposer with backside conductive elements. In a third embodiment, the optically interactive devices are mounted to the interposer prior to attaching a transparent cover. A layer of encapsulant material is formed over the interposer, and the interposer and encapsulant material are cut to provide individual packaging assemblies. In a fourth embodiment, the optically interactive devices are mounted in a preformed leadless chip carrier.Type: GrantFiled: September 17, 2003Date of Patent: February 7, 2006Assignee: Micron Technology, Inc.Inventors: Todd O. Bolken, Chad A. Cobbley
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Patent number: 6919628Abstract: A stack chip package structure is provided. One principal feature of the structure is the formation of a few peripheral surfaces (e.g. ladder or lead-angle surfaces) at the bottom peripheral sections of a stack structure. When the stack structure is attached to a surface of a die through an adhesive layer, the thickness of the adhesive layer under a peripheral section of the stack structure is greater than a central region. Therefore, as the chip package is subjected to a thermal stress test, the adhesive layer under the peripheral sections of the stack structure is able to provide some buffering against thermal stress so that the stress concentration around the stack structure is reduced. Consequently, damages of the die surface due to stress are prevented and the average working life of the chip package is extended.Type: GrantFiled: July 18, 2003Date of Patent: July 19, 2005Assignee: Via Technologies, Inc.Inventors: I-Tseng Lee, Hsueh Kuo Liao, Jen-Te Tseng
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Publication number: 20040164425Abstract: In a wafer, a plurality of basic chips F is arranged therein. The basic chip F has a memory capacity of i-mega bytes. By dicing, a memory chip including four basic chips F is cut out of the wafer. The memory chip has a memory capacity of 4×i-mega bytes. A dicing line is interposed between four basic chips F configuring the memory chip, Four basic chips F can change word organization by a control signal individually.Type: ApplicationFiled: February 27, 2004Publication date: August 26, 2004Inventor: Yukihiro Urakawa
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Patent number: 6740603Abstract: A method for fabricating a non-FLASH integrated circuit that minimizes Vmin shift. A protective overcoat (134) is deposited to protect and encapsulate the top metal interconnect layer (118). The protective overcoat (134) is patterned and etched to form bondpad windows either before or after depositing the final metal interconnect layer (136). A sinter that is normally performed after forming the bondpad windows is either omitted or the temperature of the sinter is kept at or below 350° C.Type: GrantFiled: February 1, 2002Date of Patent: May 25, 2004Assignee: Texas Instruments IncorporatedInventors: Steven P. Zuhoski, Mercer L. Brugler, Cameron Gross, Edward L. Mickler
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Patent number: 6690057Abstract: An EPROM structure for a nonvolatile semiconductor memory includes a plurality of memory cells that each include a floating gate transistor (6) that can be programmed by hot electrons and erased by UV light. An additional, common gate capacitance (7) is associated with each memory cell to raise the potential at the floating gate transistor (6) to the level required for writing by applying to the gate capacitances a predetermined voltage, common to all the memory cells.Type: GrantFiled: September 30, 2000Date of Patent: February 10, 2004Assignee: Micronas GmbHInventor: Heinz-Peter Frerichs
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Patent number: 6646289Abstract: An integrally packaged optronic integrated circuit device (310) including an integrated circuit die (322) containing at least one of a radiation emitter and radiation receiver and having top and bottom surfaces formed of electrically insulative and mechanically protective material, at least one of the surfaces (317) being transparent to radiation, and electrically insulative edge surfaces (314) having pads.Type: GrantFiled: September 22, 2000Date of Patent: November 11, 2003Assignee: Shellcase Ltd.Inventor: Avner Badehi
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Patent number: 6576991Abstract: An integrated circuit device is disclosed. The device includes an active film having a semiconducting material and an integrated circuit disposed on an active face of the active film. The integrated circuit includes a plurality of circuit elements. In addition, the device includes an additional film fixed to the active face of the active film, the additional film at least partially covering said integrated circuit, and an anti-fraud mechanism disposed within the additional film, the anti-fraud mechanism being positioned to align with one of the plurality of circuit elements. In some aspects, the additional film includes a protective sub-film and a sealing sub-film, wherein the protective sub-film is sealed to the active face of the active film by the sealing sub-film.Type: GrantFiled: January 28, 2002Date of Patent: June 10, 2003Assignee: Schlumberger SystemsInventors: Béatrice Bonvalot, Robert Leydier
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Publication number: 20030038350Abstract: A semiconductor device, which may be changed to a mirror package after the assembly without having to reinstall bonding wires, comprises: a plurality of fixed external terminals which include a power supply external terminal and a ground potential external terminal and which are arranged symmetrically in fixed positions; a plurality of variable external terminals of different types which are arranged symmetrically; a plurality of reverse-polarity selection external terminals which are symmetrically arranged in fixed positions, and a signal switching circuit which switches the arrangement of the symmetrically arranged variable external terminal according to the setting of the selection terminal.Type: ApplicationFiled: August 12, 2002Publication date: February 27, 2003Applicant: ELPIDA MEMORY, INC.Inventor: Yukitoshi Hirose
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Publication number: 20030030135Abstract: A replacement information storage unit stores additional replacement information determined according to testing carried out during or after assembly. A replacement information addition load unit receives additional replacement information from outside a plurality of memory chips. A replacement data retain unit stores address information corresponding to a defective memory cell found during a fabrication process of a memory chip, and can alter the output address signal according to externally applied additional replacement information.Type: ApplicationFiled: April 23, 2002Publication date: February 13, 2003Applicant: Mitsubishi Denki Kabushiki KaishaInventors: Ryuji Ohmura, Kazushi Sugiura
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Patent number: 6483030Abstract: An image sensor package includes a molding having a locking feature. The package further includes a snap lid having a tab, where the tab is attached to the locking feature of the molding. To form the image sensor package, a window is placed in a pocket of the molding. The snap lid is secured in place. Once secured, the snap lid presses against a peripheral region of an exterior surface of the window. The window is sandwiched between the molding and the snap lid and held in place.Type: GrantFiled: December 8, 1999Date of Patent: November 19, 2002Assignee: Amkor Technology, Inc.Inventors: Thomas P. Glenn, Steven Webster
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Patent number: 6441499Abstract: A method for making a flip chip ball grid array (BGA) package includes the step of thinning a die for matching a composite coefficient of thermal expansion to that of a second level board.Type: GrantFiled: August 30, 2000Date of Patent: August 27, 2002Assignee: LSI Logic CorporationInventors: Kumar Nagarajan, Sarathy Rajagopalan
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Publication number: 20010033014Abstract: A direct attachment technique is described for silicon packages housing high frequency devices. A silicon package may be shaped as either a plug or a socket or the package may have both the plug and socket capability, thus enabling the package to be directly attached to other packages The plug is trapezoidal in cross section while the socket has a dovetail-joint-like aperture. The plug is inserted into the socket thereby directly attaching one package to another. The two packages are locked together when the slanted edges of the plug are fitted to the slanted edges of the socket.Type: ApplicationFiled: January 3, 2001Publication date: October 25, 2001Inventor: Philip Joseph Koh