Abstract: A method of manufacturing includes arranging an integral resin sleeve formed by integrating a plurality of sleeve parts so that the sleeve parts are respectively fitted with a plurality of electrode terminals. There is a press-fitting of the sleeve parts to the electrode terminals by performing mold clamping on molds to apply a force downward on the integral resin sleeve. Further, there is a filling of a molding resin into a hollow cavity of the molds.

Abstract: Provided is a power semiconductor device including: an insulating substrate; a circuit pattern formed on an upper surface of the insulating substrate; a power semiconductor formed on the circuit pattern; a plurality of metal socket electrode terminals formed perpendicularly to the circuit pattern or the power semiconductor so as to be in conduction with external terminals; an integral resin sleeve in which a plurality of sleeve parts are integrated, the plurality of sleeve parts being fitted with the plurality of metal socket electrode terminals from above the plurality of metal socket electrode terminals and having openings at both ends thereof; and a molding resin covering the insulating substrate, the circuit pattern, the power semiconductor, the electrode terminals, and the integral resin sleeve.

Abstract: The objective of the invention is to provide a method of manufacturing a semiconductor device that allows individual molding of plural semiconductor chips carried on a surface of the substrate. It includes the following process steps: a process step in which plural semiconductor elements 102 are arranged on the surface of substrate 100; a process step in which the inner side of substrate 102 is fixed on lower die 130; a process step in which liquid resin 114 is supplied from nozzle 112 onto each of the semiconductor elements in order to cover at least a portion of each of semiconductor chips 102; a process step in which the upper die having plural cavities 144 formed in one surface is pressed onto the lower die, and liquid resin 114 is molded at a prescribed temperature by means of plural cavities 144; and a process step in which cavities 144 of upper die 140 are detached from the substrate, and plural molding resin portions are formed individually.

Abstract: An embedded electronic component semiconductor package structure and a packaging process thereof are provided. By providing two or more preformed building blocks, the electronic component can be assembled to the joined building blocks to obtain the embedded component semiconductor package structure.

Abstract: A semiconductor package may include a substrate, a semiconductor chip disposed on the substrate, a communication terminal and a static electricity inducing terminal connected to a ground. The package may include a first sealant that comprises a voltage sensitive material and that covers the semiconductor chip and a static electricity blocking layer that provides a conductive pathway from the first sealant to only the static electric inducing terminal. The static electricity blocking layer may prevent the communication terminal from being electrically connected to the first sealant. If a buildup of charge is applied to the device, the first sealant may become polarized and/or conductive. The extra voltage may travel through the first sealant to the static electricity inducing terminal via an opening in the static electricity blocking layer. The semiconductor chip and the communication terminal may not be affected by the extra charge.

Abstract: A microelectronic package includes a lower unit having a lower unit substrate with conductive features and a top and bottom surface. The lower unit includes one or more lower unit chips overly/ing the top surface of the lower unit substrate that are electrically connected to the conductive features of the lower unit substrate. The microelectronic package also includes an upper unit including an upper unit substrate having conductive features, top and bottom surfaces and a hole extending between such top and bottom surfaces. The upper unit further includes one or more upper unit chips overlying the top surface of the upper unit substrate and electrically connected to the conductive features of the upper unit substrate by connections extending within the hole. The upper unit may include an upper unit encapsulant that covers the connections of the upper unit and the one or more upper unit chips.

Abstract: A method of making an electronic circuit device includes expelling air from a gap between a circuit board and an electronic element mounted on only a first side of the circuit board by filling the gap with a filling member, placing the circuit board in a mold cavity such that a second side of the circuit board is held in close contact with an inner surface of the cavity. The method further includes encapsulating the circuit board with a resin material by injecting the resin material into the cavity.

Abstract: A tamper-resistant microchip package contains fluid- or nanofluid-filled capsules, channels, or reservoirs, wherein the fluids, either alone or in combination, can destroy circuitry by etching, sintering, or thermally destructing when reverse engineering of the device is attempted. The fluids are released when the fluid-filled cavities are cut away for detailed inspection of the microchip. Nanofluids may be used for the sintering process, and also to increase the thermal conductivity of the fluid for die thermal management. Through-vias and micro vias may be incorporated into the design to increase circuitry destruction efficacy by improving fluid/chip contact. Thermal interface materials may also be utilized to facilitate chip cooling.

Abstract: A system for hermetically sealing devices includes a substrate, which includes a plurality of individual chips. Each of the chips includes a plurality of devices and each of the chips are arranged in a spatial manner as a first array. The system also includes a transparent member of a predetermined thickness, which includes a plurality of recessed regions arranged in a spatial manner as a second array and each of the recessed regions are bordered by a standoff region. The substrate and the transparent member are aligned in a manner to couple each of the plurality of recessed regions to a respective one of said plurality of chips. Each of the chips within one of the respective recessed regions is hermetically sealed by contacting the standoff region of the transparent member to the plurality of first street regions and second street regions using at least a bonding process to isolate each of the chips within one of the recessed regions.

Abstract: A semiconductor die has first and second discrete semiconductor components mounted over a plurality of wettable contact pads formed on a carrier. Conductive pillars are formed over the wettable contact pads. A semiconductor die is mounted to the conductive pillars over the first discrete components. The conductive pillars provide vertical stand-off of the semiconductor die as headroom for the first discrete components. The second discrete components are disposed outside a footprint of the semiconductor die. Conductive TSV can be formed through the semiconductor die. An encapsulant is deposited over the semiconductor die and first and second discrete components. The wettable contact pads reduce die and discrete component shifting during encapsulation. A portion of a back surface of the semiconductor die is removed to reduce package thickness. An interconnect structure is formed over the encapsulant and semiconductor die. Third discrete semiconductor components can be mounted over the semiconductor die.

Abstract: The present invention directs to fabrication methods of the embedded component package structures by providing preformed lamination structures, joining or stacking the preformed laminate structures and mounting at least one electronic component to the joined structures. By way of the fabrication methods, the production yield can be greatly improved with lower cycle time.

Abstract: A manufacturing method of a single chip semiconductor coating structure includes following steps. Step 1 is providing a single chip semiconductor which has a plurality of surfaces, and two opposite surfaces selected from the plurality of surfaces are manufacturing surfaces and have a conductive area with a pad thereon, respectively. Step 2 is providing a tool to cover one of the conductive areas with the pad. Step 3 is providing a coating step to form an insulating layer on the single chip semiconductor. Step 4 is providing a removing step to remove the insulating layer for exposing the covered conductive area and the pad. Step 5 is forming two electrodes and each of the two electrodes covers the conductive area with the pad.

Abstract: An underfill technique for LEDs uses compression molding to simultaneously encapsulate an array of flip-chip LED dies mounted on a submount wafer. The molding process causes liquid underfill material (or a softened underfill material) to fill the gap between the LED dies and the submount wafer. The underfill material is then hardened, such as by curing. The cured underfill material over the top and sides of the LED dies is removed using microbead blasting. The exposed growth substrate is then removed from all the LED dies by laser lift-off, and the underfill supports the brittle epitaxial layers of each LED die during the lift-off process. The submount wafer is then singulated. This wafer-level processing of many LEDs simultaneously greatly reduces fabrication time, and a wide variety of materials may be used for the underfill since a wide range of viscosities is tolerable.

Abstract: An integrated circuit package system comprising: fabricating a package base including: forming a lead frame, coupling a first integrated circuit device under the lead frame, coupling a second integrated circuit device over the first integrated circuit device, and molding an enclosure on the lead frame, the first integrated circuit device, and the second integrated circuit device for forming an integration port; and coupling a third integrated circuit device on the integration port.

Abstract: A power semiconductor element and a capacitor have their electrodes joined to each other in a module. The power semiconductor element is formed on a semiconductor substrate having first and second main surfaces. A power semiconductor module includes an electrode through which a main current flows, joined to the first main surface, an electrode through which the main current flows, joined to the second main surface, and a resin portion sealing the semiconductor substrate, the capacitor and the electrodes. The capacitor includes electrodes. The electrode of the capacitor and the electrode of the semiconductor element are joined to each other by solder such that surfaces exposed through the resin portion are arranged on one continuous surface on which a cooler can be attached. Therefore, a power semiconductor module can be provided in which the capacitor and the power semiconductor element can effectively be cooled and the surge voltage can be reduced.

Abstract: A semiconductor device includes a multi-layer substrate. A ground shield is disposed between layers of the substrate and electrically connected to a ground point. A plurality of semiconductor die is mounted to the substrate over the ground shield. The ground shield extends beyond a footprint of the plurality of semiconductor die. An encapsulant is formed over the plurality of semiconductor die and substrate. Dicing channels are formed in the encapsulant, between the plurality of semiconductor die, and over the ground shield. A plurality of metal-filled holes is formed along the dicing channels, and extends into the substrate and through the ground shield. A top shield is formed over the plurality of semiconductor die and electrically and mechanically connects to the ground shield through the metal-filled holes. The top and ground shields are configured to block electromagnetic interference generated with respect to an integrated passive device disposed in the semiconductor die.

Abstract: A blank and a semiconductor device are include a composite panel with semiconductor chips embedded in a plastic package molding compound. The blank includes a composite panel with semiconductor chips arranged in rows and columns in a plastic package molding compound with active upper sides of the semiconductor chips forming a coplanar surface area with the upper side of the composite panel. The blank further includes an orientation indicator impressed into the plastic package molding compound when the semiconductor chips are embedded within the molding compound.

Abstract: Some embodiments include a device having a number of memory cells and associated circuitry for accessing the memory cells. The memory cells of the device may be formed in one or more memory cell dice. The associated circuitry of the device may also be formed in one or more dice, optionally separated from the memory cell dice.

Abstract: A panel with a reconfigured wafer including semiconductor chips arranged in rows and columns on semiconductor device positions includes: at least one semiconductor chip having a front, a rear and edge sides provided per semiconductor device position. The reconfigured wafer includes: a front side that forms a coplanar area with the front sides of the at least one semiconductor chip and a plastic housing composition embedding the edge sides and the rear side of the at least one semiconductor chip. The reconfigured wafer includes, on a rear side of the wafer, structures configured to stabilize the panel. The structures are composed of the plastic housing composition and are formed as thickenings of the reconfigured wafer.

Abstract: A thermal interface device (100) includes a base member (102) and a pocket (104) which is filled with a thermally conductive material or medium such as diamond dust suspended in a solvent such as propylene glycol or a thermally conductive material such as thermally conductive rubber. The pocket (104) is hermitically sealed to the base member (102) in order to keep the thermally conductive material within the pocket. The filled pocket (104) forms a deformable “pillow” having a high thermal conductance. The deformable pocket (104) can contour to the shape of a device it is pressed against such as an electronic device undergoing testing.

Abstract: This is a PCBA that can be used in any system where one component or package is connected to another component or package. This invention provides a very short connector or signal path that avoids the necessity of a signal trace termination in the PCB. The PCB has on its upper surface a first component or package and on its lower surface a second component or package in vertical physical and signal alignment with the first component or package. The first component or package has a BGA on its bottom surface and the second component has a BGA on its top surface, both of these BGAs are in electrical contact with each other. Because of the short signal trace provided, the PCB provides signal transitions as fast as 200 pS.

Abstract: A backgrinding machine 10 of a semiconductor wafer W includes: a table 13 set on the working plane of a mount 11; a multiple number of holding jigs 20 arranged via check tables 15 on table 13; a grinding machine 30 for performing a grinding process of the rear side of semiconductor wafer W held by holding jig 20; and a washing device 40 for ground semiconductor wafers W. Each holding jig 20 is constructed of a concave 22 depressed on the surface of a base plate 21, a multiple number of supporting projections 23 projectively arrayed on the bottom surface of concave 22, a deformable contact film 24, covering the concave 22, being supported by the multiple supporting projections 23, for detachably holding semiconductor wafer W in close contact with it; and an exhaust path 25 for conducting air from the concave 22 covered by contact film 24 to the outside.

Abstract: A power semiconductor module having a substrate, a housing and a pressure device. The substrate further includes a body formed of an insulating material and structured conductor tracks which are arranged thereon and have load and auxiliary potentials. The substrate also includes recesses in the region of the structured conductor tracks in at least two areas that are not covered by a power semiconductor component. Furthermore, the pressure device has latching lugs, which are disposed in the recesses and are arranged therein in a form-fitting and/or frictional manner, at least two points on the side of the pressure device which faces the substrate.

Abstract: Proposed is a package structure having a micro-electromechanical (MEMS) element, including a chip having a plurality of electrical connecting pads and a MEMS element formed thereon; a lid disposed on the chip for covering the MEMS element; a stud bump disposed on each of the electrical connecting pads; an encapsulant formed on the chip with part of the stud bumps being exposed from the encapsulant; and a metal conductive layer formed on the encapsulant and connected to the stud bumps. The invention is characterized by completing the packaging process on the wafer directly to enable thinner and cheaper package structures to be fabricated within less time. This invention further provides a method for fabricating the package structure as described above.

Abstract: An integrated heat spreader (IHS) lid over a semiconductor die connected to a substrate forms a cavity. A bead of foaming material may be placed within the IHS cavity. During an IHS cure and reflow process the foaming material will expand and fill the IHS cavity and the foam's shape conforms to the various surface features present, encapsulating a thermal interface material (TIM) material, and increasing contact area of the foam sealant.

Abstract: A stacked-chip packaging structure includes chip sets, a heat sink, a substrate, a circuit board, and solder balls. The chip sets are stacked together, each of which has a heat-dissipation structure and a chip. The heat-dissipation structure has a chip recess, through holes arranged in the chip recess, and an extending portion extending from the chip recess. The chip disposed in the chip recess has bumps. Each bump on the chip is correspondingly disposed in one of the through holes of the heat-dissipation structure. The extending portion of the heat-dissipation structure of each chip set contacts that of the neighboring chip set. The heat sink and the substrate are disposed at two opposite sides of the chip sets, respectively. The circuit board is below the substrate. The solder balls are between the circuit board and the substrate.

Abstract: In one embodiment of the present invention, an IC chip mounting package is arranged such that an IC chip and a film base member are connected via an interposer, and a section in which the IC chip, the film base member, and the interposer are connected is sealed with sealing resin. The sealing resin is provided by potting sealing resin around the interposer via a potting nozzle, or is provided by potting the sealing resin around the IC chip, that is, via a device hole. Moreover, the sealing resin has a coefficient of linear expansion of not more than 80 ppm/° C., a viscosity of not less than 0.05 Pa·s but not more than 0.25 Pa·s, and also includes filler having a particle size of not more than 1 ?m.

Abstract: A semiconductor package assembly has a first semiconductor package. A plurality of first solder balls is attached to the first semiconductor package. A circuit board is provided having a plurality of mounting pads that is electrically connected to the plurality of first solder balls. A first underfill is disposed on each of the plurality of first solder balls. The first underfill is disposed on interfaces between each of the plurality of first solder balls and the first semiconductor package and each of the plurality of first solder balls and the circuit board. The first underfill is removed from an area between adjacent first solder balls.

Abstract: A fixture assembly and method of forming a chip assembly is provided. The fixture assembly includes a first plate having an opening sized to accommodate a chip mounted on a laminate. The fixture assembly further includes a second plate mated to the first plate by at least one mechanical fastening mechanism. The fixture assembly further includes a space defined by facing surfaces of the first plate and the second plate and confined by a raised stepped portion of at least one of the first plate and the second plate. The space is coincident with the opening. The space is sized and shaped such that the laminate is confined within the space and directly abuts the stepped portion and the facing surfaces of the first plate and the second plate to be confined in X, Y and Z directions.

Abstract: Methods and apparatus for improved thermal performance and electromagnetic interference (EMI) shielding in integrated circuit (IC) packages are described. A die-up or die-down package includes an IC die, a die attach pad, a heat spreader cap coupled to the die attach pad defining a cavity, and one or more peripheral rows of leads surrounding the die attach pad. The leads do not protrude substantially from the footprint of the encasing structure. The die attach pad and the heat spreader cap defines an encasing structure that substantially encloses the IC die, and shields EMI emanating from and radiating towards the IC die. The encasing structure also dissipates heat generated by the IC die during operation.

Abstract: A light-emitting diode (LED) package structure including a carrier substrate, at least one LED chip, an optical element and a highly thermal-conductive transparent liquid is provided. The LED chip is disposed on the carrier substrate and has an active layer. The optical element is disposed on the substrate and forms a sealed space with the carrier substrate, and the LED chip is disposed in the sealed space. The highly thermal-conductive transparent liquid fills up the sealed space.

Abstract: This application relates to a method of manufacturing a semiconductor device comprising: providing multiple chips each comprising contact elements on a first main face of each of the multiple chips, and a first layer applied to each of the first main faces of the multiple chips; placing the multiple chips over a carrier with the first layers facing the carrier; applying encapsulation material to the multiple chips and the carrier to form an encapsulation workpiece embedding the multiple chips; and removing the carrier from the encapsulation workpiece.

Abstract: This invention discloses an electronic package for containing a vertical semiconductor chip that includes a laminated board having a via connector and conductive traces distributed on multiple layers of the laminated board connected to the via connector. The semiconductor chip having at least one electrode connected to the conductive traces for electrically connected to the conductive traces at a different layer on the laminated board and the via connector dissipating heat generated from the vertical semiconductor. A ball grid array (BGA) connected to the via connector functioning as contact at a bottom surface of the package for mounting on electrical terminals disposed on a printed circuit board (PCB) wherein the laminated board having a thermal expansion coefficient in substantially a same range the PCB whereby the BGA having a reliable electrical contact with the electrical terminals.

Abstract: An electronic circuit device that suppresses deformation of an adhesive layer of a flexible printed circuit board during formation of a resin seal portion, and suppresses deterioration of the circuit board caused by deformation of the adhesive layer. The electronic circuit device includes a substrate mounted with an electronic component; a flexible printed circuit board electrically connectable to the substrate and an external device, and includes a wiring conductor and a pair of insulation films covering upper and lower surfaces of the wiring conductor; and a resin molding portion to seal the substrate and a portion of the circuit board. The wiring conductor of the circuit board is adhered through an adhesive layer to at least one of the pair of insulation films, and a dummy wiring material that does not function as wiring is disposed on an outer side of a border between the circuit board and an outer peripheral portion of the plastic molding portion, and disposed between the pair of insulation films.

Abstract: A semiconductor component has a substrate and a projecting electrode on the substrate. The projecting electrode is configured suitably for electrically and mechanically connecting the semiconductor component to an external substrate. Furthermore, the projecting electrode is formed by a one-dimensional or two-dimensional array of projecting sub-electrodes, which are separated from each other by an electrically insulating fluid beginning from a substrate surface. The semiconductor component has an improved projecting-electrode. It provides the projecting electrode with a sub-structure, which achieves sufficient flexibility without introducing much constructive complexity and processing complexity during fabrication.

Abstract: A disclosed semiconductor device includes a reinforcing board having first and second faces, an electronic part accommodating portion penetrating the reinforcing board, a through hole, an electronic part having a front face on which an electrode pad is formed and a back face, a through electrode installed inside the through hole, a first sealing resin filling a gap between the through electrode and an inner wall of the through hole, a second sealing resin filled into the electronic part accommodating portion while causing the bonding face of the electrode pad of the electronic part accommodating portion to be exposed to an outside, and a multi-layered wiring structure configured to include insulating layers laminated on the first face of the reinforcing board and an interconnection pattern, wherein the interconnection pattern is directly connected to the electrode pad of the electronic part and the through electrode.

Abstract: Provided is an electronic device of high reliability having an exposed functional portion. An electronic device 10 comprises an electronic element 11 having an exposed functional portion 11a on a first surface, a frame member 12 having a first penetration hole 12a, and a board 13 having a second penetration hole 13a. The frame member 12 is provided on the first surface of the electronic element 11 such that the first penetration hole 12a faces at least a part of the functional portion 11a. The electronic element 11 is mounted on the board 13 such that at least a part of the functional portion 11a faces the second penetration hole 13a. The frame member 12 does not contact with the board 13.

Abstract: Methods and apparatuses for improved thermal, electrical and/or mechanical performance in integrated circuit (IC) packages are described. An IC circuit package comprises a substrate having a central opening. An IC die, resides within the opening in the substrate. Wirebonds couples a plurality of bond pads on a top surface of the IC die to a plurality of bond fingers on a top surface the substrate. An encapsulating material encapsulates at least the IC die and the wirebonds such that at least a bottom surface of the IC die is left exposed. The encapsulating material suspends the die such that at least a portion of the die is held within the opening in the substrate.

Abstract: A computer or microchip comprising an outer chamber and at least one inner chamber inside the outer chamber. The outer chamber and the inner chamber being separated at least in part by an internal sipe, and at least a portion of a surface of the outer chamber forming at least a portion of a surface of the internal sipe. The internal sipe has opposing surfaces that are separate from each other and therefore can move relative to each other, and at least a portion of the opposing surfaces are in contact with each other in a unloaded condition. The outer chamber including a Faraday Cage. A computer, comprising a semiconductor wafer having a multitude of microchips. The multitude of microchips forming a plurality of independently functioning computers, each computer having independent communication capabilities.

Abstract: The present invention includes a base, a rectification chip, a conductive element and a coupling collar. The base has an installation pedestal to hold the rectification chip. The conductive element has a root portion to hold the rectification chip. The coupling collar is located at one end of the base to hold a package. The coupling collar has a plurality of anchor portions in contact with the package. Each anchor portion has a convex portion and a concave portion extended to two ends of the coupling collar. The convex portion and concave portion of two neighboring anchor portions are formed in a staggered manner. The cross section area of the convex portion on the annular edge of the coupling collar is different from the cross section area of the inner wall of the coupling collar. Hence fabrication and assembly are easier. Turning and loosening of the package can be prevented.

Abstract: Embodiments of the invention relate to a method for creating a flexible circuit, including defining a cavity in a top surface of a substrate before disposing a semiconductor chip within the cavity, such that a backside of the chip is disposed beneath the top surface of the substrate and above a bottom surface of the cavity. The method also includes forming a flexible connecting layer on the top surface of the substrate and extending over the chip. Other embodiments relate to a flexible circuit including a substrate defining a cavity in a top surface thereof. The cavity has encapsulant and a chip disposed therein, wherein a frontside of the chip is substantially coplanar with the top surface of the substrate. A flexible connecting layer is disposed on the top surface of the substrate and is partially supported by the substrate.

Abstract: Partitioning electronic sensor packages is provided. The electronic sensor package includes an electronic component, a sensor device, and electrical connections between the electronic component and the sensor device. A dam is written in the electronic sensor package to partition the package into two or more sections, where the sensor device is situated at least partially in one section and the electronic component is situated at least partially in another section. The partitioning of the dam allows the two sections to be filled with different fill materials. For example, the section with the sensor device can be filled with a soft gel-like material to provide some moisture protection to the sensor device without causing detrimental stresses to the sensor device, while the section with the electronic component can be filled with a highly moisture protective epoxy.

Abstract: A package structure of flexible display device includes a flexible opto-electronic display panel, a first barrier layer and a second barrier layer. The flexible opto-electronic display panel includes a backplane, a flexible frontplane, and a display media layer. The display media layer is disposed between the flexible frontplane and the backplane, where the display media layer is substantially corresponding to a display region of the backplane, and at least one side of the display media layer aligns with one corresponding side of the backplane. The first barrier layer is disposed on a first surface of the flexible frontplane, where the flexible frontplane, the display media layer and the first barrier layer expose a bonding region of the backplane. The second barrier layer is disposed on a second surface of the backplane.

Abstract: An object is to provide a thin and small semiconductor device that has high reliability and high resistance to external stress and electrostatic discharge. Another object is to manufacture a semiconductor device with high yield while shape defects and defective characteristics which are caused by external stress or electrostatic discharge are prevented in the manufacturing process. A conductive shield covering a semiconductor integrated circuit prevents electrostatic breakdown (malfunction of the circuit or damage to a semiconductor element) of the semiconductor integrated circuit due to electrostatic discharge. By providing an antenna on the external side of the conductive shield, a sufficient communication capability is secured. With the use of a pair of insulators which sandwich the semiconductor integrated circuit, a thin and small semiconductor device that has resistance properties and high reliability can be provided.

Abstract: An interconnect structure of an integrated circuit and a method for forming the same are provided. The interconnect structure includes a semiconductor substrate, a low-k dielectric layer over the semiconductor substrate, a conductor in the low-k dielectric layer, and a cap layer on the conductor. The cap layer has at least a top portion comprising a metal silicide/germanide.

Abstract: A tamper-resistant microchip package contains fluid- or nanofluid-filled capsules, channels, or reservoirs, wherein the fluids, either alone or in combination, can destroy circuitry by etching, sintering, or thermally destructing when reverse engineering of the device is attempted. The fluids are released when the fluid-filled cavities are cut away for detailed inspection of the microchip. Nanofluids may be used for the sintering process, and also to increase the thermal conductivity of the fluid for die thermal management. Through-vias and micro vias may be incorporated into the design to increase circuitry destruction efficacy by improving fluid/chip contact. Thermal interface materials may also be utilized to facilitate chip cooling.

Abstract: A circuit carrier having a metal support layer, at least some portions of which are covered by a dielectric layer, the dielectric layer having a plurality of pores, with the pores being sealed by glass at least on the opposite side of the dielectric layer to the support layer.

Abstract: The present invention provides a light emitting diode package including: a package mold having a first cavity and a second cavity with a smaller size than that of the first cavity; first and second electrode pads provided on the bottom surfaces of the first cavity and the second cavity, respectively; an LED chip mounted on the first electrode pad; a wire for providing electrical connection between the LED chip and the second electrode pad; and a molding material filled within the first cavity and the second cavity.

Abstract: Disclosed are a semiconductor package and a method of making the same. In the semiconductor package, a substrate and a semiconductor die are covered with and encapsulated by vertically pressing thermosetting resin having fluidity in a predetermined temperature range and denaturalizing itself in gel. Thus, it is possible to reduce a thickness of the semiconductor package and prevent wire sweeping.

Abstract: A plurality of FPGA dice is disposed upon a semiconductor substrate. In order to supply the immense power required by the plurality of FPGA dice, power is routed through the semiconductor substrate vertically from thick metal layers and large integral metal structures located on the other side of the semiconductor substrate. Because the semiconductor substrate has a different coefficient of thermal linear expansion than metal layers in contact with the substrate, delamination may occur when the structure is subject to changes in temperature. To prevent delamination of metal layers connected to the semiconductor substrate and in electrical contact with the integral metal structures, the integral metal structures are manufactured with an array of post portions. During changes in temperature, the post portions of the integral metal structures bend and slide relative to metal layers connected to the semiconductor substrate and prevent linear stresses that may otherwise cause delamination.