Abstract: A semiconductor device includes a substrate, a semiconductor element disposed on the main surface of the substrate and generating a heat of 200° C. or more, an enclosure surrounding the semiconductor element, and a liquid sealant containing a heat-resistant oil. The enclosure controls the flow of the sealant and seals the semiconductor element.

Abstract: Some embodiments include a device having a number of memory cells and associated circuitry for accessing the memory cells. The memory cells of the device may be formed in one or more memory cell dice. The associated circuitry of the device may also be formed in one or more dice, optionally separated from the memory cell dice.

Abstract: A system for hermetically sealing devices includes a substrate, which includes a plurality of individual chips. Each of the chips includes a plurality of devices and each of the chips are arranged in a spatial manner as a first array. The system also includes a transparent member of a predetermined thickness, which includes a plurality of recessed regions arranged in a spatial manner as a second array and each of the recessed regions are bordered by a standoff region. The substrate and the transparent member are aligned in a manner to couple each of the plurality of recessed regions to a respective one of said plurality of chips. Each of the chips within one of the respective recessed regions is hermetically sealed by contacting the standoff region of the transparent member to the plurality of first street regions and second street regions using at least a bonding process to isolate each of the chips within one of the recessed regions.

Abstract: A method (10) for manufacturing a monolithic molded electronic assembly (12). A mold (14) having first and second mold potions (14a-b) that mate to form an interior chamber (16) is provided. The mold has an injection port (22) and channel (24) connecting into the chamber. Electronic parts (30) having electronic contacts (32) are populated onto the second mold portion, to be substantially contained in the chamber. The mold potions are mated together and a liquid insulating molding material (36) is injected through the injection port channel to fill the chamber. The molding material is hardened to a solid, thereby embedding the electronic parts in the molding material as a monolithic sub-assembly (40). The monolithic sub-assembly is removed from the mold and one or more solderless conductive circuits (50) are applied to the electronic contacts of the electronic parts, thereby providing the electronic assembly.

Abstract: There is provided a semiconductor device whose cost is low and whose case is restrained from breaking. In the semiconductor device having a semiconductor sensor chip, a signal processing circuit for processing signals output from the semiconductor sensor chip and a hollow case for mounting the semiconductor sensor chip and the signal processing circuit therein, the case is constructed by bonding a concave bottom member whose one end is opened with a plate-like lid member that covers the opening of the bottom member. Then, the bottom and lid members are both made of a semiconductor material and are bonded by means of anode bonding or metal bonding for example.

Abstract: A packaging structure for hermetically sealing a functional device by solder connection at a wafer level in which a first Si substrate having a concave portion metallized on its internal surface and a second Si substrate metallized at a position opposed to said concave portion are used, the metallization applied to the internal surface of the concave portion of the first Si substrate and the metallization applied to the second Si substrate at the position opposed to the concave portion are connected by molten solder to hermetically seal the functional device between the first Si substrate and the second Si substrate, whereby the wettability of the solder for the two Si substrates is improved, the bondability between the Si substrates is enhanced, and the yield at which the package is manufactured is improved.

Abstract: An airtight sealed package with a device sealed therein in an airtight manner under vacuum, the device being placed in a space defined in the airtight sealed package by a lid and a substrate, includes at least one pressure adjustment unit provided on at least one of the lid and the substrate, and configured to receive energy from an outside of the airtight sealed package, with the device sealed in the airtight manner in the airtight sealed package, to adjust pressure in the space. An energy transmission member transmits the energy to the pressure adjustment unit.

Abstract: An apparatus and a method for producing three-dimensional integrated circuit packages. In one embodiment, an electronics package with at least two dice are stacked one atop another is disclosed. A top die is of smaller size compared with a bottom die such that after a die attach operation, wire-bond pads of the bottom die will be exposed for a subsequent wire bonding operation. The bottom die contains contact pads on the front side that couple with one or more passive components fabricated on the back side of the top die to complete the circuit. In another exemplary embodiment, a method to form one or more three-dimensional passive components in a stacked-die package is disclosed wherein partial inductor elements are fabricated on the front side of the bottom die and the back side of the top die. The top and bottom elements are coupled together completing the passive component.

Abstract: A semiconductor device includes a first circuit substrate having a plurality of lower wiring lines and a plurality of upper wiring lines on the lower surface side and upper surface side thereof, respectively. A second circuit substrate is provided on a lower side of the first circuit substrate, the second circuit substrate having an opening which exposes part of the first circuit substrate, the second circuit substrate also having, on the lower surface side thereof, a plurality of external-connection connection pads and a plurality of test connection pads connected to the lower wiring lines. A first semiconductor construct is disposed on the lower side of the first circuit substrate within the opening of the second circuit substrate, the first semiconductor construct having a plurality of external connection electrodes connected to the lower wiring lines.

Abstract: A substrate having a blind hole and a method for forming the blind hole. The method includes: (a) providing a substrate having a lower dielectric layer, a copper layer, and an upper dielectric layer; and (b) forming an upper dielectric layer through hole and a copper layer through hole by etching through the upper dielectric layer and the copper layer with laser, and forming a cavity on the lower dielectric layer by using the laser, in which the aperture of the cavity on the upper surface of the lower dielectric layer is larger than that of the copper layer through hole. Therefore, a blind hole space in a shape of a rivet is formed, so that after the blind hole space is electroplated with an electroplating copper layer, the bonding force between the electroplating copper layer and the copper layer is enhanced.

Abstract: An electronic device and method is disclosed. In one embodiment, a method includes providing an electrically insulating substrate. A first electrically conductive layer is applied over the electrically insulating substrate. A first semiconductor chip is placed over the first electrically conductive layer. The first semiconductor chip comprises a first electrode on a first main surface and a second electrode on a second main surface. An electrically insulating layer is applied over the first electrically conductive layer. A second electrically conductive layer is applied over the electrically insulating layer. A through connection is provided in the electrically insulating layer to couple the first electrically conductive layer to the second electrically conductive layer.

Abstract: A semiconductor device includes a semiconductor chip with bonding pads, the bonding pads being arranged along one side of an element forming surface of the semiconductor chip, a lead frame including first and second internal leads arranged such that tips thereof correspond to some of the bonding pads of the semiconductor chip, and first and second bonding wires by which the first internal leads and the some of the bonding pads are bonded to each other. The semiconductor device further includes a hanging pin section provided on the element non-forming surface of the semiconductor chip, and a sealing member with which the semiconductor chip is sealed including the hanging pin section and a bonding section between the first and second internal leads and the first and second bonding wires.

Abstract: A semiconductor module includes a first metal foil; an insulating sheet mounted on a top surface of the first metal foil; at least one second metal foil mounted on a top surface of the insulating sheet; at least one semiconductor device mounted on the second metal foil; and a resin case for surrounding the first metal foil, insulating sheet, second metal foil, and semiconductor device. A bottom end of a peripheral wall of the resin case is located above a bottom surface of the first metal foil. A resin is provided inside the resin case to fill the inside of the resin case. The bottom surface of the first metal foil and the resin form a flat bottom surface so that the flat bottom surface contacts an external mounting member.

Abstract: A semiconductor package includes a carrier, a chip, a stiffener and an encapsulant. The chip is disposed on the carrier. The stiffener is disposed around the chip, directly contacts the carrier, and is mounted on the carrier. The encapsulant is adapted to seal the chip and the stiffener.

Abstract: A process for packaging a number of micro-components on the same substrate wafer, in which each micro-component is enclosed in a cavity. This process includes making a covering plate comprising a re-useable matrix, a polymer layer, and a metal layer; covering the wafer with the covering plate; applying a contact pressure equal to at least one bar on the covering plate and on the wafer; heating the metal layer during pressing until sealing is obtained, each cavity thus being provided with a sealing area and closed by metal layer; and dissolving the polymer to recover and recycle the matrix.

Abstract: A semiconductor chip with a chip selection structure suitable for a stacked semiconductor chip includes a semiconductor chip body and a chip selection structure. The chip selection structure includes a chip selection pad disposed over the semiconductor chip body, a main through electrode electrically connected to the chip selection pad, and a sub through electrode interposed between the main through electrode and the chip selection pad. A plurality of the semiconductor chips, each having the same chip selection structure, can be stacked by offsetting the stacked semiconductor chips.

Abstract: A package structure of a compound semiconductor device comprises a thin film substrate, a die, at least one metal wire and a transparent encapsulation material. The thin film substrate comprises a first conductive film, a second conductive film, and an insulating dielectric material. The die is mounted on the surface of the first conductive film, and is electrically connected to the first conductive film and the second conductive film through the metal wire. The transparent encapsulation material overlays the first conductive film, second conductive film, and die. The surfaces of the first conductive film and second conductive film which is opposite the transparent encapsulation material act as electrodes. The insulating dielectric material is between the first conductive film and second conductive film.

Abstract: A semiconductor device and a fabrication method thereof are provided. An opening having at least one slanted side is formed on a substrate. At least one chip and at least one passive component are mounted on the substrate. An encapsulant having a cutaway corner is formed on the substrate to encapsulate the chip and the passive component, wherein the cutaway corner of the encapsulant is spaced apart from the slanted side of the opening by a predetermined distance. A singulation process is performed to cut the encapsulant to form a package with a chamfer. The package is embedded in a lid to form the semiconductor device, wherein a portion of the substrate located between the slanted side of the opening and the cutaway corner of the encapsulant is exposed from the encapsulant to form an exposed portion. The present invention also provides a carrier for the semiconductor device.

Abstract: The present invention is directed to a method and electronic computer package that is formed by placing an integrated circuit, having a plurality of bonding pads with solder bumps deposited thereon, in contact with the substrate so that one of the plurality of solder bumps is in superimposition with respect to one of the contacts and one of the plurality of bonding pads, with a volume being defined between region of the substrate in superimposition with the integrated circuit. A portion of the volume is filled with a quantity of underfill. A fluid flow barrier is formed on the substrate and defines a perimeter of the volume, defining a flow restricted region. The fluid flow barrier has dimensions sufficient to control the quantity of underfill egressing from the flow restricted region.

Abstract: A method of forming a semiconductor package with smooth edges, and a semiconductor package formed thereby is disclosed. In embodiments, after encapsulation, the semiconductor packages may be at least partially singulated from the panel by making one or more cuts through the panel to define one or more edges of the semiconductor package. The one or more edges may be smoothed by applying a laminate to the edges. The edges receiving the laminate may include any edge between a top and bottom surface of the package.

Abstract: A semiconductor device has a semiconductor die with a peripheral region around the die. A first insulating material is deposited in the peripheral region. A conductive via is formed through the first insulating material. A conductive layer is formed over the semiconductor die. The conductive layer is electrically connected between the conductive via and a contact pad of the semiconductor die. A second insulating layer is deposited over the first insulating layer, conductive layer, and semiconductor die. A profile is formed in the first and second insulating layers in the peripheral region. The profile is tapered, V-shaped, truncated V-shape, flat, or vertical. A shielding layer is formed over the first and second insulating layers to isolate the semiconductor die from inter-device interference. The shielding layer conforms to the profile in the peripheral region and electrically connects the shielding layer to the conductive via.

Abstract: An optical device package comprises: a metal frame including a substrate and a rectangular die pad portion integrally connected to the substrate, wherein the substrate is a metal plate, and the die pad portion is bent from the substrate such that the die pad portion extends from the substrate at an angle of 90 degrees; signal lead pins extend in the opposite directions from the die pad portion relative to the substrate such that the first lead pins intersect the principal surfaces of the substrate at a right angle and are spaced apart from the metal frame; and a molded resin member including a plate-like resin base extending across and in contact with one of the principal surfaces of the substrate, wherein the signal lead pins protrude from a surface of the resin base; surfaces of the signal lead pins are covered with the molded resin member; and the metal frame and the signal lead pins are secured in place by the molded resin member.

Abstract: Prepackaged chips, such a memory chips, are vertically stacked and bonded together with their terminals aligned. The exterior lead frames are removed including that portion which extends into the packaging. The bonding wires are now exposed on the collective lateral surface of the stack. In those areas where no bonding wire was connected to the lead frame, a bare insulative surface is left. A contact layer is disposed on top of the stack and vertical metalizations defined on the stack to connect the ends of the wires to the contact layer and hence to contact pads on the top surface of the contact layer. The vertical metalizations are arranged and configured to connect all commonly shared terminals of the chips, while the control and data input/output signals of each chip are separately connected to metalizations, which are disposed in part on the bare insulative surface.

Abstract: An interconnect structure (i.e., an interposer) which is mounted and electrically connected to a bottom semiconductor package substrate either prior or subsequent to such bottom substrate being populate with one or more electronic components. Subsequently, a top semiconductor package substrate which may also be populated with one or more electronic components is mounted to the interposer, such that all of the electronic components are disposed between the top and bottom interposers. Thereafter, a suitable mold compound is injected between the top and bottom substrates, the mold compound flowing about the electronic components, between the BGA joints, and at least partially about the interposer, thus helping to lock the interposer in place in the completed semiconductor package.

Abstract: A light source apparatus and a fabrication method thereof can prevent light interference between light emitting devices adjacent to each other and increase the luminous efficiency by collecting light emitted from the side of the light emitting device toward the front of a metal stem by forming grooves at a sub-mounts, bonding the light emitting device to the inside of the groove by a flip chip bonding method and forming a reflective layer inside the groove.

Abstract: An integrated circuit package system comprising: providing a first conductive line adjacent to a second conductive line; forming a first connection stack over the first conductive line with the first connection stack overhanging the second conductive line; connecting an integrated circuit device and the first connection stack; and encapsulating the integrated circuit device and the first connection stack.

Abstract: A semiconductor module includes components in a plastic casing. The semiconductor module includes a plastic package molding compound and a semiconductor chip. Also provided in the module are a first principal surface including an upper side of the plastic package molding compound and at least one active upper side of the semiconductor chip, a second principal surface including a back side of the plastic package molding compound, and a multilayered conductor track structure disposed on the first principal surface and a second metal layer disposed on the second principal surface.

Abstract: A protective structure is provided on a substrate to which a semiconductor die is attached. The protective structure surrounds the die and reduces the thermo-mechanical stresses to which the die is subject. The die is protected against cracking, warping, and delamination.

Abstract: A package structure includes a substrate, a first die and at least one second die. The substrate includes a first pair of parallel edges and a second pair of parallel edges. The first die is mounted over the substrate. The first die includes a third pair of parallel edges and a fourth pair of parallel edges, wherein the third pair of parallel edges and the fourth pair of parallel edges are not parallel to the first pair of parallel edges and the second pair of parallel edges, respectively. The at least one second die is mounted over the first die.

Abstract: The present invention provides a semiconductor device and a fabrication method therefor, the semiconductor device including a first semiconductor chip disposed on a substrate, a first sealing resin sealing the first semiconductor chip, a built-in semiconductor device disposed on the first sealing resin, and a second sealing resin sealing the first sealing resin and the built-in semiconductor device and covering a side surface of the substrate. According to an aspect of the present invention, it is possible to provide a high-quality semiconductor device and a fabrication method therefor, in which downsizing and cost reduction can be realized.

Abstract: A method of manufacture of an integrated circuit package stacking system including: forming a base frame includes: providing a support panel, and forming a coupling pad, a mounting pad, a base frame trace, a discrete component pad, or a combination thereof on the support panel; fabricating a package substrate; coupling an integrated circuit die to the package substrate; mounting the base frame over the integrated circuit die and the package substrate; and removing the support panel from the base frame.

Abstract: A semiconductor device is disclosed. One embodiment provides a module including a first carrier having a first mounting surface and a second mounting surface, a first semiconductor chip mounted onto the first mounting surface of the first carrier and having a first surface facing away from the first carrier, a first connection element connected to the first surface of the first semiconductor chip, a second semiconductor chip having a first surface facing away from the first carrier, a second connection element connected to the first surface of the second semiconductor chip, and a mold material covering the first connection element and the second connection element only partially.

Abstract: A semiconductor package 100 is constructed of a semiconductor chip 110, a sealing resin 106 for sealing this semiconductor chip 110, and wiring 105 formed inside the sealing resin 106. And, the wiring 105 is constructed of pattern wiring 105b connected to the semiconductor chip 110 and also formed so as to be exposed to a lower surface 106b of the sealing resin 106, and a post part 105a formed so as to extend in a thickness direction of the sealing resin 106, the post part in which one end is connected to the pattern wiring 105b and also the other end is formed so as to be exposed to an upper surface 106a of the sealing resin 106.

Abstract: An electrical device and method is disclosed. One embodiment provides a substrate, a sensor chip disposed completely above a plane section of a surface of the substrate. A structurally homogeneous material layer is disposed above the substrate and the sensor chip. A cavity is formed between the substrate and the material layer. The sensor chip is disposed inside the cavity.

Abstract: A chip package including a circuit substrate, a chip, a B-staged adhesive layer, a leadframe, a number of first bonding wires, a number of second bonding wires, and a number of third bonding wires. The chip is disposed on the circuit substrate. The B-staged adhesive layer is disposed on the circuit substrate. The leadframe is disposed on the circuit substrate and includes a number of leads. Portions of the leads are embedded in the B-staged adhesive layer, and an end of each of the leads is exposed by the B-staged adhesive layer. The first bonding wires are electrically connected between the chip and the circuit substrate. The second bonding wires are electrically connected between the chip and the leads. The third bonding wires are electrically connected between the leads and the circuit substrate. In addition, a manufacturing method of a chip package is also provided.

Abstract: This invention discloses an electronic package for containing a vertical semiconductor chip that includes a laminated board having a via connector and conductive traces distributed on multiple layers of the laminated board connected to the via connector. The semiconductor chip having at least one electrode connected to the conductive traces for electrically connected to the conductive traces at a different layer on the laminated board and the via connector dissipating heat generated from the vertical semiconductor. A ball grid array (BGA) connected to the via connector functioning as contact at a bottom surface of the package for mounting on electrical terminals disposed on a printed circuit board (PCB) wherein the laminated board having a thermal expansion coefficient in substantially a same range the PCB whereby the BGA having a reliable electrical contact with the electrical terminals.

Abstract: An integrated circuit package system includes: providing an integrated circuit; mounting a lead on the periphery of the integrated circuit; connecting the integrated circuit to the lead with an interconnect; and forming a conformable material by pressing the conformable material on the integrated circuit, the lead, and the interconnect.

Abstract: An electronic package for containing at least a top packaging module vertically stacked on a bottom packaging module. Each of the packaging modules includes a semiconductor chip packaged and connected by via connectors and connectors disposed on a laminated board fabricated with a standard printed-circuit board process wherein the top and bottom packaging module further configured as a surface mountable modules for conveniently stacking and mounting to prearranged electrical contacts without using a leadframe. At least one of the top and bottom packaging modules is a multi-chip module (MCM) containing at least two semiconductor chips. At least one of the top and bottom packaging modules includes a ball grid array (BGA) for surface mounting onto the prearranged electrical contacts. At least one of the top and bottom packaging modules includes a plurality of solder bumps on one of the semiconductor chips for surface mounting onto the prearranged electrical contacts.

Abstract: An electronic device housing includes a substrate, a film structure, and a protective film. The film structure includes an adhesive film, a film stack, and a protective film. The adhesive film is deposited onto the substrate. The film stack is deposited onto the adhesive film alternating dielectric films and metal films. The metal films are non-continuous with a total thickness of the metal films at a predetermined value. The protective film is deposited onto an upper film of the film stack.

Abstract: A semiconductor device includes a first die pad, a first semiconductor chip provided on the first die pad, a second die pad, a second semiconductor chip provided on the second die pad, and a sealing resin made of a first resin material, sealing the first die pad, the first semiconductor chip, the second die pad and the second semiconductor chip. A lower surface of the first semiconductor chip is connected to the first die pad. A first portion of a lower surface of the second semiconductor chip is connected to the second die pad, and a second portion not connected to the second die pad of the lower surface of the second semiconductor chip is connected to an upper surface of the first semiconductor chip via a second resin material different from the first resin material.

Abstract: A MEMS microphone package includes a carrier, an application specific IC, an encapsulant and a microphone chip. The application specific IC and the microphone chip are respectively disposed on first and second surfaces of the carrier, and the application specific IC and the microphone chip are electrically connected to the carrier. The encapsulant includes first and second encapsulants, the first encapsulant is formed on the first surface to seal the application specific IC, the second encapsulant is formed on the second surface to become a cavity and the microphone chip is located at the cavity. Because the application specific IC and the microphone chip are disposed on the first and second surfaces of the carrier, respectively, the second encapsulant surrounds the microphone chip, and the first and second encapsulants are formed at the same time, it can increase the structural strength of package and reduce the process.

Abstract: Semiconductor die packages and methods of making them are disclosed. An exemplary package comprises a leadframe having a source lead and a gate lead, and a semiconductor die coupled to the source and gate leads at a first surface of the leadframe. The source lead has a protruding region at a second surface of the leadframe. A molding material is disposed around the semiconductor die, the gate lead, and the source lead such that a surface of the die and a surface of the protruding region are left exposed by the molding material. An exemplary method comprises obtaining the semiconductor die and leadframe, and forming a molding material around at least a portion of the leadframe and die such that a surface of the protruding region is exposed through the molding material.

Abstract: A packaging apparatus for optical-semiconductors includes a mold base having a longitudinal receiving space, an encapsulating module attached to the mold base, and a fixing member attached to the encapsulating module. The bottom of the mold base has at least one air-vent and the mold base has a predetermined width. The encapsulating module includes a plate engaged with the mold base, a plurality of molding bodies penetrating the plate and received in the receiving space, and a plurality of supporting members connected to the molding bodies. The fixing member has a plurality of holding slots to hold the supporting members so that the supporting members are more stable. Furthermore, the width of the mold base is optimized with the dimension of a furnace so that the production rate is increased and the stability of the packaging structure is improved.

Abstract: An electronic device and method is disclosed. In one embodiment, a method includes providing an electrically insulating substrate. A first electrically conductive layer is applied over the electrically insulating substrate. A first semiconductor chip is placed over the first electrically conductive layer. An electrically insulating layer is applied over the first electrically conductive layer. A second electrically conductive layer is applied over the electrically insulating layer. A through connection is formed in the electrically insulating layer to couple the second electrically conductive layer to the first electrically conductive layer.

Abstract: A semiconductor package has a substrate with solder balls. A first semiconductor die is disposed on the substrate. A first double side mold (DSM) internal stackable module (ISM) is in physical contact with the first semiconductor die through a first adhesive, such as a film on wire adhesive. A second DSM ISM is in physical contact with the first DSM ISM through a second adhesive. The arrangement of the first and second DSM ISM reduce headroom requirements for the package and increase device packing density. Each DSM ISM has semiconductor die disposed in cavities. An interposer is disposed above the top DSM ISM. Wire bonds connect the semiconductor die and DSM ISMs to the solder balls. An encapsulant surrounds the first semiconductor die and first DSM ISM with an exposed mold area in the encapsulant above the interposer.

Abstract: A power semiconductor circuit has a power semiconductor module (2) embodied as a flat assembly. A particularly compact and space-saving production of a power semiconductor circuit may be achieved with the possibilities provided by an embodiment of the power semiconductor module, whereby the power semiconductor module (2) is arranged directly on a top track (3) of a power supply and/or output tracking (11) and a cooling device (5) is integrated in the tracking (11).

Abstract: A sealing apparatus for sealing by resin a semiconductor wafer having semiconductor elements on its surface. The apparatus includes an upper mold and a lower mold having an area where the semiconductor wafer is mounted, the lower mold having an uneven surface in the area and a shock absorber under the lower mold.

Abstract: A semiconductor device includes: a semiconductor chip mounted on a mounting substrate; a first resin filling a gap between the chip and the substrate; a frame-shaped stiffener surrounding the chip; a first adhesive for bonding the stiffener to the substrate; a lid for covering the stiffener and an area surrounded by the stiffener; and a second resin filling a space between the stiffener and the chip. A thermal expansion coefficient of the second resin is smaller than that of the first resin. The first resin includes an underfill part filling a gap between the chip and the substrate and a fillet part extended from the chip region.

Abstract: A redistributed lead frame for use in molded plastic semiconductor package (38) is formed from an electrically conductive substrate by a sequential metal removal process. The process includes: (a) patterning a first side of an electrically conductive substrate to form an array of lands separated by channels, (b) disposing a first molding compound (18) within these channels, (c) patterning a second side of the electrically conductive substrate to form an array of chip attach sites (24) and routing circuits (26) electrically interconnecting the array of lands and the array of chip attached sites (24), (d) directly electrically interconnecting input/output pads on the at least one semiconductor device (28) to chip attach site members (24) of the array of chip attach sites (24), and (e) encapsulating the at least one semiconductor device (28), the array of chip attach sites (24) and the routing circuits (26) with a second molding compound (36).

Abstract: An electronic component has a first semiconductor chip and a second semiconductor chip that is arranged on a plastic compound in which the first semiconductor chip is embedded. The semiconductor chips are connected to one another by rewiring layers and vias which extend between the rewiring layers, the vias being widened at a transition to one of the rewiring layers.