Rigid Electrode Portion Patents (Class 257/689)
  • Patent number: 11908826
    Abstract: A clip preform includes a die contact portion and an aligner structure. An intermediate portion connects the die contact portion to a lead contact portion in the aligner structure. The die contact portion is configured to contact a semiconductor die. The aligner structure is configured to attach the lead contact portion to a lead post. The die contact portion, the intermediate portion, and the aligner structure form a structure of a primary clip for connecting the semiconductor die to the lead post. The clip preform is severable by removing parts of the die contact portion and the intermediate portion of the clip preform to form a secondary clip for connecting the semiconductor die to the lead post. The aligner structure, a remaining part of the die contact portion, and a remaining part of the intermediate portion of the clip preform form a structure of the secondary clip.
    Type: Grant
    Filed: April 12, 2022
    Date of Patent: February 20, 2024
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Keunhyuk Lee, Jerome Teysseyre, Tiburcio A. Maldo
  • Patent number: 11289629
    Abstract: A light-emitting device having high output and high contrast with simple configuration is provided. The light-emitting device includes a substrate, a light-emitting element disposed on the substrate, a light-transmitting member disposed on the light-emitting element, and a covering body disposed on the substrate so as to surround the light-transmitting member and cover a side surface of the light-transmitting member. The covering body has a particle group including a plurality of metal oxide particles having a light scattering property and dispersed in the covering body, and the metal oxide particles existing in the vicinity of the side surface of the covering body have a portion having a bandgap smaller than that of other portions in each particle.
    Type: Grant
    Filed: December 5, 2019
    Date of Patent: March 29, 2022
    Assignee: STANLEY ELECTRIC CO., LTD.
    Inventors: Yoichi Shimoda, Yasuhiro Ono, Yusuke Yamashita
  • Patent number: 11139219
    Abstract: A bypass thyristor device includes a semiconductor device providing a thyristor with a cathode electrode on a cathode side, a gate electrode on the cathode side surrounded by the cathode electrode and an anode electrode on an anode side; an electrically conducting cover element arranged on the cathode side and in electrical contact with the cathode electrode on a contact side; and a gate contact element electrically connected to the gate electrode and arranged in a gate contact opening in the contact side of the cover element; wherein the cover element has a gas expansion volume in the contact side facing the cathode side, which gas expansion volume is interconnected with the gate contact opening for gas exchange.
    Type: Grant
    Filed: January 8, 2020
    Date of Patent: October 5, 2021
    Assignee: ABB Schweiz AG
    Inventors: Tobias Wikström, Remo Baumann, Sascha Populoh, Bjoern Oedegard
  • Patent number: 10651118
    Abstract: A solder resist is configured such that pattern covering portions of the solder resist covering straight portions of adjacent wiring patterns are separated from each other in an area outside of a resin mold part. Thus, even if the solder resist is cracked, cracks will not be formed so as to connect between the adjacent wiring patterns. As such, even if moisture generated by condensation or the like enters in the crack, it is less likely that a short circuit will occur between the adjacent wiring patterns.
    Type: Grant
    Filed: April 16, 2019
    Date of Patent: May 12, 2020
    Assignee: DENSO CORPORATION
    Inventors: Kosuke Suzuki, Atsushi Kashiwazaki, Yuki Sanada, Toshihiro Nakamura, Shinya Uchibori
  • Patent number: 10396056
    Abstract: A semiconductor device includes a printed circuit board in a peripheral portion of a housing portion of a case in which a laminated substrate is housed. A terminal block holding control terminals from which control signals are outputted to the printed circuit board is disposed over the printed circuit board. A gate electrode of a semiconductor chip and the printed circuit board are electrically connected by a wire.
    Type: Grant
    Filed: June 8, 2016
    Date of Patent: August 27, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Shin Soyano
  • Patent number: 10147699
    Abstract: In a pressure contact type semiconductor apparatus, a second intermediate electrode on a second semiconductor chip has one or more second through holes. The one or more second through holes are fluidly separated from a space hermetically sealed by a cylindrical body, a first common electrode plate and a second common electrode plate. The pressure contact type semiconductor apparatus thereby has high reliability.
    Type: Grant
    Filed: March 25, 2016
    Date of Patent: December 4, 2018
    Assignee: Mitsubishi Electric Corporation
    Inventors: Satoshi Okuda, Akihiko Furukawa, Tomohiro Ikeda
  • Patent number: 9831350
    Abstract: Provided is a thin film transistor (TFT) that includes a first electrode on a substrate separated from a second electrode, an oxide semiconductor pattern on the second electrode including a channel region, a third electrode on the oxide semiconductor pattern, a first insulating layer on the substrate including the third electrode including first contact holes exposing a part of the first electrode, a part of the second electrode, and a part of the third electrode, a gate electrode on the first insulating layer and corresponding to a part of the oxide semiconductor pattern, a second insulating layer on the substrate including the gate electrode including a second contact hole corresponding to the first contact hole that exposes a part of the second electrode, and a pixel electrode on the second insulating layer electrically connected to the second electrode through the first contact hole and the second contact hole.
    Type: Grant
    Filed: October 19, 2015
    Date of Patent: November 28, 2017
    Assignee: Samsung Display Co., Ltd.
    Inventors: Yeon-Keon Moon, Je-Hun Lee
  • Patent number: 9793244
    Abstract: Embodiments of the present disclosure describe scalable package architecture of an integrated circuit (IC) assembly and associated techniques and configurations.
    Type: Grant
    Filed: July 11, 2014
    Date of Patent: October 17, 2017
    Assignee: Intel Corporation
    Inventors: Sanka Ganesan, Bassam Ziadeh, Nitesh Nimkar
  • Patent number: 9717161
    Abstract: A board assembly including a cooling system includes: a wiring board; a first heat generating component mounted on a surface of the wiring board; a first heat receiving portion mounted on the first heat generating component and configured to allow a coolant to pass therethrough; a second heat generating component mounted on another surface of the wiring board; a second heat receiving portion mounted on the second heat generating component and configured to allow the coolant to pass therethrough; and a support post disposed through the wiring board so as to extend between the first heat receiving portion and the second heat receiving portion, the support post having a space through which the coolant flows from the first heat receiving portion to the second heat receiving portion or from the second heat receiving portion to the first heat receiving portion.
    Type: Grant
    Filed: October 1, 2015
    Date of Patent: July 25, 2017
    Assignee: FUJITSU LIMITED
    Inventors: Kenji Katsumata, Jie Wei, Masumi Suzuki
  • Patent number: 9437797
    Abstract: A cooling structure of a heating element includes: the heating element having at least one cooling surface from which a plurality of pin fins project; a heat receiving plate which has a shape complying with the cooling surface and in which holes are formed at positions facing each pin fin, each pin fin being movably inserted into the holes; a cooler which has a pair of clamping members that sandwich therebetween the heating element and the heat receiving plate while pressing the heating element and the heat receiving plate, and which cools the heat receiving plate; and a space securing part which is provided on the heat receiving plate and suppresses a distance between the pair of clamping members so as not to apply a pressing force by the clamping members to the heating element.
    Type: Grant
    Filed: August 5, 2015
    Date of Patent: September 6, 2016
    Assignee: Hitachi, Ltd.
    Inventors: Daisuke Matsumoto, Akira Mima, Tetsuya Kawashima, Yuuichi Mabuchi, Yukio Hattori, Hiroshi Kamizuma, Ryouhei Miyagawa, Tomonori Ichikawa
  • Patent number: 9214432
    Abstract: A semiconductor module has a carrier, a semiconductor chip mounted on the carrier, a bond wire, a module housing, and a first sound absorber. The module housing has a housing side wall. The bond wire is arranged in the module housing. At least a section of the first sound absorber is arranged between the semiconductor chip and the housing side wall.
    Type: Grant
    Filed: September 29, 2014
    Date of Patent: December 15, 2015
    Assignee: Infineon Technologies AG
    Inventors: Guido Boenig, Olaf Hohlfeld
  • Patent number: 8970047
    Abstract: A 3D stacked multichip module comprises a stack of W IC die. Each die has a patterned conductor layer, including an electrical contact region with electrical conductors and, in some examples, device circuitry over a substrate. The electrical conductors of the stacked die are aligned. Electrical connectors extend into the stack to contact landing pads on the electrical conductors to create a 3D stacked multichip module. The electrical connectors may pass through vertical vias in the electrical contact regions. The landing pads may be arranged in a stair stepped arrangement. The stacked multichip module may be made using a set of N etch masks with 2N-1 being less than W and 2N being greater than or equal to W, with the etch masks alternatingly covering and exposing 2n-1 landing pads for each mask n=1, 2 . . . N.
    Type: Grant
    Filed: August 21, 2014
    Date of Patent: March 3, 2015
    Assignee: Macronix International Co., Ltd.
    Inventor: Shih-Hung Chen
  • Patent number: 8927996
    Abstract: An organic light emitting diode (OLED) display device, including a first substrate and a second substrate facing each other, a sealant arranged between the first and second substrates to adhere the first and second substrates together, a plurality of interconnections arranged on one of the first and second substrates and a plurality of cladding parts covering at least a portion of each of the plurality of interconnections at a location that corresponds to the sealant, each of the cladding parts including a material having a higher melting point than that of the interconnections. By including the cladding parts, a short circuit between the interconnections caused by heat applied to the sealant can be prevented, and safety and reliability of the OLED display device can be improved.
    Type: Grant
    Filed: November 26, 2010
    Date of Patent: January 6, 2015
    Assignee: Samsung Display Co., Ltd.
    Inventors: Seung-Yeon Cho, Zail Lhee, Tae-Wook Kang, Hun Kim, Mi-Sook Suh, Hyun-Chol Bang
  • Patent number: 8907376
    Abstract: A stretchable electronic circuit that includes a stretchable base substrate having a plurality of stretchable conductors formed onto a surface thereof, with both the stretchable base substrate and conductors being bendable together about two orthogonal axes. The stretchable circuit also includes a stretchable sensor layer attached to the base substrate with a cavity formed therein which has a contact point exposing one of the plurality of stretchable conductors. The stretchable electronic circuit further includes a surface mount device (SMD) package with a conductor contact protrusion installed into the cavity, and wherein a substantially constant electrical connection is established between the conductor contact protrusion and the stretchable conductor at the contact point by tensile forces interacting between the stretchable base substrate and the stretchable sensor layer.
    Type: Grant
    Filed: November 8, 2012
    Date of Patent: December 9, 2014
    Assignee: University of Utah Research Foundation
    Inventors: Stephen Mascaro, Debra Mascaro, Jumana Abu-Khalaf, Jungwoo Park
  • Patent number: 8860203
    Abstract: A stretchable organic light-emitting display device includes a stretchable base plate including a stretchable substrate, first metal electrodes that are separated from each other and located in a plurality of rows on a the stretchable substrate, and first power wirings electrically coupling respective ones of the metal electrodes of each row, a light-emitting layer on the stretchable base plate, second metal electrodes located in a plurality of rows on the light-emitting layer and corresponding to the first metal electrodes, second power wirings for electrically coupling respective ones of the second metal electrodes of each row, and an encapsulation substrate covering the second power wiring.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: October 14, 2014
    Assignee: Samsung Display Co., Ltd.
    Inventors: Chang-Hoon Lee, Jong-Ho Hong, Won-Sang Park, Jong-In Baek
  • Patent number: 8810020
    Abstract: A semiconductor device has external, exposed electrical contacts at an device active face and a semiconductor die, which has internal, electrical contacts at a die active face. The exposed contacts are offset from the internal contacts laterally of the device active face. A redistribution layer includes a layer of insulating material and redistribution interconnectors within the insulating material, the interconnectors connecting with the exposed contacts. A set of conductors connect the internal contacts and the interconnectors. The conductors have oblong, tear drop shaped cross-sections extending laterally of the die active face beyond the respective internal contacts, and contact the interconnectors at positions spaced further apart than the internal contacts. The redistribution layer may be prefabricated using less costly manufacturing techniques such as lamination.
    Type: Grant
    Filed: June 22, 2012
    Date of Patent: August 19, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Navas Khan Oratti Kalandar, Chee Seng Foong, Norazham Mohd Sukemi, Kesvakumar V. C. Muniandy
  • Patent number: 8791578
    Abstract: This invention discloses a through-silicon via (TSV) structure for providing an electrical path between a first-side surface and a second-side surface of a silicon chip, and a method for fabricating the structure. In one embodiment, the TSV structure comprises a via penetrated through the chip from the first-side surface to the second-side surface, providing a first end on the first-side surface and a second end on the second-side surface. A local isolation layer is deposited on the via's sidewall and on a portion of the first-side surface surrounding the first end. The TSV structure further comprises a plurality of substantially closely-packed microstructures arranged to form a substantially non-random pattern and fabricated on at least the portion of the first-side surface covered by the local isolation layer for promoting adhesion of the local isolation layer to the chip. A majority of the microstructures has a depth of at least 1 ?m.
    Type: Grant
    Filed: November 12, 2012
    Date of Patent: July 29, 2014
    Assignee: Hong Kong Applied Science and Technology Research Institute Company Limited
    Inventors: Pui Chung Simon Law, Bin Xie, Dan Yang
  • Patent number: 8742602
    Abstract: A die assembly includes a die mounted to a support, in which the support has interconnect pedestals formed at bond pads, and the die has interconnect terminals projecting beyond a die edge into corresponding pedestals. Also, a support has interconnect pedestals. Also, a method for electrically interconnecting a die to a support includes providing a support having interconnect pedestals formed at bond pads on the die mount surface of the support, providing a die having interconnect terminals projecting beyond a die edge, positioning the die in relation to the support such that the terminals are aligned with the corresponding pedestals, and moving the die and the support toward one another so that the terminals contact the respective pedestals.
    Type: Grant
    Filed: March 12, 2008
    Date of Patent: June 3, 2014
    Assignee: Invensas Corporation
    Inventors: Terrence Caskey, Lawrence Douglas Andrews, Jr., Scott McGrath, Simon J. S. McElrea, Yong Du, Mark Scott
  • Patent number: 8654537
    Abstract: Electrical components such as integrated circuits may be mounted on a printed circuit board. To prevent the electrical components from being subjected to electromagnetic interference, radio-frequency shielding structures may be formed over the components. The radio-frequency shielding structures may be formed from a layer of metallic paint. Components may be covered by a layer of dielectric. Channels may be formed in the dielectric between blocks of circuitry. The metallic paint may be used to coat the surfaces of the dielectric and to fill the channels. Openings may be formed in the surface of the metallic paint to separate radio-frequency shields from each other. Conductive traces on the surface of the printed circuit board may be used in connecting the metallic paint layer to internal printed circuit board traces.
    Type: Grant
    Filed: December 1, 2010
    Date of Patent: February 18, 2014
    Assignee: Apple Inc.
    Inventors: Joseph Fisher, Jr., Sean Mayo, Dennis R. Pyper, Paul Nangeroni, Jose Mantovani
  • Patent number: 8614502
    Abstract: A semiconductor assembly board includes a supporting board, a coreless build-up circuitry and a built-in electronic device. The supporting board includes a bump, a flange and a via hole in the bump. The built-in electronic device extends into the via hole and is electrically connected to the build-up circuitry. The build-up circuitry extends from the flange and the built-in electronic device and provides signal routing for the built-in electronic device. The supporting board provides mechanical support, ground/power plane and heat sink for the coreless build-up circuitry.
    Type: Grant
    Filed: April 26, 2012
    Date of Patent: December 24, 2013
    Assignee: Bridge Semiconductor Corporation
    Inventors: Charles W.C. Lin, Chia-Chung Wang
  • Patent number: 8497581
    Abstract: A semiconductor device includes: a semiconductor chip; a protective film and an insulating film sequentially stacked over the semiconductor chip, and each having openings that expose source, drain, and gate pads; a heat dissipation terminal made of a material having a higher thermal conductivity than the insulating film; connection terminals formed on the source, drain, and gate pads and surrounded by the insulating film; and a mount substrate having connection pads. The semiconductor chip has a source electrode having a plurality of source fingers, a drain electrode having a plurality of drain fingers, and a gate electrode having a plurality of gate fingers. The source, drain, and gate pads are connected to the source electrode, the drain electrode, and the gate electrode, respectively. The connection terminals are respectively connected to the connection pads. The heat dissipation terminal is in close contact with the mount substrate.
    Type: Grant
    Filed: August 29, 2011
    Date of Patent: July 30, 2013
    Assignee: Panasonic Corporation
    Inventors: Ayanori Ikoshi, Yasuhiro Uemoto, Manabu Yanagihara, Tatsuo Morita
  • Patent number: 8466546
    Abstract: A semiconductor package including a conductive clip preferably in the shape of a can, a semiconductor die, and a conductive stack interposed between the die and the interior of the can which includes a conductive platform and a conductive adhesive body.
    Type: Grant
    Filed: April 21, 2006
    Date of Patent: June 18, 2013
    Assignee: International Rectifier Corporation
    Inventors: Andy Farlow, Mark Pavier, Andrew N. Sawle, George Pearson, Martin Standing
  • Patent number: 8445323
    Abstract: A semiconductor device includes an IPD structure, a first semiconductor die mounted to the IPD structure with a flipchip interconnect, and a plurality of first conductive posts that are disposed adjacent to the first semiconductor die. The semiconductor device further includes a first molding compound that is disposed over the first conductive posts and first semiconductor die, a core structure bonded to the first conductive posts over the first semiconductor die, and a plurality of conductive TSVs disposed in the core structure. The semiconductor device further includes a plurality of second conductive posts that are disposed over the core structure, a second semiconductor die mounted over the core structure, and a second molding compound disposed over the second conductive posts and the second semiconductor die. The second semiconductor die is electrically connected to the core structure.
    Type: Grant
    Filed: March 19, 2012
    Date of Patent: May 21, 2013
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Yaojian Lin, Jianmin Fang, Kang Chen, Haijing Cao
  • Patent number: 8378473
    Abstract: In inlets used for ID tags and the like, a defective connection between an integrated circuit part and an antenna is suppressed by improvement of tolerance for a bending or a pressing pressure. The integrated circuit part includes a semiconductor chip and a multilayer substrate having a concave portion. The semiconductor chip is mounted on the bottom of the concave portion. The multilayer substrate includes a connection electrode at the top surface and a connection electrode connected to the semiconductor chip on the bottom of the concave portion. The connection electrode on the bottom of the concave portion is connected to the connection electrode at the top surface by a penetration electrode inside a multilayer substrate. By such a configuration, the semiconductor chip is connected to the antenna.
    Type: Grant
    Filed: November 23, 2010
    Date of Patent: February 19, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Yasuyuki Arai
  • Patent number: 8313982
    Abstract: A method of through substrate via (TSV) die assembly includes positioning a plurality of TSV die with their topside facing down onto a curable bonding adhesive layer on a carrier. The plurality of TSV die include contactable TSVs that include or are coupled to bondable bottomside features protruding from its bottomside. The curable bonding adhesive layer is cured after the positioning. A plurality of second IC die each having a plurality of second bonding features are bonded onto the plurality of TSV die to form a plurality of stacked die assemblies on the carrier. Debonding after the bonding separates the carrier from the plurality of stacked die assemblies. The plurality of stacked die assemblies are then singulated to form a plurality of singulated stacked die assemblies.
    Type: Grant
    Filed: September 20, 2010
    Date of Patent: November 20, 2012
    Assignee: Texas Instruments Incorporated
    Inventors: Rajiv Dunne, Margaret Rose Simmons-Matthews
  • Patent number: 8217269
    Abstract: Devices and methods for electrical interconnection for microelectronic circuits are disclosed. One method of electrical interconnection includes forming a bundle of microfilaments, wherein at least two of the microfilaments include electrically conductive portions extending along their lengths. The method can also include bonding the microfilaments to corresponding bond pads of a microelectronic circuit substrate to form electrical connections between the electrically conductive portions and the corresponding bond pads. A microelectronic circuit can include a bundle of microfilaments bonded to corresponding bond pads to make electrical connection between corresponding bonds pads and electrically-conductive portions of the microfilaments.
    Type: Grant
    Filed: August 18, 2011
    Date of Patent: July 10, 2012
    Assignee: Raytheon Company
    Inventors: Stephen C. Jacobsen, David P. Marceau, Shayne M. Zum, David T. Markus
  • Patent number: 8168985
    Abstract: A semiconductor module having one or more silicon carbide diode elements mounted on a switching element is provided in which the temperature rise is reduced by properly disposing each of the diode elements on the switching element, to thereby provide a thermal dissipation path for the respective diode elements. The respective diode elements are arranged on a non-central portion of the switching element, to facilitate dissipation of the heat produced by each of the diode elements, whereby the temperature rise in the semiconductor module is reduced.
    Type: Grant
    Filed: August 19, 2009
    Date of Patent: May 1, 2012
    Assignee: Mitsubishi Electric Corporation
    Inventors: Kiyoshi Arai, Gourab Majumdar
  • Patent number: 8159072
    Abstract: The present invention includes a base, a rectification chip, a conductive element and a coupling collar. The base has an installation pedestal to hold the rectification chip. The conductive element has a root portion to hold the rectification chip. The coupling collar is located at one end of the base to hold a package. The coupling collar has a plurality of anchor portions in contact with the package. Each anchor portion has a convex portion and a concave portion extended to two ends of the coupling collar. The convex portion and concave portion of two neighboring anchor portions are formed in a staggered manner. The cross section area of the convex portion on the annular edge of the coupling collar is different from the cross section area of the inner wall of the coupling collar. Hence fabrication and assembly are easier. Turning and loosening of the package can be prevented.
    Type: Grant
    Filed: December 18, 2009
    Date of Patent: April 17, 2012
    Inventor: Wen-Huo Huang
  • Patent number: 8154124
    Abstract: A semiconductor chip has a main surface, a back surface and a plurality of side surfaces. A plurality of electrodes is provided on the main surface of the semiconductor chip so as to be arranged in a plurality of lines. An insulating film is formed on the main surface of the semiconductor chip so as to expose at least one of the plurality of electrodes. A plurality of leads are formed on the insulating film, each of the plurality of leads having a first end and a second end, and the first end of the lead being connected to the one of the plurality of electrodes. A base resin film is formed on the insulting film and the plurality of leads, the base resin film having a plurality of electrodes holes exposing a part of the second end of each of the leads and a device hole in which the first end of the lead and the one of the plurality of electrodes are located.
    Type: Grant
    Filed: December 17, 2007
    Date of Patent: April 10, 2012
    Assignee: Oki Electric Industry Co., Ltd.
    Inventors: Yoshikazu Takahashi, Masami Suzuki, Masaru Kimura
  • Patent number: 8143645
    Abstract: Each of first base regions of sequentially layered first IGBT and second IGBT has a peripheral section in the vicinity of the side face of the semiconductor substrate. Each of the IGBTs includes a P-type peripheral base region that is adjacent to the peripheral section of the first base region of the N-type to form a diode and a diode electrode that is formed on an upper face of the peripheral section of the first base region, thereby electrically connecting the diode electrode and a collector electrode of each of the IGBTs. When the semiconductor device is ON, current flows at the center side of the semiconductor substrate separated from the side face. When current in a reverse direction is generated when the semiconductor device is OFF, current in a reverse direction flows in the vicinity of the side face of the semiconductor substrate.
    Type: Grant
    Filed: March 22, 2006
    Date of Patent: March 27, 2012
    Assignee: Sanken Electric Co., Ltd.
    Inventor: Katsuyuki Torii
  • Patent number: 8129277
    Abstract: A method of machining a wafer in which, at the time of grinding the back-side surface of the wafer, only a back-side surface region corresponding to a device formation region where semiconductor chips are formed is thinned by grinding, to form a recessed part on the back side of the wafer. An annular projected part surrounding the recessed part is utilized to secure rigidity of the wafer. Next, the recessed part is etched to cause metallic electrodes to project from the bottom surface of the recessed part, thereby forming a back-side electrode parts, then an insulating film is formed in the recessed part, and the insulating film and end surfaces of the back-side electrode parts are cut.
    Type: Grant
    Filed: June 18, 2008
    Date of Patent: March 6, 2012
    Assignee: Disco Corporation
    Inventors: Yusuke Kimura, Kuniaki Tsurushima
  • Patent number: 8125069
    Abstract: A method for manufacturing a semiconductor device comprises dry-etching a thin film using a resist mask carrying patterns in which at least one of the width of each pattern and the space between neighboring two patterns ranges from 32 to 130 nm using a halogenated carbon-containing compound gas with the halogen being at least two members selected from the group consisting of F, I and Br. The ratio of at least one of I and Br is not more than 26% of the total amount of the halogen atoms as expressed in terms of the atomic compositional ratio to transfer the patterns onto the thin film. Such etching of a thin film avoids causing damage to the resist mask used. The resulting thin film carrying the transferred patterns is used as a mask for subjecting the underlying material to dry-etching.
    Type: Grant
    Filed: July 6, 2010
    Date of Patent: February 28, 2012
    Assignee: Philtech Inc.
    Inventors: Toshio Hayashi, Yasuhiro Morikawa, Michio Ishikawa, Yuji Furumura, Naomi Mura
  • Patent number: 8124453
    Abstract: An electronic package for containing at least a top packaging module vertically stacked on a bottom packaging module. Each of the packaging modules includes a semiconductor chip packaged and connected by via connectors and connectors disposed on a laminated board fabricated with a standard printed-circuit board process wherein the top and bottom packaging module further configured as a surface mountable modules for conveniently stacking and mounting to prearranged electrical contacts without using a leadframe. At least one of the top and bottom packaging modules is a multi-chip module (MCM) containing at least two semiconductor chips. At least one of the top and bottom packaging modules includes a ball grid array (BGA) for surface mounting onto the prearranged electrical contacts. At least one of the top and bottom packaging modules includes a plurality of solder bumps on one of the semiconductor chips for surface mounting onto the prearranged electrical contacts.
    Type: Grant
    Filed: November 8, 2010
    Date of Patent: February 28, 2012
    Assignee: Alpha & Omega Semiconductor, Ltd
    Inventors: Ming Sun, Yueh Se Ho
  • Patent number: 8115266
    Abstract: A microelectromechanical system (MEMS) device includes a semiconductor substrate, a MEMS including a fixed electrode and a movable electrode formed on the semiconductor substrate through an insulating layer, and a well formed in the semiconductor substrate below the fixed electrode. The well is one of an n-type well and a p-type well. The p-type well applies a positive voltage to the fixed electrode while the n-type well applies a negative voltage to the fixed electrode.
    Type: Grant
    Filed: June 28, 2011
    Date of Patent: February 14, 2012
    Assignee: Seiko Epson Corporation
    Inventors: Toru Watanabe, Akira Sato, Shogo Inaba, Takeshi Mori
  • Patent number: 8106501
    Abstract: A semiconductor die package. The semiconductor die package comprises a semiconductor die and a molded clip structure comprising a clip structure and a first molding material covering at least a portion of the clip structure. The first molding material exposes an outer surface of the clip structure. The clip structure is electrically coupled to the semiconductor die. The semiconductor die package further comprises a leadframe structure comprising a die attach pad and a plurality of leads extending from the die attach pad. The semiconductor die is on the die attach pad of the leadframe structure. A second molding material covers at least a portion of the semiconductor die and the leadframe structure. The semiconductor die package also includes a heat slug and a thermally conductive material coupling the heat slug to the exposed surface of the clip structure.
    Type: Grant
    Filed: December 12, 2008
    Date of Patent: January 31, 2012
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Maria Clemens Y. Quinones, Maria Cristina B. Estacio
  • Patent number: 8093706
    Abstract: A mounting structure includes: at least one semiconductor device having solder bumps as outer terminals and a flexible wiring board with wiring formed thereon. The semiconductor device is structured to be wrapped by the flexible wiring board, the mounting structure is provided with outer electrodes on both sides of the flexible wiring board, one side being a side where outer terminals of the semiconductor device are formed, and the other side being an opposite side thereof. At least one wiring layer is formed on the flexible wiring board. A supporting member is provided covering side faces and a surface of the semiconductor device opposite to the side where the outer terminals are formed and protruding from the side faces of the semiconductor device and extending toward the surface on which the outer terminals are formed.
    Type: Grant
    Filed: March 24, 2009
    Date of Patent: January 10, 2012
    Assignee: NEC Corporation
    Inventors: Shinji Watanabe, Takao Yamazaki
  • Patent number: 8030749
    Abstract: A semiconductor device includes a resin case, a plurality of external connection terminals fixedly provided on the resin case, and at least one semiconductor element provided in the resin case. At least one terminal block has at least one wiring terminal for electrically connecting the semiconductor element and the external connection terminals.
    Type: Grant
    Filed: November 20, 2008
    Date of Patent: October 4, 2011
    Assignee: Fuji Electric Systems Co., Ltd.
    Inventors: Shin Soyano, Katsumichi Ueyanagi
  • Patent number: 7977699
    Abstract: A light emitting device package and a method of manufacturing the light emitting device package are provided. A base is first provided and a hole is formed on the base. After a light emitting portion is formed on the base, a mold die is placed on the light emitting portion and a molding material is injected through the hole. The mold die is removed to complete the package.
    Type: Grant
    Filed: June 7, 2006
    Date of Patent: July 12, 2011
    Assignee: LG Innotek Co., Ltd.
    Inventors: Jun Seok Park, Seok Hoon Kang
  • Patent number: 7931206
    Abstract: A wireless IC device includes a radiation plate, a feeding circuit substrate on which a feeding circuit including a resonant circuit including an inductance element is provided, the feeding circuit being electromagnetically coupled to the radiation plate, and a wireless IC chip including a connection electrode, the wireless IC chip being disposed on the feeding circuit substrate. A mounting electrode is provided on the feeding circuit substrate. The frequency of signals sent and received using the radiation plate substantially corresponds to the resonant frequency of the resonant circuit. The wireless IC chip is electromagnetically coupled to the mounting electrode.
    Type: Grant
    Filed: May 21, 2009
    Date of Patent: April 26, 2011
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Noboru Kato, Yuya Dokai, Nobuo Ikemoto
  • Patent number: 7919835
    Abstract: The present invention provides a semiconductor device having a low-k film including an interconnect layer and a highly-reliable through-substrate contact plug. The semiconductor device includes: a semiconductor substrate having a first surface and a second surface facing each other; a first insulating film formed on the first surface of the semiconductor substrate and having a specific permittivity of 4 or higher; a circuit constituent element formed on the first surface of the semiconductor substrate and covered with the first insulating film); a contact plug formed in the first insulating film and electrically connected to the circuit constituent element; a through-substrate contact plug penetrating through the semiconductor substrate and the first insulating film; a second insulating film formed on the first insulating film and having a specific permittivity of 3.
    Type: Grant
    Filed: December 10, 2008
    Date of Patent: April 5, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Kazutaka Akiyama
  • Patent number: 7893528
    Abstract: A package structure of a compound semiconductor device comprises a thin film substrate, a die, at least one metal wire and a transparent encapsulation material. The thin film substrate comprises a first conductive film, a second conductive film, and an insulating dielectric material. The die is mounted on the surface of the first conductive film, and is electrically connected to the first conductive film and the second conductive film through the metal wire. The transparent encapsulation material overlays the first conductive film, second conductive film, and die. The surfaces of the first conductive film and second conductive film which is opposite the transparent encapsulation material act as electrodes. The insulating dielectric material is between the first conductive film and second conductive film.
    Type: Grant
    Filed: February 13, 2009
    Date of Patent: February 22, 2011
    Assignee: Advanced Optoelectronic Technology, Inc.
    Inventors: Pin Chuan Chen, Shen Bo Lin
  • Patent number: 7859088
    Abstract: A semiconductor device manufacturing method capable of making in-plane temperature distribution on a wafer uniform at heat treatment time. Before heat treatment is performed by irradiating the wafer with lamp light from the side of a device formed area where semiconductor devices are to be formed, an SiN film with certain thickness the reflection factor of which is equal to the average reflection factor of the device formed area is formed in an edge portion outside the device formed area. By doing so, reflection factors on the surface of the wafer irradiated with lamp light can be made uniform and uniform temperature distribution on the wafer can be obtained at heat treatment time. As a result, in-plane variations in the characteristics of semiconductor devices on the wafer can be made small and high-quality semiconductor devices can be manufactured.
    Type: Grant
    Filed: January 22, 2008
    Date of Patent: December 28, 2010
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Takae Sukegawa, Ryou Nakamura
  • Patent number: 7847384
    Abstract: A semiconductor package 100 is constructed of a semiconductor chip 110, a sealing resin 106 for sealing this semiconductor chip 110, and wiring 105 formed inside the sealing resin 106. And, the wiring 105 is constructed of pattern wiring 105b connected to the semiconductor chip 110 and also formed so as to be exposed to a lower surface 106b of the sealing resin 106, and a post part 105a formed so as to extend in a thickness direction of the sealing resin 106, the post part in which one end is connected to the pattern wiring 105b and also the other end is formed so as to be exposed to an upper surface 106a of the sealing resin 106.
    Type: Grant
    Filed: August 17, 2006
    Date of Patent: December 7, 2010
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Tsuyoshi Kobayashi, Tetsuya Koyama, Takaharu Yamano
  • Patent number: 7829989
    Abstract: An electronic package for containing at least a top packaging module vertically stacked on a bottom packaging module. Each of the packaging modules includes a semiconductor chip packaged and connected by via connectors and connectors disposed on a laminated board fabricated with a standard printed-circuit board process wherein the top and bottom packaging module further configured as a surface mountable modules for conveniently stacking and mounting to prearranged electrical contacts without using a leadframe. At least one of the top and bottom packaging modules is a multi-chip module (MCM) containing at least two semiconductor chips. At least one of the top and bottom packaging modules includes a ball grid array (BGA) for surface mounting onto the prearranged electrical contacts. At least one of the top and bottom packaging modules includes a plurality of solder bumps on one of the semiconductor chips for surface mounting onto the prearranged electrical contacts.
    Type: Grant
    Filed: December 22, 2005
    Date of Patent: November 9, 2010
    Assignee: Alpha & Omega Semiconductor, Ltd.
    Inventors: Ming Sun, Yueh Se Ho
  • Patent number: 7825468
    Abstract: A semiconductor package may include a semiconductor pattern, a bonding pad, and a polymer insulation member. The semiconductor pattern may include a semiconductor device and first hole. The bonding pad may include a wiring pattern and plug. The wiring pattern may be formed on an upper face of the semiconductor pattern. The plug may extend from the wiring pattern to fill the first hole. The polymer insulation member may be formed on a lower face of the semiconductor pattern and may include a second hole exposing a lower end of the plug. A method of manufacturing a semiconductor package may include forming a first hole through a semiconductor substrate; forming a bonding pad and plug; attaching a supporting member to the upper face of the substrate; reducing a thickness of the substrate; forming a polymer insulation member on the lower face of the substrate; and cutting the substrate.
    Type: Grant
    Filed: December 28, 2007
    Date of Patent: November 2, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yong-Chai Kwon, Dong-Ho Lee
  • Patent number: 7816745
    Abstract: A hermetically sealed microelectromechanical system (MEMS) package includes a MEMS switch having a movable portion and a stationary portion with an electrical contact thereon. A glass lid is anodically bonded to the MEMS switch to form a sealed cavity over the movable portion of the MEMS switch. The glass lid includes a contact aperture to allow access to the electrical contact on the stationary portion of the MEMS switch. A family of body-implantable hermetically-sealed MEMS packages are provided according to certain aspects and embodiments of the present invention.
    Type: Grant
    Filed: February 25, 2005
    Date of Patent: October 19, 2010
    Assignee: Medtronic, Inc.
    Inventors: Rogier Receveur, Cornel Marxer
  • Patent number: 7786565
    Abstract: A semiconductor apparatus includes a semiconductor chip 61 including a power semiconductor device using a wide band gap semiconductor, base materials 62 and 63, first and second intermediate members 65 and 68a, a heat conducting member 66, a radiation fin 67, and an encapsulating material 68 for encapsulating the semiconductor chip 61, the first and second intermediate member 65 and 68a and the heat conducting member 66. The tips of the base materials 62 and 63 work respectively as external connection terminals 62a and 63a. The second intermediate member 68a is made of a material with lower heat conductivity than the first intermediate member 65, and a contact area with the semiconductor chip 61 is larger in the second intermediate member 68a than in the first intermediate member.
    Type: Grant
    Filed: September 6, 2004
    Date of Patent: August 31, 2010
    Assignee: Panasonic Corporation
    Inventors: Makoto Kitabatake, Osamu Kusumoto, Masao Uchida, Kunimasa Takahashi, Kenya Yamashita
  • Patent number: 7759784
    Abstract: A 3D circuit module which is highly reliable, easily layered and able to mount electronic components in high density is obtained by providing a support member having a frame in the periphery thereof and a recess; a coating layer for coating the frame and filling in the recess, the coating layer being made of resin material which is adhesive and has a softening temperature lower than the softening temperature of the support member; a wiring pattern formed on the coating layer, the wiring pattern including a first land on the frame, a second land on the recess, and a wiring part for connecting between the first land and the second land; and an electronic component having a projecting electrode formed on a side thereof, the electronic component being bonded to the coating layer and accommodated in the recess, with the projecting electrode connected to the second land.
    Type: Grant
    Filed: August 4, 2005
    Date of Patent: July 20, 2010
    Assignee: Panasonic Corporation
    Inventors: Masahiro Ono, Shigeru Kondou, Kazuhiro Nishikawa, Kazuto Nishida
  • Patent number: 7709951
    Abstract: Methods, apparatus and assemblies for enhancing heat transfer in electronic components using a flexible thermal pillow. The flexible thermal pillow has a thermally conductive material sealed between top and bottom conductive layers, with the bottom layer having a flexible reservoir residing on opposing sides of a central portion of the pillow that has a gap. The pillow may have roughened internal surfaces to increase an internal surface area within the pillow for enhanced heat dissipation. In an electronic assembly, the central portion of the pillow resides between a heat sink and heat-generating component for the thermal coupling there-between. During thermal cycling, the flexible reservoir of the pillow expands to retain thermally conductive material extruded from the gap, and then contracts to force such extruded material back into the gap. An external pressure source may contact the pillow for further forcing the extruded thermally conductive material back into the gap.
    Type: Grant
    Filed: March 16, 2007
    Date of Patent: May 4, 2010
    Assignee: International Business Machines Corporation
    Inventors: William L. Brodsky, Peter J. Brofman, James A. Busby, Bruce J. Chamberlin, Scott A. Cummings, David L. Edwards, Thomas J. Fleischman, Michael J. Griffin, IV, Sushumna Iruvanti, David C. Long, Jennifer V. Muncy, Robin A. Susko
  • Patent number: 7705442
    Abstract: A contact device for use with a power semiconductor component in a power semiconductor module or a disc-type thyristor, the module or thyristor having a molded body with a first recess disposed above the component. The contact device makes electrical contact with the auxiliary connection of the component, and is disposed within a second recess in the module or thyristor. The contact device includes a spring having a pin-like extension at a first end thereof that faces the component and a metal molded body that is arranged at the opposite end thereof and has a first connecting device formed as a flat section of the metal molded body. The flat section is arranged generally parallel to the component, and has a second connecting device for connection to a connecting cable. The connecting device may also have a multipart insulating housing for holding the contact spring and the metal molded body.
    Type: Grant
    Filed: July 30, 2007
    Date of Patent: April 27, 2010
    Assignee: SEMIKRON Elektronik GmbH & Co. KG
    Inventor: André Schlötterer