Abstract: A contact device for use with a power semiconductor component in a power semiconductor module or a disc-type thyristor, the module or thyristor having a molded body with a first recess disposed above the component. The contact device makes electrical contact with the auxiliary connection of the component, and is disposed within a second recess in the module or thyristor. The contact device includes a spring having a pin-like extension at a first end thereof that faces the component and a metal molded body that is arranged at the opposite end thereof and has a first connecting device formed as a flat section of the metal molded body. The flat section is arranged generally parallel to the component, and has a second connecting device for connection to a connecting cable. The connecting device may also have a multipart insulating housing for holding the contact spring and the metal molded body.

Abstract: A semiconductor apparatus having improved thermal fatigue life is provided by lowering maximum temperature on jointing members and reducing temperature change. A jointing member is placed between a semiconductor chip and a lead electrode, and a thermal stress relaxation body is arranged between the chip and a support electrode. Jointing members are placed between the thermal stress relaxation body and the chip and between the thermal stress relaxation body and the support electrode. A second thermal stress relaxation body made from a material having a thermal expansion coefficient between the coefficients of the chip and the lead electrode is located between the chip and the lead electrode. The first thermal stress relaxation body is made from a material which has a thermal expansion coefficient in between the coefficients of the chip and the support electrode, and has a thermal conductivity of 50 to 300 W/(m·° C.).

Abstract: A microelectronic device includes a die having an active surface and a non-active surface. To assemble the microelectronic device, the active surface of the die is placed on a substrate. A first material is dispensed between the active surface of the die and the substrate. A second material is dispensed on at least a portion of the non-active surface of the die. The second material is different than the first material and the first material and the second material are simultaneously cured.

Abstract: The present invention relates to a process for preparing a robust crack-absorbing integrated circuit chip comprising a crack trapping structure containing two metal plates and a via-bar structure sandwiched between said plates.

Abstract: A semiconductor device includes: a semiconductor substrate having an active surface and a back surface; an integrated circuit formed on the active surface; a feedthrough electrode penetrating the semiconductor substrate, and projecting from the active surface and the back surface; a first resin layer formed on the active surface, having a thickness greater than a height of a portion of the feedthrough electrode that projects from the active surface, and having an opening portion for exposing at least a portion of the feedthrough electrode; a wiring layer which is formed on the first resin layer, and which is connected to the feedthrough electrode through the opening portion; and an external connecting terminal connected to the wiring layer.

Abstract: A semiconductor device includes: a substrate; a semiconductor element mounted on the substrate; a sealing structure for sealing the semiconductor element, the sealing structure being mounted on the substrate; and an adhesive for bonding the sealing structure and the substrate, wherein the sealing structure has a groove for storing the adhesive.

Abstract: A rectify element as a semiconductor device has a disk section, a first solder part, a buffer plate, a second solder part, a semiconductor chip, and a lead, and a sealing member with which the semiconductor chip is sealed. A cylindrical concave part is formed at one end surface of the disk section. A side wall of the cylindrical concave part faced to an inner peripheral wall at the upper surface of the disk section has a sloped shape of an angle of more than 90° to a contact surface of the upper surface of the disk section on which the semiconductor chip is placed.

Abstract: Microelectronic imagers with curved image sensors and methods for manufacturing curved image sensors. In one embodiment, a microelectronic imager device includes an imager die having a substrate, a curved microelectronic image sensor having a face with a convex and/or concave portion at one side of the substrate, and integrated circuitry in the substrate operatively coupled to the image sensor. The imager die can further include external contacts electrically coupled to the integrated circuitry and a cover over the curved image sensor.

Abstract: The pesent invention discloses a memory module and a signal line arrangement method thereof. The memory module includes memory chips mounted on both sidees in a mirror form; and a printed circuit board (PCB) having same signal applying contact pads arranged on both sodes which same signal applying balls of the memory chips contact in the mirror form, wherein a via is formed at a location close to the same signal applying contact pad of one side among the same signal applying contact pads arranged on both sides in the mirror form, the via connecting the other side to the signal line of one side, and a signal transmitted from the other side is connected to a contact junction, the contact junction is connected to the same signal applying contact pad of the other side, the contact junction is connected to the via of the other side, and the via of one side is connected to the same signal applying contact pad of one side.

Abstract: In a multilayer printed wiring board having a plurality of laminated resin layers, a plurality of wiring patterns formed on the interfacial surface of the resin layers, and a plurality of lands formed on the outermost layer of the resin layers and on which the solder is provided, at least one of the wiring patterns has a plurality of openings in the form of a mesh, the size of openings of the wiring patterns in a region corresponding to the position of solder in which a stress generated in the solder provided on the lands becomes a value larger than a desired value due to thermal deformation of the semiconductor device and the multilayer printed wiring board is larger than that of openings in the other regions.

Abstract: A semiconductor chip includes: a semiconductor substrate; a penetrating electrode which is formed through the semiconductor substrate from a first surface to a second surface of the semiconductor substrate and has a projection which projects from the second surface; an insulating layer formed over an entire surface of the second surface. The insulating layer includes a first insulating section formed in a region around the projection and a second insulating section other than the first insulating section. The second insulating section is formed to be thinner than a thickest area of the first insulating section.

Abstract: Disclosed are a semiconductor device, a method for manufacturing the same, and a method for mounting the same.

Abstract: A novel micro optical system as a platform technology for electrical and optical interconnections, thermal and mechanical assembly and integration of electronic, optoelectronic, passive and active components. This platform provides optical coupling and chip-to-chip interconnection by microwave electrical, optical guided and unguided waves, and power or bias electrical contacts or interfaces by a novel chip in flexible circuit, rigid or inflexible embodiments.

Abstract: A semiconductor component includes a plastic housing including: plastic outer surfaces; lower outer contact surfaces arranged on an underside of the housing; upper outer contact surfaces arranged on a top side of the housing that is opposite the underside; and outer interconnects electrically connecting the lower outer contact surfaces to the upper outer contact surfaces, the outer interconnects including a layer of solder arranged on conduction paths along an outer contour of the housing.

Abstract: An integrated circuit package system is provided including forming a mounting structure having an external interconnect, a paddle, and a tie bar; mounting an integrated circuit die on the paddle; soldering a stiffener structure; having an opening; on the mounting structure; connecting the stiffener structure to a ground; and molding the integrated circuit die and partially the stiffener structure through the opening.

Abstract: A multilayer wiring board assembly component comprises: an insulating substrate component (the insulating resin layer 111); a conductive layer 112 formed on one surface of said insulating substrate component 111 in the form of an electrode pattern; an adhesive layer 113 formed on the other surface of said insulating substrate component 111; and a conductive resin composition 115 with which is filled a through hole passing through said insulating substrate component 111, said adhesive layer and said conductive layer in order to make interlayer interconnection. The bore diameter of the conductive layer portion 114b of the through hole 114 is smaller than the bore diameter of the insulating resin layer portion and the adhesive layer portion 114a to establish electrical connection between the conductive resin composition 115 and the conductive layer 112 by the rare surface 112a of the conductive layer 112.

Abstract: A electronic circuit device is provided with an electronic component provided with an electrode, a substrate having an upper surface on which the electronic component is mounted, external electrode that is formed near the electronic component mounted on the upper surface of the substrate and that is connected to the electrode, an insulating protrusion that is provided across the upper surface of the external electrode, and a sealing resin that seals the electronic component without covering the external electrode. The upper surface of the external electrode is partitioned by the protrusion into a first area that is located on the sealing resin side and a second area that is located the side opposite to the first area. The adherence of fine particles such as flakes of the sealing resin to the external electrode is suppressed, so that a stable electric connection between the external electrode and the electric equipment can be maintained.

Abstract: A chip size package semiconductor device can have reliable solder mounting and improved mounting reliability. A semiconductor device of one embodiment can include a semiconductor chip (1) mounted to a bottom portion (11) of a metal base (10A). A metal base (10A) can have side portions (12) with connection electrodes (15A) having a surface level higher than that of electrodes (7 and 8) on a surface of the semiconductor chip (1) by a difference (d). The connection electrode (15A) can be formed on a projecting piece (16) that is bent outward away from remaining portions of the side portion (12). The semiconductor device can be mounted face down without abutting the semiconductor chip (1) against a mounting substrate, thereby preventing mechanical damage to a semiconductor chip (1). At the same time, a solder layer can be formed in the gap between electrodes (7 and 8) and the mounting substrate, thereby raising the reliability of the soldering connection.

Abstract: First alignment marks are provided on a film substrate in a manner that they are located at positions offset from the disposed positions of second alignment marks provided on a semiconductor chip. The amount of expansion or contraction of the film substrate is obtained by measuring the distance between the first alignment marks. Based on the amount of expansion or contraction, the semiconductor chip is shifted with respect to the film substrate and mounted thereon.

Abstract: Provided is a semiconductor device which prevents displacement of a semiconductor element and a wiring pattern of a wiring substrate so as to ensure the connection of the semiconductor element and the wiring pattern. The semiconductor device of the present invention includes a semiconductor element and a wiring substrate which is provided with a film substrate and a wiring pattern which is formed on the film substrate, the semiconductor element is connected to the wiring pattern, and the semiconductor element and the wiring substrate are sealed with a resin. A metallic film, made of material having a smaller coefficient of linear thermal expansion than the film substrate, is formed in a region where the wiring pattern is not formed on at least one surface of the film substrate.

Abstract: In a wiring substrate of the present invention in which a bump of an electronic parts is bonded to a connection pad of a wiring pattern provided on an insulating film by an ultrasonic flip-chip packaging, a via hole into which a via post acting as a strut to support the connection pad upon the ultrasonic flip-chip packaging is filled is arranged in the insulating film under the connection pad.

Abstract: To provide an electro-optical device having a buffer layer which planarizes a gas barrier layer so that stress-concentration in the gas barrier layer is reduced, the buffer layer being prevented from leaking out of a predetermined area, and to provide a method of producing the same and an electronic apparatus. In an electro-optical device 1 having, on a substrate 200, a plurality of first electrodes 23, a bank structure 221 having a plurality of openings 221a positioned correspondingly to the formed first electrodes, electro-optical layers 60 arranged in the respective openings 221a, and a second electrode 50 covering the bank structure 221 and the electro-optical layers 60, the device includes a buffer layer 210 formed so as to cover the second electrode 50 and have a substantially flat upper surface, a frame 215 made of a material having no affinity to the buffer layer 210 and surrounding the periphery of the buffer layer 210, and a gas barrier layer 30 covering the buffer layer 210 and the frame 215.

Abstract: Structures and techniques for mounting semiconductor dies are disclosed. In one embodiment, the invention includes a stack of printed wiring board assemblies that are connected via interconnection components. At least one of the printed wiring board assemblies includes an interposer substrate having a constraining layer that includes carbon.

Abstract: A wafer level semiconductor package with a build-up layer is provided, which includes a glass frame having a through hole for receiving a semiconductor chip therein, a low-modulus buffer material filled within the space formed between the semiconductor chip and the glass frame, a build-up layer formed on the glass frame and the semiconductor chip such that the build-up layer is electrically connected to the semiconductor chip, and a plurality of conductive elements mounted on the build-up layer so that the semiconductor chip is electrically connected to external devices. With the use of the glass frame and low-modulus buffer material, the wafer level semiconductor package thus-obtained is free from warpage, chip-crack, and delamination problems and the reliability thereof is enhanced. A method for fabricating the wafer level semiconductor package is also provided.

Abstract: Provided are a flexible film package module and a method of manufacturing the same that can be adapted for manufacture at lower cost and/or to adapt the characteristics of the flexible film package module for specific applications. The lower-cost flexible film package module includes a tape film that combines both a first insulating substrate, typically formed from a higher-cost polyimide material, and a second insulating substrate, typically formed from an insulating material or materials that are less expensive and/or provide modified performance when compared with the first insulating material. Both the first and second substrates will include complementary circuit patterns that will be electrically and physically connected to allow the composite substrate to function as a unitary substrate. The first and second substrates will also include connection regions that may be adapted for connection to printed circuit boards and/or electronic devices such as liquid crystal displays.

Abstract: A semiconductor device comprises a semi-conductor chip bonded on a top surface inside a case electrode by a bonding material and a lead electrode bonded on a top surface of the semiconductor chip by a bonding material with a space of the case electrode filled with an insulating material for sealing the bonded sections, wherein a groove is provided on a top surface of the case electrode from an edge of the semiconductor chip, to thereby reduce heat distortion which is generated on a large scale at an end of the bonding material on account of a difference in coefficients of linear thermal expansion between the semiconductor chip and the case electrode and improve the thermal fatigue life.

Abstract: A packaged semiconductor device structure comprises a semiconductor chip (20) having a bump electrode (5), a facing substrate (9) having on one face thereof a facing electrode (8) contacting an end face of the bump electrode (5) and a bonding agent (7) filled in between the semiconductor chip (20) and the facing substrate (9). The bump electrode (5) is of a double layer structure composed of a core part (5b) and a convex-shaped electrode end part (5a) fabricated above the core part (5b) separately from the core part.

Abstract: Disclosed is a rectifier diode device. The rectifier diode device includes a conductive base, a semiconductor chip, a conductive lead and insulation resin. A trench and a post are formed in the conductive base in order to increase a bonding surface between the conductive base and the insulating resin and to lengthen a humidity transfer path for the semiconductor chip. Due to the trench and the post, the bonding surface between the conductive base and the insulating resin increases and the humidity transfer path for the semiconductor chip lengthens, thereby improving heat emission performance of the rectifier diode device. A plurality of prismatic protrusions is formed at an outer peripheral wall of the conductive wire so that coupling force between the conductive wire and an external device is improved. A protrusion ring is provided at a lower surface of the conductive wire so that stress applied to the semiconductor chip is minimized when the rectifier diode device is press-fitted into the external device.

Abstract: A rectification chip terminal structure for soldering a rectification chip encased in a glass passivated pallet (GPP) on a terminal filled with a packaging material to form a secured mounting for the rectification chip is to be inserted in a coupling bore of a circuit board. The structure includes a conductive element which has a buffer portion and a base seat to prevent the GPP from fracturing when the packaging material is heated and expanded or prevent the conductive element from bending and deforming under external forces, and has a stress buffer zone to prevent the chip from being damaged and moisture from entering. It can prevent the GPP from fracturing when the packaging material is heated and expanded and be installed easily in the coupling bore of the circuit board and hold the packaging material securely without breaking away.

Abstract: An interconnect substrate including a first substrate on which a first interconnect pattern is formed, having a mounting region for an electronic chip; and a second substrate on which a second interconnect pattern electrically connected to the first interconnect pattern is formed. The second substrate includes a region to which at least a part of the first substrate is adhered, and a mounting region for an electronic chip.

Abstract: An integrated circuit package includes a lid with EMI containment features. The lid may include a plurality of projections adapted to couple a ground plane of a circuit board.

Abstract: A semiconductor device, a microelectromechanical system package and a method of making the same utilize high performance vias for vertical IC packaging. A semiconductor die of the device/package has a substrate with integrated circuitry formed on a front side of the substrate. A metal bonding pad overlies the substrate on the front side of the substrate and is electrically connected to the integrated circuitry. A solder bump is located on the metal bonding pad. An electrically conductive via extends through the substrate from the metal bonding pad to a back side of the substrate where the via forms a side wall of a via hole. A plurality of the substrates are stacked on one another with the outer end of the solder bump of one substrate fitting within the via hole of an adjacent substrate. During reflow soldering, surface tension forces of the molten solder bump self-align the substrates.

Abstract: A chip size package semiconductor device can have reliable solder mounting and improved mounting reliability. A semiconductor device (10) of one embodiment can include a semiconductor chip (1) mounted to a bottom portion (11) of a metal base (10). A metal base (10) can have side portions (12) with connection electrodes (15) having a surface level higher than that of electrodes (7 and 8) on a surface of the semiconductor chip (1) by a difference (d). The semiconductor device (10) can be mounted face down without abutting the semiconductor chip (1) against a mounting substrate, thereby preventing mechanical damage to a semiconductor chip (1). At the same time, a solder layer can be formed in the gap between electrodes (7 and 8) and the mounting substrate, thereby raising the reliability of the soldering connection.

Abstract: A chip size package semiconductor device can have reliable solder mounting and improved mounting reliability. A semiconductor device (10) of one embodiment can include a semiconductor chip (1) mounted to a bottom portion (11) of a metal base (10). A metal base (10) can have side portions (12) with connection electrodes (15) having a surface level higher than that of electrodes (7 and 8) on a surface of the semiconductor chip (1) by a difference (d). The semiconductor device (10) can be mounted face down without abutting the semiconductor chip (1) against a mounting substrate, thereby preventing mechanical damage to a semiconductor chip (1). At the same time, a solder layer can be formed in the gap between electrodes (7 and 8) and the mounting substrate, thereby raising the reliability of the soldering connection.

Abstract: A semiconductor device including a substrate (10). An interconnect pattern (12) is formed over the substrate (10), and the substrate (10) has a first portion (14) and a second portion (16) to be superposed on the first portion (14). The first portion (14) has edges (22), (24), (26) and (28) as positioning references. The second portion (16) has a shape to be superposed over the first portion (14) except the edges (22), (24), (26) and (28).

Abstract: A small footprint package for two or more semiconductor die includes first and second die, mounted on opposite respective surfaces of a lead frame pad in vertical alignment with one another. A conductive or insulation adhesive can be used. The die can be identical MOSgated devices connected in series, or can be one power die and a second IC die for the control of the power die.

Abstract: A chip size package semiconductor device can have reliable solder mounting and improved mounting reliability. A semiconductor device (10) of one embodiment can include a semiconductor chip (1) mounted to a bottom portion (11) of a metal base (10). A metal base (10) can have side portions (12) with connection electrodes (15) having a surface level higher than that of electrodes (7 and 8) on a surface of the semiconductor chip (1) by a difference (d). The semiconductor device (10) can be mounted face down without abutting the semiconductor chip (1) against a mounting substrate, thereby preventing mechanical damage to a semiconductor chip (1). At the same time, a solder layer can be formed in the gap between electrodes (7 and 8) and the mounting substrate, thereby raising the reliability of the soldering connection.

Abstract: The present invention provides flip-chip packaging for optically interactive devices such as image sensors and methods of assembly. In a first embodiment of the invention, conductive traces are formed directly on the second surface of a transparent substrate and an image sensor chip is bonded to the conductive traces. Discrete conductive elements are attached to the conductive traces and extend below a back surface of the image sensor chip. In a second embodiment, a secondary substrate having conductive traces formed thereon is secured to the transparent substrate. In a third embodiment, a backing cap having a full array of attachment pads is attached to the transparent substrate of the first embodiment or the secondary substrate of the second embodiment. In a fourth embodiment, the secondary substrate is a flex circuit having a mounting portion secured to the second surface of the transparent substrate and a backing portion bent over adjacent to the back surface of the image sensor chip.

Abstract: A method and structure for isolating a die from thermally induced or pressure induced differential stresses between a die and a package includes providing an intermediate layer having therein a plurality of relief channels arranged to provide a flexure for absorbing such differential stresses. The relief channels define interior and peripheral portions of the intermediate layer, and the die is typically mounted on the interior portion. The peripheral portion of the intermediate layer is then bonded to the package. The channels may be disposed along both the upper and lower surfaces of the intermediate layer, or may be disposed on only one surface. Likewise, the channels may be disposed along one or both of the length and width of the upper or lower surfaces. Reservoir channels may also be provided to prevent adhesive from flowing and bridging the relief channels.

Abstract: A plurality of electronic circuits and associated signal lines are positioned at respective locations on a base wafer. A cover wafer, which fits over the base wafer, includes a corresponding like number of locations each including one or more cavities to accommodate the electronic circuit and associated signal lines. The cover wafer includes a plurality of vias for making electrical connection to the signal lines. A multi layer metallic arrangement hermetically seals the periphery of each location as well as sealing the bottom of each via. The joined base and cover wafers may then be diced to form individual die packages.

Abstract: A semiconductor chip includes: a semiconductor substrate; a penetrating electrode which is formed through the semiconductor substrate from a first surface to a second surface of the semiconductor substrate and has a projection which projects from the second surface; an insulating layer formed over an entire surface of the second surface. The insulating layer includes a first insulating section formed in a region around the projection and a second insulating section other than the first insulating section. The second insulating section is formed to be thinner than a thickest area of the first insulating section.

Abstract: In a semiconductor device including a semiconductor wafer having a main surface where a circuit element is formed, electrode pads are formed at an upper portion of the main surface of the semiconductor wafer as electrically connected with the circuit element. A sealing resin seals the upper portion of the main surface of the semiconductor wafer, and external connection terminals are formed at the upper portion of the main surface so as to project out from the surface of the sealing resin and are arrayed in a substantially regular pattern over specific intervals from one another. At least one of the external connection terminals has a shape different from the shape of the other external connection terminals. The shape of the external connection terminal is used as an index mark, so that the index mark forming process is simplified and the index mark does not come off.

Abstract: A resin-sealed semiconductor device includes a metallic plate and a semiconductor element soldered thereto. The metallic plate has a semiconductor element mounting region formed on one surface thereof and a plurality of squared recesses defined lengthwise and crosswise in the one surface at approximately regular intervals at locations other than the semiconductor element mounting region.

Abstract: The present invention relates to apparatus and methods for providing a low resistance power supply to a microelectronic package through the use of dual conductive paths. A first conductive path contained within the substrate and supplies current, primarily in responding to transient current demands to the microelectronic package. A lower resistance second conductive path supplies primarily steady state current to the microelectronic package through an electrical connection to an edge of the microelectronic package. Resistance in the second conductive path is reduced by using a power clamp to connect the second power supply to the microelectronic package.

Abstract: A semiconductor device arrangement includes a plurality of three-dimensional semiconductor units. Each of the three-dimensional semiconductor units includes a semiconductor chip in a shape of a rectangular parallelepiped having six surfaces, and semiconductor devices formed on at least one among the six surfaces. The three-dimensional semiconductor units are mechanically connected and supported, and are electrically connected in a suitable way.

Abstract: A semiconductor device has a semiconductor element housed in a ceramic cylinder as an insulated vessel, and plural gate terminals. Plural through-holes are formed in the ceramic cylinder. Leads connected to gate terminals pass through their respective through-holes. The leads are connected to internal gate terminals (electrodes). Each internal gate terminal is provided for each lead and connected electrically to a gate electrode of the semiconductor element.

Abstract: A circuit component package of the present invention includes a mounting member including a substrate and a wiring pattern provided on the substrate, a circuit component including a component body and an external electrode provided at an end of the component body, the circuit component being arranged on the mounting member, and a conductive material that electrically connects the external electrode with the wiring pattern. In the circuit component, the component body is shaped so that a first portion of the component body on which the external electrode is provided is thinner than a second portion of the component body, the second portion being a portion on which the external electrode is not provided, and further, the external electrode is arranged in a region on a side on which the component body is positioned with respect to a reference plane containing a predetermined surface of the component body.

Abstract: The present invention is provides an LSI package without employing steps for forming solder bumps on a bare chip and soldering to an interposer. In the present invention, a bare chip is mounted on the LSI package by forming wiring patterns which connect to bare chip I/O terminals in a build-up layer of a substrate. Furthermore, the wiring patterns are formed so as to connect outer I/O terminals on the substrate.

Abstract: In order to keep the mounting outlay for shielding measures as low as possible, a semiconductor device having a semiconductor component in a housing element is proposed. At least one capacitive element having a first electrode, a second electrode and a dielectric is provided in an integrated manner in the housing element or in the region thereof. The electrode regions of the capacitive element are electrically contact-connected to terminal regions of the semiconductor component, in such a way that high-frequency interference signals between terminal regions can be suppressed.

Abstract: A semiconductor device has first and second substrates (10, 20) disposed so as to be overlaid, and a semiconductor chip (30) mounted on each of the first and second substrates (10, 20). A first interconnect pattern (12) formed on the first substrate (10) has bent portions (16) which project from the surface of the first substrate (10). The bent portions (16) are bonded to a flat portion (26) of a second interconnect pattern (22) formed on the second substrate (20).