For High Frequency (e.g., Microwave) Device Patents (Class 257/728)
  • Patent number: 11380635
    Abstract: A semiconductor device may include a substrate, a first semiconductor chip buried in the substrate, a first antenna pattern, a second antenna pattern, and outer terminals. A bottom surface of the substrate may include first and second regions spaced apart from each other. The first semiconductor chip may have a first active surface that is directed to the top surface of a core portion of the substrate. The first antenna pattern may be provided on the top surface of the substrate and electrically connected to the first semiconductor chip. The outer terminals may be provided on the first region of the bottom surface of the substrate, and the second antenna pattern may be provided on the second region of the bottom surface of the substrate.
    Type: Grant
    Filed: December 15, 2020
    Date of Patent: July 5, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Se-Ho You, Seongho Shin, Bangweon Lee
  • Patent number: 11382207
    Abstract: An electronic device module may include: a board; a ground electrode disposed on a first surface of the board; a sealing portion disposed on the first surface of the board; electronic devices mounted on the first surface of the board such that at least one of the electronic devices is embedded in the sealing portion; a first shielding wall connected to the ground electrode and disposed along a side surface of the sealing portion; and a shielding layer formed of a conductive material and disposed along a surface formed by the sealing portion and the first shielding wall.
    Type: Grant
    Filed: September 16, 2020
    Date of Patent: July 5, 2022
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventor: Kyung Ho Han
  • Patent number: 11362634
    Abstract: A filter module includes a first ground terminal, a second ground terminal, a low pass filter, and a second inductor. The low pass filter includes a first inductor provided in an input/output path of signal, a first capacitor provided in a first path connecting a first node and the first ground terminal, and a second capacitor provided in a second path connecting a second node and the second ground terminal. The second inductor is connected in series to the second capacitor in a path connecting the second capacitor and the second ground terminal. The first path and the second path are not connected to each other by any path except the one between the first node and the second node.
    Type: Grant
    Filed: July 31, 2020
    Date of Patent: June 14, 2022
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Hisanori Murase, Naru Morito, Hiromichi Kitajima, Ryangsu Kim, Yasushi Shigeno, Kenta Seki
  • Patent number: 11336032
    Abstract: Methods and apparatus for providing a radiator having an antenna comprising a patch antenna layer and a first ground plane layer, wherein the antenna has a reactive field region of the radiator between the patch antenna layer and the first ground plane layer, and an integrated circuit located in the active region.
    Type: Grant
    Filed: May 15, 2020
    Date of Patent: May 17, 2022
    Assignee: Raytheon Company
    Inventors: Thomas V. Sikina, John P. Haven, Channing P. Favreau
  • Patent number: 11328987
    Abstract: A wafer-level packaging based module includes an antenna board and a chip board. The antenna board includes at least one antenna layer with introduced antenna element and a shielding layer with introduced shielding element in the area of the at least one antenna element opposite to the antenna layer. The chip board includes a contacting layer, a rewiring layer opposite to the contacting layer and the shielding layer having at least one shielding element arranged on the rewiring layer. A chip layer having at least one chip is arranged between the contacting layer and the rewiring layer. Further, the chip layer includes at least one via connecting the contacting layer to the rewiring layer.
    Type: Grant
    Filed: November 26, 2019
    Date of Patent: May 10, 2022
    Assignee: Fraunhofer-Gesellschaft zur Foerderung der angewandten Forschung e.V.
    Inventors: Ivan Ndip, Tanja Braun, Klaus-Dieter Lang
  • Patent number: 11264341
    Abstract: Provided is a microwave integrated circuit including: a semiconductor substrate; a plurality of amplification units that are formed in the semiconductor substrate; a wiring that is formed in one layer wiring excluding an uppermost layer wiring and a lowermost layer wiring among a plurality of layer wirings formed on the semiconductor substrate and is used for supplying power to the plurality of amplification units; and a plurality of vias that connect a plurality of conductive regions formed in the layer wiring with the wiring interposed therebetween and other conductive regions formed in a region interposing the wiring in the two layer wirings immediately above and immediately below the layer wiring, in which each of the plurality of vias forms a via structure connected to the conductive regions of the lowermost layer wiring by a plurality of other vias.
    Type: Grant
    Filed: March 11, 2020
    Date of Patent: March 1, 2022
    Assignee: SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.
    Inventor: Kenshi Naito
  • Patent number: 11256049
    Abstract: An apparatus includes a dielectric support substrate with one or more planar major surfaces and one or more optical fiber interfaces fixed to the support substrate adjacent one of the one or more planar major surfaces. Each optical fiber interface has optical modulators and photodetectors. The apparatus also includes one or more digital signal processing chips fixed to the support substrate adjacent one of the one or more planar major surfaces, and laterally separated from and communicatively connected via metallic lines to the one or more optical fiber interfaces. The apparatus also includes a first set of one or more metallic heatsinks adjacent the one or more digital signal processing chips to provide heat dissipation therefrom. The apparatus also includes a second set of one or more metallic heatsinks being located adjacent the one or more optical fiber interfaces to provide heat dissipation therefrom and physically separated by a distance from the one or more metallic heatsinks of the first set.
    Type: Grant
    Filed: April 22, 2020
    Date of Patent: February 22, 2022
    Assignee: Nokia Solutions and Networks Oy
    Inventor: William dos Santos Fegadolli
  • Patent number: 11257762
    Abstract: The present invention ultra-low loss high energy density dielectric layers having femtosecond (10?15 sec) polarization response times within a chip stack assembly to extend impedance-matched electrical lengths and mitigate ringing within the chip stack to bring the operational clock speed of the stacked system closer to the intrinsic clock speed(s) of the semiconductor die bonded within chip stack.
    Type: Grant
    Filed: November 22, 2019
    Date of Patent: February 22, 2022
    Inventor: L. Pierre de Rochemont
  • Patent number: 11233018
    Abstract: Wireless modules having a semiconductor package attached to an antenna package is disclosed. The semiconductor package may house one or more electronic components as a single die package and/or a system in a package (SiP) implementation. The antenna package may be communicatively coupled to the semiconductor package using by one or more coupling pads. The antenna package may further have one or more radiating elements for transmitting and or receiving wireless signals. The antenna package and the semiconductor package may have dissimilar number of interconnect layers and/or dissimilar materials of construct.
    Type: Grant
    Filed: February 12, 2020
    Date of Patent: January 25, 2022
    Assignee: INTEL CORPORATION
    Inventors: Sidharth Dalmia, Ana M. Yepes, Pouya Talebbeydokhti, Miroslav Baryakh, Omer Asaf
  • Patent number: 11211714
    Abstract: Embodiments herein disclose techniques for apparatuses and methods for making a slot antenna on a PCB with a cutout. A PCB may include a metal layer. The metal layer may include a cavity to be a first radiating element of an antenna, and a slot to be a second radiating element of the antenna. In addition, the cavity may extend to be the cutout of the PCB through other layers of the PCB. The first and second radiating elements may provide a determined transmission frequency for the antenna. The metal layer may further include a portion of a transmission line of the antenna, and the transmission line is in contact with the cavity and the slot. A package may be affixed to the PCB, where a portion of the package may be within the cutout of the PCB. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: November 21, 2017
    Date of Patent: December 28, 2021
    Assignee: Intel Corporation
    Inventors: Eng Huat Goh, Min Suet Lim, Boon Ping Koh, Wil Choon Song, Khang Choong Yong
  • Patent number: 11141062
    Abstract: The invention includes a location tracking device in an RFID environment, a system and method for tracking tag objects. Preferred embodiments include location tracking for livestock and a system and method for categorizing animal health. The location tracking device is an active or passive RFID device having a low power, long range transceiver for tracking the location and movement of the tag animal. The RFID device further includes a temperature reader circuit that induces an activation voltage on an inductive coupled temperature sensor having an LC circuit. The activation voltage is selectively cycled on and off to measure the decay of the LC circuit by its resonant frequency. Changes in capacitance of the LC circuit are converted to temperature readings thereby providing temperature monitoring of the animal. The system and method includes logic in the form of predetermined movement categories which indicate whether an animal may be potentially sick or healthy.
    Type: Grant
    Filed: December 10, 2018
    Date of Patent: October 12, 2021
    Assignee: GEISSLER COMPANIES, LLC
    Inventors: Randolph K. Geissler, Steve A. Lewis
  • Patent number: 11143889
    Abstract: An optical transmission device includes: a substrate; a waveguide that is provided in the substrate and transmits an optical signal; a signal wiring that is provided in the substrate and transmits an electric signal; and a silicon wiring that is provided in the substrate and is silicon added with an impurity. The signal wiring is placed in an area of the substrate, the area being away from an end of the substrate by a predetermined distance or more. One end of the silicon substrate is connected to the signal wiring, and the other end of the silicon wiring extends to the end of the substrate.
    Type: Grant
    Filed: April 14, 2020
    Date of Patent: October 12, 2021
    Assignee: FUJITSU OPTICAL COMPONENTS LIMITED
    Inventor: Masaki Sugiyama
  • Patent number: 11063025
    Abstract: Gates of a plurality of semiconductor switching elements are electrically connected to a common gate control pattern by gate wires. Sources of the plurality of semiconductor switching elements are electrically connected to a common source control pattern by source wires. The gate control pattern is disposed to interpose the source control pattern between the gate control pattern and each of the plurality of semiconductor switching elements that are connected in parallel and that operate in parallel. Hence, each of the gate wires becomes longer than each of the source wires, and has an inductance larger than the source wire. Accordingly, gate oscillation is reduced or suppressed in the plurality of semiconductor switching elements that are connected in parallel and that operate in parallel.
    Type: Grant
    Filed: August 27, 2018
    Date of Patent: July 13, 2021
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Junichi Nakashima, Shota Morisaki, Yoshiko Tamada, Yasushi Nakayama, Tetsu Negishi, Ryo Tsuda, Yukimasa Hayashida, Ryutaro Date
  • Patent number: 11049824
    Abstract: Disclosed is an antenna apparatus including a radiating layer with a plurality of antenna elements forming an antenna array; a semiconductor wafer including multiple tiles each having beamforming circuits; and a multi-layer interposer. The multi-layer interposer may include: a lower dielectric layer adjacent to the substrate; an upper dielectric layer adjacent to the radiating layer; a metal layer between the lower and upper layers and including a plurality of conductive traces; a plurality of first vias extending through both the upper and lower layers and electrically coupling the beamforming circuits to the plurality of antenna elements; and a plurality of second vias extending between the beamforming circuits and the conductive traces to interconnect the tiles.
    Type: Grant
    Filed: October 17, 2019
    Date of Patent: June 29, 2021
    Assignee: VIASAT, INC.
    Inventors: Steven J. Franson, Joseph J. Luna
  • Patent number: 10992055
    Abstract: A component carrier with a base structure, an antenna arrangement, and an electronic component are disclosed. The antenna arrangement has a first antenna element and a second antenna element, wherein both antennas elements are embedded within the base structure. The electronic component is embedded within the base structure and is operatively connected both with the first antenna element and the second antenna element. The electronic component is an active electronic component capable of providing a first transmit signal to the first antenna element and a second transmit signal to the second antenna element and/or processing a first receive signal received from the first antenna element and a second receive signal received from the second antenna element. Further, an electronic apparatus comprising such a component carrier and a manufacturing method for such a component carrier are described.
    Type: Grant
    Filed: April 28, 2017
    Date of Patent: April 27, 2021
    Assignee: AT&S Austria Technologie & Systemtechnik Aktiengesellschaft
    Inventor: Urs Hunziker
  • Patent number: 10944379
    Abstract: An integrated radio frequency (RF) circuit combines complementary features of passive devices and acoustic filters and includes a first die, a second die, and a third die. The first die includes a substrate having one or more passive devices. The second die includes a first acoustic filter. The second die is stacked and coupled to a first surface of the first die. The third die includes a second acoustic filter. The third die is stacked and coupled to a second surface opposite the first surface of the first die.
    Type: Grant
    Filed: December 14, 2016
    Date of Patent: March 9, 2021
    Assignee: Qualcomm Incorporated
    Inventors: David Francis Berdy, Changhan Hobie Yun, Shiqun Gu, Niranjan Sunil Mudakatte, Mario Francisco Velez, Chengjie Zuo, Jonghae Kim
  • Patent number: 10943845
    Abstract: A three-dimensional packaging structure and a packaging method of power devices. The packaging structure includes power devices, direct copper bonded substrates (i.e., DBC substrates), flexible printed circuit boards (i.e., FPC boards), bonding wires, heat dissipation substrates, decoupling capacitors, a heatsink with integrating the fan, shells, and forms a half-bridge circuit structure composed by the power devices. The power circuit structure is optimized, parasitic inductance in the commutation loop is reduced by mutual inductance cancellation, thus overvoltage and oscillation during the power device switching process can be reduced. Additionally, by using the flexible characteristic of the flexible PCB, a three-dimensional packaging structure is formed and power density is improved.
    Type: Grant
    Filed: June 4, 2019
    Date of Patent: March 9, 2021
    Assignee: Huazhong University of Science and Technology
    Inventors: Cai Chen, Zhizhao Huang, Yuxiong Li, Yu Chen, Yong Kang
  • Patent number: 10909338
    Abstract: A radio frequency communication guiding device comprising: a generally elongated body having an elongated cavity therein arranged to house a communication circuit, wherein the communication circuit is supported within the cavity by a substrate layer arranged to place within the cavity so as to support the communication circuit within the cavity.
    Type: Grant
    Filed: March 15, 2017
    Date of Patent: February 2, 2021
    Assignee: Hong Kong R&D Centre for Logistics and Supply Chain Management Enabling Technologies Limited
    Inventors: Chi Lun Mak, Jing Tian Xi
  • Patent number: 10813226
    Abstract: A process for improving the performance of the sliding rheostat of 5G communication high-frequency signal board with the sliding rheostat slides along between two bonding pads, includes the following steps: outer layer etching; resin plugging: a. plugging the resinous ink into the pre-plugging position; b: baking, baking on the baking plate of the oven after the plugging is finished; board polishing: using a ceramic brush to process the plugged board, then using a non-woven fabric blush to polish the surface that is polished by ceramic brush. The present invention provides a process for improving the performance of the sliding rheostat of 5G communication high-frequency signal board. The resin plugging method is used to plug the gap between the conductors of the sliding rheostat, so as to prevent the sliding rheostat from being unable to slide due to the altitude difference between conductors of the high-frequency signal board.
    Type: Grant
    Filed: February 14, 2018
    Date of Patent: October 20, 2020
    Assignee: KUNSHAN TVS ELECTRONIC TECHNOLOGY CO., LTD
    Inventors: Jiting Liu, Qingfeng Liu
  • Patent number: 10777550
    Abstract: A plurality of gate finger electrodes (2) is each arranged in a manner alternately adjacent to a corresponding one of drain electrodes (3) and a corresponding one of source electrode (4). The plurality of gate finger electrodes (2) is each connected to a corresponding one of gate routing lines (6). A resistor (7) has one end separating the gate routing lines (6) on respective two sides at a center portion between the gate routing lines (6), and has another end connected to an input line (10). Capacitors (8) are arranged on the respective two sides with respect to the resistor (7) and each connected to the corresponding gate routing line (6) by a corresponding one of air bridges (9).
    Type: Grant
    Filed: December 16, 2016
    Date of Patent: September 15, 2020
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Yutaro Yamaguchi, Masatake Hangai, Koji Yamanaka
  • Patent number: 10709045
    Abstract: A high frequency module includes an insulating substrate, a mountable element, and a shield conductor. The mountable element is mounted to a surface of the insulating substrate and includes a first mounting terminal. The shield conductor covers the mountable element in a spaced relationship to the mountable element. An exposing portion in which at least the first terminal is exposed is provided in the shield conductor, and a linear distance from the first terminal to the exposing portion is shorter than a linear distance from the first terminal to the shield conductor.
    Type: Grant
    Filed: September 11, 2018
    Date of Patent: July 7, 2020
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Takanori Uejima
  • Patent number: 10665555
    Abstract: A transition structure disposed in a package is disclosed. The transition structure comprises a first ground lead and a second ground lead; and a signal lead, disposed between the first ground lead and the second ground lead, wherein the first ground lead and the second ground lead have an exterior edge and an interior edge, the signal lead is coupled to a metal line formed on a printed circuit board (PCB) and a signal terminal of the die within the package; wherein an exterior gap formed between the first ground lead and the second ground lead at the exterior edge is wider than an interior gap formed between the first ground lead and the second ground lead at the interior edge.
    Type: Grant
    Filed: February 7, 2018
    Date of Patent: May 26, 2020
    Assignee: WIN Semiconductors Corp.
    Inventors: Jui-Chieh Chiu, Chih-Wen Huang, Chen-Yang Hsieh, You-Cheng Lai
  • Patent number: 10629543
    Abstract: A package substrate includes a core layer including a first surface and a second surface, which are opposite to each other. The package substrate also includes a power plane interconnection layer disposed on the first surface of the core layer and a ground plane interconnection layer disposed on the second surface of the core layer. The package substrate additionally includes an electromagnetic (EM) bandgap structure disposed in the core layer and electrically coupled between the power plane interconnection layer and the ground plane interconnection layer. The EM bandgap structure includes an EM bandgap via protruding from a portion of the power plane interconnection layer toward the ground plane interconnection layer. The EM bandgap structure further includes an EM bandgap cylindrical structure extending from a portion of the ground plane interconnection layer toward the power plane interconnection layer and surrounding a side surface of the EM bandgap via.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: April 21, 2020
    Assignee: SK hynix Inc.
    Inventors: Sung Mook Lim, Hye Won Kim, Won Duck Jung
  • Patent number: 10553543
    Abstract: An integrated circuit package is provided. The integrated circuit package comprises a first and second guard bond wire. The first guard bond wire has a first and second end coupled to ground. The second guard bond wire has a first and second end coupled to ground. The integrated circuit package further comprises a die. The die is mounted between the first and second guard bond wires such that the first and second guard bond wires distort a magnetic field between at least an input terminal and an output terminal of the die.
    Type: Grant
    Filed: May 12, 2016
    Date of Patent: February 4, 2020
    Assignee: Ampleon Netherlands B.V.
    Inventors: Vittorio Cuoco, Youri Volkhine, Yi Zhu, Josephus Van Der Zanden, Anna Walesieniuk
  • Patent number: 10553551
    Abstract: A flip chip IC device utilized in RF transceivers includes a bare die having a number of metalized pads and each metalized pad has a solder ball deposited thereon. The flip chip IC device further includes a substrate having a number of connector pads corresponding to the metalized pads. The connector pads are connected to one or more electronic components disposed on the substrate via a number of connector strips. The bare die is flipped up-side-down such that the metalized solder pads are aligned and connected with the connector pads of the substrate via the solder balls. At least one of the connector strips includes a strip section having an uneven strip width configured to compensate an impedance of a transmission line formed based on a connection between a metalized pad of the bare die and a connector pad of the substrate to match predetermined impedance.
    Type: Grant
    Filed: May 8, 2018
    Date of Patent: February 4, 2020
    Assignee: SPEEDLINK TECHNOLOGY INC.
    Inventors: Che-Chun Kuo, Taiyun Chi, Thomas Chen
  • Patent number: 10546839
    Abstract: An electronic apparatus includes a wiring board including a main surface on which a first wiring and a second wiring are formed, a first semiconductor device mounted on the main surface of the wiring board, and a second semiconductor device mounted on the main surface of the wiring board. Each of the first semiconductor device and the second semiconductor device includes a first semiconductor chip including an insulated gate bipolar transistor, a second semiconductor chip including a diode, a first lead electrically connected to an emitter electrode pad formed on a first front surface of the first semiconductor chip, a second lead electrically connected to an anode electrode pad formed on a second front surface of the second semiconductor chip, and a first terminal electrically connected to a collector electrode formed on a first back surface of the first semiconductor chip.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: January 28, 2020
    Assignee: RENESAS ELECTRONIC CORPORATION
    Inventors: Akira Muto, Norio Kido
  • Patent number: 10490896
    Abstract: Disclosures of the present invention describe an antenna device by forming a HF conductive section, a ground electrode, two first LF conductive sections, two first bending conductive sections, two second LF conductive sections, and a second bending conductive section on one surface of a substrate as well as disposing a cover electrode on the other surface of the same substrate. The HF conductive section is designed to have an area extending portion for making a horizontal electrical coupling occur between the area extending portion and the two LF conductive sections. Moreover, the cover electrode covers a portion of the second bending conductive section, all of the ground electrode, a portion of the signal inputting portion, and a portion of the two LF conductive sections, such that a vertical electrical coupling is achieved for enhancing the efficiency of the antenna device during the transmission of LF signal.
    Type: Grant
    Filed: August 13, 2018
    Date of Patent: November 26, 2019
    Assignee: LANNER ELECTRONIC INC.
    Inventor: Jung-Tai Wu
  • Patent number: 10468763
    Abstract: An antenna that is formed of a conductor pattern is disposed on a dielectric substrate. A high-frequency semiconductor device that supplies a high-frequency signal to the antenna is mounted on the bottom surface of the dielectric substrate. A plurality of conductor columns project from the bottom surface. The conductor columns are embedded in a dielectric member that is disposed on the bottom surface. An end of each of the conductor columns is exposed through the dielectric member. The dielectric member defines a mounting surface that faces a mounting substrate. A step is formed in a side surface of a composite structure that includes the dielectric substrate and the dielectric member, and a side surface extending from the mounting surface to the step is more recessed than a side surface that is located above the step.
    Type: Grant
    Filed: April 27, 2017
    Date of Patent: November 5, 2019
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Michiharu Yokoyama, Nobumitsu Amachi
  • Patent number: 10431882
    Abstract: An antenna that is formed of a conductor pattern is disposed on a dielectric substrate. A high-frequency semiconductor device that supplies a high-frequency signal to the antenna is mounted on the bottom surface of the dielectric substrate. A plurality of conductor columns project from the bottom surface. The conductor columns are embedded in a dielectric member that is disposed on the bottom surface. An end of each of the conductor columns is exposed through the dielectric member. The dielectric member defines a mounting surface that faces a mounting substrate. A step is formed in a side surface of a composite structure that includes the dielectric substrate and the dielectric member, and a side surface extending from the mounting surface to the step is more recessed than a side surface that is located above the step.
    Type: Grant
    Filed: April 27, 2017
    Date of Patent: October 1, 2019
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Michiharu Yokoyama, Nobumitsu Amachi
  • Patent number: 10312592
    Abstract: A manufacturing method of a coil component including the steps of: holding a plurality of semi-finished products, each of which includes a base and a coil before forming the coil component, with a jig having a holding portion; setting the plurality of semi-finished products held by the jig to the setting positions of the jig in a mold; and sealing at least a portion within the base and the coil with resin by filling the resin into a cavity of the mold.
    Type: Grant
    Filed: March 29, 2016
    Date of Patent: June 4, 2019
    Assignee: Sumida Corporation
    Inventors: Yasunori Morimoto, Yasuo Shimanuki, Keiji Oyagi, Masakazu Fukuoka
  • Patent number: 10303225
    Abstract: Methods/structures of forming package structures are described. Those methods/structures may include a conductive pin comprising: a cantilever beam portion physically coupled with a first side of a package substrate; a contact pin portion, wherein a terminal end of the contact pin portion is physically and electrically coupled to a board; a housing structure comprising a housing cavity, wherein the contact pin portion is disposed at least partially within the housing cavity; and a conductive material disposed on housing sides and/or adjacent a surface of the housing cavity. The placement of the conductive material is optimized to meet the requirements for either double data rate (DDR) and/or peripheral component interface express (PCIe) interfaces.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: May 28, 2019
    Assignee: Intel Corporation
    Inventors: Kemal Aygun, Zhichao Zhang, Cemil Geyik, Guneet Kaur
  • Patent number: 10305189
    Abstract: A circuit element mounting portion provided on a dielectric substrate is configured so as to mount a high-frequency integrated circuit element, and includes a ground land and a plurality of high-frequency signal lands. The dielectric substrate is provided with an antenna element including at least one radiation element. The dielectric substrate is provided with an exposed terminal portion including an exposed ground land and an exposed high-frequency signal land. The dielectric substrate is provided with a first transmission line connecting one high-frequency signal land of the circuit element mounting portion and the radiation element. Furthermore, a second transmission line connecting another high-frequency signal land of the circuit element mounting portion and the high-frequency signal land of the exposed terminal portion, and a ground conductor connecting the ground land of the circuit element mounting portion and the ground land of the exposed terminal portion are provided.
    Type: Grant
    Filed: August 24, 2017
    Date of Patent: May 28, 2019
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Hideki Ueda
  • Patent number: 10217727
    Abstract: For example, a semiconductor device capable of achieving a high performance applicable to an SR motor is provided. The semiconductor device includes a chip mounting portion TAB1 on which a semiconductor chip CHP1 having an IGBT is mounted, and a chip mounting portion TAB2 on which a semiconductor chip CHP2 having a diode is formed. The semiconductor device also includes a lead LD1A electrically connected to an emitter electrode pad EP of the semiconductor chip CHP1 via a clip CLP1, and a lead LD1B electrically connected to an anode electrode pad ADP of the semiconductor chip CHP2 via a clip CLP2. At this time, the chip mounting portion TAB1 is separated electrically from the chip mounting portion TAB2, and the clip CLP1 is separated electrically from the clip CLP2.
    Type: Grant
    Filed: August 25, 2014
    Date of Patent: February 26, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Akira Muto, Norio Kido
  • Patent number: 10204858
    Abstract: A semiconductor device having a plurality of first wirings (X-direction) which include a first power supply line and a second power supply line, a plurality of third wirings (X-direction) which include a third (fourth) power supply line that is located above the first (second) power supply line and is electrically connected to the first (second) power supply line. The semiconductor device also has a plurality of second wirings (Y-direction) that include a first (second) connection wiring located above the first (second) power supply line and below the third (fourth) power supply line that is electrically connected to the first (second) power supply line and to the third (fourth) power supply line.
    Type: Grant
    Filed: October 17, 2017
    Date of Patent: February 12, 2019
    Assignee: SOCIONEXT INC.
    Inventor: Tomoyuki Kirimura
  • Patent number: 10189702
    Abstract: A semiconductor device has a first semiconductor die and a modular interconnect structure adjacent to the first semiconductor die. An encapsulant is deposited over the first semiconductor die and modular interconnect structure as a reconstituted panel. An interconnect structure is formed over the first semiconductor die and modular interconnect structure. An active area of the first semiconductor die remains devoid of the interconnect structure. A second semiconductor die is mounted over the first semiconductor die with an active surface of the second semiconductor die oriented toward an active surface of the first semiconductor die. The reconstituted panel is singulated before or after mounting the second semiconductor die. The first or second semiconductor die includes a microelectromechanical system (MEMS). The second semiconductor die includes an encapsulant and an interconnect structure formed over the second semiconductor die.
    Type: Grant
    Filed: November 28, 2016
    Date of Patent: January 29, 2019
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: Yaojian Lin, Won Kyoung Choi, Kang Chen, Ivan Micallef
  • Patent number: 10153245
    Abstract: Provided is a semiconductor device which can be prevented from increasing in size. The semiconductor device includes a semiconductor chip having a first main surface and a second main surface opposite to the first main surface and a wiring substrate over which the semiconductor chip is mounted such that the second main surface of the semiconductor chip faces a first main surface of the wiring substrate. Over the second main surface of the semiconductor chip, a plurality of first terminals connected with a first circuit and a plurality of second terminals connected with a second circuit are arranged. An arrangement pattern of the plurality of first terminals and an arrangement pattern of the plurality of second terminals include the same arrangement pattern. In a region of the wiring substrate where the first circuit is close to the second circuit when viewed from the first main surface of the semiconductor chip, a voltage line which supplies a power supply voltage to the first circuit is formed.
    Type: Grant
    Filed: October 27, 2017
    Date of Patent: December 11, 2018
    Assignee: Renesas Electronics Corporation
    Inventors: Takafumi Betsui, Motoo Suwa
  • Patent number: 10109537
    Abstract: An extension of conventional IC fabrication processes to include some of the concepts of flip-chip assemblies while producing a final “non-flip chip” circuit structure suitable for conventional packaging or for direct usage by customers. Multiple IC dies are fabricated on a semiconductor wafer in a conventional fashion, solder bumped, and singulated. The singulated dies are then flip-chip assembled onto a single tile substrate of thin-film material which has been patterned with vias, peripheral connection pads, and one or more ground planes. Once dies are flip-chip mounted to the thin-film tile, all of the dies on the entire tile may be probed using automated testing equipment. Once test probing is complete, the dies and tile are singulated into die/tile assemblies.
    Type: Grant
    Filed: October 31, 2017
    Date of Patent: October 23, 2018
    Assignee: pSemi Corporation
    Inventors: Mark Moffat, Andrew Christie, Duncan Pilgrim
  • Patent number: 9997508
    Abstract: An integrated photo detector with enhanced electrostatic discharge damage (ESD) protection. The integrated photo detector includes a first photodiode formed in the SOI substrate and associated with a first p-electrode and a first n-electrode. Additionally, the integrated photo detector includes a second photodiode formed in the SOI substrate associated with a second p-electrode and a second n-electrode forming a capacitance no larger than a few femto Faradays. Moreover, the integrated photo detector includes a first electrode and a second electrode disposed respectively on the SOI substrate. The first/second electrode is respectively connected to the first p/n-electrode via a first/second metallic layer patterned with a reduced width from the first/second electrode to the first p/n-electrode and connected to the second p/n-electrode via a first/second metallic wire to make a parallel coupling between the first photodiode and the second photodiode with an ESD threshold of about 100V.
    Type: Grant
    Filed: June 29, 2017
    Date of Patent: June 12, 2018
    Assignee: INPHI CORPORATION
    Inventors: Jie Lin, Masaki Kato
  • Patent number: 9870066
    Abstract: Input device manufacture techniques are described. In one or more implementations, a plurality of layers of a key assembly is positioned in a fixture such that one or more projections of the fixture are disposed through one or more openings in each of the one or more layers. The positioned plurality of layers is secured to each other.
    Type: Grant
    Filed: April 21, 2015
    Date of Patent: January 16, 2018
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: David Otto Whitt, III, Matthew David Mickelson, Joel Lawrence Pelley, Amey M. Teredesai, Timothy Carlyle Shaw, Christopher Strickland Beall, Christopher Harry Stoumbos
  • Patent number: 9853696
    Abstract: Tightly-coupled near-field transmitter/receiver pairs are deployed such that the transmitter is disposed at a terminal portion of a first conduction path, the receiver is disposed at a terminal portion of a second conduction path, the transmitter and receiver are disposed in close proximity to each other, and the first conduction path and the second conduction path are discontiguous with respect to each other. In some embodiments of the present invention, close proximity refers to the transmitter antenna and the receiver antenna being spaced apart by a distance such that, at wavelengths of the transmitter carrier frequency, near-field coupling is obtained. In some embodiments, the transmitter and receiver are disposed on separate substrates that are moveable relative to each other. In alternative embodiments, the transmitter and receiver are disposed on the same substrate.
    Type: Grant
    Filed: October 7, 2013
    Date of Patent: December 26, 2017
    Assignee: Keyssa, Inc.
    Inventor: Gary D. McCormack
  • Patent number: 9837325
    Abstract: An extension of conventional IC fabrication processes to include some of the concepts of flip-chip assemblies while producing a final “non-flip chip” circuit structure suitable for conventional packaging or for direct usage by customers. Multiple IC dies are fabricated on a semiconductor wafer in a conventional fashion, solder bumped, and singulated. The singulated dies are then flip-chip assembled onto a single tile substrate of thin-film material which has been patterned with vias, peripheral connection pads, and one or more ground planes. Once dies are flip-chip mounted to the thin-film tile, all of the dies on the entire tile may be probed using automated testing equipment. Once test probing is complete, the dies and tile are singulated into die/tile assemblies.
    Type: Grant
    Filed: June 16, 2015
    Date of Patent: December 5, 2017
    Assignee: Peregrine Semiconductor Corporation
    Inventors: Mark Moffat, Andrew Christie, Duncan Pilgrim
  • Patent number: 9800213
    Abstract: The embodiments described herein provide an amplifier device that utilizes bonding pad capacitance in an impedance matching network. In one specific embodiment, the amplifier device comprises: an amplifier formed on a semiconductor die, the amplifier including an amplifier input and an amplifier output, the amplifier configured to generate an amplified radio frequency (RF) signal at the amplifier output; and an impedance matching network coupled to the amplifier, the impedance matching network including a capacitor, where the capacitor includes a first plate, a second plate, and dielectric material between the first and second plates, where the first plate includes or is directly electrically coupled to a bond pad on the semiconductor die.
    Type: Grant
    Filed: June 20, 2016
    Date of Patent: October 24, 2017
    Assignee: NXP USA, INC.
    Inventors: Ibrahim Khalil, Ebrahim M. Al Seragi, Jeffrey K. Jones
  • Patent number: 9693492
    Abstract: A high-frequency package includes a first dielectric substrate having a signal line and a grounding conductor provided on a back side, a high-frequency element connected to a back side of the first dielectric substrate with a first connection conductor therebetween, a second dielectric substrate having a signal line and a grounding conductor provided on a front side facing the back side with the high-frequency element therebetween, and second connection conductors that are arranged so as to surround the high-frequency element and connect the grounding conductor on the back side of the first dielectric substrate and the grounding conductor on the front side of the second dielectric substrate. In the high-frequency package, a dielectric space surrounded by a conductor pattern is formed in the front side of the second dielectric substrate under the high-frequency element.
    Type: Grant
    Filed: January 31, 2012
    Date of Patent: June 27, 2017
    Assignee: Mitsubishi Electric Corporation
    Inventors: Yusuke Kitsukawa, Takuya Suzuki, Tomoyuki Unno
  • Patent number: 9673117
    Abstract: A semiconductor module includes a plurality of insulating circuit boards including semiconductor chips, each of the plurality of insulating circuit boards including a first outer edge among outer edges of the insulating circuit board facing an adjacent insulating circuit board of the plurality of insulating circuit boards, and a second outer edge among the outer edges excluding the first outer edge; a resin frame body having a crosspiece abutting against the first outer edges, and a frame element abutting against the second outer edges; a conductive component striding over the crosspiece to electrically connect the insulating circuit boards to each other; and an upper lid having a lid element covering an opening disposed at an upper part of the resin frame body and a partition protruding from a face of the lid element facing the insulating circuit boards to abut against a part of the crosspiece.
    Type: Grant
    Filed: January 7, 2016
    Date of Patent: June 6, 2017
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Rikihiro Maruyama, Takahito Harada
  • Patent number: 9633951
    Abstract: A semiconductor package that includes a semiconductor die, an insulation around the die, and a conforming conductive pad coupled to an electrode of the die.
    Type: Grant
    Filed: November 10, 2006
    Date of Patent: April 25, 2017
    Assignee: Infineon Technologies Americas Corp.
    Inventors: Mark Pavier, Andrew N. Sawle, Martin Standing
  • Patent number: 9583811
    Abstract: A microwave device includes a semiconductor package comprising a microwave semiconductor chip and a waveguide part associated with the semiconductor package. The waveguide part is configured to transfer a microwave waveguide signal. It includes one or more pieces. The microwave device further includes a transformer element configured to transform a microwave signal from the microwave semiconductor chip into the microwave waveguide signal or to transform the microwave waveguide signal into a microwave signal for the microwave semiconductor chip.
    Type: Grant
    Filed: August 7, 2014
    Date of Patent: February 28, 2017
    Assignee: Infineon Technologies AG
    Inventors: Ernst Seler, Maciej Wojnowski, Walter Hartner, Josef Boeck
  • Patent number: 9577308
    Abstract: An interconnecting structure for electrically connecting a first electronic device with a second electronic device is provided. The first electronic device has two first bond-pads, and the second electronic device has two second bond-pads electrically connected to the two first bond-pads respectively. The interconnecting structure includes a signal transmission structure electrically connected to the two first bond-pads and the two second bond-pads; and a ground device disposed between the first electronic device and the second electronic device so that the first electronic device and the second electronic device have a same ground potential.
    Type: Grant
    Filed: March 11, 2014
    Date of Patent: February 21, 2017
    Assignee: NATIONAL CHAIO TUNG UNIVERSITY
    Inventors: Chun-Hsing Li, Chien-Nan Kuo, Chun-Lin Ko
  • Patent number: 9544057
    Abstract: The present invention relates to an interconnect structure for coupling at least one electronic unit for outputting and/or receiving electric signals, and at least one optical unit for converting said electric signals into optical signals and/or vice versa, to a further electronic component. The interconnect structure comprises an electrically insulating substrate (102) and a plurality of signal lead pairs (104, 120) to be coupled between said electronic unit (108, 116) and a front end contact region (106) for electrically contacting said interconnect structure by said further electronic component.
    Type: Grant
    Filed: September 17, 2013
    Date of Patent: January 10, 2017
    Assignee: FINISAR CORPORATION
    Inventors: Andrei Kaikkonen, Lennart Lundquist, Lars-Goete Svensson, Robert Smith
  • Patent number: 9520373
    Abstract: Provided is a semiconductor package including a semiconductor chip having one surface on which chip pads are formed, and a redistribution structure formed on the one surface of the semiconductor chip. The redistribution structure includes a redistribution layer connected to the chip pads and a redistribution insulating layer interposed between the semiconductor chip and the redistribution layer. The redistribution insulating layer includes a first insulating portion having a first dielectric constant and a second insulating portion having a second dielectric constant that is different from the first dielectric constant. The first insulating portion and the second insulating portion are connected to each other in a horizontal direction.
    Type: Grant
    Filed: December 22, 2015
    Date of Patent: December 13, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yong-hoon Kim, Keung-beum Kim
  • Patent number: 9455157
    Abstract: A packaged IC has a package with a die paddle, a signal lead, and a ground lead. The packaged IC also has a die, secured to the package, with a ground pad and a signal pad. The signal pad is electrically connected to the signal lead, and the ground pad is electrically connected to both the die paddle and the ground lead.
    Type: Grant
    Filed: September 4, 2015
    Date of Patent: September 27, 2016
    Assignee: Anokiwave, Inc.
    Inventors: Vipul Jain, Noyan Kinayman, Amir Esmaili, Guarav Menon, Nitin Jain