Abstract: A semiconductor device which includes a substrate, a semiconductor chip which is mounted on the substrate, a package in which an upper surface of the substrate and the semiconductor chip are sealed using an insulating material, and a molding material which is exposed to the upper surface of the package. In addition, the device includes a lead of which one end is connected to the mold material and the other end is electrically connected to the substrate, which is integrally formed of the same material as from a connection portion with the mold material to a connection portion with the substrate, and of which the connection portion with the mold material is exposed to the upper surface of the package.

Abstract: A package substrate including a conductive pattern disposed on a die attach surface of the package substrate; at least one bumping trace inlaid into the conductive pattern; and at least one gap disposed along with the bumping trace in the conductive pattern to separate the bumping trace from a bulk portion of the conductive pattern. The bumping trace may have a lathy shape from a plan view and a width substantially between 10 ?m and 40 ?m and a length substantially between 70 ?m and 130 ?m, for example.

Abstract: Examples of high-speed ball grid array packages and a process of forming a package are provided. A package may include contact pads disposed on a bottom surface, conductive balls, and a signal via structure. The package may also include a first ground via structure arranged along one or more first semi-circular contours around the signal via structure and extending vertically and a second ground via structure arranged along one or more second semi-circular contours around the signal via structure and extending vertically. The package may include a ground interface plane disposed in separation from the signal contact pad by a distance. The distance may be determined based on at least a size of the signal contact pad, a dielectric constant of a transition layer between the ground interface plane and the signal contact pad, and a distance between the signal via structure and the second ground via structure.

Abstract: A monolithic microwave integrated circuit (MMIC) flip chip interconnect is formed by coating an active side of the chip with a dielectric coating, such as benzocyclobutene (BCB), that inhibits deposition of metal plating materials. A portion of the dielectric coating is removed to expose bond pads on the active side of the chip, stud bumps are bonded to the bond pads, and the active side is then plated with first and second consecutive metal plating materials, such as nickel and gold, respectively, that do not adhere to the dielectric coating. The chip is then oriented such that the plated stud bumps on the active side of the chip face bond pads on a substrate, and the stud bumps on the chip are bonded to the bond pads on the substrate.

Abstract: A package includes: a metal wall disposed on a conductive base plate; a through-hole disposed in input/output portions of the metal wall; a lower layer feed through disposed on the conductive base plate; a wiring pattern disposed on the lower layer feed through; an upper layer feed through disposed on a part of the lower layer feed through and a part of the wiring pattern; and a terminal disposed on the wiring pattern, wherein a width of a part of the lower layer feed through and a width of the upper layer feed through are wider than a width of the through-hole, the lower layer feed through is adhered to a side surface of the metal wall, the upper layer feed through is adhered to the side surface of metal wall, and an air layer is formed between the wiring pattern and an internal wall of the through-hole.

Abstract: A semiconductor circuit substrate includes a transistor-forming substrate and a circuit-forming substrate. The transistor-forming substrate is a GaN substrate and has a Bipolar Junction Transistor (BJT) located in its top surface. The bottom surface of the transistor-forming substrate is flat and has contact regions. The circuit-forming substrate is a material other than a compound semiconductor and has no semiconductor active elements. The circuit-forming substrate has a flat top surface, contact regions buried in and exposed at the top surface, and passive circuits. The transistor-forming substrate and the circuit-forming substrate are directly bonded together without any intervening film, such as an insulating film.

Abstract: In a hybrid integrated circuit device, a circuit board on which an island portion of a lead is fixedly attached and a control board on which a control element and the like are mounted are disposed in an overlapping manner. The circuit board and the control board are integrally encapsulated with an encapsulating resin. A transistor disposed on an upper surface of the circuit board and a control element mounted on an upper surface of the control board are also covered by the encapsulating resin. Thus, a module in which an inverter circuit and a control circuit are integrally encapsulated with resin is provided.

Abstract: Methods and systems for communicating via flip-chip die and package waveguides are disclosed and may include communicating one or more signals between sections of an integrated circuit via one or more waveguides integrated in a multi-layer package. The integrated circuit may be bonded to the multi-layer package. The waveguides may be configured via switches in the integrated circuit or by MEMS switches integrated in the multi-layer package. The signals may include a microwave signal and a low frequency control signal that may configure the microwave signal. The low frequency control signal may include a digital signal. The waveguides may comprise metal and/or semiconductor layers deposited on and/or embedded within the multi-layer package.

Abstract: A semiconductor package includes a print circuit part, a lower chip, an upper chip, a thermal conductivity part, and an encapsulation resin. The lower chip and the upper chip are mounted on the print circuit part through wire bonding connection. The thermal conductivity part efficiently dissipates heat from the chips to the outside of the package. The encapsulation resin entirely seals the package while exposing the thermal conductivity part. A adhesive sheet is hardened to form a bonding layer between the thermal conductivity part and the upper chip, a bonding layer between the semiconductor chips, and a bonding layer between the semiconductor chip and the wired component. The configuration contributes to miniaturization, high integration, and heat resistance reduction of a semiconductor package using high-heat-generating ICs.

Abstract: In wireless communication devices, internally matching impedance in millimeter wave packaging enables better signal retention at high frequencies in the range of 15 GHz and above. Through the use of differential wire bond signal transmission, the inherent inductance of a millimeter wave package can be matched by the capacitance of the package wire bonds if the capacitance is tailored. The capacitance can be tailored by calculating a suitable distance between wire bonds and tuning the dielectric constant of the over-mold material. A differential set of wire bonds act like a differential transmission line whose characteristic impedance can be tuned by configuring the dielectric constant of the over-mold of the millimeter wave package.

Abstract: Methods and systems for configuring one or more electrical waveguides in an integrated circuit by adjusting a geometry of the one or more electrical waveguides, and communicating one or more electrical signals between components within the integrated circuit via the one or more electrical waveguides. The geometry of the one or more electrical waveguides may be configured by adjusting a length of the one or more electrical waveguides utilizing switches in the integrated circuit. The switches may include CMOS transistors. The one or more signals may include a microwave signal and a low frequency digital control signal that configures the microwave signal. The electrical waveguides may include metal and/or semiconductor layers deposited on and/or embedded within the integrated circuit.

Abstract: A shielded embedded electronic component substrate includes a core dielectric layer having a die opening. An electrically conductive die shield lines the die opening. An electronic component is mounted within the die opening and to the die shield, where the die shield shields the electronic component. By mounting the electronic component within the die opening, the shielded embedded electronic component substrate is made relatively thin. Further, heat generated by the electronic component is dissipated to the die shield and to the ambient environment. Accordingly, the shielded embedded electronic component substrate is well suited for use when the electronic component generates a significant amount of heat, e.g., in high power applications.

Abstract: A chip-to-chip multi-signaling communication system with common conductive layer, which comprises a first chip, a second chip, and a common conductive layer, is disclosed. The first chip has at least a first metal pad and a second metal pad. The second chip has at least a first metal pad and a second metal pad. The common conductive layer is to a conductive material and glued directly to the first chip and the second chip. Wherein, the first metal pad of the second chip is aligned with the first metal pad of the first chip for receiving the signal from the first metal pad of the first chip through the common conductive layer. The interference generated by other pads of the first and the second chips is suppressed by the design of the pads and the common conductive layer.

Abstract: A method and a system for routing electrical connections are disclosed. A semiconductor device includes a first semiconductor chip and a routing plane having a plurality of routing lines. A first connecting line is electrically coupled to the first semiconductor chip and one of the plurality of routing lines and a second connecting line is electrically coupled to the one of the plurality of routing lines and to one of a second semiconductor chip or a first external contact element.

Abstract: An RF package includes a substrate mountable on a base plate, a non-conductive cover overlying the substrate, and quasi-serpentine stepped source leads attached to an upper surface of the substrate and extending from at least one of a pair of opposite sides of the upper surface of the substrate to tapered lower surfaces of the cover. The cover includes a recess to receive the substrate. The recess includes stress distribution surface areas to engage and press outer edge portions of opposite sides of the substrate against a base plate or heat sink. The tapered lower surfaces of the cover engage with and press against the stepped source leads when securing the RF package to the base plate or heat sink using one or more fasteners or bolts. The cover includes structural features to improve preferential deformation when a mounting force is applied.

Abstract: Provided are a semiconductor package and a method for fabricating the same. The semiconductor package includes a lower package comprising a lower substrate, a lower semiconductor chip mounted on the lower substrate and comprising a redistribution, and a molding layer molding the lower semiconductor chip, an upper package comprising an upper substrate and an upper semiconductor chip mounted on the upper substrate, with the upper package being stacked on the lower package. The semiconductor package further includes an electrical interconnector extending from the upper substrate into the molding layer and connected to the redistribution to electrically connect the upper and lower packages to each other, and a dummy interconnector extending from the upper substrate into the molding layer to physically couple the upper and lower packages to each other.

Abstract: Microwave or millimeter wave system packaging having a system with a baseplate, transition board and cover. The baseplate includes microwave or millimeter wave components attached thereto. The transition board includes a first connector attached to a first side thereof and operatively connected to the components, and a second connector attached to a second side thereof and operatively connected to the components through the board. The cover and baseplate form a cavity containing the board and components, and the second connector may be operatively connected to a third connector such as a printed circuit board disposed outside of the cavity and on a higher level assembly. The transition board may further include a fourth connector operatively connected to the components for providing a signal to an external component or device or receiving a signal from an external component or device.

Abstract: In a chip package, semiconductor dies in a vertical stack of semiconductor dies or chips (which is referred to as a ‘plank stack’) are separated by a mechanical spacer (such as a filler material or an adhesive). Moreover, the chip package includes a substrate at a right angle to the plank stack, which is electrically coupled to the semiconductor dies along an edge of the plank stack. In particular, electrical pads proximate to a surface of the substrate (which are along a stacking direction of the plank stack) are electrically coupled to pads that are proximate to edges of the semiconductor dies by an intervening conductive material, such as: solder, stud bumps, plated traces, wire bonds, spring connectors, a conductive adhesive and/or an anisotropic conducting film. Note that the chip package may facilitate high-bandwidth communication of signals between the semiconductor dies and the substrate.

Abstract: In inlets used for ID tags and the like, a defective connection between an integrated circuit part and an antenna is suppressed by improvement of tolerance for a bending or a pressing pressure. The integrated circuit part includes a semiconductor chip and a multilayer substrate having a concave portion. The semiconductor chip is mounted on the bottom of the concave portion. The multilayer substrate includes a connection electrode at the top surface and a connection electrode connected to the semiconductor chip on the bottom of the concave portion. The connection electrode on the bottom of the concave portion is connected to the connection electrode at the top surface by a penetration electrode inside a multilayer substrate. By such a configuration, the semiconductor chip is connected to the antenna.

Abstract: A first semiconductor chip and a second semiconductor chip are overlapped with each other in a direction in which a first multilayer interconnect layer and a second multilayer interconnect layer are opposed to each other. When seen in a plan view, a first inductor and a second inductor are overlapped. The first semiconductor chip and the second semiconductor chip have non-opposed areas which are not opposed to each other. The first multilayer interconnect layer has a first external connection terminal in the non-opposed area, and the second multilayer interconnect layer has a second external connection terminal in the non-opposed area.

Abstract: A wiring board between which and a chip to be mounted a resin is filled includes: a substrate body on which a conductor portion to be connected to an electrode terminal of the chip is formed; and an insulating protection film formed on the substrate body and having an opening portion formed therein to expose the conductor portion. The opening portion is formed in such a manner that the edge thereof is positioned along and outside the outer shape of the chip except for a specific corner portion, and that the edge in the specific corner portion is positioned on a side of or inside the outer shape of the chip.

Abstract: An assembly component and a technique for assembling a chip package using the assembly component are described. This chip package includes a set of semiconductor dies that are arranged in a stack in a vertical direction, which are offset from each other in a horizontal direction to define a stepped terraced at one side of the vertical stack. Moreover, the chip package may be assembled using the assembly component. In particular, the assembly component may include a housing having another stepped terrace. This other stepped terrace may include a sequence of steps in the vertical direction, which are offset from each other in the horizontal direction. Furthermore, the housing may be configured to mate with the set of semiconductor dies such that the set of semiconductor dies are arranged in the stack in the vertical direction. For example, the other stepped terrace may approximately be a mirror image of the stepped terrace.

Abstract: The present invention relates to a semiconductor package having at least one first layer chip, a plurality of first metal bumps, at least one second layer chip and a package body. The first layer chip includes a first active surface upon which the first metal bumps are disposed and a plurality of first signal coupling pads disposed adjacent to the first active surface. The second layer chip is electrically connected to the first layer chip, and includes a second active surface that faces the first active surface and a plurality of second signal coupling pads. The second signal coupling pads are capacitively coupled to the first signal coupling pads so as to provide proximity communication between the first layer chip and the second layer chip. The package body encapsulates the first layer chip, the first metal bumps, and the second layer chip, and the first metal bumps are partially exposed.

Abstract: An ultra wideband hermetically sealed surface mount package for a microwave monolithic integrated circuit (MMIC) is provided including: an integrated circuit; a package body being mounted with the integrated circuit and comprising a plurality of first dielectrics formed in a multilayer, a first line unit mounted to a circuit substrate and is electrically connected with an external circuit, a second line unit upwardly extended from the first line unit and is electrically connected with the first line unit, a third line unit extended to the right angle from the second line unit and is electrically connected with the second line unit, and a bonding unit that electrically connects the third line unit and the mounted integrated circuit; and a package cover being formed on the package body to seal the integrated circuit and comprising a plurality of second dielectrics formed in a multilayer.

Abstract: A shielded package includes a shield assembly having a shield fence, a shield lid, and a shield lid adhesive electrically coupling the shield lid to the shield fence. The shield fence includes a porous sidewall through which molding compound passes during molding of the shielded package. Further, the shield fence includes a central aperture through which an electronic component is die attached and wire bonded.

Abstract: The invention provides semiconductor material (e.g., gallium nitride material) devices (e.g., transistors) and methods associated with the same. The devices may be supported within a package that is formed, in part, of a polymeric material. In other embodiments, the devices may be mounted to a support (e.g., circuit board) and a polymeric material may encapsulate a portion of the device extending from the support.

Abstract: A device includes a first semiconductor chip and a first encapsulant that encapsulates the first semiconductor chip and that includes a cavity. A carrier and an electrical component are mounted on the carrier. The carrier is arranged such that the electrical component is enclosed by the cavity.

Abstract: In one embodiment of the disclosure, a method includes providing a carrier substrate, forming a first region over an upper surface of the substrate, creating an electrical component using a planar process, embedding the electrical component in the dielectric layer, and removing a substrate portion of the electrical component. The first region includes a dielectric layer and may be made of any material that electrically isolates the electrical component from the carrier substrate. The electrical component may be created using a planar process thereby having an epitaxial surface that is embedded in the dielectric layer.

Abstract: 3-D ICs (18, 18?, 90) with integrated passive devices (IPDs) (38) having reduced cross-talk and high packing density are provided by stacking separately prefabricated substrates (20, 30, 34) coupled by through-substrate-vias (TSVs) (40). An active device (AD) substrate (20) has contacts on its upper portion (26). An isolator substrate (30) is bonded to the AD substrate (20) so that TSVs (4030) in the isolator substrate (30) are coupled to the contacts (26) on the AD substrate (20), and desirably has an interconnect zone (44) on its upper surface. An IPD substrate (34) is bonded to the isolator substrate (30) so that TSVs (4034) therein are coupled to the interconnect zone (44) on the isolator substrate (30) and/or TSVs (4030) therein. The IPDs (38) are formed on its upper surface and coupled by TSVs (4034, 4030) in the IPD (34) and isolator (30) substrates to devices (26) in the AD substrate (20).

Abstract: According to one embodiment, there is a high frequency circuit having a multi-chip module structure, including a semiconductor substrate set formed with discrete transistors connected in series, a first dielectric substrate set formed with capacitors, and a second dielectric substrate set formed with strip lines.

Abstract: A semiconductor device package is provided. The semiconductor device package includes a laminate comprising a first metal layer disposed on a dielectric film; a plurality of vias extending through the laminate according to a predetermined pattern; one or more semiconductor devices attached to the dielectric film such that the semiconductor device contacts one or more vias; a patterned interconnect layer disposed on dielectric film, said patterned interconnect layer comprising one or more patterned regions of the first metal layer and an electrically conductive layer, wherein a portion of the patterned interconnect layer extends through one or more vias to form an electrical contact with the semiconductor device. The patterned interconnect layer comprises a top interconnect region and a via interconnect region, wherein the package interconnect region has a thickness greater than a thickness of the via interconnect region.

Abstract: Stacked semiconductor chips. One embodiment provides a device having a first body. A first power semiconductor chip and first external contact elements is provides. A second body includes a second semiconductor chip and second external contact elements. The second body is placed over the first body. The first external contact elements and the second external contact elements define a first plane.

Abstract: A stacked die package for an electromechanical resonator system includes a chip that contains an electromechanical resonator bonded onto the control chip for the electromechanical resonator by a thermally and/or electrically conductive epoxy. In various embodiments, the electromechanical resonator can be a micro-electromechanical system (MEMS) resonator or a nano-electromechanical system (NEMS) resonator. Packaging configurations that may include the chip that contains the electromechanical resonator and the control chip include chip-on-lead (COL), chip-on-paddle (COP), and chip-on-tape (COT) packages. The stacked die package provides small package footprint and/or low package thickness, as well as low thermal resistance and a robust conductive path between the chip that contains the electromechanical resonator and the control chip.

Abstract: A high-frequency device having high-frequency-signal-treating circuits in and on a laminate substrate comprising pluralities of dielectric layers having conductor patterns, the high-frequency-signal-treating circuits having amplifier circuits and switch circuits; terminals including input and output terminals of high-frequency signals, the power supply terminals of the amplifier circuits and the power supply terminals of the switch circuits being formed on one main surface of the laminate substrate; power supply lines each having one end connected to each of the power supply terminals of the amplifier circuits and power supply lines each having one end connected to each of the power supply terminals of the switch circuits being formed on one dielectric layer to constitute a power supply line layer; a first ground electrode being arranged on the side of the main surface with respect to the power supply line layer, the first ground electrode overlapping at least part of the power supply lines in a lamination di

Abstract: A semiconductor packaged device, and method of packaging that incorporates the formation of cavities about electronic devices during the packaging process. In one example, the device package includes a first substrate having a first recess formed therein, a second substrate having a second recess formed therein, and an electronic device mounted in the first recess. The first and second substrates are joined together with the first and second recesses substantially overlying one another so as to form a cavity around the electronic device.

Abstract: A power semiconductor module assembly is disclosed including a power semiconductor module comprising a load terminal electrically conductively joined to a contact conductor. Part of the heat materializing during operation of the power semiconductor module in the load terminal is dissipated by using a heat dissipating element.

Abstract: Encapsulated radio frequency identification (RFID) articles having enhanced break strength and/or temperature resistance and methods of making these articles. The RFID articles include an RFID tag embedded within a thermoplastic substrate to form the RFID article. In one embodiment, the RFID article includes an over-molded barrier material that enables the RFID article to have enhanced temperature resistance such that the articles are able to sustain repeated exposure to high temperatures and/or sterilization procedures, thereby enabling the RFID articles to be utilized in applications heretofore unavailable. In other embodiments, the RFID articles are made using an injection molding process that provides very thin encapsulated RFID tags that also exhibit an increased level of temperature resistance.

Abstract: Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods may include forming a cavity in a carrier material, attaching a die in the cavity, wherein a backside of the die comprises a metal filled DBF, forming a dielectric material adjacent the die and on a bottom side of the carrier material, forming a coreless substrate by building up layers on the dielectric material, and removing the carrier material from the coreless substrate.

Abstract: Embodiments of a microelectronic package are generally described herein. A microelectronic package may include a die having a first side and a second side, opposite the first side, a flange coupled to the first side of the die, and a lead frame proximately positioned relative to the die and coupled to the second side of the die. Other embodiments may be described and claimed.

Abstract: In a microwave module with at least one semiconductor chip, which provides on its upper side a connecting-line structure formed in particular as a coplanar line, which is connected to at least one adjacent incoming and/or outgoing line structure formed on the upper side of the substrate, the chip is glued with its underside and all lateral surfaces, on which no high-frequency connecting lines lead to the chip, within a recess of a metal part with good thermal conduction.

Abstract: A ramp-stack chip package is described. This chip package includes a vertical stack of semiconductor dies or chips that are offset from each other in a horizontal direction, thereby defining a terrace with exposed pads. A high-bandwidth ramp component, which is positioned approximately parallel to the terrace, is electrically and mechanically coupled to the exposed pads. For example, the ramp component may be coupled to the semiconductor dies using: solder, microsprings and/or an anisotropic conducting film. Furthermore, each of the semiconductor dies includes a static bend so that an end segment of each of the semiconductor dies is parallel to the direction and is mechanically coupled to the ramp component. These end segments may facilitate high-bandwidth communication of signals between the chips and the ramp component, for example, via proximity communication.

Abstract: Described herein are wafer-level semiconductor device packages with stacking functionality and related stacked package assemblies and methods. In one embodiment, a semiconductor device package includes a set of connecting elements disposed adjacent to a periphery of a set of stacked semiconductor devices. At least one of the connecting elements is wire-bonded to an active surface of an upper one of the stacked semiconductor devices.

Abstract: An integrated circuit structure includes an interconnect structure over a semiconductor substrate and a coaxial transmission line. The coaxial transmission line includes a signal line, a top plate over the signal line and electrically insulated from the signal line, and a bottom plate under the signal line and electrically insulated from the signal line. At least one of the top plate and the bottom plate includes metal strip shields and dielectric strips, with each of the dielectric strips being between two of the metal strip shields. The integrated circuit structure further includes a ground conductor electrically connecting the top plate and the bottom plate. The ground conductor is insulated from the signal line by a dielectric material.

Abstract: A semiconductor module comprises components in one wafer level package. The module comprises an integrated circuit (IC) chip embedded within a package molding compound. The package comprises a molding compound package layer coupled to an interface layer for integrating an antenna structure and a bonding interconnect structure to the IC chip. The bonding interconnect structure comprises three dimensional interconnects. The antenna structure and bonding interconnect structure are coupled to the IC chip and integrated within the interface layer in the same wafer fabrication process.

Abstract: A circuit substrate has one or more active components and a plurality of passive circuit elements on a first surface. An active semiconductor device has a substrate with layers of material and a plurality of terminals. The active semiconductor device is flip-chip mounted on the circuit substrate and at least one of the terminals of the device is electrically connected to an active component on the circuit substrate. The active components on the substrate and the flip-chip mounted active semiconductor device, in combination with passive circuit elements, form preamplifiers and an output amplifier respectively. In a power switching configuration, the circuit substrate has logic control circuits on a first surface. A semiconductor transistor flip-chip mounted on the circuit substrate is electrically connected to the control circuits on the first surface to thereby control the on and off switching of the flip-chip mounted device.

Abstract: Methods and systems for intra-printed circuit board communication via waveguides are disclosed and may include communicating one or more signals between or among a plurality of integrated circuits via one or more waveguides integrated on a printed circuit board. The integrated circuits may be bonded to the printed circuit board. The waveguides may be configured via switches integrated within each of the plurality of integrated circuits. The one or more signals may include microwave signals. The one or more waveguides may be configured for communicating microwave signals with a frequency of 60 GHz or greater. The communication of the one or more signals may be configured via a low frequency control signal, which may include a digital signal. The one or more waveguides may include metal and/or semiconductor layers deposited on and/or embedded within the printed circuit board.

Abstract: A semiconductor device package and a method of fabricating the same are disclosed. The semiconductor device package includes a substrate, a buffer structure, two active chips and a bridge chip. The substrate has a cavity, a first surface and a second surface opposite to the first surface. The cavity is extended from the first surface toward the second surface, and the buffer structure is disposed in the cavity. The active chips are disposed on and electrically connected to the first surface and around the cavity. The active chips both have a first active surface. The bridge chip is disposed in the cavity and above the buffer structure. The bridge chip has a second active surface, the second active surface faces the first active surfaces and is partially overlapped with the first active surfaces, the bridge chip is used for providing a proximity communication between the active chips.

Abstract: Methods and systems for inter-chip communication via integrated circuit package waveguides are disclosed and may include communicating one or more signals between or among a plurality of integrated circuits via one or more waveguides integrated in a multi-layer package. The integrated circuits may be bonded to the multi-layer package. The waveguides may be configured via switches in the integrated circuits or by MEMS switches integrated in the multi-layer package. The signals may include a microwave signal and a low frequency control signal that may configure the microwave signal. The low frequency control signal may include a digital signal. The waveguides may comprise metal and/or semiconductor layers deposited on and/or embedded within the multi-layer package.

Abstract: A communication device according to an embodiment includes an antenna transmitting/receiving a high frequency signal, a semiconductor chip having four corners and four sides processing the high frequency signal, and a substrate on which a first wiring connected to ground, a second wiring supplying power to the semiconductor chip, a third wiring connected to a protection element or circuit of the semiconductor chip, and fourth wirings transmitting a signal from the semiconductor chip are formed by plating, and the semiconductor chip is mounted.

Abstract: A multi-chip device which includes a plurality of integrated circuit die disposed one over another. Each integrated circuit die includes one or a plurality of bond pads. One or a plurality of conductors are disposed to electrically couple the bond pads of vertically adjacent integrated circuit die. Each conductor is designed, calculated, specified and/or predetermined to have a length so as to behave as a segment in a multi-drop transmission line. The multi-drop transmission line may be terminated at one end or utilized in a flow-through approach. In one embodiment, an integrated circuit die may be horizontally offset with respect to a vertically adjacent integrated circuit die to expose the periphery region. In another embodiment, each integrated circuit die may be stacked and aligned in a vertical column. In this embodiment, a spacer such as a thermally conductive spacer is disposed between each integrated circuit die in the stack.