Schottky Barrier To Polycrystalline Semiconductor Material Patents (Class 257/73)
  • Patent number: 10340356
    Abstract: A laminated body comprising a substrate, an ohmic electrode layer, a metal oxide semiconductor layer, a Schottky electrode layer and a buffer electrode layer in this order, wherein a reduction suppressing layer is provided between the Schottky electrode layer and the buffer electrode layer.
    Type: Grant
    Filed: December 26, 2016
    Date of Patent: July 2, 2019
    Assignee: IDEMITSU KOSAN CO., LTD.
    Inventors: Emi Kawashima, Takashi Sekiya, Yuki Tsuruma, Yoshihiro Ueoka, Shigekazu Tomai, Motohiro Takeshima
  • Patent number: 10141439
    Abstract: A semiconductor device according to an embodiment includes a first GaN based semiconductor layer of a first conductive type, a second GaN based semiconductor layer of the first conductive type provided above the first GaN based semiconductor layer, a third GaN based semiconductor layer of a second conductive type provided above a part of the second GaN based semiconductor layer, a epitaxially grown fourth GaN based semiconductor layer of the first conductive type provided above the third GaN based semiconductor layer, a gate insulating film provided on the second, third, and fourth GaN based semiconductor layer, a gate electrode provided on the gate insulating film, a first electrode provided on the fourth GaN based semiconductor layer, a second electrode provided at the side of the first GaN based semiconductor layer opposite to the second GaN based semiconductor layer, and a third electrode provided on the second GaN based semiconductor layer.
    Type: Grant
    Filed: February 3, 2017
    Date of Patent: November 27, 2018
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Miki Yumoto, Masahiko Kuraguchi
  • Patent number: 9735290
    Abstract: An integrated diode (100) comprising a substrate (102); a Schottky cell (104) on the substrate (102); a heterojunction cell (106) on the substrate (102); a common anode contact (108) for both the Schottky cell (104) and the heterojunction cell (106); and a common cathode contact (110) for both the Schottky cell (104) and the heterojunction cell (106).
    Type: Grant
    Filed: December 30, 2015
    Date of Patent: August 15, 2017
    Assignee: Nexperia B.V.
    Inventors: Tim Boettcher, Jan Philipp Fischer, Thomas Igel-Holtzendorff
  • Patent number: 8975719
    Abstract: A planar diode and method of making the same employing only one mask. The diode is formed by coating a substrate with an oxide, removing a central portion of the oxide to define a window through which dopants are diffused. The substrate is given a Ni/Au plating to provide ohmic contact surfaces, and the oxide on the periphery of the window is coated with a polyimide passivating agent overlying the P/N junction.
    Type: Grant
    Filed: August 2, 2013
    Date of Patent: March 10, 2015
    Assignee: Vishay General Semiconductor LLC
    Inventors: Benson Wang, Kevin Lu, Warren Chiang, Max Chen
  • Patent number: 8957461
    Abstract: A TMBS diode is disclosed. In an active portion and voltage withstanding structure portion of the diode, an end portion trench surrounds active portion trenches. An active end portion which is an outer circumferential side end portion of an anode electrode is in contact with conductive polysilicon inside the end portion trench. A guard trench is separated from the end portion trench and surrounds it. A field plate provided on an outer circumferential portion of the anode electrode is separated from the anode electrode, and contacts both part of a surface of n-type drift layer in a mesa region between the end portion trench and the guard trench and the conductive polysilicon formed inside the guard trench. The semiconductor device has high withstand voltage without injection of minority carriers, and relaxed electric field intensity of the trench formed in an end portion of an active portion.
    Type: Grant
    Filed: July 29, 2013
    Date of Patent: February 17, 2015
    Assignee: Fuji Electric Co., Ltd.
    Inventors: Tomonori Mizushima, Michio Nemoto
  • Publication number: 20150041819
    Abstract: To improve switching characteristics of a transistor in which a channel is formed in an oxide semiconductor layer. A parasitic channel is formed at an end portion of the oxide semiconductor layer because a source and a drain of the transistor are electrically connected to the end portion. That is, when at least one of the source and the drain of the transistor is not electrically connected to the end portion, the parasitic channel is not formed at the end portion. In view of this, a transistor having a structure in which at least one of a source and a drain of the transistor is not or less likely to be electrically connected to an end portion of an oxide semiconductor layer is provided.
    Type: Application
    Filed: October 23, 2014
    Publication date: February 12, 2015
    Inventor: Masashi Tsubuku
  • Patent number: 8946796
    Abstract: An image sensor may include at least one device isolation layer that passes through an epitaxial layer in a semiconductor substrate to isolate pixel regions, a light-receiving element in each pixel region, and a transistor in the active region of the semiconductor substrate partitioned by the device isolation layer.
    Type: Grant
    Filed: January 28, 2013
    Date of Patent: February 3, 2015
    Assignee: Dongbu HiTek Co., Ltd.
    Inventor: Jin Youn Cho
  • Patent number: 8928130
    Abstract: A lead frame includes a plurality of leads defined by an opening extending in a thickness direction. An insulating resin layer fills the opening to entirely cover side surfaces of each lead and to support the leads. A first surface of each lead is exposed from a first surface of the insulating resin layer.
    Type: Grant
    Filed: March 21, 2013
    Date of Patent: January 6, 2015
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Toshio Kobayashi, Hiroshi Shimizu, Toshiyuki Okabe, Yasuyuki Kimura, Kazutaka Kobayashi
  • Patent number: 8912622
    Abstract: A semiconductor device includes a first-conductivity-type semiconductor substrate, a first first-conductivity-type semiconductor layer, a second first-conductivity-type semiconductor layer, a second-conductivity-type bottom layer, a Schottky metal, and a cathode electrode. The first first-conductivity-type semiconductor layer is provided on the semiconductor substrate and has a lower first-conductivity-type impurity concentration than the semiconductor substrate. The second first-conductivity-type semiconductor layer is provided on the first first-conductivity-type semiconductor layer and has a higher first-conductivity-type impurity concentration than the first first-conductivity-type semiconductor layer. The Schottky metal is provided on the second first-conductivity-type semiconductor layer. The Schottky metal contacts with partly the first first-conductivity-type semiconductor layer.
    Type: Grant
    Filed: May 29, 2013
    Date of Patent: December 16, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masatoshi Arai, Takashi Tabuchi
  • Patent number: 8878327
    Abstract: A Schottky barrier device includes a semiconductor substrate, a first contact metal layer, a second contact metal layer and an insulating layer. The semiconductor substrate has a first surface, and plural trenches are formed on the first surface. Each trench includes a first recess having a first depth and a second recess having a second depth. The second recess extends down from the first surface while the first recess extends down from the second recess. The first contact metal layer is formed on the second recess. The second contact metal layer is formed on the first surface between two adjacent trenches. The insulating layer is formed on the first recess. A first Schottky barrier formed between the first contact metal layer and the semiconductor substrate is larger than a second Schottky barrier formed between the second contact metal layer and the semiconductor substrate.
    Type: Grant
    Filed: December 28, 2012
    Date of Patent: November 4, 2014
    Assignee: Industrial Technology Research Institute
    Inventors: Cheng-Tyng Yen, Young-Shying Chen, Chien-Chung Hung, Chwan-Ying Lee
  • Patent number: 8853705
    Abstract: An image sensor including a deep guard ring and a noise blocking area and a method of manufacturing the same. The image sensor includes the deep guard ring and a deep P well surrounding the noise blocking area, thereby preventing crosstalk between adjacent pixels. In addition, an ion implantation layer is divided by the noise blocking area, so that substrate crosstalk is effectively eliminated.
    Type: Grant
    Filed: November 1, 2011
    Date of Patent: October 7, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kyung Ho Lee, Jung Chak Ahn
  • Patent number: 8822255
    Abstract: A method of manufacturing a solar cell, which includes an edge deletion step using a laser beam, and a manufacturing apparatus which is used in such a method, the method and the apparatus being capable of preventing a shunt and cracks from being generated are provided. By radiating a first laser beam to a multilayer body, which includes a transparent electrode layer, a photoelectric conversion layer, and a back electrode layer sequentially formed on a transparent substrate, from a side of the transparent substrate, the photoelectric conversion layer and the back electrode layer in a first region are removed, and by radiating a second laser beam into the region such that the second laser beam is spaced from a peripheral rim of the region, the transparent electrode layer in a second region is removed.
    Type: Grant
    Filed: August 30, 2010
    Date of Patent: September 2, 2014
    Assignee: Ulvac, Inc.
    Inventors: Yoshiaki Yamamoto, Hitoshi Ikeda, Tomoki Ohnishi, Kouichi Tamagawa
  • Patent number: 8785906
    Abstract: An area illumination inorganic electro-luminescent device including a substrate; and an array of one or more commonly addressed, light-emitting elements. Each commonly-addressed, light-emitting element includes a first electrode layer formed over the substrate, one or more light-emitting layers formed over the first electrode layer and a second electrode layer formed over the light-emitting layer. The light-emitting layers include multiple core/shell quantum dot emitters formed in a common polycrystalline semiconductor matrix, and a number of different core/shell quantum dot emitters emit light with a spectral power distribution having a peak and a FWHM bandwidth, such that the peak wavelengths differ by an amount less than or equal to the average FWHM bandwidth of the different core/shell quantum dot emitters within the range of 460 to 670 nm.
    Type: Grant
    Filed: May 30, 2007
    Date of Patent: July 22, 2014
    Assignee: Eastman Kodak Company
    Inventors: Michael E. Miller, Paul J. Kane, Ronald S. Cok
  • Patent number: 8765523
    Abstract: A method for manufacturing a semiconductor device includes the steps of preparing a substrate made of silicon carbide and having an n type region formed to include a main surface, forming a p type region in a region including the main surface, forming an oxide film on the main surface across the n type region and the p type region, by heating the substrate having the p type region formed therein at a temperature of 1250° C. or more, removing the oxide film to expose at least a part of the main surface, and forming a Schottky electrode in contact with the main surface that has been exposed by removing the oxide film.
    Type: Grant
    Filed: November 6, 2012
    Date of Patent: July 1, 2014
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Keiji Wada, Takeyoshi Masuda
  • Patent number: 8742533
    Abstract: This invention reveals a constant current semiconductor device of an N-type or a P-type epitaxial layer on a semi-insulating substrate, the device is treated by using a Schottky barrier to cut off current in conduction channels under certain bias and to provide constant current within cut-off voltage and breakdown voltage region between Schottky barrier section/ohmic contact section as the first electrode and the other ohmic contact section as the second electrode respectively, and has excellent characteristics as lower cut-off voltage (Vkp) than bipolar devices and easily gets higher constant current (Ip) by integrating several constant current units.
    Type: Grant
    Filed: August 29, 2011
    Date of Patent: June 3, 2014
    Assignee: Formosa Microsemi Co., Ltd
    Inventors: Sheau-Feng Tsai, Wen-Ping Huang, Tzuu-Chi Hu
  • Patent number: 8679954
    Abstract: A schottky diode includes a SiC substrate which has a first surface and a second surface facing away from the first surface, a semiconductor layer which is formed on the first surface of the SiC substrate, a schottky electrode which is in contact with the semiconductor layer, and an ohmic electrode which is in contact with the second surface of the SiC substrate. The first surface of the SiC substrate is a (000-1) C surface, upon which the semiconductor layer is formed.
    Type: Grant
    Filed: May 6, 2013
    Date of Patent: March 25, 2014
    Assignee: Rohm Co., Ltd.
    Inventors: Shingo Ohta, Tatsuya Kiriyama, Takashi Nakamura, Yuji Okamura
  • Patent number: 8664657
    Abstract: A circuit is disclosed. The circuit includes at least one nanostructure and a carbon interconnect formed by a substantially carbon layer, wherein the nanostructure and the carbon interconnect are directly coupled to one another.
    Type: Grant
    Filed: October 11, 2005
    Date of Patent: March 4, 2014
    Assignee: Qimonda AG
    Inventors: Georg Duesberg, Franz Kreupl, Robert Seidel, Gernot Steinlesberger
  • Patent number: 8643134
    Abstract: A method for fabricating a III-nitride semiconductor device includes providing a III-nitride substrate having a first surface and a second surface opposing the first surface, forming a III-nitride epitaxial layer coupled to the first surface of the III-nitride substrate, and removing at least a portion of the III-nitride epitaxial layer to form a first exposed surface. The method further includes forming a dielectric layer coupled to the first exposed surface, removing at least a portion of the dielectric layer, and forming a metallic layer coupled to a remaining portion of the dielectric layer such that the remaining portion of the dielectric layer is disposed between the III-nitride epitaxial layer and the metallic layer.
    Type: Grant
    Filed: November 18, 2011
    Date of Patent: February 4, 2014
    Assignee: Avogy, Inc.
    Inventors: Madhan Raj, Richard J. Brown, Thomas R. Prunty, David P. Bour, Isik C. Kizilyalli, Hui Nie, Andrew P. Edwards, Linda Romano
  • Patent number: 8637855
    Abstract: An organic light emitting device having a light emitting unit that includes an anode layer, a second wire, an insulating layer, first and second organic light emitting layers and a cathode layer is provided. The anode layer includes first and second sub-electrodes and a first wire connecting the first and second sub-electrodes that are arranged in a first direction. The second wire is disposed between the first and second sub-electrodes. The insulating layer is disposed on the first and second sub-electrodes and the second wire, and has a plurality of openings to expose the first sub-electrode, the second sub-electrode and the second wire. The first and second organic light emitting layers are disposed in two openings. The cathode layer is disposed on the first and second organic light emitting layers, and the cathode layer fills another opening to electrically connect to the second wire through the another opening.
    Type: Grant
    Filed: February 8, 2011
    Date of Patent: January 28, 2014
    Assignee: Au Optronics Corporation
    Inventors: Chen-Chi Lin, Ting-Kuo Chang, Chieh-Wei Chen
  • Patent number: 8592938
    Abstract: A method for fabricating a III-nitride semiconductor device includes providing a III-nitride substrate having a first surface and a second surface opposing the first surface, forming a III-nitride epitaxial layer coupled to the first surface of the III-nitride substrate, and removing at least a portion of the III-nitride epitaxial layer to form a first exposed surface. The method further includes forming a dielectric layer coupled to the first exposed surface, removing at least a portion of the dielectric layer, and forming a metallic layer coupled to a remaining portion of the dielectric layer such that the remaining portion of the dielectric layer is disposed between the III-nitride epitaxial layer and the metallic layer.
    Type: Grant
    Filed: November 18, 2011
    Date of Patent: November 26, 2013
    Assignee: Avogy, Inc.
    Inventors: Madhan Raj, Richard J. Brown, Thomas R. Prunty, David P. Bour, Isik C. Kizilyalli, Hui Nie, Andrew P. Edwards, Linda Romano
  • Patent number: 8546831
    Abstract: A reflection convex mirror structure is applied to a vertical light-emitting diode (LED) which comprises a P-type electrode, a permanent substrate, a binding layer, a buffer layer, a mirror layer, a P-type semiconductor layer, a light-emitting layer, an N-type semiconductor layer and an N-type electrode that are stacked in sequence. Between the P-type semiconductor layer and the mirror layer, a filler and a mirror are disposed right below the N-type electrode. The filler is made of a transparent material and has a convex surface facing the light-emitting layer. The mirror is formed on the convex surface of the filler. By utilizing the filler and the mirror to form the reflection convex mirror structure, excited light is reflected towards two sides, so that the excited light can dodge the N-type electrode without being shielded to increase light extraction efficiency.
    Type: Grant
    Filed: May 17, 2012
    Date of Patent: October 1, 2013
    Assignee: High Power Opto Inc.
    Inventors: Fu-Bang Chen, Wei-Yu Yen, Li-Ping Chou, Wei-Chun Tseng, Chih-Sung Chang
  • Patent number: 8541786
    Abstract: The invention relates to semiconductor devices and methods of manufacturing. In certain embodiments, a semiconductor device can include: a) a contact pad with pre-shaped sidewalls; b) a semiconductor chip having a terminal that is electrically connected to the contact pad, and c) a protective compound covering the semiconductor chip and at least part of the sidewalls. The sidewall can be rough or the sidewall can be tapered to facilitate locking of the contact pad into the compound.
    Type: Grant
    Filed: June 20, 2011
    Date of Patent: September 24, 2013
    Assignee: NXP B.V.
    Inventors: Rene Wilhelmus Johannes Maria van den Boomen, Jan van Kempen
  • Publication number: 20130153916
    Abstract: One embodiment of an integrated circuit includes a semiconductor body. In the semiconductor body a first trench region extends into the semiconductor body from a first surface. The integrated circuit further includes a diode including an anode region and a cathode region. One of the anode region and the cathode region is at least partly arranged in the first trench region. The other one of the anode region and the cathode region includes a first semiconductor region adjoining the one of the anode region and the cathode region from outside of the first trench region.
    Type: Application
    Filed: December 16, 2011
    Publication date: June 20, 2013
    Applicant: INFINEON TECHNOLOGIES AG
    Inventors: Joachim Weyers, Anton Mauder, Franz Hirler, Andreas Meiser, Ulrich Glaser
  • Patent number: 8450724
    Abstract: A device is provided by use of a helical substituted polyacetylene. The device comprises a structure comprised of a helical substituted polyacetylene having a helical main chain, and a pair of electrodes for applying a voltage or electric current to the structure, wherein the molecule of the helical substituted polyacetylene has a length larger than the distance between the pair of the electrodes.
    Type: Grant
    Filed: September 21, 2007
    Date of Patent: May 28, 2013
    Assignee: Canon Kabushiki Kaisha
    Inventors: Takeyuki Sone, Akira Kuriyama, Koji Yano, Otto Albrecht, Masayoshi Tabata
  • Patent number: 8441017
    Abstract: A schottky diode includes a SiC substrate which has a first surface and a second surface facing away from the first surface, a semiconductor layer which is formed on the first surface of the SiC substrate, a schottky electrode which is in contact with the semiconductor layer, and an ohmic electrode which is in contact with the second surface of the SiC substrate. The first surface of the SiC substrate is a (000-1) C surface, upon which the semiconductor layer is formed.
    Type: Grant
    Filed: June 1, 2011
    Date of Patent: May 14, 2013
    Assignee: Rohm Co., Ltd.
    Inventors: Shingo Ohta, Tatsuya Kiriyama, Takashi Nakamura, Yuji Okamura
  • Publication number: 20130032809
    Abstract: An electronic device includes a silicon carbide layer including an n-type drift region therein, a contact forming a Schottky junction with the drift region, and a p-type junction barrier region on the silicon carbide layer. The p-type junction barrier region includes a p-type polysilicon region forming a P-N heterojunction with the drift region, and the p-type junction barrier region is electrically connected to the contact.
    Type: Application
    Filed: September 6, 2012
    Publication date: February 7, 2013
    Inventors: Scott Thomas Allen, Qingchun Zhang
  • Publication number: 20120305876
    Abstract: A schottky diode, a resistive memory device including the schottky diode and a method of manufacturing the same. The resistive memory device includes a semiconductor substrate including a word line, a schottky diode formed on the word line, and a storage layer formed on the schottky diode. The schottky diode includes a first semiconductor layer, a conductive layer formed on the first semiconductor layer and having a lower work function than the first semiconductor layer, and a second semiconductor layer formed on the to conductive layer.
    Type: Application
    Filed: December 20, 2011
    Publication date: December 6, 2012
    Inventors: Seung Beom BAEK, Young Ho LEE, Jin Ku LEE, Mi Ri LEE
  • Patent number: 8304783
    Abstract: Hybrid semiconductor devices including a PIN diode portion and a Schottky diode portion are provided. The PIN diode portion is provided on a semiconductor substrate and has an anode contact on a first surface of the semiconductor substrate. The Schottky diode portion is also provided on the semiconductor substrate and includes a polysilicon layer on the semiconductor substrate and a ohmic contact on the polysilicon layer. Related Schottky diodes are also provided herein.
    Type: Grant
    Filed: June 3, 2009
    Date of Patent: November 6, 2012
    Assignee: Cree, Inc.
    Inventors: Saptharishi Sriram, Qingchun Zhang
  • Patent number: 8154048
    Abstract: In a pn junction diode having a conductivity modulating element provided on a first principal surface of a semiconductor substrate, when an impurity concentration of a p type impurity region is lowered to shorten a reverse recovery time, hole injection is suppressed, thereby causing a problem that a forward voltage value is increased at a certain current point. Moreover, introduction of a life time killer to shorten the reverse recovery time leads to a problem of increased leak current. On an n? type semiconductor layer that is a single crystal silicon layer, a p type polycrystalline silicon layer (p type polysilicon layer) is provided. Since the polysilicon layer has more grain boundaries than the single crystal silicon layer, an amount of holes injected into the n? type semiconductor layer from the p type polysilicon layer in forward voltage application can be suppressed.
    Type: Grant
    Filed: March 9, 2009
    Date of Patent: April 10, 2012
    Assignees: Semiconductor Components Industries, LLC, SANYO Semiconductor Co., Ltd.
    Inventors: Seiji Miyoshi, Tetsuya Okada
  • Patent number: 8154025
    Abstract: A CMOS device and method of fabrication are disclosed. The present invention utilizes Schottky barrier contacts for source and/or drain contact fabrication within the context of a CMOS device and CMOS integrated circuits, to eliminate the requirement for halo/pocket implants, shallow source/drain extensions to control short channel effects, well implant steps, and complex device isolation steps. Additionally, the present invention eliminates the parasitic bipolar gain associated with CMOS device operation, reduces manufacturing costs, tightens control of device performance parameters, and provides for superior device characteristics as compared to the prior art. The present invention, in one embodiment, uses a silicide exclusion mask process to form the dual silicide Schottky barrier source and/or drain contact for the complimentary PMOS and NMOS devices forming the CMOS device.
    Type: Grant
    Filed: September 18, 2009
    Date of Patent: April 10, 2012
    Assignee: Avolare 2, LLC
    Inventors: John P. Snyder, John M. Larson
  • Patent number: 8063406
    Abstract: Various illustrative embodiments of methods for manufacturing a semiconductor device are described. These methods may include, for example, forming a first polysilicon layer above a substrate, wherein the first polysilicon layer comprises a doped portion, and forming a second polysilicon layer over a surface of the first polysilicon layer. Also, various illustrative embodiments of semiconductor devices are described that may be manufactured such as by the various methods described herein.
    Type: Grant
    Filed: October 22, 2010
    Date of Patent: November 22, 2011
    Assignee: Infineon Technologies AG
    Inventors: Haoren Zhuang, Matthias Lipinski, Jingyu Lian, Chandrasekhar Sarma
  • Patent number: 8048784
    Abstract: Methods for manufacturing a semiconductor device include forming a seed layer containing a silicon material on a substrate. An amorphous silicon layer containing amorphous silicon material is formed on the seed layer. The amorphous silicon layer is doped with an impurity. A laser beam is irradiated onto the amorphous silicon layer to produce a phase change of the amorphous silicon layer and change the amorphous silicon layer into a single-crystal silicon layer based on the seed layer.
    Type: Grant
    Filed: September 23, 2008
    Date of Patent: November 1, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Pil-Kyu Kang, Yong-Hoon Son, Jong-Wook Lee
  • Patent number: 8048763
    Abstract: A deep isolation trench extending from the main surface of a substrate to a desired depth is formed on the substrate with an insulating film in buried in it to form a through isolation portion. Subsequently, after a MOSFET is formed on the main surface of the substrate, an interlayer insulating film is deposited on the main surface of the substrate. Then, a deep conduction trench extending from the upper surface of the interlayer insulating film to a depth within the thickness of the substrate is formed in a region surrounded by the through isolation potion. Subsequently, a conductive film is buried in the deep conduction trench to form through interconnect portion. Then, after the undersurface of the substrate is ground and polished to an extent not to expose the through isolation portion and the through interconnect portion, wet etching is performed to an extent to expose parts of the lower portion of each of the through isolation portion and the through interconnect portion.
    Type: Grant
    Filed: March 5, 2010
    Date of Patent: November 1, 2011
    Assignee: Honda Motor Co., Ltd.
    Inventors: Nobuaki Miyakawa, Takanori Maebashi, Takahiro Kimura
  • Patent number: 8043912
    Abstract: A semiconductor device is provided with a semiconductor substrate comprising element isolation regions and an element region surrounded by the element isolation regions, a first polysilicon layer formed in the element region of the semiconductor substrate, an element-isolating insulation film formed in the element isolation region of the semiconductor substrate, a second polysilicon layer formed on the element-isolating insulation film, a first silicide layer formed on the first polysilicon layer. And the device further comprising a second silicide layer formed on the second polysilicon layer and being thicker than the first silicide layer.
    Type: Grant
    Filed: October 25, 2007
    Date of Patent: October 25, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Satoshi Matsuda
  • Patent number: 8030193
    Abstract: To fabricate a Schottky barrier diode in which a decrease in on current due to parasitic resistance is suppressed, variations in on current are suppressed, and an increase in off current is suppressed. The fabricating method includes the steps of forming an island-shape semiconductor film; doping the island-shape semiconductor film with a first impurity element to form a first impurity region; forming an insulating film so as to cover the island-shape semiconductor film; etching the insulating film to form a first opening and a second opening that partly expose the first impurity region; forming a mask over the insulating film so as to cover the first opening and expose the second opening; doping the first impurity region with a second impurity element to form a second impurity region; and forming a first wiring in contact with the first impurity region exposed at the first opening, and forming a second wiring in contact with the second impurity region exposed at the second opening.
    Type: Grant
    Filed: December 13, 2007
    Date of Patent: October 4, 2011
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Atsuo Isobe, Suguru Ozawa
  • Publication number: 20110215338
    Abstract: An electronic device includes a silicon carbide layer including an n-type drift region therein, a contact forming a junction, such as a Schottky junction, with the drift region, and a p-type junction barrier region on the silicon carbide layer. The p-type junction barrier region includes a p-type polysilicon region forming a P-N heterojunction with the drift region, and the p-type junction barrier region is electrically connected to the contact. Related methods are also disclosed.
    Type: Application
    Filed: March 8, 2010
    Publication date: September 8, 2011
    Inventor: Qingchun Zhang
  • Patent number: 7999346
    Abstract: A semiconductor device provided with a silicon carbide semiconductor substrate, and an ohmic metal layer joined to one surface of the silicon carbide semiconductor substrate in an ohmic contact and composed of a metal material whose silicide formation free energy and carbide formation free energy respectively take negative values. The ohmic metal layer is composed of, for example, a metal material such as molybdenum, titanium, chromium, manganese, zirconium, tantalum, or tungsten.
    Type: Grant
    Filed: June 17, 2010
    Date of Patent: August 16, 2011
    Assignee: Rohm Co., Ltd.
    Inventors: Yuji Okamura, Masashi Matsushita
  • Patent number: 7999267
    Abstract: A display device includes a substrate having a display region and a driver region; a gate line and a data line crossing each other to define a pixel region in the display region, the pixel region having a pixel electrode; an insulation layer between the gate line and the data line; a first thin film transistor in the display region; and a second thin film transistor having a first polarity and a third thin film transistor having a second polarity in the driver region, wherein the pixel electrode, the gate line and the gate electrodes of the first to third thin film transistors have a double-layer structure in which a metal layer is formed on a transparent conductive layer, and the transparent conductive layer of the pixel electrode is exposed through a transmission hole passing through the insulation layer and the metal layer in the pixel region.
    Type: Grant
    Filed: November 3, 2009
    Date of Patent: August 16, 2011
    Assignee: LG Display Co., Ltd.
    Inventor: Yong In Park
  • Patent number: 7999266
    Abstract: A semiconductor device including polysilicon (poly-Si) and method of manufacturing the same are provided. The semiconductor device includes a TaNx material layer and a poly-Si layer formed on the TaNx material layer. The semiconductor device including poly-Si may be manufactured by forming a TaNx material layer and forming a poly-Si layer by depositing silicon formed on the TaNx material layer and annealing silicon.
    Type: Grant
    Filed: December 11, 2007
    Date of Patent: August 16, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Wenxu Xianyu, Jung-hyun Lee, Hyung-jin Bae, Young-soo Park
  • Patent number: 7989816
    Abstract: A semiconductor device is, constituted by: a nitride group semiconductor functional layer which includes a first nitride group semiconductor region, a second nitride group semiconductor region provided on the first nitride group semiconductor region by a hetero junction, and a two-dimensional carrier gas channel near the hetero junction of the first nitride group semiconductor region; a first main electrode and a second main electrode connected to the two-dimensional carrier gas channel by ohmic contact; and a gate electrode disposed between the first main electrode and the second main electrode. The nitride group semiconductor region has different thicknesses between the second main electrode and the gate electrode, and between the first main electrode and the gate electrode.
    Type: Grant
    Filed: May 22, 2009
    Date of Patent: August 2, 2011
    Assignee: Sanken Electric Co., Ltd.
    Inventor: Ken Sato
  • Patent number: 7973318
    Abstract: A schottky diode includes a SiC substrate which has a first surface and a second surface facing away from the first surface, a semiconductor layer which is formed on the first surface of the SiC substrate, a schottky electrode which is in contact with the semiconductor layer, and an ohmic electrode which is in contact with the second surface of the SiC substrate. The first surface of the SiC substrate is a (000-1) C surface, upon which the semiconductor layer is formed.
    Type: Grant
    Filed: October 18, 2007
    Date of Patent: July 5, 2011
    Assignee: Rohm Co., Ltd.
    Inventors: Shingo Ohta, Tatsuya Kiriyama, Takashi Nakamura, Yuji Okamura
  • Publication number: 20100308337
    Abstract: Hybrid semiconductor devices including a PIN diode portion and a Schottky diode portion are provided. The PIN diode portion is provided on a semiconductor substrate and has an anode contact on a first surface of the semiconductor substrate. The Schottky diode portion is also provided on the semiconductor substrate and includes a polysilicon layer on the semiconductor substrate and a ohmic contact on the polysilicon layer. Related Schottky diodes are also provided herein.
    Type: Application
    Filed: June 3, 2009
    Publication date: December 9, 2010
    Applicant: Cree, Inc.
    Inventors: Saptharishi Sriram, Qingchun Zhang
  • Patent number: 7800093
    Abstract: An integrated circuit including a memory cell includes a vertical bipolar select device including a base and an emitter. The memory cell includes a resistive memory element coupled to the emitter and a buried metallized word line contacting the base.
    Type: Grant
    Filed: February 1, 2007
    Date of Patent: September 21, 2010
    Assignee: Qimonda North America Corp.
    Inventors: Thomas Happ, Jan Boris Philipp
  • Patent number: 7700975
    Abstract: Metal-Semiconductor-Metal (“MSM”) photodetectors and methods to fabricate thereof are described. The MSM photodetector includes a thin heavily doped (“delta doped”) layer deposited at an interface between metal contacts and a semiconductor layer to reduce a dark current of the MSM photodetector. In one embodiment, the semiconductor layer is an intrinsic semiconductor layer. In one embodiment, the thickness of the delta doped layer is less than 100 nanometers. In one embodiment, the delta doped layer has a dopant concentration of at least 1×1018 cm?3. A delta doped layer is formed on portions of a semiconductor layer over a substrate. Metal contacts are formed on the delta doped layer. A buffer layer may be formed between the substrate and the semiconductor layer. In one embodiment, the substrate includes silicon, and the semiconductor layer includes germanium.
    Type: Grant
    Filed: March 31, 2006
    Date of Patent: April 20, 2010
    Assignee: Intel Corporation
    Inventors: Titash Rakshit, Miriam Reshotko
  • Patent number: 7692222
    Abstract: A semiconductor structure and method wherein a recess is disposed in a surface portion of a semiconductor structure and a dielectric film is disposed on and in contract with the semiconductor. The dielectric film has an aperture therein. Portions of the dielectric film are disposed adjacent to the aperture and overhang underlying portions of the recess. An electric contact has first portions thereof disposed on said adjacent portions of the dielectric film, second portions disposed on said underlying portions of the recess, with portions of the dielectric film being disposed between said first portion of the electric contact and the second portions of the electric contact, and third portions of the electric contact being disposed on and in contact with a bottom portion of the recess in the semiconductor structure. The electric contact is formed by atomic layer deposition of an electrically conductive material over the dielectric film and through the aperture in such dielectric film.
    Type: Grant
    Filed: November 7, 2006
    Date of Patent: April 6, 2010
    Assignee: Raytheon Company
    Inventors: Kamal Tabatabaie, Robert B. Hallock
  • Patent number: 7642556
    Abstract: A compound semiconductor element is provided which electrically connects an electrode 3 formed on one main surface 2a of a compound semiconductor region 2 with a substrate 5 to fix an electric potential of substrate 5 at an electric potential of electrode 3, thereby preventing fluctuation in electric potential of substrate 5 under the changing operating condition of the device for stabilization in electric property of the device. Also, formed between compound semiconductor region 2 and substrate 5 is an insulating layer 6 for blocking a leakage current which may flow longitudinally between one main surface 2a of compound semiconductor region 2 and substrate 5 so that sufficiently high withstand voltage property can be given between compound semiconductor region 2 and substrate 5.
    Type: Grant
    Filed: September 19, 2007
    Date of Patent: January 5, 2010
    Assignee: Sanken Electric Co., Ltd.
    Inventor: Shinichi Iwakami
  • Patent number: 7508014
    Abstract: A field effect transistor including an i-type first semiconductor layer and a second semiconductor layer formed on the first semiconductor layer and having a band gap energy higher in magnitude than that of the first semiconductor layer. The first semiconductor layer and second semiconductor layer are each made of a gallium nitride-based compound semiconductor layer. A gate electrode is formed on the second semiconductor layer and a second electrode is formed on the first semiconductor layer. Thus, the field effect transistor is constructed in such a manner as the first semiconductor layer and second semiconductor layer are interposed between the gate electrode and the second electrode. Thus field effect transistor is able to discharge the holes that are accumulated in the channel from the elemental structure and to improve the withstand voltage of the field effect transistor.
    Type: Grant
    Filed: November 16, 2005
    Date of Patent: March 24, 2009
    Assignee: Nichia Corporation
    Inventor: Masashi Tanimoto
  • Patent number: 7476896
    Abstract: A thin film transistor (TFT) and a method of fabricating the same, in which a fabrication process is simplified and damage to a gate insulating layer is decreased. The method of fabricating the TFT includes forming at least one buffer layer on a substrate, forming a first semiconductor layer formed on the buffer layer and a second semiconductor layer by depositing a semiconductor doped with a dopant on the first semiconductor layer, patterning the second semiconductor layer to form source and drain regions, forming a gate insulating layer on the source and drain regions, and forming a gate electrode on the gate insulating layer.
    Type: Grant
    Filed: February 23, 2006
    Date of Patent: January 13, 2009
    Assignee: Samsung SDI Co., Ltd.
    Inventors: Dae Chul Choi, Byoung Deog Choi, Choong Youl Im
  • Patent number: 7411218
    Abstract: A Schottky barrier silicon carbide device has a Re Schottky metal contact. The Re contact 27 is thicker than 250 Angstroms and may be between 2000 and 4000 Angstroms. A termination structure is provided by ion milling an annular region around the Schottky contact.
    Type: Grant
    Filed: March 18, 2005
    Date of Patent: August 12, 2008
    Assignee: Fairchild Semiconductor Corporation
    Inventors: William F. Seng, Richard L. Woodin, Carl Anthony Witt
  • Patent number: 7400030
    Abstract: In the present invention, there is provided semiconductor devices such as a Schottky UV photodetector fabricated on n-type ZnO and MgxZn1-xO epitaxial films. The ZnO and MgxZn1-xO films are grown on R-plane sapphire substrates and the Schottky diodes are fabricated on the ZnO and MgxZn1-xO films using silver and aluminum as Schottky and ohmic contact metals, respectively. The Schottky diodes have circular patterns, where the inner circle is the Schottky contact, and the outside ring is the ohmic contact. Ag Schottky contact patterns are fabricated using standard liftoff techniques, while the Al ohmic contact patterns are formed using wet chemical etching. These detectors show low frequency photoresponsivity, high speed photoresponse, lower leakage current and low noise performance as compared to their photoconductive counterparts. This invention is also applicable to optical modulators, Metal Semiconductor Field Effect Transistors (MESFETs) and more.
    Type: Grant
    Filed: January 25, 2005
    Date of Patent: July 15, 2008
    Assignee: Rutgers, the State University of New Jersey
    Inventors: Yicheng Lu, Haifeng Sheng, Sriram Muthukumar, Nuri William Emanetoglu, Jian Zhong, Shaohua Liang