Abstract: The power module housing comprises two electrically insulating housing elements (1, 2) that are attached to each other. A first of said housing elements (2) comprises at least two openings (24) for electric power terminals (31, 32) and a slot-like recess (23). Between the openings (24) three insulating walls (11, 21, 22) are arranged on and perpendicular to a surface of the housing. One insulating wall (11) is part of a second of said housing elements (1) and is inserted into the recess (23) in said first housing element (2), while an at least one second of said insulating walls (21, 22) is part of the first housing element (2). The insulating walls between the openings for the power terminals allow a compact arrangement of the terminals.

Abstract: A multichip wirebond-less integrated circuit and power die package is based on a folded single-layer flex circuit. The package is formed with metal-studbumped power dies and IC's flipchiped to a patterned flex substrate. Extensions of the flex substrate are folded and attached to the backside of the dies for electrical and/or thermal contact. I/O pins are along the periphery of the package for standard SMT mounting while heatspreaders are attached to both sides of the package for double-sided cooling.

Abstract: The invention encompasses microelectronic package lids, heat spreaders, and semiconductor packages comprising microelectronic lids or heat spreaders. In particular aspects of the present invention, a microelectronic lid comprises a material having a rectangular peripheral shape that defines 4 peripheral sides. Further, the lid has projecting peripheral rails along less than all of the peripheral edge. For instance, the lid can have projecting peripheral rails along only 2 of the sides. Alternatively, such microelectronic lid can be described as comprising a generally rectangular shape defining four peripheral edges, with two of the edges having a greater thickness than the other two edges.

Abstract: A semiconductor package including a conical or pyramidal vapor chamber body coupled to a package bottom to enclose a vapor chamber within which are disposed a semiconductor die and working fluid. A matching conical or pyramidal heatsink is coupled to the vapor chamber body. The conical or pyramidal shape allows a tight fit and good thermal performance, without undue force being applied to the package bottom, and further allows a variety of heatsinks to be used with a standardized shape vapor chamber body.

Abstract: A semiconductor device according to one embodiment includes a substrate, a semiconductor chip arranged on the substrate, a first electrode formed in the substrate and connected to the semiconductor chip, a concave portion provided on a side of the substrate, the concave portion being formed to a depth not to reach a top of the substrate from a back of the substrate, and at least part of the first electrode being exposed to the concave portion, and a metal layer formed on the at least part of the first electrode.

Abstract: A manufacturing method using a modular substrate-based processing scheme for producing semiconductor devices, provides multiple modular processing units which may be arranged together to form any of various cohesive processing units or individually or sequentially processed through standard semiconductor processing equipment. The cohesive processing units are processed unitarily providing for multiple modular processing units to be processed simultaneously. The modular processing units may be formed of a thick semiconductor substrate or a semiconductor substrate mounted on a further substrate such as a ceramic material. The modular processing units may each contain ribs, grooves, posts or other features to aid in handling and placement of the individual units.

Abstract: A high power semiconductor device comprising a heat sink on which a semiconductor element is mounted, and a sidewall which is attached onto the heat sink and which surrounds the semiconductor element. One of the heat sink and the sidewall has a plurality of projections formed on a joining surface thereof to be joined to an opposing surface of the other one of the heat sink and the sidewall. A gap is formed by the projections between the sidewall and the heat sink when the sidewall is disposed on the heat sink. The sidewall and the heat sink are joined together by thermally curing low elasticity liquid resin which fills at least the gap formed by the projections between the sidewall and the heat sink. The projections are formed, for example, on the heat sink.

Abstract: A support member for packaging a light-emitting element is provided at a top with a cup-shaped recess, which has a flat bearing bottom surface and a curved inner wall surface for stably bearing the light-emitting element therein. The support member is also provided with a plurality of venting and heat-dissipating holes irregularly distributed around the cup-shaped recess. A temperature difference between any two of these venting and heat-dissipating holes produces a minor turbulent airflow to naturally and quickly dissipate heat produced by the light-emitting element, so that a temperature rise of the light-emitting element is effectively reduced to maintain normal operation of the light-emitting element without decreasing the usable life and reliability thereof.

Abstract: A power module for low voltage applications, which does not include an insulated metal substrate is disclosed. The module includes a power shell and a plurality of lead frames each lead frame including a conductive pad on which one or more MOSFETs may be electrically mounted. The MOSFETs are electrically connected via wire bonds.

Abstract: An apparatus on a wafer, comprising; a first metal layer of a wall, a second metal layer of the wall, a third metal layer of the wall comprising; one or more base frames, a fourth metal layer of the wall comprising; one or more vertical frame pairs each on top of the one or more base frames and having a pass-thru therein, a fifth metal layer of the wall comprising; one or more top frames each over the pass-thru; and a metal lid.

Abstract: The thermomechanical stress sensitivity of ball grid array (BGA) solder connections is significantly reduced, when the solder connections solidify in column-like contours after the reflow process—a result achieved by using the solder material in tapered openings of a thick sheet-like elastic polymer adhered to the BGA substrate and selected for its characteristics of non-wettability to solder and volumetric shrinkage greater than solder.

Abstract: A stack of integrated circuits in thin small outline packages (TSOP's) is constructed with an air space in between adjacent packages. The TSOP's have a plurality of connection terminals extending therefrom. A lead frame is disposed adjacent to the packages, positioned medially of the air space and having a plurality of connection terminals in registration with and in electric contact with the plurality of TSOP connection terminals. The TSOP's have a chip select terminal and several unused terminals. The lead frame has a strain-relieved conductor extending between the chip select terminal on a TSOP higher in the stack to the adjacent TSOP lower in the stack. Moreover, TSOP locating surfaces are included on the lead frame in the finished stack.

Abstract: In accordance with a press contact type semiconductor device, a metallic body having macroscopic vacancies inside is arranged between a main electrode of the semiconductor device and a main electrode plate, or between an intermediate electrode plate arranged on a respective main plane of the semiconductor element and a main electrode plate.

Abstract: A method for singulating a substrate containing semiconductor components is performed using a nest for holding the substrate, a prestage alignment base for aligning the substrate during a prestage alignment step, and a vacuum cutting base for holding the nest and the substrate during a cutting step. The prestage alignment base includes locator pins configured to engage locator openings on the substrate to align the substrate on the nest. As the cutting base does not include the locator pins, the cutting step can be performed without saw scrap collecting on the locator pins. A system for performing the method includes the nest and the prestage alignment base having the locator pins configured to engage the locator openings on the substrate. The system also includes the sawing base which includes pedestals with vacuum conduits for holding the substrate stationary on the nest for sawing.

Abstract: A groove having a V-shaped section is provided on a bonding surface of an IC chip being as a first small part, while an elongate projection having a V-shaped section to engage with the groove of the first IC chip is provided on a corresponding portion of a bonding surface of an IC chip being as a second small part. Then, the IC chips are bonded together by the action of a holding force resulting from fitting the elongate protection of the second IC chip to the groove of the first IC chip, together with a bonding force produced between the bonding surfaces by interatomic force and metallic bond.

Abstract: A method for processing a semiconductor substrate is disclosed. The method includes providing a mask having an aperture on a semiconductor substrate having a conductive region. An aperture in the mask is disposed over the conductive region. A pre-formed conductive column is placed in the aperture and is bonded to the conductive region.

Abstract: An electronic packaging structure and method of forming thereof wherein the structure is constituted of a modular arrangement which reduces stresses generated in a chip, underfill, and ball grid array connection with a flexible substrate in the form of an organic material, which stresses may result in potential delamination due to thermally-induced warpage between the components of the modular arrangement.

Abstract: An electronic component having recesses on side faces of its package for housing an electric element therein. A metal layer that does not reach the bottom end of the package is formed on the surface of the recess. The metal layer has excellent wettability to a brazing material and helps extra material flow into the recess easily. In addition, the interface between the top end face of the recess and the side face is curved to make the brazing material flow into the recess easily. When the opening of the package is sealed with a lid using the brazing material, the extra brazing material flows into the recess. This prevents the brazing material from protruding outside of the package and thus improves dimensional accuracy of the electronic component. Therefore, mounting accuracy of the electronic component can be improved and short circuit can be prevented.

Abstract: A co-package semiconductor device including an outer clip in the form of a metal can includes also two semiconductor dies, at least one of which uses the outer clip as an electrical connector. An inner clip is used to dispose one of the dies within the outer clip. The inner clip may be insulated from the outer clip by an insulating layer.

Abstract: The present invention is directed toward methods and apparatuses for encapsulating a microelectronic die or another type of microelectronic device. One aspect of the present invention is directed toward packaging a microelectronic die that is attached to either a first surface or a second surface of a substrate. The die can be encapsulated by positioning the die in a cavity of a substrate and sealing the substrate to the substrate. The method can further include injecting an encapsulation compound into the cavity at a first end of the substrate to move along the first surface of the substrate. This portion of the compound defines a first flow of compound along the first surface that moves in a first direction from a first end of the substrate toward a second end of the substrate.

Abstract: A mold (1) for a semiconductor chip (9) has two mold halves (2, 3). One mold half (3) includes sealing means (10) adapted to exert a sealing pressure between a surface of the mold and a surface (18) of a substrate (8) located in the mold (1) during a molding operation.

Abstract: An improved semiconductor chip package capable of independently aligning with testing equipment during the manufacturing phase of electrical testing. Independent alignment is realized by directly connecting the semiconductor chip package to the test alignment apparatus by fitting together two substantially conforming surfaces, one on the chip package and one on the alignment apparatus. The conforming surfaces are arranged so that only one matable position is achievable. The substantially conforming surfaces can equate to three substantially conical indentations on the chip package and three substantially conical protrusions or protuberances of substantially conforming size and depth extending from the alignment apparatus.

Abstract: A packaged electronic device includes connection contacts that are formed on the contact pads on the second surface of the substrate. In contrast to the prior art, the connection contacts are not solder contacts but are formed of nickel/aluminum plated copper and are therefore harder and less malleable and subject to deformation than prior art solder balls. The connection contacts are formed to align with, and contact, attachment pads formed on the motherboard or other system component. A tension device is then used to mechanically attach the packaged electronic device of the invention to the motherboard.

Abstract: An interconnect substrate includes an upper substrate (30) on which an upper interconnect pattern (32) is formed, and a lower substrate (40) on which a lower interconnect pattern (42) is formed and to which the upper substrate (30) is adhered. The lower interconnect pattern (42) includes first lower land section (53) which are formed in the center portion of a first region (50) and are connected to the upper interconnect pattern (32), second lower land sections (64) which are formed in a second region (60) and are electrically connected to a second electronic chip, and lower connection sections (45) which run outside the center portion in the first region (50) than the center portion and connect the first lower land section (53) to the second lower land section (64).

Abstract: A package for an integrated circuit chip is disclosed, along with structures and methods for making and mounting the package. An exemplary embodiment of the package includes a molded body having leads embedded therein with an aperture adjacent each of the leads. A portion of each lead that is internal to the periphery of the package body is exposed through the corresponding aperture. Electrical connection to the leads is made within the respective corresponding apertures.

Abstract: A semiconductor device of the present invention includes: a semiconductor chip having an electrode at a periphery thereof, a wiring board having a first surface and a second surface, the first surface of the wiring board being attached to the semiconductor chip, the board having an opening to expose the electrode of said semiconductor chip, and an external terminal arranged on the second surface of the wiring board and arranged inside of the wiring board compared with the opening. The semiconductor device has a wiring line laid on the second surface of the wiring board to electrically connect the electrode and the external terminal. The wiring line extends outside of said wiring board from the external terminal and detours said opening to reach the electrode.

Abstract: A structure and technique for forming an I/C chip module and circuit card construction is provided. An I/C chip module having a flexible substrate, with first and second opposite sides concave, results from the CTE mismatch between the I/C chip and substrate. The I/C chip module is mounted on a flexible circuit card by solderball connection. The curvature of the I/C chip module causes the circuit card to curve correspondingly. A heatsink in thermal contact with the I/C chip places pressure on the I/C chip module in a direction to decrease the curvature. A rigid backing member retains the circuit card, generating a curved space between the backing member and the circuit card. A leaf spring applies pressure to the I/C chip module against the backing member. A compliant member is interposed between the backing member and the circuit board filling a portion of the curved space therebetween.

Abstract: A semiconductor device using a lead frame as a wiring base member, in which lead electrodes connected to a semiconductor chip through a connecting lead are arranged radially around the semiconductor chip having an upper surface and an under surface. The semiconductor chip, connecting leads, and lead electrodes are integrally sealed in a resin. Each of the lead electrodes includes a thin internal lead portion having a connection part on an upper surface side, and a thick external electrode portion protruding toward an under surface side to form a connection part. The resin has an underside which is substantially co-planar with the under surface of the internal lead portion of the lead electrodes, and the external electrode portion protrudes from the underside of the resin.

Abstract: A semiconductor chip package and method of providing same including a semiconductor die, an insulating package body encapsulating the semiconductor die, and an aperture extending through and between opposing sides of the package body, wherein at least a portion of an inner surface of the aperture is electrically connected to the semiconductor die.

Abstract: A multi-functional memory chip connector includes an insulation frame having a memory chip insertion portion, a plurality of connecting slots on an inside surface of the memory chip insertion portion for electrically coupling a variety of memory chips, and a plurality of connector terminals extending from the connecting slots and distributed to three sides of the insulation frame for electrically coupling with a circuit board. The connector also includes a plurality of card insertion slots for receiving a plurality of memory chips with various connection specifications, and an upper lid for mounting on the top of the insulation frame.

Abstract: A transistor (200) is provided with a semiconductor chip (1) inside a resin package (20). An outer lead (41, 42, 43, 44) is arranged on a first side surface (23) of the resin package (20) to serve as an external drain electrode. A lead frame (5) includes the outer lead (41, 42, 43, 44) and a sheet-like portion (51). The sheet-like portion (51) is connected to a first surface (1a) of the semiconductor chip (1) for holding a drain electrode. An outer lead (45, 46, 47, 48) is arranged on a second side surface (24) of the resin package (20) to serve as an external source electrode. The outer lead (45, 46, 47, 48) is connected by a wire (4) to a second surface (1b) of the semiconductor chip (1) for holding a source electrode. An ejector pin site (22) formed on a top surface (21) of the resin package (20) is located on the side of the first side surface (23).

Abstract: Apparatus and methods for forming semiconductor assemblies. An interposer includes a perimeter wall surrounding at least a portion of an upper surface thereof to form a recess. An array of electrical connection pads is located within the recess. A semiconductor die can be flip chip attached to the interposer by at least partial insertion of the semiconductor die within the recess with discrete conductive elements between bond pads of the semiconductor die and electrical connection pads of the interposer. The electrical connection pads communicate with a number of other electrical contact pads accessible elsewhere on the interposer, preferably on a lower surface thereof. A low viscosity underfill encapsulant is disposed between the semiconductor die and the interposer and around the discrete conductive elements by permitting the same to flow into the space between the die and the perimeter wall.

Abstract: A plurality of leads are arrayed around an island (1) to which a semiconductor chip (3) is bonded. A plurality of first wires (4) interconnects each electrode terminal of the semiconductor chip (3) and each of the plurality of leads (2), while a second wire (4b) electrically connects a ground terminal of the semiconductor chip (3) with the island (1). This island (1) is so formed that a slit (1c) may be interposed between a wire bonding portion (1b) and a die pad portion (1a). In this configuration, the island and the leads are covered by a resin package (6) in such a manner that their back faces may be exposed from this package. As a result, even in a QFN type resin-packaged semiconductor device in which the back faces of the island and the leads are exposed for direct soldering at the time of mounting, the wire bonded to the island can be prevented from being disconnected or cut off, thus making that resin-packaged semiconductor device more stable in quality.

Abstract: A chip stack comprising a flex circuit which itself comprises a flexible substrate having opposed, generally planar top and bottom surfaces. Disposed on the top surface of the substrate in spaced relation to each other are at least first and second top conductive patterns. Similarly, disposed on the bottom surface of the substrate in spaced relation to each other are at least first and second bottom conductive patterns. The first top and bottom conductive patterns are electrically connected to each other, as are the second top and bottom conductive patterns. At least one top chip package including a first packaged chip is electrically connected to the first top conductive pattern, with at least one bottom chip package including a second packaged chip being electrically connected to the second bottom conductive pattern. The substrate is folded such that the second top conductive pattern is electrically connected to the top chip package.

Abstract: A semiconductor integrated circuit device and a printed wired board which self-align to each other in an exact and precise manner. The semiconductor integrated circuit device has conductive bumps. The printed wired board has conductive recessed members at positions corresponding to the conductive bumps. Each of the conductive bumps is fitted into the corresponding conductive recessed member so that the printed wired board is aligned with the semiconductor integrated circuit device.

Abstract: A coin-shaped IC tag which can be endowed with a predetermined weight is described. The coin-shaped IC tag ensures a normal operation and affords a satisfactory feeling of weightiness as a value medium. The coin-shaped IC tag comprises an IC tag core. The IC tag core comprises an IC packaging base member including a base and an electronic circuit for communicating data and for recording data, the electronic circuit mounted on the base. The IC tag core also comprises a high specific gravity resin layer joined to the IC packaging base member.

Abstract: A flexible carrier substrate assembly or module that facilitates stacking of multiple carrier substrates bearing semiconductor dice for high density electronic systems. After the dice are placed on the flexible substrate, a flexible support frame may be applied to the flexible substrate. The support frame includes conductive paths therethrough to connect to circuit traces running from the dice on the substrate to the substrate perimeter to interconnect superimposed carrier substrates. The flexible carrier substrates may be bent to a radius of any given curvature to conform to various non-planar regular and irregular surfaces. Furthermore, since the frame as well as the substrate may be flexible, multiple, flexible substrate assemblies may be stacked one on top of another wherein an upper assembly has a different radius than a lower module and any intermediate assemblies have progressively differing radii from bottom to top position.

Abstract: The lead frame has a spring element, which can be compressed during the injection molding of the package by an injection mold. The resultant resilience has the effect that a contact surface of the lead is pressed against an inside wall of the injection mold. The biasing of the contact surface against the inside wall prevents polymer flash from forming on the contact surface. Also, the spring element fixes the lead during the injection operation and anchors the lead in the completed package. Hold-down pins within the injection mold are thus obviated.

Abstract: Wire bonding or printed wiring board leads or, alternatively, lead frames or equivalents thereof are used to electrically connect external electrodes of high withstand voltage capacitors formed on a plurality of semiconductor chips. A driver circuit for signal transmission or receiver circuit for signal receipt formed on the semiconductor chips are electrically connected with substrate-side electrodes of said high withstand voltage capacitors, causing the plurality of semiconductor chips to be received within either a single package or a single module. Using this arrangement, a semiconductor device is capable of achieving both dielectricity and size reduction.

Abstract: The present invention provides a semiconductor device comprising: a tape wiring substrate; a semiconductor element mounted one main surface of the tape wiring substrate; a solder ball or pump electrode provided on the other surface of the tape wiring substrate while electrically connected with a predetermined position of the main surface of the tape wiring substrate including the semiconductor element; and a hollow pipe-shaped substrate; wherein the tape wiring substrate is wound around the hollow pipe-shaped substrate with the main surface arranged toward the hollow pipe-shaped substrate.

Abstract: An apparatus for enclosing logic chips includes a substrate upon which a logic chip is mounted and a mold cap disposed upon the substrate and covering the logic chip. The mold cap includes at least one extension of sufficient size and shape to provide structural support to a corner section of the substrate.

Abstract: A method of manufacturing a COF package comprises the steps of providing a resin film substrate with a hole for receiving a chip, providing an IC chip having electrodes, inserting the IC chip into the hole so as to fix it with its electrodes exposed above the substrate surface, and forming a circuit pattern on the substrate surface for connection with the electrodes. The hole and the IC chip are tapered, and the IC chip is secured in the hole with sealant or adhesive.

Abstract: A semiconductor device having a plated heat sink (PHS) layer on the back surface, preventing a short circuit between a bonding wire, and a first metal layer. A method of making a semiconductor device including forming a catalyst layer on a bottom of a first separation groove in the front surface of a semiconductor substrate, and forming the first metal layer selectively in the first separation groove by electroless plating, using the catalyst layer as a catalyst.

Abstract: To increase the reliability of a non-contact IC card for use in such applications as a door key, etc., two separate combinations of an IC chip and an antenna coil coupled to that chip are provided in the card, with each IC chip storing the same information, such as a key code. Since the probability of both of the IC chips being damaged concurrently due to application of external force is very much smaller than the probability of failure of a single IC chip, the objective of enhanced reliability is effectively achieved.

Abstract: A semiconductor device comprises a semiconductor chip. The semiconductor chip has an internal active region, an external active region, and a plurality of electrodes for electrically connecting the internal active region and the external active region to outside thereof, respectively. The semiconductor device also comprises a boarding portion that carries the semiconductor chip, a plurality of external electrode terminals for electrical connection to an external device, a plurality of connecting wires each connecting the electrode of the semiconductor chip and the external electrode terminal; and a mold resin that seals the semiconductor chip, the boarding portion and the connecting wires. The electrodes are disposed around the internal active region, and the external active region is disposed outside the electrodes.

Abstract: A semiconductor card includes a printed circuit substrate upon which is mounted a card circuit including one or more semiconductor components such as dice or packages. External contacts link the card circuit to the circuit of another apparatus by removable insertion therein. The substrate is defined by a peripheral opening in a surrounding frame, which may be part of a multiframe strip. The substrate is connected to the frame by connecting segments. The card includes a first plastic casting molded to the substrate and encapsulating the semiconductor components while leaving a peripheral portion of the substrate uncovered. A second plastic casting is molded to the peripheral portion to abut the first plastic casting and form the card periphery. A method for fabricating the semiconductor card is also included.

Abstract: A semiconductor device module includes one or a plurality of semiconductor devices, each including a semiconductor element having first and second surfaces, pads formed on the first surface on which electrode terminals are also formed and curved, flexible wires having first ends fixed to the pads. The semiconductor devices are mounted on a mounting board such that second ends of the wires are connected to terminals on the mounting board. A heat spreader has a recessed inner wall and a peripheral edge which is adhered to or engaged with the mounting board in such a manner that the second surfaces of the semiconductor elements face a bottom interior surface of the recessed inner wall. A thermal conductive resin layer of a substantially constant thickness is disposed between the second surface of the semiconductor element and the bottom interior surface of the recessed inner wall of the heat spreader.

Abstract: A packaged power device includes a substrate including a first conductive layer, a second dielectric layer, and a third conductive layer. The first conductive layer is bonded to the second dielectric layer, and the second dielectric layer is bonded to the third conductive layer. The first and third conductive layers are electrically isolated from each other. The substrate has a lower surface. A semiconductor die is bonded to the first conductive layer of the substrate. A plastic package encloses the die and has a lower surface. A curved backside includes the lower surfaces of the plastic package and substrate.

Abstract: A method of making a microelectronic package includes providing a sacrificial layer having a first surface and providing an optoelectronic element having a front face including one or more contacts and a rear surface and securing the rear surface of the optoelectronic element over the first surface of the sacrificial layer. The one or more contacts are then electrically interconnected with one or more conductive pads on the sacrificial layer and a curable and at least partially transparent encapsulant is provided over the first surface of the sacrificial layer so as to encapsulate the optoelectronic element and the conductive pads. The encapsulant is then cured the sacrificial layer is at least partially removed so as to leave said one or more conductive pads on a bottom surface of the encapsulant, the bottom surface of the encapsulant defining the bottom of the package.

Abstract: In a semiconductor device functioning as a three-dimensional device composed of two semiconductor chips bonded to each other, the back surface of the upper semiconductor chip is polished, the entire side surfaces of the upper semiconductor chip are covered with a resin layer, or the center portion of the upper semiconductor chip is formed to be thicker than the peripheral portion thereof. This suppresses the occurrence of a package crack and improves the reliability of the semiconductor device.