Abstract: A semiconductor chip includes a semiconductor substrate including first and second surfaces and a plurality of side surfaces, the first and second surfaces being parallel to each other and facing in opposite directions, the side surfaces connecting peripheries of the first and second surfaces. At least one of the side surfaces is an inclined surface with respect to the first and second surfaces, and a groove is formed in the inclined surface. The groove extends in a direction which intersects a plane parallel to the first and second surfaces and extends in a direction which intersects a plane which intersects the first and second surfaces at right angles.

Abstract: A substrate strip with warpage-preventive linkage structure is proposed for a BGA (Ball Grid Array) application. The proposed substrate strip is composed of a series of substrates, each being used for the construction of an individual unit of a BGA package, and which is characterized by the provision of a warpage-preventive linkage structure, by which each substrate on the substrate strip is supported by means of no more than two tie bars, i.e., either by a two-point linkage structure or a one-point linkage structure, in contrast to the four-point linkage structure utilized by the prior art. During high-temperature fabrication steps when the substrate is subjected to thermal stresses, the substrate can freely expand toward the corners where no tie bars are provided; and consequently, it can be unwarped by the thermal stresses. This unwarped substrate allows the subsequently implanted ball grid array thereon to have high coplanarity.

Abstract: The present invention provides a semiconductor device which includes a U-shaped metal package base, and a semiconductor chip having at least surface electrodes and being mounted on the inner bottom portion of the U-shaped metal package base, wherein the metal package base has, in a portion thereof ranging from the opened side end portion of the inner side wall to the semiconductor chip, a creep-up preventive zone preventing solder entering from the opened side end portion from creeping up.

Abstract: A circuit component built-in module can be produced by filling a conducting material in through holes of a sheet-like member, stacking the sheet-like member and a metal foil on a circuit component package, and applying heat and pressure to embed the circuit component in the sheet-like member, and patterning the metal foil. The circuit component package includes a mounting member with substrate and wiring pattern and a circuit component. The circuit component includes a component body and external electrode, with the component body being thinner at a portion on which the external electrode is provided. The external electrode is provided on a surface of the circuit component that is opposed to the mounting member, and the component body is in contact with the mounting member.

Abstract: A lead frame comprises a lead frame body having cut-away portions cut away from the side surfaces of the lead frame body, a die pad for securing a semiconductor chip, bonding electrodes surrounding the die pad, external electrodes for allowing the lead frame to be mounted, wiring for surface treatment extending on the lead frame body with its end being located at a portion of each of the side surfaces of the lead frame body, the portion being opposed to the cut-away portions. The bonding electrode and the wiring for surface treatment, as well as the external electrode and the wiring for surface treatment, are electrically connected, respectively. Even when the lead frame is electrostatically charged by friction with a transfer unit, the semiconductor chip on the lead frame avoids electrostatic damage.

Abstract: A semiconductor package structure includes a semiconductor component, a substrate, solder bumps, underfill, a buffer means, and solder balls. The substrate is under the semiconductor component. A joint area is formed between the first surface of the semiconductor and the upper surface of the substrate. Several solder bumps are disposed in the joint area, for electrically connecting the semiconductor component and the substrate. The underfill is filled in the joint area, for coating the solder bumps and tightly jointing the semiconductor component and the substrate. The buffer means is situated in the jointing area, for buffering the underfill to be confined in the joint area. Several solder balls are disposed on the lower surface of the substrate.

Abstract: There is provided a metal/ceramic bonding substrate having improved reliability to heat cycles, and a method for producing the same. In a metal/ceramic bonding substrate 10 wherein a circuit forming metal plate 14 is bonded to one side of a ceramic substrate 12 and a radiating metal base plate 16 is bonded to the other side thereof, at least part of the ceramic substrate 12 is embedded in the metal base plate 16. The ceramic substrate 12 is arranged substantially in parallel to the metal base member 16.

Abstract: A semiconductor device (21) can include, e.g., a recessed portion (25) on the reverse surface (224) of an insulating resin (22) which is the mounting surface of the semiconductor device (21). Additionally, on the outer peripheral surface of the recessed portion (25), the exposed region of leads (26) and the reverse surface (224) of the insulating resin (22) form generally the same plane. This allows, e.g., a QFN semiconductor device (21) according to preferred embodiments herein to place dust particles in the recessed portion (25) even in the presence of dust particles such as crushed burr particles of the leads (26) or plastic burrs, thereby avoiding mounting deficiencies when mounting the semiconductor device.

Abstract: In a drive circuit for an electric motor, there is provided a circuit board, at least one semiconductor device mounted to the circuit board and a spacer. The semiconductor device has a semiconductor chip, a chip package incorporating therein the semiconductor chip and comprising a mounting member for mounting on the circuit board, and terminals for connections of the semiconductor chip to the circuit board. The spacer is interposed between the circuit board and the mounting member of the chip package so as to provide a space between the circuit board and the chip package.

Abstract: An integrated circuit (IC) chip, semiconductor wafer with IC chips in a number of die locations and a method of making the IC chips on the wafer. The IC chips have plated chip interconnect pads. Each plated pad includes a noble metal plated layer electroplated to a platable metal layer. The platable metal layer may be copper and the noble metal plated layer may be of gold, platinum, palladium, rhodium, ruthenium, osmium, iridium or indium.

Abstract: Provided are a flexible film package module and a method of manufacturing the same that can be adapted for manufacture at lower cost and/or to adapt the characteristics of the flexible film package module for specific applications. The lower-cost flexible film package module includes a tape film that combines both a first insulating substrate, typically formed from a higher-cost polyimide material, and a second insulating substrate, typically formed from an insulating material or materials that are less expensive and/or provide modified performance when compared with the first insulating material. Both the first and second substrates will include complementary circuit patterns that will be electrically and physically connected to allow the composite substrate to function as a unitary substrate. The first and second substrates will also include connection regions that may be adapted for connection to printed circuit boards and/or electronic devices such as liquid crystal displays.

Abstract: A stacked MCM is manufactured at reduced cost without using expensive apparatus. A first wiring and a second wiring are formed on a surface of a semiconductor chip of a first semiconductor device through an insulation film. A glass substrate having an opening to expose the second wiring is bonded to the surface of the semiconductor chip on which the first wiring and the second wiring are formed. A third wiring is disposed on a back surface and a side surface of the semiconductor chip through an insulation film and connected to the first wiring. And a conductive terminal of another semiconductor device is connected to the second wiring through the opening.

Abstract: A semiconductor device comprising a substrate, a semiconductor element mounted on the substrate, an inner annular stiffener provided on the substrate in an outer side of the semiconductor element, and an outer annular stiffener provided on the substrate in an outer side of the inner annular stiffener. The inner annular stiffener and the outer annular stiffener are made of different materials. Particularly, the thermal expansion coefficient of the inner annular stiffener is selected to be smaller than that of the substrate, and the thermal expansion coefficient of the outer annular stiffener is selected to be larger than that of the substrate. The amount of deformation of the substrate is thus decreased.

Abstract: A jumper chip component of the present invention includes a connection conductor formed of a conductive layer over an upper face and opposite side faces of an insulating substrate, and a conductive material formed of a conductive layer between plates of the insulating substrate and on a side face at the corner of the insulating substrate so as not to be electrically connected to the connection conductor. Since the conductive material formed between the plates of the insulating substrate opposes the connection conductor formed on the upper face of the insulating substrate, the connection conductor formed on the upper face of the insulating substrate and a second conductive pattern disposed under the insulating substrate are shielded from each other by the conductive material, and good isolation is possible.

Abstract: In a semiconductor memory integrated circuit (IC), a plurality of first data IO pads, a plurality of address and instruction pads, and a plurality of second data IO/address pads, are arranged in groups adjacent each other. Each of the plurality of the second data IO/address pads is used as a second data IO pad in response to a control signal when packaged into a first package form and is used as an address pad in response to the control signal when packaged into a second package form. The semiconductor memory IC of the present invention can selectively use a portion of pads as data IO pads or address/instruction pads, and thus the IC is compatible for use with different types of packages. The semiconductor memory IC of the present invention further allows for simplified wire bonding when it is packaged into different types of packages, and thus the possibility of failure of the semiconductor memory device is reduced.

Abstract: The present disclosure suggests various microelectronic component assembly designs and methods for manufacturing microelectronic component assemblies. In one particular implementation, a microelectronic component assembly includes a microelectronic component mounted to a substrate. The substrate carries a plurality of bond pads at a location substantially coplanar with a terminal surface of the microelectronic component. This enables a smaller package to be produced by moving the bond pads laterally inwardly toward the periphery of the microelectronic component.

Abstract: A supporting frame is used to solidly bridge to the two metallic contacts of a surface mount diode chip. Any bending or twisting stress between the two contacts is borne by the supporting frame instead of the diode chip. Otherwise the stress may damage the diode chip.

Abstract: A semiconductor device package comprises a perimeter wall snap fitted to a base having a semiconductor die mounted on the base. A lead is mounted on the opposite side of the die, and the die and a portion of the lead are protected by an encapsulant disposed within the perimeter wall.

Abstract: A semiconductor chip includes a logic circuit unit, at least one memory macro unit having a redundant memory cell which recovers a defect cell, electrode pad rows being arranged around the outside of the logic circuit unit and the memory macro unit, and the least one fuse unit group storing addresses of the defect cell and being arranged in a region along any edge of the semiconductor chip, and on the outside of the logic circuit unit, the memory macro unit and the electrode pad rows. Here, the logic circuit unit, the memory macro unit, the electrode pad rows and the fuse unit group are positioned on a semiconductor chip surface.

Abstract: Integrated circuit arrangement, in which bearing areas of mutually opposing sides of a carrier and of a substrate layer, which carries circuit structures, are bonded by means of an adhesive layer. The adhesive bond is produced from adhesives forming at least two adhesive tracks. The first adhesive track is formed in a region of an externally accessible seam between the substrate layer and the carrier, and the second adhesive track is formed parallel to the first adhesive track in an inner region of the bearing areas that face one another.

Abstract: An optoelectronic assembly for an electronic system includes a transparent substrate having a first surface and an opposite second surface, the transparent substrate being thermally conductive and being metallized on the surface. A support electronic chip set is configured for at least one of providing multiplexing, demultiplexing, coding, decoding and optoelectronic transducer driving and receive functions and is bonded to the second surface of the transparent substrate. A first substrate having a first surface and an opposite second surface, is in communication with the transparent substrate via the metallized second surface and support chip set therebetween. A second substrate is in communication with the second surface of the first substrate and is configured for mounting at least one of data processing, data switching and data storage chips.

Abstract: A semiconductor die package is disclosed. In one embodiment, the die package includes a semiconductor die including a first surface and a second surface, and a leadframe structure having a die attach region and a plurality of leads extending away from the die attach region. The die attach region includes one or more apertures. A molding material is around at least portions of the die attach region of the leadframe structure and the semiconductor die. The molding material is also within the one or more apertures.

Abstract: In the high-frequency module of the present invention, an insulating resin is formed so as to seal a high-frequency semiconductor element mounted on a surface of a substrate and further to seal electronic components. Furthermore, a metal thin film is formed on the surface of the insulating resin. This metal thin film provides an electromagnetic wave shielding effect.

Abstract: A micro-electro-mechanical system (MEMS) package with a side sealing member and a method of manufacturing the package are disclosed. In the MEMS package and method of the present invention, a sealing member is formed on a side surface of a lid glass that is mounted on a spacer surrounding MEMS elements provided on a base substrate and covers the MEMS elements, so that the sealing member hermetically seals the MEMS elements from the external environment.

Abstract: A chip package substrate having a soft circuit board jas a multi-layer soft and hard composite PCB, a plurality of conducting components and a plurality of conducting holes. The conducting holes are formed in the multi-layer soft and hard composite PCB. The conducting components are electroplated on the inner edges of the conducting holes on the multi-layer soft and hard composite PCB. An image-sensing chip can thus be packaged on the chip package substrate with the soft circuit board used as external signal connection lines, thereby saving the manufacturing cost and increasing the yield thereof.

Abstract: A circuit board assembly includes a circuit board, an electronic component, a plurality of incremental detents and at least one projection. The plurality of incremental detents are coupled to one of the circuit board and the electronic component and are retained relative to said one of the circuit board and the electronic component against linear movement in both directions along a first axis. The at least one projection is coupled to the other of the circuit board and the electronic component and is retained against linear movement along the first axis. The at least one projection is received within at least one of the plurality of detents to retain the electronic component relative to the circuit board against linear movement in both directions along the axis.

Abstract: A semiconductor flipchip package includes a central cavity area on the first major side for receiving a flipchip die therein. The package substrate is substantially made from a single material that serves as the support and stiffener and provides within the cavity floor all the connecting points for flipchip interconnection to the silicon die. The integral cavity wall serves as a stiffener member of the package and provides the required mechanical stability of the whole arrangement without the need for a separate stiffener material to be adhesively attached. The cavity walls may contain extra routing metallization to create bypass capacitors to enhance electrical performance. Optional methods to cover the silicon die enhance thermal performance of the package.

Abstract: A method for packing a semiconductor device 301 in a carrier tape 406 without damage to the leads 302 includes an interlocking mechanism between the molded semiconductor device with indentations 305 formed into the package body, and the carrier tape having mating protrusions 407 slightly smaller than the indentations which cause the device to be held securely without significant movement after a cover tape 409 is adhered to the carrier tape. The features of correctly sized pockets and pedestals, the cover tape, and the interlocking device indentations and tape protrusions prevent damage to the device leads as a result of impact.

Abstract: A lead frame for making a semiconductor package is disclosed. The leadframe's leads include a lead lock provided at a free end of each inner lead that is adapted to increase a bonding force of the inner lead to a resin encapsulate, thereby effectively preventing a separation of the inner lead from occurring in a singulation process involved in the fabrication of the semiconductor package. A semiconductor package fabricated using the lead frame and a fabrication method for the semiconductor package are also disclosed.

Abstract: An optical semiconductor component has multiple conducting wire holders, multiple chip carriers secured, multiple semiconductor chips, a first curved surface made of the conducting wire holders, the semiconductor chips being placed at its focus, multiple connecting components made of the conducting wire holders, and a second curved surface surrounded by a package body, the semiconductor chips being placed at its focus. The chip carriers are independent components and have a multi-layer structure. The middle layer is an insulator used to separate the chip from the conducting wire holder electrically or thermally. Hence, when connected with a metal radiator, the chip carrier does not cause electric leakage. Further, the connecting components of the present invention are mutually independent, which can provide multiple photodiodes with different driving voltages to connect with each other in series or parallel.

Abstract: A microelectronic package is made by a process which includes folding a substrate. Alignment elements on different parts of the substrate engage one another during the folding process to position the parts of the substrate precisely relative to one another. One or more of the alignment elements may be a mass of an overmolding encapsulant covering a chip.

Abstract: A packaged semiconductor device structure comprises a semiconductor chip (20) having a bump electrode (5), a facing substrate (9) having on one face thereof a facing electrode (8) contacting an end face of the bump electrode (5) and a bonding agent (7) filled in between the semiconductor chip (20) and the facing substrate (9). The bump electrode (5) is of a double layer structure composed of a core part (5b) and a convex-shaped electrode end part (5a) fabricated above the core part (5b) separately from the core part.

Abstract: Electronic contacts, including spherical cores and attachment layers on the cores, are provided for attaching a semiconductor package substrate to a printed circuit board. The spherical cores are made of high-melting-temperature copper, and the attachment layers are made of a low-melting-temperature eutectic. The attachment layers melt in a reflow process. The spherical cores do not melt, and thereby control movement or “collapsing” of the package substrate toward the printed circuit board.

Abstract: Packaged microelectronic devices, interconnecting units for packaged microelectronic devices, and methods and apparatuses for packaging microelectronic devices with pressure release elements. In one aspect of the invention, a packaged microelectronic device includes a microelectronic die, an interconnecting unit coupled to the die, and a protective casing over the die. The interconnecting unit can have a substrate with a first side and a second side to which the die is attached, a plurality of contact elements operatively coupled to corresponding bond-pads on the die, and a plurality of ball-pads on the first side of the substrate electrically coupled to the contact elements. The protective casing can have at least a first cover encapsulating the die on the first side of the substrate. The packaged microelectronic device can also include a pressure relief element through at least a portion of the first cover and/or the substrate.

Abstract: Enhanced ACF bonding pads for use in conjunction with anisotropic conductive film (ACF) in electronic devices, such as, liquid crystal display panels and plasma display panels have at least two finger-like portions. Such bonding pads, typically provided on a flexible wiring lead, when bonded to other metal structures via the ACF film, make better electrical contact with the other metal structures because the spaces between the finger-like portions of the improved bonding pads allow the ACF film's binder material to reside between the finger-like portions preventing the bonding pad metal in the center region of the bonding pad from separating away from the other metal structures.

Abstract: A crystalline substrate based device including a crystalline substrate having formed thereon a microstructure and at least one packaging layer which is formed over the microstructure and defines therewith at least one gap between the crystalline substrate and the at least one packaging layer and at least one opening in the packaging layer communicating with the at least one gap.

Abstract: A power semiconductor module, having a metal base plate for mounting on a heat sink. The module comprises a framelike housing, a cover, terminal elements, leading to the outside of the housing, for load contacts and auxiliary contacts, and having at least one electrically insulating substrate, disposed inside the housing. The substrate includes an insulating body and a plurality of metal connecting tracks, electrically insulated from one another. Power semiconductor components are located on the connecting tracks and connected to these connecting tracks via appropriate circuitry. The base plate has a stiffening structure, which extends near and along a side of the base plate, and in the longitudinal direction of the base plate. The stiffening structure is formed of the base plate material itself by deformation and protrudes out of the upper surface of the base plate.

Abstract: A process for manufacturing an integrated circuit including the steps of providing a chip carrier including a base, an inner well formed about the periphery of the base, and an outer well formed about the periphery of the inner well. An integrated circuit is positioned on the base. The process further includes the steps of pre or post processing the integrated circuit.

Abstract: Methods of fabricating leadless packages are described that provide good solder joint reliability. In most respects, the packages are fabricated in a manner similar to current lead frame based leadless packaging techniques. However, at some point in the process, the contacts are provided with undercut regions that are left exposed during solder plating so that the solder plating also covers the exposed side and undercut segments of the contacts. When the resultant devices are soldered to an appropriate substrate (after singulation), each resulting solder joint includes a fillet that adheres very well to the undercut portion of contact. This provides a high quality solder joint that can be visually inspected from the side of the package.

Abstract: An electronic chip component includes a component body and a plurality of terminal electrodes disposed on outer surfaces of the component body. At least one of the terminal electrodes includes a cured resin film including dispersed conductive particles, an outer conductive film formed on the cured resin film by electroplating, and additional conductive metallic particles being dispersed on an interface between the cured resin film and the outer conductive film.

Abstract: There is described novel bonding and interconnecting techniques for use with semiconductor die for the creation of thermally efficient, physically compliant Ultra High Vacuum Tubes and the novel tube resulting therefrom.

Abstract: A semiconductor device comprising a substrate. An interconnect pattern is formed over the substrate, and the substrate has a first portion and a second portion to be superposed on the first portion. The first portion has edges as positioning references. The second portion has a shape to be superposed over the first portion except the edges.

Abstract: A semiconductor device includes a semiconductor chip having a main surface provided with an integrated circuit including a photoelectric converter and a first wiring for electrically connecting the integrated circuit of the semiconductor chip to respective external terminals. The semiconductor device also includes a sealing resin for sealing the main surface of the semiconductor chip and the first wiring, formed so as to have an opening over the surface of the integrated circuit and a light-transmitting cap for covering the opening of the sealing resin.

Abstract: A semiconductor module, comprising a wiring substrate on which wiring is formed, a semiconductor device electrically connected to the wiring formed on the wiring substrate, and an external connection terminal arranged on the semiconductor device mounted side of the wiring substrate so as to be a connected portion between the wiring and the outside electrically connected thereto, wherein there is formed an insulating resin layer thicker than the semiconductor device between the wiring substrate and the external connection terminal.

Abstract: The present invention provides a flat film carrier tape for mounting electronic devices thereon which tape can enhance reliability of a semiconductor chip mounting line. The film carrier tape includes a continuous insulating layer, a wiring pattern formed of a conductor layer provided on a surface of the insulating layer, a row of sprocket holes provided along respective longitudinal edges of the insulating layer, which said row of sprocket holes are at the outer sides of the wiring pattern, and a metallic layer formed around said row of sprocket holes, wherein the metallic layer is provided in a discontinuous manner in the longitudinal direction of the insulating layer by provision of slits on the insulating layer at intervals of three to eight said sprocket holes.

Abstract: The invention relates to a method for making an integrated circuit (40) of the surface-mount type the comprising, first of all, manufacture of a package having a rear face and a pin grid array extending under this rear face perpendicular thereto, and a ball (44) of low melting point alloy is then formed at the end of each pin surrounding this end and soldered thereto. The invention also relates to an integrated circuit (40) of the surface-mount type, comprising a package having a rear face and a pin grid array, of a cross section roughly constant along the pin (42), extending under the rear face perpendicular thereto. A ball (44) of low melting point alloy is soldered to the end of each pin (42) surrounding this end.

Abstract: The present invention is directed to a high-performance system on a chip which uses multi-layer wiring/insulation through-hole interconnections to provide short wiring and controlled low-impedance wiring including ground planes and power supply distribution planes between chips.

Abstract: A semiconductor device comprises a semiconductor IC chip provided with bond pads on its first surface, a wiring substrate provided with a through hole extending between the opposite surfaces thereof, conductive members electrically connecting the bond pads of the semiconductor IC chip to the conductive lines formed on the wiring substrate respectively, and a sealing resin coating coating the first surface of the semiconductor IC chip and the conductive members, and bonding the side surface of the semiconductor IC chip to the side surface of the through hole of the wiring substrate.

Abstract: An interconnect substrate including a first substrate on which a first interconnect pattern is formed, having a mounting region for an electronic chip; and a second substrate on which a second interconnect pattern electrically connected to the first interconnect pattern is formed. The second substrate includes a region to which at least a part of the first substrate is adhered, and a mounting region for an electronic chip.

Abstract: A wiring board is constructed such that a base layer constituted of photosensitive polyimide, a conductor layer constituted of copper, and a cover layer constituted of photosensitive polyimide are formed in this order on a stainless layer. On an electronic part mounting portion, a plurality of lands are formed so as to correspond to electrode terminals of an electronic part to be mounted. On the periphery of the electronic part mounting portion, an underfill diffusion preventing portion formed by removing the cover layer in a trench shape is provided so as to surround the periphery thereof.