Abstract: An optical device with a CAN package is disclosed, where the cap is resistance-welded to the stem without causing failures due to fragments by the welding flying within the package. The cap of the invention has a flange portion to be welded to the stem. The flange portion provides a ringed groove in addition to the ringed projection for the welding. The fragment due to the welding may be captured in the ringed groove and is prevented from flying within the package. The ringed groove and the ringed projection are simultaneously formed in the stamping to form the body portion of the cap.

Abstract: Microelectronic devices having intermediate contacts, and associated methods of packaging microelectronic devices with intermediate contacts, are disclosed herein. A packaged microelectronic device configured in accordance with one embodiment of the invention includes a microelectronic die attached to an interconnecting substrate. The microelectronic die includes an integrated circuit electrically coupled to a plurality of terminals. Each of the terminals is electrically coupled to a corresponding first contact on the die with an individual wire-bond. Each of the first contacts on the die is electrically coupled to a corresponding second contact on the interconnecting substrate by a conductive coupler such as a solder ball.

Abstract: A semiconductor package and a method for manufacturing the same. The semiconductor package includes a semiconductor chip having bonding pads; a first insulation layer pattern; redistribution line patterns; a second insulation layer pattern; and conductive balls. The first insulation layer pattern having first openings exposing the bonding pads. The redistribution line patterns are located on the first insulation layer pattern and are electrically connected with the bonding pads. The second insulation layer pattern covering the redistribution line patterns and having second openings having first open areas which expose portions of the redistribution line patterns and having second open areas which extend from the first open areas along the semiconductor chip. The conductive balls are electrically connected with the portions of the redistribution line patterns which are exposed through the first open areas of the second insulation layer pattern.

Abstract: A power semiconductor module and a method of manufacture thereof includes a lead frame carrying lead having inner and outer lead portions. The outer lead portions, which are connected by soldering to semiconductor chips simultaneously, eliminate the need for using bonding wires. Since no bonding wire is used for connecting the leads and the semiconductor chips, a sufficient current capacity is obtained. The bonding between an insulating circuit board and the semiconductor chips and the bonding between the semiconductor chips and the leads can be made simultaneously in a single step of reflow-soldering. As a result, the mounting time can be shortened and the power semiconductor module can be manufactured more efficiently.

Abstract: A microelectronic package includes a microelectronic element having faces and contacts, a flexible substrate overlying and spaced from a first face of the microelectronic element, and a plurality of conductive terminals exposed at a surface of the flexible substrate. The conductive terminals are electrically interconnected with the microelectronic element and the flexible substrate includes a gap extending at least partially around at least one of the conductive terminals. In certain embodiments, the package includes a support layer, such as a compliant layer, disposed between the first face of the microelectronic element and the flexible substrate. In other embodiments, the support layer includes at least one opening that is at least partially aligned with one of the conductive terminals.

Abstract: A power module with low thermal resistance buffers the stress put on a substrate during a package molding operation to virtually always prevent a fault in the substrate of the module. The power module includes a substrate, a conductive adhesive layer formed on the substrate, a device layer comprising a support tab, a power device, and a passive device which are formed on the conductive adhesive layer, and a sealing material hermetically sealing the device layer. The support tab is buffers the stress applied by a support pin to the substrate, thereby virtually always preventing a ceramic layer included in the substrate from cracking or breaking. As a result, a reduction in the isolation breakdown voltage of the substrate is virtually always prevented and the failure of the entire power module is do to a reduction in the breakdown voltage of the substrate is virtually always prevented.

Abstract: A semiconductor component includes a semiconductor substrate having a substrate contact, and a through wire interconnect (TWI) attached to the substrate contact. The through wire interconnect provides a multi level interconnect having contacts on opposing first and second sides of the semiconductor substrate. The through wire interconnect (TWI) includes a via through the substrate contact and the substrate, a wire in the via having a bonded connection with the substrate contact, a first contact on the wire proximate to the first side, and a second contact on the wire proximate to the second side. The through wire interconnect (TWI) also includes a polymer layer which partially encapsulates the through wire interconnect (TWI) while leaving the first contact exposed. The semiconductor component can be used to fabricate stacked systems, module systems and test systems. A method for fabricating the semiconductor component can include a film assisted molding process for forming the polymer layer.

Abstract: The present invention provides a stackable semiconductor having an interconnect board for providing electrical interconnections, the package includes a plurality of solders disposing onto the interconnect board; and a conducting metal pin passing through each solder and the interconnect board, the metal pins having at least one end disposes on the semiconductor package, wherein when a plurality of the stackable semiconductor packages are stacked together, the exposed end of the corresponding conducting pins are bonded together. A method of manufacturing the same is also provided.

Abstract: A chip package is provided, which includes a dielectric layer, at least a conductive layer, a chip, a wiring layer and at least a conductive via. The dielectric layer has a first surface, a second surface opposite to the first surface and a plurality of lateral surfaces joined between the first surface and the second surface. One of the lateral surfaces has at least a groove, wherein the groove is extended from the first surface to the second surface. The conductive layer is disposed on the wall of the groove. The chip is inserted in the dielectric layer. The wiring layer is located on the first surface and electrically connected to the conductive layer. The conductive via is located in the dielectric layer to electrically connect the chip to the wiring layer.

Abstract: A panel and a semiconductor component including a composite board with semiconductor chips and plastic package molding compound and a method for the production thereof is disclosed. In one embodiment, the panel includes a composite board with semiconductor chips arranged in rows and columns in a corresponding plastic package molding compound with a plurality of semiconductor component positions. The thickness of the plastic package molding compound corresponds to the thickness of the semiconductor chips so that a coplanar upper side and a coplanar rear side are formed on the composite board. Located on the coplanar rear side of the composite board is a plastic layer whose coefficient of thermal expansion corresponds to the coefficient of thermal expansion of the composite board. Located on the coplanar upper side of the composite board is a wiring structure which has corresponding external contacts.

Abstract: An upper sealing ring and a lower sealing ring are adhered by sealing solder. The width of tip end of sealing projection is narrower than the width of the lower sealing ring. Therefore, the sealing solder is placed on lower sealing ring and on the side surface of upper sealing ring. Further, an upper connection pad and a lower connection pad are adhered by connecting solder. The width of a tip end of a connection projection is narrower than the width of lower connection pad. Therefore, the connecting solder is placed on the lower connection pad and on the side surface of upper connection pad. Thus, a package is provided, which attains satisfactory electrical connection and hermetic seal after solder joint of the upper and lower substrates.

Abstract: An advantage of the present invention is to suppress moisture infiltrating from a pad electrode portion from spreading over the surface of a wiring pattern and improve the reliability of a packaging board. The wiring pattern of the packaging board is formed on an insulating substrate and includes a wiring region, an electrode region (pad electrode) connected with a semiconductor device, and a boundary region provided between the wiring region and the electrode region. A gold plating layer is provided on the surface of the electrode region of the wiring pattern. The top surface of the boundary region of the wiring pattern is so formed as to be dented from the top surface of the wiring region of the wiring pattern, and there is provided a stepped portion in the boundary region.

Abstract: An electronic device (1) has a base plate (2) and an electronics housing (3) connected thereto, with a bonding contact terminal (5). The latter is supported relative to the base plate (2) via a supporting body (6) in such a manner that the supporting body (6) exerts a pre-stressing force onto the bonding contact terminal (5). Due to this support of the bonding contact terminal (5), its position is well defined during the bonding procedure. A secure bond is the result.

Abstract: A semiconductor device includes a base member made of a material containing at least a thermosetting resin, and at least one semiconductor constructing body mounted on the base member, and having a semiconductor substrate and a plurality of external connecting electrodes formed on the semiconductor substrate. An insulating layer is formed on the base member around the semiconductor constructing body. An interconnection of at least one layer is formed on one sides of the semiconductor constructing body and insulating layer, electrically connected to the external connecting electrode of the semiconductor constructing body, and having a connecting pad portion, the semiconductor substrate is fixed to the base member by fixing force of the base member.

Abstract: A wafer level package for a surface acoustic wave (SAW) device and a fabrication method thereof. The SAW device wafer level package includes a SAW device in which a SAW element is formed on a top surface of a device wafer, a cap wafer which is bonded with a top surface of the SAW device and has a viahole penetrating the cap wafer, and a conductive member to fill a part of the viahole. The viahole has a first via portion and a second via portion, the first via portion has a gradually smaller diameter from a bottom surface of the cap wafer until a certain depth, and the second via portion has a gradually greater diameter from the first via portion until a top surface of the cap wafer.

Abstract: A semiconductor device includes: a substrate; a semiconductor element mounted on the substrate; a sealing structure for sealing the semiconductor element, the sealing structure being mounted on the substrate; and an adhesive for bonding the sealing structure and the substrate, wherein the sealing structure has a groove for storing the adhesive.

Abstract: One of the aspects of the present invention is to provide a power semiconductor device, including a first substrate having a first circuit pattern formed thereon, and a second substrate having a second circuit pattern formed thereon. The first substrate has a first center line extending along a predetermined transverse direction. At least one power semiconductor chip is mounted on the first circuit pattern of the first substrate, and has at least one chip electrode opposing to the second circuit pattern of the second substrate. Also, a plurality of first conductive connectors on the first circuit pattern is provided for electrical connection with the second circuit pattern of the second substrate. The first conductive connectors are arranged symmetrically in relative to the first center line of the first substrate.

Abstract: A temperature sensing system for a flange mounted device is provided. The temperature sensing system (100) can be comprised of a flexible wiring board (102). The temperature sensing system can be further comprised of a temperature sensing device (122) mounted to the flexible wiring board. The flexible wiring board can have one or more conductive traces (114a, 114b, 114c) disposed thereon. The conductive traces can form an electrical connection with the temperature sensing device. The temperature sensing system can also comprise a thermal pad directly connected to the temperature sensing device. The thermal pad can be formed of a thermal conductor. The thermal pad can also have a thermal contact surface. The thermal contact surface can be sized and shaped for direct physical contact with a portion of the device (302), wherein thermal energy is communicated directly from the thermal pad to the temperature sensing device. A method for sensing a temperature of a flange mounted device is also provided.

Abstract: A semiconductor device carrier comprising; a carrier housing having a housing portion for accommodating a semiconductor device; an electrode sheet disposed in the carrier housing, having a front surface wiring conductively arranged on a front surface of an insulation substrate, a rear surface wiring conductively arranged on a rear surface of the insulation substrate, a rear surface bump contact placement wiring, and a bump contact disposed in a contact placement portion and an elastic sheet disposed in the carrier housing to be in contact with the bottom of the electrode sheet; wherein a width of the rear surface bump contact placement wiring in correspondence to a bump contact to be in contact with an extreme electrode section of the semiconductor device is smaller than a width of the front surface bump contact placement wiring on which a bump contact to be in contact with the extreme electrode section is arranged.

Abstract: To improve EMC shielding for an electronic unit containing at least one electronic power device operated at high frequency and a metal housing thermally coupled to the device to provide heat dissipation, the power device with a device terminal is thermally and electrically coupled to a first metal plate. The first metal plate is coupled in turn to a second metal plate in a particular manner via a first insulating layer. A metal housing with a heat sink through which a cooling fluid can flow is disposed, on another side of a second insulating layer. The improvement in EMC is based on an internal short-circuiting of an interference current produced by the power device over a very short loop.

Abstract: Provides semiconductor devices and method for fabricating devices having a high thermal dissipation efficiency. An example device comprises a thermally conducting structure attached to a surface of the semiconductor device via soldering. The thermally conducting structure is essentially formed of a thermally conducting material and comprises an array of freestanding fins, studs or frames, or a grid of connected fins. A process for fabricating such a semiconductor device includes forming a thermally conducting structure on a carrier and attaching the thermally conducting structure formed on the carrier to a surface of the semiconductor device via soldering.

Abstract: The present invention provides a low cost device that has a true die to external fiber optic connection. Specifically, the present invention relates to an optical device package joined to a semiconductor device package. In some cases, the combination is joined using wirebond studs and an adhesive material. In other cases, the combination is joined using an anisotropic conductive film. Yet, in other cases, the combination is joined using solder material. Each of these joining mechanisms provides high levels of thermal, electrical and optical performance. The joining mechanisms can apply to optical sub-assembly and chip sub-assembly interfaces in transceivers, transmitters, as well as receivers for opto-electronic packages.

Abstract: In a wiring substrate of the present invention in which a bump of an electronic parts is bonded to a connection pad of a wiring pattern provided on an insulating film by an ultrasonic flip-chip packaging, a via hole into which a via post acting as a strut to support the connection pad upon the ultrasonic flip-chip packaging is filled is arranged in the insulating film under the connection pad.

Abstract: A semiconductor device includes a base, a semiconductor element having a plurality of electrodes, a plurality of conductive lines connected to the electrodes of the semiconductor element, plating stubs attached to the conductive lines, and a plurality of wiring layers formed in a plurality of layers on the base. The plating stub attached to a first conductive line, and the plating stubs attached to one or a plurality of second conductive lines adjacent to the first conductive line, exist in different conductive wiring layers.

Abstract: A semiconductor device comprising a substrate, a semiconductor element mounted on the substrate, an inner annular stiffener provided on the substrate in an outer side of the semiconductor element, and an outer annular stiffener provided on the substrate in an outer side of the inner annular stiffener. The inner annular stiffener and the outer annular stiffener are made of different materials. Particularly, the thermal expansion coefficient of the inner annular stiffener is selected to be smaller than that of the substrate, and the thermal expansion coefficient of the outer annular stiffener is selected to be larger than that of the substrate. The amount of deformation of the substrate is thus decreased.

Abstract: A semiconductor device package comprises a perimeter wall snap fitted to a base having a semiconductor die mounted on the base. A lead is mounted on the opposite side of the die, and the die and a portion of the lead are protected by an encapsulant disposed within the perimeter wall.

Abstract: A stacked package for electronic elements is provided, a plurality of stud bumps are formed on a substrate by means of a stud bump process to align with a plurality of vias of one provided electronic element. The stud bumps respectively pass through the vias and electrically connect the electronic element. Furthermore, additional electronic elements are stacked on the carrier according to a similar way to form a stacked electronic package.

Abstract: A laser device includes a can package of a laser diode having a lead terminal secured to a through hole in a stem by a sealant, and a flexible substrate having a transmission line on a front surface of a polyimide film. The lead terminal of the can package and one end of a transmission line of the flexible substrate are connected by soldering. A resistor for matching the impedance of the transmission line and the impedance of the lead terminal is located in the vicinity of a connection of the transmission line and the lead terminal.

Abstract: A stacked chip-packaging structure consisting of a plurality of chip-packaging units is provided. Each of the chip-packaging units includes a substrate, a chip, a plurality of wires, a molding compound, and a plurality of solder balls. The chip-packaging units are, for example, of a BGA structure with high pin count, and are stacked up one over another and electrically connected through solder balls. With such structural features, the space that the stacked chip-packaging structure occupies is reduced and consequently the entire structure can be miniaturized.

Abstract: A discrete circuit component having an up-right circuit die with lateral electrical connections. The component comprises a substrate having a pair of electrically conductive traces, and a circuit die is planted between the pair of consecutive traces, wherein one electrode of the circuit die on the surface thereof vertical to the substrate is electrically bonded to one of the conductive trace immediately next thereto, while the other electrode of the circuit die on the opposite surface thereof vertical to the substrate is electrically bonded to the other of the pair of conductive traces immediately next thereto. A body of electrical insulation material hermetically seals the circuit die, and a pair of surface electrodes formed on the surface of the body of insulation material are each electrically connected to the corresponding one of the pair of electrically conductive traces extending from the circuit die.

Abstract: A method and structure for isolating a die from thermally induced or pressure induced differential stresses between a die and a package includes providing an intermediate layer having therein a plurality of relief channels arranged to provide a flexure for absorbing such differential stresses. The relief channels define interior and peripheral portions of the intermediate layer, and the die is typically mounted on the interior portion. The peripheral portion of the intermediate layer is then bonded to the package. The channels may be disposed along both the upper and lower surfaces of the intermediate layer, or may be disposed on only one surface. Likewise, the channels may be disposed along one or both of the length and width of the upper or lower surfaces. Reservoir channels may also be provided to prevent adhesive from flowing and bridging the relief channels.

Abstract: The present invention is to provide a power semiconductor device including a heat radiator having a principal surface and an insulating substrate bonded on the principal surface of the heat radiator via a first solder layer. The power semiconductor device also includes at least one semiconductor chip mounted on the insulating substrate via a second solder layer. The insulating substrate has a thin-layer and thick-layer edges, and is bonded on the principal surface of the heat radiator so that the first solder layer has a thickness thinner towards a direction from the thin-layer edge to the thick-layer edge (T1>T2). Also, the semiconductor chip is mounted on the insulating substrate so that a first distance between the thick-layer edge and the semiconductor chip is less than a second distance between the thin-layer edge and the semiconductor chip (L1<L2).

Abstract: A surface mount-type microelectronic component assembly which does not physically attach the microelectronic component to its carrier substrate. Electrical contact is achieved between the microelectronic component and the carrier with solder balls attached to either the microelectronic component or the carrier substrate. A force is exerted on the assembly to achieve sufficient electrical contact between the microelectronic component and the carrier substrate.

Abstract: A semiconductor-chip mounting substrate with a high degree of reliability of an electrical connection between a substrate and a semiconductor chip such as IC chips is provided. The substrate has at least one projection thereon, which is integrally molded with the substrate. A conductive layer is formed on the projection to obtain a first bump. The semiconductor chip has a terminal projecting as a second bump on its surface. The semiconductor chip is mounted on the substrate such that the first bump contacts the second bump. A required contact pressure between the first bump and the second bump is held by use of a pressure holding means.

Abstract: A packaged electronic device includes connection contacts that are formed on the contact pads on the second surface of the substrate. In contrast to the prior art, the connection contacts are not solder contacts but are formed of nickel/aluminum plated copper and are therefore harder and less malleable and subject to deformation than prior art solder balls. The connection contacts are formed to align with, and contact, attachment pads formed on the motherboard or other system component. A tension device is then used to mechanically attach the packaged electronic device of the invention to the motherboard.

Abstract: A metal base substrate for mounting a plurality of bare semiconductor chip devices thereon has first and second main surfaces. The first main surface has formed thereon at least one projection, and at least two recesses in which the bare semiconductor chip devices are to be mounted. The depth of these recesses is smaller than the length of said projection, and the recesses have a higher surface smoothness than said main surfaces of said metal substrate. The metal base substrate is partially chemically etched to form the projection, and the first main surface of the substrate is mechanically worked to form at least the recesses. The conductive projection is isolated from the portion on which the bare semiconductor chip devices are mounted, of the base substrate, and the conductive projection acts as a terminal that can be electrically connected to the outside on the first and second main surfaces of the base substrate.

Abstract: The present invention relates to a capsule (1) for at least one high power transistor chip (17) for high frequencies, comprising an electrically and thermally conductive flange (10), at least two electrically insulating substrates (15), and at least two electrical connections (16), and a cover member, where the high power transistor chip (17) is arranged on the flange (10). The high power transistor chip (17) and the electrically insulating substrates (15) are arranged on the flange (10). The electrical connections (16) are arranged on electrically insulating substrates (15) and the electrically insulating substrates (15) are connected to the flange (10) and open and separate from the high power transistor chip (17).

Abstract: A circuit board assembly has (i) a circuit board including a section of circuit board material and a circuit board component mounted to the section of circuit board material, (ii) a support assembly that supports the circuit board, and (iii) a heatsink that cools the circuit board component mounted to the circuit board. The heatsink includes a receptacle that fastens to the support assembly, and an adjustable member that engages with the receptacle. The adjustable member is movable relative to the receptacle in order to control a distance between the adjustable member and the circuit board component. The adjustable member can be positioned properly (e.g., with the correct pressure) for proper heat transfer therethrough. Moreover, circuit board assembly can include multiple heatsinks for cooling multiple circuit board components with the adjustable member of each heatsink being individually adjusted to accommodate any tolerance differences between the circuit board components.

Abstract: An object is to suppress resonance phenomenon. A pair of reinforcing members (18) are fixed on a gate drive substrate (7) with spacers (37) interposed therebetween and upright portions (40) of the pair of reinforcing members (18) are fastened with screws on a side wall of a cathode flange. A spacer (118) is fixed on the gate drive substrate (7) and a projection (118a) of the spacer (118) is inserted in an engaging member (119) fixed on the bottom of the cathode fin electrode (5) and thus fixed on the bottom of the cathode fin electrode (5). The pair of upright portions (40) as the first and second supporting points and the projection (118a) as the third supporting point stably support the gate drive substrate (7) on the cathode fin electrode (5) without freedom of rotation at the three positions arranged to surround an opening (49).

Abstract: An object is to provide a semiconductor device of a TCP or COF configuration including semiconductor chips mounted on a tape, which realizes compact mounting of a plurality of semiconductor chips on a single tape. In order to do so, a semiconductor chip having a lengthwise rectangular shape is mounted so as to have a long side substantially perpendicular to an extending direction of a Cu wiring pattern, thereby wiring numerous wires of the Cu wiring patterns substantially in parallel with each other, and substantially straight-line with respect to a destination of in-/output. Further, in the mounting of the plurality of semiconductor chips, a tape width can be reduced so as to miniaturize devices to be connected.

Abstract: An apparatus package for high temperature thermal applications for ball grid array semiconductor devices and a method of packaging ball grid array semiconductor devices.

Abstract: A process for forming a thermally enhanced Chip On Board semiconductor device with a heat sink is described. In one aspect, a thermally conducting filled gel elastomer material or a silicon elastomeric material or elastomeric material, if the material is to be removed, is applied to the die surface to which the heat sink is to be bonded. During the subsequent glob top application and curing steps, difficult-to-remove glob top material which otherwise may be misapplied to the die surface adheres to the upper surface of the elastomer material. The elastomer material is removed by peeling prior to adhesion bonding of the heat sink to the die. In another aspect, the thermally conducting filled gel elastomer material is applied between a die surface and the inside attachment surface of a cap-style heat sink to eliminate overpressure on the die/substrate interface.

Abstract: A resin-molded semiconductor device includes: signal leads; a die pad with a central portion elevated above a peripheral portion thereof; support leads, each including a raised portion higher in level than the other portions; and DB paste for use in die bonding. All of these members are encapsulated within a resin encapsulant. The lower part of each of these signal leads protrudes downward out of the resin encapsulant and functions as an external electrode. Each of the support leads is provided with two bent portions to cushion the deforming force. By forming a half-blanked portion in the die pad, the central portion is elevated above the peripheral portion, thus preventing the semiconductor chip from being hampered by the support leads. Accordingly, the size of the semiconductor chip mounted can be selected from a broader range and the humidity resistance of the device can also be improved.

Abstract: Terminal pins with two lateral portions and a bridge-shaped elevated middle portion are provided. The terminal pin and perpendicularly rising hybrid circuit typically together have an inverted T shape. On the one hand, the hybrid circuit stands on its own on the substrate without further means of assistance and can be soldered. On the other hand, the bridge-shaped construction effects a sufficient elasticity and carrying capacity relative to swivellings, or respectively, accelerations, as well as effecting the presence of two defined support surfaces whose co-planarity is guaranteed by the springing configuration of the terminal pins.

Abstract: A surface mount type semiconductor package is mounted on a printed board by bonding, by means of solder bumps signal electrodes, electrically connected to respective terminals of a semiconductor chip incorporated in the package, with lands provided on the printed board. On a mount surface of the package, there are provided auxiliary electrodes formed as electrodes which are not electrically connected to the respective terminals of the semiconductor chip and have a thickness greater than that of the signal electrodes. As a result, solder thickness is secured for the solder bumps between each signal electrode and corresponding land by the difference in thickness between the auxiliary electrode and the signal electrode.

Abstract: In the manufacturing process of electronic modules a problem could arise when the modules have non-flat top surface. This is due to the fact that most of the automatic picking tools uses a vacuum nozzle to pick and place the module. According to the present invention a flat feature (a cap or a stud) is added to the module. This flat feature can be either fixed on the module or removable after the manufacture in order to reduce the dimensions.

Abstract: A liquid crystal display apparatus is provided which requires a small, thin and compact area for mounting semiconductor chips for driving liquid crystal and, accordingly, has a reduced cost. Semiconductor chips for driving liquid crystal are mounted on a surface (for example, a first layer) of a multi-layer substrate. The surface has input lines to the chips and output lines from the chips. The input lines have lands for connecting adjacent multi-layer substrates to each other. At least one intermediate layer is formed between an upper layer and a lower layer, the intermediate layer having bus lines. The bus lines and the input lines of the first layer are connected to one another via through holes in the first layer. The output lines of the first layer and terminals of the third layer are connected to one another via through holes in the first, second and third layers.

Abstract: A socket for attaching a flip chip die or ball grid array devices to a printed circuit board substrate having a pattern of solder covered lands, with resources for removing the flip chip die or ball grid array device, resources for directly aligning the solder balls of the flip chip die or ball grid array device to the printed circuit board, resources for using an interposer of dendrite coated vias or pads to electrically and physically connect the solder balls of the flip chip die or ball grid array devices to the solder deposits of the printed circuit board, resources for having the interposer reconfigure the wiring for testing or replacement purposes, resources for utilizing the flexibility and resilience of the interposer to improve dendrite connections, and resources for heat sinking the flip chip die or ball grid array device by direct thermal contact.

Abstract: A package for relatively high power transistors including heat conducting mounting flange having a relatively large "footprint" relative to the area covered by at least one active chip supported thereby and comprised of a plurality of bipolar silicon-carbide transistors. The transistors are located on a dielectric substrate brazed to the flange. A plurality of screw mounting holes, preferably eight in number, are included in the mounting flange adjacent the outer edge of the dielectric substrate so as to surround the chip. Mounting screws in the eight mounting holes together with a relatively large flange/ground plane interface significantly improves heat dissipation for the heat generated by the silicon carbide transistors by promoting radial heat spreading through the heat conductive metal flange.

Abstract: A stacked semiconductor multi-package including a plurality of individual semiconductor chip packages stacked over one another. The individual packages have a substrate provided with a plurality of bonding pads, electrode pads electrically connected to the bonding pads through wires, and chips attached to upper and lower surfaces of the substrate. A paddles lead frame is provided onto which the individual packages are attached to upper and lower surfaces thereof, and variants thereof. For these packages, since individual packages are mounted on upper and lower surfaces of a single printed circuit board or lead frame, the mounting density can be significantly increased and their production can be simplified.