Abstract: Embodiments include semiconductor device packages and methods of forming such packages. In an embodiment, the package may include a die-side reinforcement layer with a cavity formed through the die-side reinforcement layer. A die having a first side and an opposite second side comprising a device side may be positioned in the cavity with the first side of the die being substantially coplanar with a first side of the die-side reinforcement layer. In an embodiment, a build-up structure may be coupled to a second side of the die. Embodiments include a build-up structure that includes a plurality of alternating layers of patterned conductive material and insulating material.

Abstract: Embodiments include semiconductor device packages and methods of forming such packages. In an embodiment, the package may include a die-side reinforcement layer with a cavity formed through the die-side reinforcement layer. A die having a first side and an opposite second side comprising a device side may be positioned in the cavity with the first side of the die being substantially coplanar with a first side of the die-side reinforcement layer. In an embodiment, a build-up structure may be coupled to a second side of the die. Embodiments include a build-up structure that includes a plurality of alternating layers of patterned conductive material and insulating material.

Abstract: A semiconductor package includes a substrate having at least one recessed portion, a semiconductor device located on a surface of the substrate, the surface having the at least one recessed portion, and a resin insulating layer covering the semiconductor device.

Abstract: A semiconductor device has a semiconductor element provided with a functional surface on which a functional circuit is formed and with a back surface facing in the opposite direction to the functional surface, while also having a lead supporting the semiconductor element and electrically connected to the semiconductor element, and a resin package covering at least a portion of the semiconductor element and the lead. The semiconductor element has a functional surface side electrode formed on the functional surface and equipped with a functional surface side raised part that projects in the direction in which the functional surface faces. The functional surface side raised part of the functional surface side electrode is joined to the lead by solid state bonding.

Abstract: The mechanisms for forming bumps on packaged dies and package substrates reduce variation of bump heights across the packaged dies and packaged substrates. Bumps are designed to have different widths to counter the higher plating current near edge(s) of dies or substrates. Bump sizes can be divided into different zones depending on the bump patterns and densities across the packaged die and/or substrates. Smaller bumps near edges reduce the thickness of plated film(s), which would have been thicker due to being near the edges. As a result, the bump heights across the packaged dies and/or substrates can be kept significantly constant and chip package can be properly formed.

Abstract: A semiconductor device includes a semiconductor substrate, a pad electrode formed on the semiconductor substrate, a post electrode formed on the pad electrode and made of a copper film, a solder ball electrode formed on the post electrode and made of ternary alloy containing tin, a terminal connected to the solder ball electrode and formed on a front surface of a wiring board, and a sealing material filling a gap between the semiconductor substrate and the wiring board. The post electrode includes a cylindrical stem portion and an overhanging portion positioned in an upper part of the stem portion and protruding to an outer side of the stem portion, the solder ball electrode is connected to an upper surface of the post electrode over the stem portion and the overhanging portion, and a sidewall of the stem portion contacts with the sealing material over the entire circumference thereof.

Abstract: A device includes a Through-Assembly Via (TAV) Module, which includes a substrate, a plurality of through-vias penetrating through the substrate, and a second plurality of metal posts at a bottom surface of the TAV module and electrically coupled to the plurality of through-vias. A polymer includes a first portion between and contacting sidewalls of the first package component and the TAV module, a second portion disposed between the first plurality of metal posts, and a third portion disposed between the second plurality of metal posts. A first plurality of Redistribution Lines (RDLs) is underlying a bottom surface of the second and the third portions of the polymer. A second plurality of RDLs is over the first package component and the TAV module. The first plurality of RDLs is electrically coupled to the second plurality of RDLs through the plurality of through-vias in the TAV module.

Abstract: A power semiconductor device comprises a lead frame unit, a control die, a first MOSFET die and a second MOSFET die, wherein the lead frame unit comprises at least a die paddle for mounting the first and second MOSFET dies, a first pin and a second pin for connecting to top electrodes of the first and second MOSFET dies, a first row of carrier pins and a second row of carrier pins disposed in-line with the first and second pins respectively for the control die to mount thereon.

Abstract: A packaged semiconductor device includes at least first and second lead-fingers. A molded structure forms a cavity and is molded around portions of each of the first and second lead-fingers to thereby mechanically attach each of the first and second lead-fingers to the molded structure. A semiconductor structure (e.g., a IC, chip or die) is attached within the cavity. First and second bond wires respectively providing electrical connections between the semiconductor structure and the first and second lead-fingers. A further portion of each of the first and second lead-fingers is mechanically attached to a bottom surface of the semiconductor structure to inhibit relative mechanical motion between the semiconductor structure, the molded structure and the first and second lead-fingers.

Abstract: A metal plate covers an opening on the upper surface of a core substrate and exposes an outer edge of the upper surface of the core substrate. A conductive layer covers the lower surface of the core substrate. A semiconductor chip bonded to a first surface of the metal plate is exposed through the opening. A first insulating layer covers the upper and side surface of the metal plate and the outer edge of the upper surface of the core substrate. A second insulating layer fills the openings of the metal plate and the conductive layer and covers the outer edge of the lower surface of the core substrate, the conductive layer, and the semiconductor chip. The metal plate is thinner than the semiconductor chip. Total thickness of the conductive layer and the core substrate is equal to or larger than the thickness of the semiconductor chip.

Abstract: To obtain a semiconductor module that can fix itself onto a fixing object while enabling further miniaturization, in addition to alleviating load applied on a molded resin, a semiconductor module includes: a semiconductor element; a placing frame on which the semiconductor element is placed; a control substrate onto which a control component for controlling the semiconductor element is mounted; and a molded resin in which the semiconductor element, the placing frame, and the control substrate are integrally molded. Fixing bases exposed from the molded resin are provided on the control substrate for fixing the semiconductor module onto a chassis.

Abstract: Provided are semiconductor devices with a through electrode and methods of fabricating the same. The methods may include forming a via hole at least partially penetrating a substrate, the via hole having an entrance provided on a top surface of the substrate, forming a via-insulating layer to cover conformally an inner surface of the via hole, forming a buffer layer on the via-insulating layer to cover conformally the via hole provided with the via-insulating layer, the buffer layer being formed of a material whose shrinkability is superior to the via-insulating layer, forming a through electrode to fill the via hole provided with the buffer layer, and recessing a bottom surface of the substrate to expose the through electrode.

Abstract: A semiconductor device includes a substrate having a first side and a second side, the second side having a mounting location for at least one semiconductor element, and the first side having a plurality of locations electrically connected to locations on the second side. A plurality of electrically conductive interconnects are provided at the locations, each having a first end attached at the location and a second end spaced from the substrate, and an encapsulant partially encapsulates the plurality of interconnects and has a surface lying in a first plane. The second ends are located on the side of the first plane opposite from the substrate first side, an annular space in the encapsulant surrounds each of the plurality of electrically conductive interconnects, and the annular space has a bottom located between the first plane and the substrate first side. Also a method for making such a semiconductor device.

Abstract: A semiconductor device package is formed of DBC in which thinned MOSgated and/or diode die are soldered to the bottom of an etched depression in the upper conductive layer. A via in the insulation layer of the DBC is filled with a conductive material to form a resistive shunt. Plural packages may be formed in a DBC card and may be separated individually or in clusters. The individual packages are mounted in various arrays on a support DBC board and heat sink. Integrated circuits may be mounted on the assembly and connected to the die for control of the die conduction.

Abstract: A security device for protecting stored sensitive data includes a closed housing including an array of conductor paths and tamper detecting means adapted to detect a change in impedance of the array of conductor paths above a predetermined threshold value.

Abstract: Thermally-induced stress on a silicon micro-electromechanical pressure transducer (MEMS sensor) is reduced by attaching the MEMS sensor to a plastic filled with low CTE fillers that lowers the plastic's coefficient of thermal expansion (CTE) to be closer to that of silicon. The MEMS sensor is attached to the housing using an epoxy adhesive/silica filler mixture, which when cured has a CTE between about ten PPM/° C. and about thirty PPM/° C. in order to match the housing CTE. The adhesive also has a glass transition temperature (Tg) above the operating temperature range. This design provides good sealing of the sensor and stable sensor outputs.

Abstract: A semiconductor device includes: a package; an input matching circuit and an output matching circuit in the package; and transistor chips between the input matching circuit and the output matching circuit in the package. Each transistor chip includes a semiconductor substrate having long sides and short sides that are shorter than the long sides, and a gate electrode, a drain electrode and a source electrode on the semiconductor substrate. The gate electrode has gate fingers arranged along the long sides of the semiconductor substrate and a gate pad commonly connected to the gate fingers and connected to the input matching circuit via a first wire. The drain electrode is connected to the output matching circuit via a second wire. The long sides of the semiconductor substrates of the transistor chips are oblique with respect to an input/output direction extending from the input matching circuit to the output matching circuit.

Abstract: An integrated circuit chip includes a semiconductor substrate; a first interconnection wire having a first portion and a second portion on the semiconductor substrate, wherein the second portion is separated from the first portion; a second interconnection wire situated under the first interconnection wire; a first conductive via electrically coupling the first portion with the second interconnection wire; a conductive layer situated between the first interconnection wire and the second interconnection wire; and a second conductive via electrically coupling the conductive layer with the second portion.

Abstract: Microelectronic chip including a semiconductor substrate; at least one area of its surface which is suitable to be electrically connected to a metal frame designed to accommodate the chip; at least one interconnect area formed by a copper-based conductive layer and comprising a connecting device, the interconnect area being connected to the area by a conductor, wherein the area is formed by a layer forming a copper diffusion barrier inserted between interconnect area and the substrate.

Abstract: An LED lamp (A1) includes a plurality of LEDs (2), a retainer (1) on which the light LEDs (2) are mounted, and a wiring pattern formed on the retainer (1) and electrically connected to the LEDs (2). The retainer (1) includes a plurality of substrates (11, 12, 15). Of the plurality of substrates (11, 12, 15), two adjacent substrates (11, 12) are connected to each other by a pair of bendable connection members (32a, 32b). The two substrates (11, 12) are arranged in such a manner that their normal line directions differ from each other.

Abstract: A hybrid integrated optical device includes a substrate comprising a silicon layer and a compound semiconductor device bonded to the silicon layer. The device also includes a bonding region disposed between the silicon layer and the compound semiconductor device. The bonding region includes a metal-semiconductor bond at a first portion of the bonding region. The metal-semiconductor bond includes a first pad bonded to the silicon layer, a bonding metal bonded to the first pad, and a second pad bonded to the bonding metal and the compound semiconductor device. The bonding region also includes an interface assisted bond at a second portion of the bonding region. The interface assisted bond includes an interface layer positioned between the silicon layer and the compound semiconductor device, wherein the interface assisted bond provides an ohmic contact between the silicon layer and the compound semiconductor device.

Abstract: A composite integrated optical device includes a substrate including a silicon layer and a waveguide disposed in the silicon layer. The composite integrated optical device also includes an optical detector bonded to the silicon layer and a bonding region disposed between the silicon layer and the optical detector. The bonding region includes a metal-assisted bond at a first portion of the bonding region. The metal-assisted bond includes an interface layer positioned between the silicon layer and the optical detector. The bonding region also includes a direct semiconductor-semiconductor bond at a second portion of the bonding region.

Abstract: A semiconductor device package is formed of DBC in which thinned MOSgated and/or diode die are soldered to the bottom of an etched depression in the upper conductive layer. A via in the insulation layer of the DBC is filled with a conductive material to form a resistive shunt. Plural packages may be formed in a DBC card and may be separated individually or in clusters. The individual packages are mounted in various arrays on a support DBC board and heat sink. Integrated circuits may be mounted on the assembly and connected to the die for control of the die conduction.

Abstract: A photoelectric device package and a detachable package structure are provided. The photoelectric device package includes a bottom-plate, a top-plate, at least one photoelectric device, and at least one light-guiding element. The bottom-plate has a first carrying part and a first substrate part on the first carrying part. The first carrying part has first alignment portions. The first substrate part has second alignment portions. The top-plate has a second carrying part and a second substrate part on the second carrying part. The second carrying part has third alignment portions. The second substrate part has fourth alignment portions. The top-plate and the bottom-plate are assembled by the first and third alignment portions. The first and second substrate parts are positioned by the second and fourth alignment portions. Each photoelectric device is disposed on the first substrate part. Each light-guiding element is disposed between the first and second substrate parts.

Abstract: A power module includes at least one semiconductor die holding structure. Each die holding structure has a substantially cylindrical outer profile and a central axis. Each die holding structure is disposed within a common cylindrical EMI shield. A plurality of semiconductor devices are mounted to each die holding structure to form a substantially symmetric die mounting pattern respect to the central axis of the die holding structure.

Abstract: An integrated circuit chip includes a semiconductor substrate; a first interconnection wire having a first portion and a second portion on the semiconductor substrate, wherein the second portion is separated from the first portion; a second interconnection wire situated under the first interconnection wire; a first conductive via electrically coupling the first portion with the second interconnection wire; a conductive layer situated between the first interconnection wire and the second interconnection wire; and a second conductive via electrically coupling the conductive layer with the second portion.

Abstract: A semiconductor laser device includes a Si(100) substrate in which a recess having an opening and a bottom face surrounded by inner wall surfaces is formed, a semiconductor laser element placed on the bottom face, and a translucent sealing glass, mounted on top of the Si(100) substrate, which seals the opening. The laser light emitted from the semiconductor laser element is reflected by a metallic reflective film formed on the inner wall surface and then transmits through the sealing glass so as to be emitted externally.

Abstract: A package includes: a metal wall disposed on a conductive base plate; a through-hole disposed in input/output portions of the metal wall; a lower layer feed through disposed on the conductive base plate; a wiring pattern disposed on the lower layer feed through; an upper layer feed through disposed on a part of the lower layer feed through and a part of the wiring pattern; and a terminal disposed on the wiring pattern, wherein a width of a part of the lower layer feed through and a width of the upper layer feed through are wider than a width of the through-hole, the lower layer feed through is adhered to a side surface of the metal wall, the upper layer feed through is adhered to the side surface of metal wall, and an air layer is formed between the wiring pattern and an internal wall of the through-hole.

Abstract: A semiconductor device includes a substrate having a first side and a second side, the second side having a mounting location for at least one semiconductor element, and the first side having a plurality of locations electrically connected to locations on the second side. A plurality of electrically conductive interconnects are provided at the locations, each having a first end attached at the location and a second end spaced from the substrate, and an encapsulant partially encapsulates the plurality of interconnects and has a surface lying in a first plane. The second ends are located on the side of the first plane opposite from the substrate first side, an annular space in the encapsulant surrounds each of the plurality of electrically conductive interconnects, and the annular space has a bottom located between the first plane and the substrate first side. Also a method for making such a semiconductor device.

Abstract: A packaging substrate structure with an electronic component embedded therein and a fabricating method thereof are disclosed. The packaging substrate structure comprises a core plate; a first built-up structure disposed on a surface of the core plate and comprising a first dielectric layer and a first circuit layer disposed on the first dielectric layer; a second built-up structure disposed on the first built-up structure, wherein a cavity is disposed in the second built-up structure to expose the first built-up structure; an electronic component disposed in the cavity, wherein the electronic component has an active surface having a plurality of electrode pads and an inactive surface facing the first built-up structure; and a solder mask disposed on the surfaces of the second built-up structure and the electronic component, and having a plurality of first openings to expose the electrode pads of the electronic component.

Abstract: A package structure includes a first carrier board provided with a through hole, at least a filling hole in communication with the through hole, a semiconductor chip received in the through hole, and a fastening member disposed in the filling hole and abutting against the semiconductor chip so as to secure the semiconductor chip in position, thereby preventing the semiconductor chip in the through hole from displacement under an external force.

Abstract: A security protection device includes a cover circuit board, at least one inner wiring layer being included within the cover circuit board. The device also includes a base circuit board, at least one inner wiring layer being included within the base circuit board. The device further includes a security frame between the base circuit board and the cover circuit board, at least one electrically conductive wire being wound and included within the security frame to form at least one winding protection layer around sides of the security frame. The cover circuit board, the security frame, and the base circuit board form an enclosure enclosing a security zone, and the at least one inner wiring layer within the cover circuit board, the at least one inner wiring layer within the base circuit board, and the at least one electrically conductive wire within the security frame are connectable to a security mechanism configured to detect an intrusion into the security zone.

Abstract: A semiconductor device has a first semiconductor die with a shielding layer formed over its back surface. The first semiconductor die is mounted to a carrier. A first insulating layer is formed over the shielding layer. A second semiconductor die is mounted over the first semiconductor die separated by the shielding layer and first insulating layer. A second insulating layer is deposited over the first and second semiconductor die. A first interconnect structure is formed over the second semiconductor die and second insulating layer. A second interconnect structure is formed over the first semiconductor die and second insulating layer. The shielding layer is electrically connected to a low-impedance ground point through a bond wire, RDL, or TSV. The second semiconductor die may also have a shielding layer formed on its back surface. The semiconductor die are bonded through the metal-to-metal shielding layers.

Abstract: An electronic component mounting configuration in which an electronic component chip having a plurality of protrusion-shaped electrodes distributed on its entire mounting surface is mounted through protrusion-shaped electrodes on a printed circuit board is provided which is capable of improving reliability of an electronic component by relieving thermal stress. The solder bumps are arranged so that intervals between solder bumps adjacent to one another become smaller from a central portion of a mounting surface of the electronic component chip toward the peripheral portion thereof. For example, an interval between the solder bump “1A” arranged in the central portion of the semiconductor chip and the solder bump “1B” arranged in an outer side thereof, adjacent to each other, is set to a pitch of P1.

Abstract: Semiconductor dies are stacked offset from one another so that terminals located along two edges of each die are exposed. The two edges of the dies having terminals may be oriented in the same direction. Electrical connections may connect terminals on one die with terminals on another die, and the stack may be disposed on a wiring substrate to which the terminals of the dies may be electrically connected.

Abstract: The invention relates in a general aspect to a method of making vertically protruding elements on a substrate, said elements having a tip comprising at least one inclined surface and an elongated body portion extending between said substrate and said tip. The method comprises an anisotropic, crystal plane dependent etch forming said inclined surface(s); and an anisotropic, non crystal plane dependent etch forming said elongated body portion; combined with suitable patterning processes defining said protruding elements to have a predetermined base geometry.

Abstract: Submounts for mounting optical devices which have an excellent heat radiating property and can be formed in a wafer state in batch are provided. A metallized electrode including optical device mounting parts and wiring parts is formed on a surface of a first substrate containing an insulating material as a main component, a through hole is formed in a glass substrate serving as a second substrate, the optical device mounting parts of the first substrate are aligned to be located inside the through hole of the second substrate, and the first substrate and the second substrate are joined together by use of a method such as anodic bonding.

Abstract: A power semiconductor module system. One embodiment provides a power semiconductor module and a mounting adapter. The mounting adapter and the power semiconductor module can be latched to one another in two different latching stages such that a contact element of the power semiconductor module makes electrical contact with a contact element of the mounting adapter assigned to the contact element in a second one of the latching stages but not in a first one of the latching stages.

Abstract: An electrical interconnect assembly for electrically interconnecting terminals on a first circuit member with terminals on a second circuit member. The electrical interconnect assembly includes a housing having a plurality of through openings extending between a first surface and a second surface. A plurality of composite contacts are positioned in a plurality of the through openings. The composite contacts include a conductive member having a central portion and at least first and second interface portions. One or more polymeric layers extend along at least the central portion conductive member. One or more coupling features on the composite contacts engage with the housing. At least one engagement feature formed in the polymeric layers proximate the first interface portion mechanically couples with the terminals on the first circuit member.

Abstract: A semiconductor integrated circuit (IC) device is defined by a low-profile package without a die attach pad (DAP). In place of the DAP, an adhesive element is used to retain a die relative to a lead frame during processing. In one example, a method of manufacturing the device includes sealing the lead frame on one side using an adhesive tape and exposing a portion of the tape within a die attach region. The die is secured onto the tape adhesive and held in place during subsequent processing, such as a wire bonding procedure to couple the die to external portions of the frame.

Abstract: An electronic component includes a lead frame assembly, an insert, a semiconductor chip and an encapsulation compound. The lead frame assembly includes a mounting hole, a die pad, a plurality of bonding fingers and a plurality of lead fingers. The insert includes a hollow center and is provided at the mounting hole of the lead frame assembly. The semiconductor chip is arranged on the die pad and includes contact areas on its surface. A plurality of electrical contacts respectively links the contact areas of the semiconductor chip to the bonding fingers of the lead frame assembly. An encapsulating compound encloses the insert, the semiconductor chip, and the electrical contacts, however, leaves the hollow center of the insert uncovered.

Abstract: The specification teaches a device for use in the manufacturing of microelectronic, microoptoelectronic or micromechanical devices (microdevices) in which a contaminant absorption layer improves the life and operation of the microdevice. In a preferred embodiment the invention includes a mechanical supporting base, and a layer of a gas absorbing or purifier material is deposited on the base by a variety of techniques and a layer for temporary protection of the purification material is placed on top of the purification material. The temporary protection material is compatible for use in the microdevice and can be removed during the manufacture of the microdevice.

Abstract: Apparatus and methods for mounting of a processor coupled to a circuit board include use of a frame disposed around the processor. The frame decreases flexibility of the circuit board around the processor. Further, the frame may act as a mechanical stop limiting tilting of a heat sink coupled to the processor.

Abstract: The present invention relates to a semiconductor package transformer. There is provided a semiconductor package transformer including: a case where an opening into which a semiconductor package having a chip mounted on a substrate is inserted is formed on its front surface and an open part exposing is formed on its upper surface; and a plurality of holes that are formed on the bottom surface of the case.

Abstract: The present invention relates to a connecting structure between semiconductor device 1 of a BGA type which has external electrode terminals 9 including column-like electrode 17, insulating layer 16 formed around the column-like electrode 17 and annular electrode 15 formed around the insulating layer 16, and a printed wiring board capable of mounting the semiconductor device 1 and including lower-layer electrode 28 to be soldered to column-like electrode 17 of the aforementioned external electrode terminal 9 and upper-layer electrode 27 to be soldered to annular electrode 15 of the aforementioned external electrode terminal 9. Column-like electrode 17 of semiconductor device 1 is soldered to lower-layer electrode 28 of printed wiring board 2. Annular electrode 15 of semiconductor device 1 is soldered to upper-layer electrode 27 of printed wiring board 2.

Abstract: In an embodiment, the invention provides a PLCC package comprising first and second lead frames, a plastic structural body, a light source, an encapsulant, and an optical lens. The first lead frame comprises two tongues and a reflector cup. The first and second lead frames are attached to the plastic structural body. The light source is mounted and electrically connected at the bottom of the inside of the reflector cup. The light source is also electrically connected to the second lead frame by a wire bond. The reflector cup is surrounded on at least four sides by the encapsulant, the encapsulant having a domed portion that functions as the optical lens, the encapsulant being an integral single piece structure.

Abstract: In an embodiment, the invention provides a LFCC package comprising first, second and third lead frames, a light source, and an encapsulant. The first lead frame comprises two tongues and a reflector cup. The first, second and third lead frames are attached to the encapsulant. The light source is mounted at the bottom of the inside of the reflector cup. The light source is electrically connected to the second and third lead frames by wire bonds. The reflector cup is surrounded on at least four sides by the encapsulant, the encapsulant being an integral single piece structure.

Abstract: An electrical interconnect assembly for electrically interconnecting terminals on a first circuit member with terminals on a second circuit member. The electrical interconnect includes a housing having a plurality of through openings extending between a first surface and a second surface. A plurality of composite contacts are positioned in a plurality of the through openings. The composite contacts include a conductive member having a central portion and at least first and second interface portions. One or more polymeric layers extend along at least the central portion conductive member. One or more coupling features on the composite contacts engage with the housing. At least one engagement feature formed in the polymeric layers proximate the first interface portion mechanically couples with the terminals on the first circuit member.

Abstract: A semiconductor device package is formed of DBC in which thinned MOSgated and/or diode die are soldered to the bottom of an etched depression in the upper conductive layer. A via in the insulation layer of the DBC is filled with a conductive material to form a resistive shunt. Plural packages may be formed in a DBC card and may be separated individually or in clusters. The individual packages are mounted in various arrays on a support DBC board and heat sink. Integrated circuits may be mounted on the assembly and connected to the die for control of the die conduction.

Abstract: A stacked electronic component comprises a first electronic component adhered on a substrate via a first adhesive layer, and a second electronic component adhered by using a second adhesive layer thereon. The second adhesive layer has a two-layer structure formed by a same material and having different modulus of elasticity. The second adhesive layer of the two-layer structure has a first layer disposed at the first electronic component side and a second layer disposed at the second electronic component side. The first layer softens or melts at an adhesive temperature. The second layer maintains a layered shape at the adhesive temperature. According to the stacked electronic component, occurrences of an insulation failure and a short circuiting are prevented, and in addition, a peeling failure between the electronic components, an increase of a manufacturing cost, and so on, can be suppressed.