Abstract: An interconnection contact structure assembly including an electronic component having a surface and a conductive contact carried by the electronic component and accessible at the surface. The contact structure includes an internal flexible elongate member having first and second ends and with the first end forming a first intimate bond to the surface of said conductive contact terminal without the use of a separate bonding material. An electrically conductive shell is provided and is formed of at least one layer of a conductive material enveloping the elongate member and forming a second intimate bond with at least a portion of the conductive contact terminal immediately adjacent the first intimate bond.

Abstract: A leadframe for an IC package and a method of manufacturing the same are provided. The leadframe can be manufactured in such a manner as to provide suitable bondability, molding compound characteristic, and solderability. The leadframe includes a base structure made from a conductive material. A silver plating is formed over the base structure of the leadframe, and a palladium plating is formed over the silver plating. Depending on actual requirements, a copper layer and a nickel plating can be formed between the silver plating and the base structure of the leadframe, and a palladium/nickel plating can be found between the silver and palladium platings. Further, a gold layer can be formed over the palladium plating. The palladium plating and the palladium/nickel plating can be formed all over the leadframe or selectively formed only in the external-lead area of the leadframe.

Abstract: A multi-layer lead frame for use in a semiconductor package is described. The described lead frame is particularly well suited for application where fine pitch leads and/or lead multi-routing capability is required. In one embodiment, the multi-layered lead frame includes a first lead trace layer superimposed over and adhered to a second lead trace layer. The first and second lead trace layers each have a plurality of leads and each layer has an external portion and an internal portion. Each of the leads in the first trace layer has an associated lead in the second trace layer that has a matching external portion. The matching external portions are bonded together when the trace layers are superimposed. At least some of the leads in the first trace layer have different lengths than the matching leads of the second trace layer. This permit the leads to be routed separately, and may be used to facilitate finer lead pitches than would be possible in full thickness lead frames.

Abstract: A semiconductor power module has semiconductor components mounted on a substrate. The semiconductor components are in electrical contact with the substrate. Internal circuit wiring is achieved by using one or more flexible circuit boards. The flexible circuit board(s) contact the semiconductor components and also provide external connection elements. Hermetical encapsulation is achieved by lamination, and height equalization of the different circuit regions is achieved by using geometrically preformed prepregs in conjunction with the flexible circuit board and the substrate.

Abstract: A lead frame for a semiconductor chip package, including a die pad onto which a semiconductor chip will be attached; leads which will be electrically connected to the chip; and side rails supporting the leads and the die pad; a second metal being contact with the rails, this second metal having a higher standard electrode potential than that of the copper metal or alloy of which the remainder of the lead frame is made.

Abstract: The present invention is to provide an electronic part mounting device including: a lamination body composed of a circuit board and a structural member; an electronic part attached in an opening formed in the lamination body; and an encapsulant layer to encapsulate the electronic part, wherein an outer circumferential line of the opening is arranged inside an outer circumferential line of the encapsulant layer. Due to the foregoing arrangement, in the electronic part mounting device of the present invention, even if the device is bent, the encapsulant layer to encapsulate the electronic part is engaged with the circuit board or the structural member arranged inside the outer circumferential line of the encapsulant layer, so that electronic parts are prevented from coming off. Further, the manufacturing process is simple. Therefore, the cost of the electronic part mounting device can be greatly reduced.

Abstract: An electronic component assembly (10) is formed by mounting an electronic component (31) to a substrate (11). An encapsulating material (33) is used to protect the electronic component (31) from environmental hazards. The encapsulating material (33) is formed by dispensing an encapsulating fluid over the electronic component (31). A trench (36) is formed in a masking layer (21) on a substrate (11) to stop the flow of the encapsulating fluid. The trench (36) provides an edge (35) which acts as a discontinuity in the surface (23) of the masking layer (21). This discontinuity is sufficient to control the flow of the encapsulating fluid until the encapsulating fluid is cured to form the encapsulating material (33).

Abstract: The present invention relates to a lead frame for the formation of a frame structure of an integrated circuit, more particularly, to a lead frame, having a structure possessing excellent bondability, solder wettability, and Ag paste adhesion. A lead frame for a semiconductor device comprises a lead frame material; a Pd plating or a Pd alloy plating, provided on the lead frame material; and a layer as an uppermost layer formed of a Pd oxide and gold or silver. A process for producing a lead frame for a semiconductor device comprises the steps of: plating a lead frame material with Pd or a Pd alloy; flasing the surface of the Pd or Pd alloy plating with gold (Au); and heat-treating the plated lead frame material in the air to provide a thin Pd oxide layer in only a Pd portion on the surface of a diffusion layer formed of Pd and Au.

Abstract: A method and structure is given for flip-chip mounting an integrated circuit on a substrate. An embodiment of the present invention is a GaAs die flip-chip 14 mounted to a silicon semiconductor 10 which has additional processing circuitry. The flip-chip bond uses an alloy metal film, preferably a thin film of AuGe 38, 40. The invention gives a high temperature bond which is suitable for subsequent high temperature processes to be performed on the flip-chip mounted combination. The bond may also include a diffusion barrier 36 which provides a short circuit free LED contact. A preferred embodiment introduces a microchip chemical sensor by integrating a GaAs LED 14 with a polyimide waveguide 56 and a silicon photosensor 16 on the same chip.

Abstract: A method of forming interconnecting layers in a semiconductor device whereby even if a via is misaligned with a metal line, a portion of the via not enclosed and capped by the metal is enclosed and capped by an etch stop spacer. The foundation layer includes a dielectric layer having a trench formed therein, the trench being filled with a plug material. The foundation layer further includes a barrier layer formed atop the dielectric layer. A metal layer is formed on the surface of the boundary layer, and a protection layer is formed on the surface of the metal layer. The protection layer and the metal layer are patterned to define a line of composite protection/metal on the surface of the boundary layer. An etch stop layer is formed which substantially conforms to the shape of the composite protection/metal line, including etch stop spacers conforming to the sidewall portions of the line.

Abstract: A semiconductor device comprises a semiconductor chip, an Au bump formed on the semiconductor chip, and Cu lead bonded to the Au bump through a bonding part. The Cu lead has a Cu core and a plated Sn layer formed on the Cu core, and the bonding part is formed of an Au--rich Au--Cu--Sn alloy of a ternary system having a single-phase structure with a composition of 15 atomic % Sn or less and 25 atomic % Cu or less.

Abstract: An electrical connection structure is provided for protecting a barrier metal layer within a contact opening during the formation of an aluminum interconnection layer overlying a tungsten plugged connection structure. The deposited tungsten plug overlying the barrier metal layer is etched back sufficiently to create a slight recess at the opening. A thin layer of tungsten is then selectively deposited for filling the recess. This layer acts as an etch stop during aluminum interconnection layer formation and protects the underlying barrier metal layer.

Abstract: A lead frame comprising an ultra-thin composite of noble metal layers on a nickel surface is disclosed. The composite ranges from 2.5 to 11 microinches in thickness and includes in succession from nickel, a 0.5 to 3.5 microinches of palladium or gold strike, a 0.5 to 5 microinches thick palladium-nickel alloy layer having 10 to 90 weight percent nickel by weight of the alloy, a 0.5 to 5 microinches thick palladium layer, and a 0 to 1 microinch thick gold layer. The gold layer is being used whenever it is desirable to achieve high speed of solder wetting, relative to the speed of solder wetting of palladium. Viable ultra-thin coatings are most effectively obtained by deposition of the layers in a reel-to-reel metal deposition process.

Abstract: A universal semiconductor interconnect test structure and method for using the test structure is provided for detecting the presence of electrical open or short circuits within the test package. In one embodiment, the test structure comprises a layer of electrically non-conductive substrate and a bonding layer of electrically conductive material over the substrate layer. In a second embodiment, the universal test die comprises a layer of electrically non-conductive substrate and a pattern of electrically conductive material over the substrate layer, wherein the pattern forms a continuous array of individual bonding areas, each of the bonding areas being electrically isolated from adjacent bonding areas by a gap, and wherein the effective pitch of the bonding areas is not more than 25 microns. The universal test die of the present invention is suitable for developing wire bond and mold processes for all pad pitches, all pad layout designs, all package types, and all pin counts.

Abstract: A plurality of electrode pads are formed on a main surface of a semiconductor chip. The electrode pads on the semiconductor chip are electrically connected to the top end of an inner lead through a metal plating layer.

Abstract: A lead frame for a semiconductor device includes a base layer which is coated by a protective coating. The protective coating includes a layer of nickel, over which is coated a layer of copper. The layer of copper is coated by a layer of silver over which is coated a layer of palladium. Protective coatings constructed in this way are bondable, solderable, oxidation resistant, corrosion resistant, free of lead (Pb), resistant to high temperatures, cost effective, and cosmetically acceptable. It is also possible to use a layer of tin or a tin alloy in place of the silver layer. It is possible to omit the nickel layer if the lead base layer is made of a ferrous material.

Abstract: A fabrication method including a semiconductor chip kerf clear process and a resulting semiconductor chip and electronic module formed thereby. The fabrication method includes providing a wafer comprising a plurality of integrated circuit chips having kerf regions between them. Chip metallization is present within the kerf regions. A photolithography process is used to protect the wafer exposing only the kerf regions. Next, the wafer is etched, clearing the chip metallization from the kerf regions. The wafer is then diced and the chips are stacked to form a monolithic electronic module. A side surface of the electronic module is processed to expose transfer metals extending thereto, thereby facilitating electrical connection to the chips within the electronic module. Specific details of the fabrication method, resulting integrated circuit chips and monolithic electronic module are set forth.

Abstract: A solderable lead frame is disclosed which includes a copper base lead frame containing a one layer or plated tin or tin alloy and another layer of plated palladium. The tin plating covers only external portions of the leads, whereas the palladium covers the external regions including the tin plating, and extends into internal portions of the lead frame. A diffusion barrier, of cobalt or nickel, is provided on the base lead frame beneath the tin plating.

Abstract: An integrated circuit chip structure, which prevents electrical shorts between adjacent electrodes and contributes to miniaturization, and a method for forming an integrated circuit chip structure are provided. A first electrode of a predetermined pattern is formed on the integrated circuit chip and a second electrode is formed on a base in correspondence with the first electrode. A first adhesive made of elastomer is deposited on the second electrode and a conductive metal substance is coated thereon. Finally, the second electrode is joined with the first electrode by pressure, after a second adhesive is deposited on the upper surface of the metal substance.

Abstract: A multichip substrate including a bonding pad, wiring layers insulated by polyimide layers and structure for protecting separation or the polyimide layers from occurring due to water oozing from the polyimide layers by: fabricating posts between the bonding pad and an inorganic insulation layer fabricated on a base substrate through the organic insulation layers by accumulating parts of the wiring layers; and providing holes for setting the water free, around the bonding pad so that the polyimide layer is exposed out of the multichip substrate; or fabricating the bonding pad directly on the inorganic insulation layer, fabricating the polyimide layers and wiring layers in terraced configuration at a periphery of the bonding pad.

Abstract: An outer lead having a plurality of external leads 1 for electrically connecting the semiconductor IC of a semiconductor IC package to external devices comprises a base plate 11, a plated base structure formed over the surface of the base plate 11 and consisting of a plurality of plated base layers 12, 13 and 14 of Ni or a Ni alloy, and a surface layer 15 of Au or an Au alloy formed over the uppermost plated base layer 14 of the plated base structure. The number of the plated base layers is at least three. Each plated base layer 12, 13 and 14 of the plated base structure is subjected to crystal-growth annealing after being formed by plating to crystal-grow the grains thereof. A method of fabricating such an outer lead is provided.

Abstract: There is disclosed a leadframe for electrically interconnecting a semiconductor device to external circuitry. The leadframe has an electrically conductive substrate that is coated with an oxidation resistant external layer. An intervening layer is disposed between a portion of the substrate and the external layer. The intervening layer is absent from the outer lead ends of the leadframe. Subsequent removal of the external layer from the outer lead ends enables a solder to directly contact the leadframe substrate.

Abstract: A semiconductor device includes a package containing a semiconductor element disposed on a die pad, and a plurality of leads extending from an inside of the package to an outside of the package. The plurality of leads are arranged up and down in a staggered manner, an interval between ends of lower stage leads in the package is narrower than a width of upper stage leads, and ends of the lower stage leads in the package are positioned nearer to the die pad than ends of the upper stage leads.

Abstract: A semiconductor package comprises an aluminum nitride substrate having a semiconductor element mounted thereon, a lead frame junctioned to the side of the aluminum nitride substrate directly contacting the mounted semiconductor element, and a ceramic sealing member junctioned to the aluminum nitride substrate so as to seal the semiconductor element. The lead frame has a coating layer of a nonmagnetic metallic material formed in a thickness of not more than 20 .mu.m on only one of the opposite surfaces of a lead frame matrix made of a ferromagnetic metal to which a bonding wire is to be junctioned. The layer of the nonmagnetic metallic material is formed by any of such thin film forming technique as the vacuum deposition technique, the spattering technique, and the plating technique. The coating layer formed on only one of the opposite surfaces of the lead frame matrix is capable of amply curbing the resistance and the dependency of inductance on frequency.

Abstract: This invention relates to a process for strengthening the adhesive bond between a lead frame and a plastic mold compound (350). The process involves plating the lead frame with a copper strike and selectively exposing the copper strike to an oxidizing agent to form a layer of cupric oxide (CuO) (318). Such lead frames are fitted with chips (324) and then encapsulated in the plastic mold compound (350), whereby the adhesive bond forms directly between the layer of CuO (318) and the plastic mold compound (350). A lead frame produced by this process may include a plurality of leads (310) having lead ends (312) and lead fingers (314) and a die pad (320) having a layer of CuO (318). The die pad (320) is encased by a plastic mold compound (350) which forms an adhesive bond directly with the layer of CuO (318). This layer (318) may have a thickness in a range of about 5 to 50.mu. inches (12.7 to 127 .mu.cm). Lead ends (312 ) and lead fingers (314) may be spot-plated with silver or palladium.

Abstract: There is provided a lead frame with enhanced adhesion to a polymer resin. The lead frame is coated with a thin layer of containing chromium, zinc or a mixture of chromium and zinc. A mixture of chromium and zinc with the zinc-to-chromium ratio in excess of about 4:1 is most preferred. The coated lead frames exhibit improved adhesion to a polymeric resin.

Abstract: A high voltage device (10) having MOS input characteristics. A low voltage MOS transistor (12) is provided which has a source (18), a drain (22), and a gate (25). A high voltage transistor (14) is also provided which has a source (20), a drain (24), and gate (16). The source (18) of the low voltage MOS transistor (12) is connected to the gate (16) of the high voltage transistor (14). The drain (22) of the low voltage MOS transistor (12)is connected to the source (20)of the high voltage transistor The low voltage MOS transistor (12) may have a silicon substrate and the substrate of the high voltage transistor (14)may comprise silicon, silicon carbide, or gallium arsenide.

Abstract: A packaged device with a lead frame, a lead frame and an article of manufacture comprising a base metal, a layer of nickel on the base metal, and a protective composite of metal layers on the nickel. The composite includes, in succession from the nickel layer, a layer of palladium or soft gold strike, a layer of palladium-nickel alloy, a layer of palladium and a layer of gold. The palladium or soft gold strike layer acts primarily as a bonding (an adhesive) layer between the Ni and Pd-Ni alloy layers and as a layer that enhances reduction in porosity of subsequent layers, Pd-Ni alloy layer acts as a trap for base metal ions, Pd layer acts as a trap for Ni ions from the Pd-Ni alloy layer, and the outer gold layer synergistically enhances the quality to the Pd layer. The various layers are in thickness sufficient to effectively accomplish each of their designated roles, depending on the processing and use conditions.

Abstract: Disclosed is a semiconductor device comprising a lead frame which includes a metal layer forming an outer lead, a thin metal layer forming an inner lead, an intermediate layer held between the thick metal layer and the thin metal layer for forming a connection portion between the outer lead and the inner lead and a bump positioned at the extreme end of the lead frame, whereby making the lead frame as an electrode leading means by directly connecting the bump to each electrode of a semiconductor element, wherein the lead formed of the thick metal layer has a thickness of 30 to 300 .mu.m, the lead formed of the thin metal layer has a thickness of 10 to 50 .mu.m, and the bump has thickness of 5 to 50 .mu.m.

Abstract: A semiconductor device having an electrode wiring which prevents generation of hillock and has good stress migration capability is disclosed. A multi layer film including at least two Al-Si-Cu alloy films and at least two titanium nitride films formed by reactive sputtering laminated alternately with the Al-Si-Cu alloy films has a high mechanical strength against deformation and can effectively prevent generation of hillock. Ti-Al intermetallic compounds are formed in grain boundaries and in interfaces, which is effective to restrict generation of a void. Propagation of a void can be prevented by the intermediate titanium nitride film. Further, the formation of the Ti-Al compounds is restricted and an increase of resistance is negligible.

Abstract: An improved semiconductor device is disclosed having a predetermined amount of solder, or other electrically conductive binder adsorbed onto the exterior package leads of the semiconductor device. A de-wettable coating comprising preferably nickel, or alternatively chromium, is plated to a superior portion of the package leads, such that, when the heat is applied to the substrate mounting end of the leads, solder desorbes from the de-wettable layer and flows down the lead to the contact pads on the mounting substrate and forms a solder joint. The amount of solder delivered to the contact pad for joint formation is determined by the thickness of the adsorbed solder layer overlying each package lead. Only enough solder is provided on each lead sufficient to form the joint thus avoiding solder bridging between adjacent contact pads.

Abstract: Actualized are fingers through which a semiconductor integrated circuit including high density electrode strings can be easily safely mounted on a circuit substrate in the same manner with the prior art. A conductor pattern capable of improving a packaging density of the integrated circuit including the fingers is actualized. The fingers are therefore configured using the multi-layered conductor pattern. The conductor pattern is multi-layered, i.e., consists of conductive layers and an insulating layer for separating these conductive layers. In addition to a wiring pattern serving as fingers for connecting an integrated circuit to a packaging substrate, an electrification path for interlayer connections is also formed in a thickness direction. The circuit substrate exhibiting a high packaging density can be actualized.

Abstract: A planarized multi-layer metal bonding pad. A first metal bonding pad layer (13) that defines a metal bonding pad is provided. A first dielectric layer (14) is provided with a multitude of vias (17) that covers the first metal bonding pad layer (13), thereby exposing portions of the first metal bonding pad layer (13) through the multitude of vias (17) in the first dielectric (14). A second metal bonding pad layer (18) that further defines the metal bonding pad is deposited on the first dielectric layer (14) making electrical contact to the first metal bonding pad layer through the multitude of vias (17). Planarization of the second metal bonding pad layer (18) is achieved by having the second metal bonding pad layer (18) cover the first dielectric layer (14) and making contact through the vias (17).

Abstract: An interconnection structure of a semiconductor device for electrically connecting a thin conductive layer and a metallization and the fabrication method thereof are disclosed. The interconnection structure includes a semiconductor substrate, an insulating layer coated on the substrate, a thick conductive layer formed on a certain portion of the insulating layer, a first interlaid insulating layer covering the thick conductive layer, a first contact hole formed within the first interlaid insulating layer on the thick conductive layer, a thin conductive layer consisting of vertical structure formed in the first contact hole and horizontal structure formed on the first interlaid insulating layer, a second interlaid insulating layer covering the thin conductive layer, a second contact hole formed within said first and second interlaid insulating layers and crossing the first contact hole, and a metallization filling the second contact hole and formed on the second interlaid insulating layer.

Abstract: A dynamic latch circuit which is fabricated in a semiconductor integrated circuit comprises a first circuit such as a clocked inverter and a second circuit such as an inverter. The first and second circuits are connected by a holding line. In the semiconductor integrated circuit, at least three interconnection layers are provided on a semiconductor substrate to be insulated by insulating layers, such that the holding line is provided as the secondly highest interconnection layer, and an output line of the second circuit is provided as the uppermost interconnection layer to be positioned on the straight upper side of the holding line. For this structure, a coupling capacitance which is formed between the holding line and a through line connected to a third circuit and provided as the uppermost interconnection layer is decreased.

Abstract: A comb insert for semiconductor packaged devices is disclosed. The comb is conductive and thus useful to function as a power supply bus in transferring power to the semiconductor die. A base, formed out of a conductive material, resides underneath the lead fingers of the semiconductor packaged device, electrically isolated from the lead fingers. The base has teeth extending from it, also formed out of the conductive material, that reside between the lead fingers of the semiconductor packaged device. Some of the teeth are electrically connected to the lead fingers for receiving external power. Some of the teeth are electrically connected to the bonding pads of the semiconductor die. Power is transferred from the lead fingers for receiving it, through the teeth electrically connected to these lead fingers, through the base, through the teeth electrically connected to the bonding pads, and to the semiconductor die.