Ball Shaped Patents (Class 257/738)
  • Patent number: 11031326
    Abstract: A wiring structure includes an insulating layer and a conductive structure. The insulating layer has an upper surface and a lower surface opposite to the upper surface, and defines an opening extending through the insulating layer. The conductive structure is disposed in the opening of the insulating layer, and includes a first barrier layer and a wetting layer. The first barrier layer is disposed on a sidewall of the opening of the insulating layer, and defines a through hole extending through the first barrier layer. The wetting layer is disposed on the first barrier layer. A portion of the wetting layer is exposed from the through hole of the first barrier layer and the lower surface of the insulating layer to form a ball pad.
    Type: Grant
    Filed: February 26, 2020
    Date of Patent: June 8, 2021
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Wen Hung Huang, Chien-Mei Huang, Yan Wen Chung
  • Patent number: 11018101
    Abstract: A semiconductor device includes a conductive component on a substrate, a passivation layer on the substrate and including an opening that exposes at least a portion of the conductive component, and a pad structure in the opening and located on the passivation layer, the pad structure being electrically connected to the conductive component. The pad structure includes a lower conductive layer conformally extending on an inner sidewall of the opening, the lower conductive layer including a conductive barrier layer, a first seed layer, an etch stop layer, and a second seed layer that are sequentially stacked, a first pad layer on the lower conductive layer and at least partially filling the opening, and a second pad layer on the first pad layer and being in contact with a peripheral portion of the lower conductive layer located on the top surface of the passivation layer.
    Type: Grant
    Filed: April 30, 2019
    Date of Patent: May 25, 2021
    Inventors: Ju-il Choi, Kwang-jin Moon, Ju-bin Seo, Dong-chan Lim, Atsushi Fujisaki, Ho-jin Lee
  • Patent number: 11011460
    Abstract: A package structure including an interposer, a semiconductor die, through insulator vias, an insulating encapsulant and a redistribution layer is provided. The interposer includes a core structure having a first and second surface, first metal layers disposed on the first and second surface, second metal layers disposed on the second surface over the first metal layers, and third metal layers disposed on the second surface over the second metal layers. The semiconductor die is disposed on the interposer. The through insulator vias are disposed on the interposer and electrically connected to the plurality of first metal layers. The insulating encapsulant is disposed on the interposer over the first surface and encapsulating the semiconductor die and the plurality of through insulator vias. The redistribution layer is disposed on the insulating encapsulant and electrically connected to the semiconductor die and the plurality of through insulator vias.
    Type: Grant
    Filed: April 27, 2020
    Date of Patent: May 18, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chuei-Tang Wang, Tin-Hao Kuo
  • Patent number: 11004816
    Abstract: A hetero-integrated structure includes a substrate, a die, a passivation layer, a first redistribution layer, a second redistribution layer, and connecting portions. The die is attached on the substrate. The die has an active surface and a non-active surface. The active surface has pads. The passivation layer covers sidewalls and a surface of the die to expose a surface of the pads. The first redistribution layer is located on the passivation layer and electrically connected to the pads. The second redistribution layer is located on the substrate and adjacent to the die. The connecting portions are connected to the first redistribution layer and the second redistribution layer.
    Type: Grant
    Filed: August 28, 2019
    Date of Patent: May 11, 2021
    Assignee: Industrial Technology Research Institute
    Inventors: Yu-Min Lin, Ang-Ying Lin, Sheng-Tsai Wu, Tao-Chih Chang, Wei-Chung Lo
  • Patent number: 11004813
    Abstract: A semiconductor device includes a lower insulating layer formed on a primary surface of a semiconductor substrate; a sealing layer formed in contact with a top surface of the lower insulating layer; and a conductive member including a first conductive member formed on the sealing layer and having a first film thickness and a second conductive member formed on the sealing layer in contact with a first conductive member and having a second film thickness that is smaller than the first film thickness.
    Type: Grant
    Filed: November 28, 2018
    Date of Patent: May 11, 2021
    Assignee: LAPIS SEMICONDUCTOR CO., LTD.
    Inventor: Masanori Shindo
  • Patent number: 11001495
    Abstract: The sensor package comprises a carrier (1) including electric conductors (13), an ASIC device (6) and a sensor element (7), which is integrated in the ASIC device (6). A dummy die or interposer (4) is arranged between the carrier (1) and the ASIC device (6). The dummy die or interposer (4) is fastened to the carrier (1), and the ASIC device (6) is fastened to the dummy die or interposer (4).
    Type: Grant
    Filed: June 14, 2017
    Date of Patent: May 11, 2021
    Assignee: Sciosense B.V.
    Inventors: Willem Frederik Adrianus Besling, Casper Van Der Avoort, Coenraad Cornelis Tak, Remco Henricus Wilhelmus Pijnenburg, Olaf Wunnicke, Hendrik Bouman
  • Patent number: 10998281
    Abstract: A package substrate of a semiconductor package includes second and third pad bonding portions respectively located at both sides of a first pad bonding portion disposed on a substrate body. First to third via landing portions are disposed to be spaced apart from the first to third pad bonding portions. First and second connection trace portions are disposed to be parallel with each other, and a first guard trace portion is disposed to be substantially parallel with the first connection trace portion. The second connection trace portion is connected to the first guard trace portion through a first connection plane portion, and the first connection plane portion connects the second connection trace portion to the second via landing portion. The third pad bonding portion is connected to the third via landing portion through a second connection plane portion.
    Type: Grant
    Filed: August 13, 2019
    Date of Patent: May 4, 2021
    Assignee: SK hynix Inc.
    Inventors: Jae Hoon Lee, Sun Kyu Kong, Ji Yeong Yoon
  • Patent number: 10996198
    Abstract: An integrated circuit sensor that enables, regardless of a type of an inspection object, the inspection object and a front surface of the integrated circuit sensor to be in reliable contact with each other in a large region is provided. A through silicon via (11) that electrically connects an inside of an integrated circuit sensor (4) and an outside of the integrated circuit sensor (4) is formed in the inside of the integrated circuit sensor (4) so as to reach a rear surface of the integrated circuit sensor (4), which faces the front surface of the integrated circuit sensor (4).
    Type: Grant
    Filed: June 10, 2016
    Date of Patent: May 4, 2021
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Kunihiko Iizuka, Akira Saito, Takeshi Mitsunaka, Nobuyuki Ashida
  • Patent number: 10985124
    Abstract: A semiconductor structure includes a substrate having a surface and a conductive via in the substrate. The surface has an inner region and an outer region surrounding the inner region. The semiconductor structure also includes an under bump metallurgy (UBM) pad on the surface and within the outer region, where the UBM pad has a first zone and a second zone. The first zone faces towards a center of the surface and the second zone faces away from the center of the surface. The conductive via is disposed outside the second zone and at least partially overlaps the first zone from a top view perspective.
    Type: Grant
    Filed: April 23, 2018
    Date of Patent: April 20, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Kuo-Chin Chang, Yen-Kun Lai, Kuo-Ching Hsu, Mirng-Ji Lii
  • Patent number: 10985101
    Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes semiconductor dies, an encapsulant and a redistribution structure. The semiconductor dies are disposed side by side. Each semiconductor die has an active surface, a backside surface, and an inner side surface connecting the active surface and the backside surface. The encapsulant wraps the semiconductor dies and exposes the active surfaces of the semiconductor dies. The redistribution structure is disposed on the encapsulant and the active surfaces of the semiconductor dies. The inner side surfaces of most adjacent semiconductor dies face each other. The redistribution structure establishes single-ended connections between most adjacent semiconductor dies by crossing over the facing inner side surfaces of the most adjacent semiconductor dies.
    Type: Grant
    Filed: March 14, 2019
    Date of Patent: April 20, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Chia Lai, Chi-Hui Lai, Tin-Hao Kuo, Hao-Yi Tsai, Chung-Shi Liu, Kuo-Chung Yee, Chen-Hua Yu
  • Patent number: 10971375
    Abstract: A method, comprises: providing a laminar support member, having a front surface, arranging on the front surface at least one semiconductor die having a front surface and a back surface, with the back surface thereof towards the front surface of the support member and with the front surface thereof having die pads, arranging at the front surface of the support member sidewise of the at least one semiconductor die a plurality of electrically-conductive bodies, the electrically-conductive bodies arranged at respective recesses in the support member, wherein the electrically-conductive bodies protrude from the plane away from the front surface of the support member, providing a filling of molding material over the laminar support member between the at least one semiconductor die and the electrically-conductive bodies, and providing electrically-conductive lines between selected ones of the die pads of the semiconductor die and selected ones of the plurality of electrically-conductive bodies.
    Type: Grant
    Filed: February 12, 2019
    Date of Patent: April 6, 2021
    Assignee: STMICROELECTRONICS S.R.L.
    Inventor: Federico Giovanni Ziglioli
  • Patent number: 10964632
    Abstract: According to one embodiment, there is provided a semiconductor device including a substrate, a semiconductor chip, and a conductive film. The substrate has a main face. The semiconductor chip has a surface equipped with an SRAM circuit. The semiconductor chip is mounted on the main face via a plurality of bump electrodes in a state where the surface faces the main face. The conductive film is disposed on the main face or the surface. The conductive film extends planarly between the plurality of bump electrodes. A region in the main face or the surface where the conductive film is disposed overlaps the SRAM circuit in a direction perpendicular to the main face.
    Type: Grant
    Filed: September 9, 2019
    Date of Patent: March 30, 2021
    Assignee: Toshiba Memory Corporation
    Inventors: Takeshi Fujimori, Soichiro Ibaraki, Shinji Yamashita
  • Patent number: 10950573
    Abstract: Disclosed are interconnects in which one substrate having a high melting temperature, lead-free solder column is joined to a second substrate having openings filled with a low melting temperature, lead-free solder such that the high melting temperature, lead-free solder column penetrates into the low melting temperature, lead-free solder so as to obtain a short moment arm of solder.
    Type: Grant
    Filed: March 19, 2019
    Date of Patent: March 16, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Charles L. Arvin, Clement J. Fortin, Christopher D. Muzzy, Krishna R. Tunga, Thomas Weiss
  • Patent number: 10950553
    Abstract: A semiconductor device and methods of forming are provided. The device includes a second die bonded to a first die and a third die bonded to the first die. An isolation material extends along sidewalls of the second die and the third die. A through via extends from the first die into the isolation material. A first passive device disposed in the isolation material, the first passive device being electrically connected to the first die.
    Type: Grant
    Filed: May 24, 2019
    Date of Patent: March 16, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Chuei-Tang Wang
  • Patent number: 10943792
    Abstract: A system in package device includes a landed first die disposed on a package substrate. The landed first die includes a notch that is contoured and that opens the backside surface of the die to a ledge. A stacked die is mounted at the ledge and the two dice are each contacted by a through-silicon via (TSV). The system in package device also includes a landed subsequent die on the package substrate and a contoured notch in the landed subsequent die and the notch in the first die form a composite contoured recess into which the stacked die is seated.
    Type: Grant
    Filed: September 27, 2016
    Date of Patent: March 9, 2021
    Assignee: Intel Corporation
    Inventors: Bok Eng Cheah, Min Suet Lim, Jackson Chung Peng Kong, Howe Yin Loo
  • Patent number: 10943880
    Abstract: Various semiconductor chips and packages are disclosed. In one aspect, an apparatus is provided that includes a semiconductor chip that has a side, and plural conductive pillars on the side. Each of the conductive pillars includes a pillar portion that has an exposed shoulder facing away from the semiconductor chip. The shoulder provides a wetting surface to attract melted solder. The pillar portion has a first lateral dimension at the shoulder. A solder cap is positioned on the pillar portion. The solder cap has a second lateral dimension smaller than the first lateral dimension.
    Type: Grant
    Filed: May 16, 2019
    Date of Patent: March 9, 2021
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventors: Priyal Shah, Milind S. Bhagavat, Lei Fu
  • Patent number: 10937745
    Abstract: Semiconductor chip package array is provided. The semiconductor chip package array includes: a lead frame, chips, an encapsulating layer, and an electroplating layer. The lead frame includes a first surface, a second surface, a plurality of support units arranged in a matrix, first grooves, second grooves, and third grooves. The first grooves are connected to the second grooves to form through holes and the third grooves are connected to adjacent support units of the plurality of support units. The chips are disposed on and electrically connected to the plurality of support units. An encapsulating material encapsulates the chips and at least a portion of the plurality of support units, and fill the first grooves to form the encapsulating layer. The electroplating layer is disposed on the second surface of the lead frame, and extends into the third grooves or into the third grooves and the second grooves.
    Type: Grant
    Filed: June 13, 2019
    Date of Patent: March 2, 2021
    Assignee: TONGFU MICROELECTRONICS CO., LTD.
    Inventor: Lei Shi
  • Patent number: 10931145
    Abstract: A wireless power receiver is provided. The wireless power receiver includes a substrate partitioned into a first area and a second area neighboring the first area, a circuit portion mounted in the first area of the substrate and including a receiving module, a resonance pattern portion directly provided on at least one surface of the substrate in the second area, and a shield mounted on a surface of the substrate in the second area.
    Type: Grant
    Filed: April 26, 2016
    Date of Patent: February 23, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sung-Bum Park, Dong-Zo Kim, Keum-Su Song
  • Patent number: 10912199
    Abstract: A method of running a printed circuit board (PCB) trace on a PCB. The PCB comprising a plurality of PCB layers. The method comprising forming a conductive trace on at least one of the plurality of PCB layers; coupling a first portion of the conductive trace to a capacitor formed on at least one of the plurality of PCB layers; coupling a second portion, different from the first portion, of the conductive trace to a conductive material formed within a first via extending through two or more of the plurality of PCB layers; and configurably setting a length of a conductive path of the conductive trace according to a predetermined impedance. The capacitor is separated laterally in a plan view at a first distance from the first via. The length of the conductive trace in the plan view is greater than the first distance. The conductive path of the conductive trace of the length has the predetermined impedance.
    Type: Grant
    Filed: March 30, 2020
    Date of Patent: February 2, 2021
    Assignee: Kioxia Corporation
    Inventor: Stephen Pardoe
  • Patent number: 10910343
    Abstract: The present disclosure provides a package structure and its packaging method. The packaging method includes: providing a bonding layer on a substrate; forming an improvement layer on the bonding layer, where the improvement layer has openings, and bottoms of the openings expose a surface of the bonding layer; providing chips, each including a non-functional surface; and mounting the chips by attaching the non-functional surface to the bonding layer at the bottoms of the openings.
    Type: Grant
    Filed: April 24, 2019
    Date of Patent: February 2, 2021
    Assignee: TONGFU MICROELECTRONICS CO., LTD.
    Inventor: Lei Shi
  • Patent number: 10903166
    Abstract: Disclosed herein are integrated circuit (IC) packages, and related structures and techniques. In some embodiments, an IC package may include: a die; a redistribution structure, wherein the die is coupled to the redistribution structure via first-level interconnects and solder; a solder resist; and second-level interconnects coupled to the redistribution structure through openings in the solder resist.
    Type: Grant
    Filed: January 28, 2016
    Date of Patent: January 26, 2021
    Assignee: Intel IP Corporation
    Inventors: Sanka Ganesan, Thorsten Meyer, Gerald Ofner
  • Patent number: 10884955
    Abstract: A computing device has a motherboard circuit substrate having at least a first layer of electrical interconnects, a socket arranged to receive a main processor for the computing device, the socket electrically coupled to at least a portion of the first layer of electrical interconnects, at least two interposer substrates between the main processor and the socket such that the interposer substrate electrically connects to the main processor and the socket, wherein the interposer substrate has a first set of interconnects that electrically connect between the socket and the first layer of electrical interconnects, at least two peripheral circuits on each interposer substrate, the peripheral circuit connected to the main processor through a second set of interconnects on the interposer substrate that connects to the main processor without connecting to the socket or the motherboard circuit substrate, wherein each interposer substrate is folded to allow each peripheral circuit to have an equal path length between
    Type: Grant
    Filed: September 23, 2019
    Date of Patent: January 5, 2021
    Assignee: MORGAN/WEISS TECHNOLOGIES INC.
    Inventors: Morgan Johnson, Frederick G. Weiss
  • Patent number: 10879292
    Abstract: A semiconductor package includes a first redistribution layer, a first semiconductor chip on the first redistribution layer, a molding layer covering the first semiconductor chip, metal pillars around the first semiconductor chip and connected to the first redistribution layer, a second redistribution layer on the molding layer and connected to the metal pillars, and a second semiconductor chip on the second redistribution layer. The metal pillars extend through the molding layer. When viewed in plan, the second semiconductor chip overlaps the first semiconductor chip and the metal pillars. A method of manufacturing the semiconductor package obtains a wafer map from a first substrate that includes a plurality of first semiconductor chips and uses the wafer map in selectively stacking second semiconductor chips on the first semiconductor chips.
    Type: Grant
    Filed: March 26, 2019
    Date of Patent: December 29, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jaegwon Jang, Seokhyun Lee, Kyoung Lim Suk
  • Patent number: 10879215
    Abstract: A method for manufacturing a semiconductor device package includes: (1) providing a first encapsulation layer; (2) disposing an adhesive layer on the first encapsulation layer; (3) disposing a first die on the adhesive layer; and (4) forming a second encapsulation layer covering the first die, the adhesive layer, and the first encapsulation layer.
    Type: Grant
    Filed: March 8, 2019
    Date of Patent: December 29, 2020
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Li-Hao Lyu, Chieh-Ju Tsai, Yu-Kai Lin, Wei-Ming Hsieh, Yu-Pin Tsai, Man-Wen Tseng, Yu-Ting Lu
  • Patent number: 10867944
    Abstract: The present disclosure provides a semiconductor structure, including a substrate, a conductive pad, a passivation layer, a recess, a bump pad, and a conductive bump. The conductive pad is disposed over the substrate. The passivation layer is disposed over the substrate and partially covers the conductive pad. The recess extends through the passivation layer and extends at least partially into the conductive pad. The bump pad is disposed over the passivation layer and within the recess; and the conductive bump is disposed over the bump pad. A method of manufacturing the semiconductor structure is also provided.
    Type: Grant
    Filed: March 27, 2019
    Date of Patent: December 15, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventor: Tung-Jiun Wu
  • Patent number: 10867951
    Abstract: A semiconductor device includes an electronic component, a package, a substrate and a plurality of first conductors and second conductors. The package is over the electronic component. T substrate is between the electronic component and the package. The substrate includes a first portion covered by the package, and a second portion protruding out of an edge of the package and uncovered by the package. The first conductors and second conductors are between and electrically connected to the electronic component and the substrate. A width of a second conductor of the plurality of second conductors is larger than a width of a first conductor of the plurality of first conductors, the first conductors are disposed between the second portion of the substrate and the electronic component, and the second conductors are disposed between the first portion of the substrate and the electronic component.
    Type: Grant
    Filed: April 16, 2019
    Date of Patent: December 15, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Kuan-Yu Huang, Tzu-Kai Lan, Shou-Chih Yin, Shu-Chia Hsu, Pai-Yuan Li, Sung-Hui Huang, Hsiang-Fan Lee, Ying-Shin Han
  • Patent number: 10867929
    Abstract: A method of forming semiconductor structure includes attaching backsides of top dies to a front side of a bottom wafer, the bottom wafer comprising a plurality of bottom dies; forming first conductive pillars on the front side of the bottom wafer adjacent to the top dies; forming a first dielectric material on the front side of the bottom wafer around the top dies and around the first conductive pillars; and dicing the bottom wafer to form a plurality of structures, each of the plurality of structures comprising at least one of the top dies and at least one of the bottom dies.
    Type: Grant
    Filed: April 1, 2019
    Date of Patent: December 15, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Tzuan-Horng Liu, Ming-Fa Chen, Chao-Wen Shih, Sung-Feng Yeh
  • Patent number: 10854531
    Abstract: A semiconductor packaging method, a semiconductor package and stacked semiconductor packages are provided. The method includes providing a carrier (10) having a plurality of semiconductor chip receiving areas (12) and attaching a plurality of first semiconductor chips (14) to the semiconductor chip receiving areas (12). The first semiconductor chips (14) are encapsulated with a first encapsulant (20) and a plurality of electrical connections (24) is formed to the first semiconductor chips (14). At least a portion of the carrier (10) is removed to provide a heat release area (38).
    Type: Grant
    Filed: June 24, 2016
    Date of Patent: December 1, 2020
    Assignee: PEP INNOVATION PTE LTD.
    Inventor: Yi Xin Chew
  • Patent number: 10854576
    Abstract: A semiconductor device includes a wiring substrate having a first surface, a stacked body on the first surface, the stacked body comprising a first chip, a second chip having a through via and positioned between the first chip and the first surface, and a third chip, a first resin contacting the first surface and the third chip, and a second resin sealing the stacked body. The first and second resins are made of different materials.
    Type: Grant
    Filed: September 3, 2017
    Date of Patent: December 1, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Yuji Karakane, Masatoshi Fukuda, Soichi Homma, Masayuki Miura, Naoyuki Komuta, Yuka Akahane, Yukifumi Oyama
  • Patent number: 10833039
    Abstract: A package includes a die having a conductive pad at a top surface of the die, a stud bump over and connected to the conductive pad, and a redistribution line over and connected to the stud bump. An electrical connector is over and electrically coupled to the redistribution line.
    Type: Grant
    Filed: December 4, 2018
    Date of Patent: November 10, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Jing-Cheng Lin, Jui-Pin Hung
  • Patent number: 10825789
    Abstract: One embodiment of a packaged semiconductor device includes: a redistributed layer (RDL) structure formed over an active side of a semiconductor die embedded in mold compound, the RDL structure includes a plurality of solder ball pads that in turn includes: a set of first solder ball pads located on a front side of the packaged semiconductor device within a footprint of the semiconductor die, and a set of second solder ball pads located on the front side of the packaged semiconductor device outside of the footprint of the semiconductor die, each first solder ball pad includes a first center portion having a first diameter measured between opposite outer edges of the first center portion, each second solder ball pad includes a second center portion having a second diameter measured between opposite outer edges of the second center portion, and the first diameter is smaller than the second diameter.
    Type: Grant
    Filed: August 26, 2019
    Date of Patent: November 3, 2020
    Assignee: NXP B.V.
    Inventors: Leo Van Gemert, Adrianus Buijsman, Jeroen Johannes Maria Zaal, Michiel Van Soestbergen, Peter Joseph Hubert Drummen
  • Patent number: 10825696
    Abstract: A method includes placing a plurality of package components over a carrier, encapsulating the plurality of package components in an encapsulant, forming a light-sensitive dielectric layer over the plurality of package components and the encapsulant, exposing the light-sensitive dielectric layer using a lithography mask, and developing the light-sensitive dielectric layer to form a plurality of openings. Conductive features of the plurality of package components are exposed through the plurality of openings. The method further includes forming redistribution lines extending into the openings. One of the redistribution lines has a length greater than about 26 mm. The redistribution lines, the plurality of package components, the encapsulant in combination form a reconstructed wafer.
    Type: Grant
    Filed: February 12, 2019
    Date of Patent: November 3, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Tin-Hao Kuo
  • Patent number: 10825788
    Abstract: Provided is a method of manufacturing compliant bumps, the method including preparing an electronic device including at least one conductive pad, forming an elastic resin layer on the electronic device, forming a photoresist layer on the elastic resin layer, forming a first photoresist pattern on a region spaced apart from a region where the conductive pad is located, forming a second photoresist pattern having a lower cross-sectional area greater than an upper cross-sectional area, forming an elastic resin pattern having a lower cross-sectional area greater than an upper cross-sectional area, on a region spaced apart from a region where the conductive pad is located, and forming a conductive wiring pattern covering at least a part of the elastic resin pattern and extending to the conductive pad.
    Type: Grant
    Filed: December 28, 2017
    Date of Patent: November 3, 2020
    Assignee: LBSEMICON CO., LTD.
    Inventor: Jae Jin Kwon
  • Patent number: 10818588
    Abstract: A package structure includes a semiconductor die, an insulating encapsulant, a first redistribution layer, a second redistribution layer, a heat dissipation element and conductive balls. The insulating encapsulant is encapsulating the semiconductor die, and has a first surface and a second surface opposite to the first surface. The first redistribution layer is located on the first surface of the insulating encapsulant and includes at least one feed line and one ground plate. The second redistribution layer is located on the second surface of the insulating encapsulant and electrically connected to the semiconductor die and the first redistribution layer. The heat dissipation element is disposed on the first redistribution layer and includes a conductive base and antenna patterns, wherein the antenna patterns is electrically connected to the feed line and is electrically coupled to the ground plate of the first redistribution layer.
    Type: Grant
    Filed: January 31, 2019
    Date of Patent: October 27, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sen-Kuei Hsu, Hsin-Yu Pan, Yi-Che Chiang
  • Patent number: 10818579
    Abstract: There is provided a lead frame. The lead frame includes: a die pad; a lead terminal that is separated from the die pad and disposed around the die pad; and a resin layer that is formed between the die pad and the lead terminal so as to fix the die pad and the lead terminal. The resin layer has an opening portion that exposes at least a lower surface of the lead terminal.
    Type: Grant
    Filed: October 15, 2018
    Date of Patent: October 27, 2020
    Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventors: Shintaro Hayashi, Kentaro Kaneko, Tsukasa Nakanishi, Misaki Imai
  • Patent number: 10804233
    Abstract: Wafer-level (chip-scale) package semiconductor devices are described that have bump assemblies configured to maintain standoff (bump) height. In an implementation, the wafer-level chip-scale package devices include an integrated circuit chip having an array of bump assemblies disposed over the integrated circuit chip. The array of bump assemblies comprises a plurality of first bump assemblies that include solder bumps composed at least substantially of a solder composition (i.e., do not include a core). The array further includes at least one second bump assembly including a solder bump having a core configured to maintain standoff height of the wafer-level package device.
    Type: Grant
    Filed: November 2, 2011
    Date of Patent: October 13, 2020
    Assignee: MAXIM INTEGRATED PRODUCTS, INC.
    Inventors: Viren Khandekar, Karthik Thambidurai, Vivek Swaminathan Sridharan
  • Patent number: 10797022
    Abstract: A semiconductor device package includes a first redistribution layer (RDL), a first die, a second die, a second RDL and an encapsulant. The first die is disposed on the first RDL and is electrically connected to the first RDL. The first die has a first electrical contact. The second die is disposed on the first RDL and is electrically connected to the first RDL. The second die has a first electrical contact. The second RDL is surrounded by the first RDL. The second RDL has a first electrical contact electrically connected to the first electrical contact of the first die and a second electrical contact electrically connected to the first electrical contact of the second die. A size of the first electrical contact of the second RDL is greater than a size of the second electrical contact of the second RDL.
    Type: Grant
    Filed: October 4, 2018
    Date of Patent: October 6, 2020
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Hsu-Nan Fang, Chun-Jun Zhuang, Yung I. Yeh, Ming-Chiang Lee
  • Patent number: 10797012
    Abstract: A multi-pin wafer level chip scale package is achieved. One or more solder pillars and one or more solder blocks are formed on a silicon wafer wherein the one or more solder pillars and the one or more solder blocks all have a top surface in a same horizontal plane. A pillar metal layer underlies the one or more solder pillars and electrically contacts the one or more solder pillars with the silicon wafer through an opening in a polymer layer over a passivation layer. A block metal layer underlies the one or more solder blocks and electrically contacts the one or more solder pillars with the silicon wafer through a plurality of via openings through the polymer layer over the passivation layer wherein the block metal layer is thicker than the pillar metal layer.
    Type: Grant
    Filed: August 25, 2017
    Date of Patent: October 6, 2020
    Assignee: Dialog Semiconductor (UK) Limited
    Inventors: Habeeb Mohiuddin Mohammed, Rajesh Subraya Aiyandra
  • Patent number: 10777531
    Abstract: A package contact structure, a semiconductor package and a manufacturing method are provided. The package contact structure includes a conductive feature and a dielectric barrier. The conductive feature includes a first portion and a second portion disposed on the first portion. Materials of the first portion and the second portion are different. The dielectric barrier is sleeved on the first portion and extends to cover at least a part of the second portion. A maximum height of the dielectric barrier is less than a maximum height of the conductive feature.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: September 15, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jung-Hua Chang, Chin-Fu Kao
  • Patent number: 10777522
    Abstract: The present disclosure provides a semiconductor structure and a method of manufacturing the semiconductor structure. The semiconductor structure includes a substrate, a plurality of metallic pillars, a plurality of metallic protrusions, a capping layer, and a passivation layer. The metallic pillars are disposed on the substrate. The metallic protrusions extend from an upper surface of the metallic pillars. The capping layer is disposed on the metallic protrusions. The passivation layer is disposed on sidewalls of the protrusions and the capping layer.
    Type: Grant
    Filed: February 14, 2019
    Date of Patent: September 15, 2020
    Assignee: Nanya Technology Corporation
    Inventor: Chih-Ching Lin
  • Patent number: 10777478
    Abstract: A semiconductor package device includes a first die having a first surface and a second surface opposite to the first surface, and a first adhesive layer disposed on the first surface of the first die. The semiconductor package device further includes an encapsulant layer encapsulating the first die and the first adhesive layer, and a first conductive via disposed in the first adhesive layer and electrically connected to the first die.
    Type: Grant
    Filed: July 13, 2017
    Date of Patent: September 15, 2020
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Bernd Karl Appelt, Kay Stefan Essig
  • Patent number: 10770451
    Abstract: A thin-film ESD protection device that includes a semiconductor substrate having a first and second principal surfaces); a first insulating layer disposed on the first principal surface; a second insulating layer disposed formed on the second principal surface; and first and second input/output electrodes, ground electrodes, a diode element, a capacitor element, and an inductor element. The capacitor element and the diode element are formed adjacent to the first principal surface, whereas the inductor element is formed adjacent to the second principal surface. The inductor element is connected to the first input/output electrode and the second input/output electrode by a first via conductor and a second via conductor, respectively, that pass through the semiconductor substrate from the first principal surface to the second principal surface.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: September 8, 2020
    Assignee: MURATA MANUFACTURING CO, LTD.
    Inventor: Souko Fukahori
  • Patent number: 10770445
    Abstract: A method of fabricating semiconductor packages may include forming stack structures on a base die wafer, disposing a top die wafer on the stack structures, and forming a molding layer filling a space between the base die wafer and the top die wafer.
    Type: Grant
    Filed: October 31, 2018
    Date of Patent: September 8, 2020
    Assignee: SK hynix Inc.
    Inventor: Kwon Whan Han
  • Patent number: 10770428
    Abstract: In an embodiment, a device includes: a first device including: an integrated circuit device having a first connector; a first photosensitive adhesive layer on the integrated circuit device; and a first conductive layer on the first connector, the first photosensitive adhesive layer surrounding the first conductive layer; a second device including: an interposer having a second connector; a second photosensitive adhesive layer on the interposer, the second photosensitive adhesive layer physically connected to the first photosensitive adhesive layer; and a second conductive layer on the second connector, the second photosensitive adhesive layer surrounding the second conductive layer; and a conductive connector bonding the first and second conductive layers, the conductive connector surrounded by an air gap.
    Type: Grant
    Filed: July 1, 2019
    Date of Patent: September 8, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Chun Hui Yu, Kuo-Chung Yee
  • Patent number: 10756038
    Abstract: A semiconductor package includes a semiconductor die and a connection structure. The semiconductor die is laterally encapsulated by an insulating encapsulant. The connection structure is disposed on the semiconductor die, the connection structure is electrically connected to the semiconductor die, and the connection structure includes at least one first via, first pad structures, second vias, a second pad structure and a conductive terminal. The at least one first via is disposed over and electrically connected to the semiconductor die. The first pad structures are disposed over the at least one first via, wherein the at least one first via contacts at least one of the first pad structures. The second vias are disposed over the first pad structures, wherein the second vias contact the first pad structures.
    Type: Grant
    Filed: February 21, 2019
    Date of Patent: August 25, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ming-Yen Chiu, Shou-Yi Wang, Tsung-Shu Lin
  • Patent number: 10756153
    Abstract: An organic light emitting display device is disclosed, which removes an inorganic film from a bending area and minimizes a crack of a routing line to enable an extreme bending. The organic light emitting display device comprises a substrate having a display area and a bending area; a display assembly provided on a display area of the substrate; a routing line arranged on the bending area of the substrate and connected to the display assembly; and an organic layer provided on the bending area of the substrate, covering the routing line, wherein the bending area of the substrate has only the routing line and the organic layer.
    Type: Grant
    Filed: December 10, 2019
    Date of Patent: August 25, 2020
    Assignee: LG Display Co., Ltd.
    Inventor: Eunah Kim
  • Patent number: 10741419
    Abstract: Embodiments of the invention include device packages and methods of forming such packages. In an embodiment, the method of forming a device package may comprise forming a reinforcement layer over a substrate. One or more openings may be formed through the reinforcement layer. In an embodiment, a device die may be placed into one of the openings. The device die may be bonded to the substrate by reflowing one or more solder bumps positioned between the device die and the substrate. Embodiments of the invention may include a molded reinforcement layer. Alternative embodiments include a reinforcement layer that is adhered to the surface of the substrate with an adhesive layer.
    Type: Grant
    Filed: July 18, 2019
    Date of Patent: August 11, 2020
    Assignee: Intel Corporation
    Inventors: Omkar G. Karhade, Nitin A. Deshpande, Debendra Mallik, Bassam M. Ziadeh, Yoshihiro Tomita
  • Patent number: 10741460
    Abstract: An interconnect assembly includes a bond pad and an interconnect structure configured to electrically couple an electronic structure to the bond pad. The interconnect structure physically contacts areas of the bond pad that are located outside of a probe contact area that may have been damaged during testing. Insulating material covers the probe contact area and defines openings spaced apart from the probe contact area. The interconnect structure extends through the openings to contact the bond pad.
    Type: Grant
    Filed: October 16, 2018
    Date of Patent: August 11, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Owen R. Fay, Kyle K. Kirby, Luke G. England, Jaspreet S. Gandhi
  • Patent number: 10734298
    Abstract: Methods of making a semiconductor device packages may involve placing a metal material at least partially around a region of integrated circuitry embedded within an active surface of a semiconductor die, the metal material located on the active surface. At least a portion of the metal material may be left electrically disconnected from the region of integrated circuitry. The semiconductor die and the metal material may be encapsulated in an encapsulant material, the encapsulant material extending to a height above the active surface higher than a maximum height of the metal material above the active surface.
    Type: Grant
    Filed: September 4, 2018
    Date of Patent: August 4, 2020
    Assignee: Microchip Technology Incorporated
    Inventors: Hyunsoo Yeom, Ajay Kumar, John House
  • Patent number: 10727185
    Abstract: An apparatus is provided which comprises: a plurality of first conductive contacts having a first pitch spacing on a substrate surface, a plurality of second conductive contacts having a second pitch spacing on the substrate surface, and a plurality of conductive interconnects disposed within the substrate to couple a first grouping of the plurality of second conductive contacts associated with a first die site with a first grouping of the plurality of second conductive contacts associated with a second die site and to couple a second grouping of the plurality of second conductive contacts associated with the first die site with a second grouping of the plurality of second conductive contacts associated with the second die site, wherein the conductive interconnects to couple the first groupings are present in a layer of the substrate above the conductive interconnects to couple the second groupings. Other embodiments are also disclosed and claimed.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: July 28, 2020
    Assignee: Intel Corporation
    Inventors: Aleksandar Aleksov, Adel A. Elsherbini, Kristof Darmawikarta, Robert A. May, Sri Ranga Sai Boyapati