Ball Shaped Patents (Class 257/738)
  • Patent number: 11404337
    Abstract: Electronic packages and methods of formation are described in which an interposer is solderlessly connected with a package substrate. The interposer may be stacked on the package substrate and joined with a conductive film, and may be formed on the package substrate during a reconstitution sequence.
    Type: Grant
    Filed: December 27, 2019
    Date of Patent: August 2, 2022
    Assignee: Apple Inc.
    Inventors: Kunzhong Hu, Chonghua Zhong, Jiongxin Lu, Jun Zhai
  • Patent number: 11404361
    Abstract: A package structure and a method for fabricating the same are provided. An electronic component such as a sensing chip and a conductive element such as a bonding wire are mounted to a carrier, encapsulated by an encapsulant, and electrically connected through a conductive layer. As such, the electronic component can further be electrically connected to the carrier through the conductive layer and the conductive element. Therefore, the sensing chip can be packaged through current packaging processes, thereby reducing the fabrication cost, shortening the fabrication time and improving the product yield.
    Type: Grant
    Filed: November 12, 2020
    Date of Patent: August 2, 2022
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Shao-Tzu Tang, Jia-Fong Yeh, Yi-Hsuan Liu, Mei-Chi Chen, Ying-Chou Tsai
  • Patent number: 11398431
    Abstract: A device includes a semiconductor substrate having first and second surfaces facing one another, and multiple through-silicon vias (TSVs). The TSVs are formed through the substrate between the first and second surfaces, at least a first TSV of the TSVs includes: (i) an electrically conductive interconnect, which is formed within the first TSV and is configured to conduct an electrical signal between the first and second surfaces, and (ii) an attenuation layer, which is formed within the first TSV, between the substrate and the electrically conductive interconnect, the attenuation layer configured to attenuate interference between electrical signals carried by two or more of the TSVs.
    Type: Grant
    Filed: January 26, 2021
    Date of Patent: July 26, 2022
    Assignee: MARVELL ASIA PTE LTD
    Inventor: Runzi Chang
  • Patent number: 11380584
    Abstract: Damage to a semiconductor device at the time of forming a via hole in which a through electrode is arranged is prevented. The semiconductor device includes a cylindrical insulating film, a front surface side pad, a conductor layer, and a back surface side pad. The cylindrical insulating film is configured in a cylindrical shape penetrating a semiconductor substrate. The front surface side pad is formed adjacent to a front surface of the semiconductor substrate inside the cylindrical insulating film. The conductor layer is arranged adjacent to the front surface side pad and an inner side of the cylindrical insulating film after removing the semiconductor substrate inside the cylindrical insulating film adjacent to the front surface side pad. The back surface side pad is arranged on a back surface of the semiconductor substrate and is connected to the front surface side pad via the conductor layer.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: July 5, 2022
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventor: Takushi Shigetoshi
  • Patent number: 11362045
    Abstract: A chip package structure including a substrate, a redistribution layer (RDL), a chip and an encapsulant is provided. The RDL is disposed on the substrate. The chip is disposed on the RDL and is electrically connected with the RDL. The encapsulant is disposed on the RDL and encapsulates the chip. The chip is located in the high stress region. From a top view, the chip is located in the high stress region, and the low stress region surrounds the high stress region. The RDL includes at least one first device located in the high stress region. From the top view, the extending direction of the at least one first device is parallel to a stress direction at a position thereof.
    Type: Grant
    Filed: February 18, 2020
    Date of Patent: June 14, 2022
    Assignee: Industrial Technology Research Institute
    Inventors: Te-Hsun Lin, Chen-Tsai Yang, Kuan-Chu Wu, Shao-An Yan
  • Patent number: 11355444
    Abstract: To provide a semiconductor device further reduced in size. A semiconductor device including: a multilayer wiring board one surface of which is provided with an external connection terminal; and a plurality of active components that are provided to be stacked inside the multilayer wiring board and are connected to the external connection terminal via a connection via. The plurality of active components include a first active component provided on another surface side that is opposite to the one surface, and a second active component that is provided closer to the one surface than the first active component is and has a smaller planar area than the first active component.
    Type: Grant
    Filed: January 20, 2017
    Date of Patent: June 7, 2022
    Assignee: SONY CORPORATION
    Inventor: Hirohisa Yasukawa
  • Patent number: 11355467
    Abstract: A semiconductor device may include a semiconductor chip in an encapsulant. A first insulation layer may be disposed on the encapsulant and the semiconductor chip. A horizontal wiring and a primary pad may be disposed on the first insulation layer. A secondary pad may be disposed on the primary pad. A second insulation layer covering the horizontal wiring may be disposed on the first insulation layer. A solder ball may be disposed on the primary pad and the secondary pad. The primary pad may have substantially the same thickness as a thickness of the horizontal wiring.
    Type: Grant
    Filed: August 3, 2020
    Date of Patent: June 7, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Taeho Ko, Daehee Lee, Hyunchul Jung
  • Patent number: 11355356
    Abstract: The method of manufacturing a semiconductor package of the present disclosure includes: providing a redistribution layer having opposing first surface and second surface; disposing a die on the first surface of the redistribution layer and electrically connecting the die to the redistribution layer; forming a mask on the second surface of the redistribution layer; performing a chemical or plasma etching process on the second surface of the redistribution layer to expose the conductive traces in the redistribution layer; removing the mask; and forming a plurality of conductive bumps on the second surface of the redistribution layer and electrically connecting the conductive bumps to the exposed conductive traces in the redistribution layer.
    Type: Grant
    Filed: February 2, 2021
    Date of Patent: June 7, 2022
    Assignee: ORIENT SEMICONDUCTOR ELECTRONICS, LIMITED
    Inventors: Yueh-Ming Tung, Chia-Ming Yang, Jung-Wei Chen, Jian-De Leu, Guan-Lin Pan
  • Patent number: 11348833
    Abstract: A support structure for use in fan-out wafer level packaging is provided that includes, a silicon handler wafer having a first surface and a second surface opposite the first surface, a release layer is located above the first surface of the silicon handler wafer, and a layer selected from the group consisting of an adhesive layer and a redistribution layer is located on a surface of the release layer. After building-up a fan-out wafer level package on the support structure, infrared radiation is employed to remove (via laser ablation) the release layer, and thus remove the silicon handler wafer from the fan-out wafer level package.
    Type: Grant
    Filed: November 25, 2019
    Date of Patent: May 31, 2022
    Assignee: International Business Machines Corporation
    Inventors: Bing Dang, Jeffrey D. Gelorme, John U. Knickerbocker
  • Patent number: 11335634
    Abstract: A method for forming a chip package structure is provided. The method includes providing a wiring substrate. The method includes sequentially forming a nickel-containing layer and a gold-containing layer over the first pad. The method includes forming a conductive protection layer covering the gold-containing layer over the nickel-containing layer. The method includes bonding a chip to the wiring substrate through a conductive bump and a flux layer surrounding the conductive bump. The conductive bump is between the second pad and the chip. The method includes removing the flux layer while the conductive protection layer covers the nickel-containing layer.
    Type: Grant
    Filed: June 5, 2020
    Date of Patent: May 17, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Huan Chen, Kuo-Ching Hsu, Chen-Shien Chen
  • Patent number: 11335641
    Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate including a dielectric material having a first surface and an opposing second surface, a first photodefinable material on at least a portion of the second surface, and a second photodefinable material on at least a portion of the first photodefinable material, wherein the second photodefinable material has a different material composition than the first photodefinable material.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: May 17, 2022
    Assignee: Intel Corporation
    Inventors: Aleksandar Aleksov, Johanna M. Swan
  • Patent number: 11328970
    Abstract: Methods of fabricating a semiconductor package may include forming a first barrier layer on a first carrier, forming a sacrificial layer, including an opening that exposes at least a portion of the first barrier layer, on the first barrier layer, and forming a second barrier layer on the first barrier layer and on the sacrificial layer. The second barrier layer may include a portion formed on the sacrificial layer.
    Type: Grant
    Filed: May 5, 2020
    Date of Patent: May 10, 2022
    Inventors: Jung-Ho Park, Jin-Woo Park, Jae Gwon Jang, Gwang Jae Jeon
  • Patent number: 11315805
    Abstract: A method includes placing a plurality of package components over a carrier, encapsulating the plurality of package components in an encapsulant, forming a light-sensitive dielectric layer over the plurality of package components and the encapsulant, exposing the light-sensitive dielectric layer using a lithography mask, and developing the light-sensitive dielectric layer to form a plurality of openings. Conductive features of the plurality of package components are exposed through the plurality of openings. The method further includes forming redistribution lines extending into the openings. One of the redistribution lines has a length greater than about 26 mm. The redistribution lines, the plurality of package components, the encapsulant in combination form a reconstructed wafer.
    Type: Grant
    Filed: November 2, 2020
    Date of Patent: April 26, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Tin-Hao Kuo
  • Patent number: 11315802
    Abstract: A method of manufacturing a semiconductor package includes forming a plurality of trenches at a first surface of a silicon substrate, forming a conductive pad inside each of the plurality of trenches, forming a redistribution layer on the first surface of the silicon substrate, forming an external connection terminal on a first surface of the redistribution layer, removing the silicon substrate to expose each conductive pad, mounting a semiconductor chip to be connected to the conductive pads, and forming an encapsulant to cover at least one surface of the semiconductor chip.
    Type: Grant
    Filed: March 6, 2019
    Date of Patent: April 26, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Il Hwan Kim, Un Byoung Kang, Chung Sun Lee
  • Patent number: 11302662
    Abstract: The present application provides a semiconductor package with air gaps for reducing capacitive coupling between conductive features and a method for manufacturing the semiconductor package. The semiconductor package includes a first semiconductor structure and a second semiconductor structure bonded with the first semiconductor structure. The first semiconductor structure has a first bonding surface. The second semiconductor structure has a second bonding surface partially in contact with the first bonding surface. A portion of the first bonding surface is separated from a portion of the second bonding surface, a space between the portions of the first and second bonding surfaces is sealed and forms an air gap in the semiconductor package.
    Type: Grant
    Filed: May 1, 2020
    Date of Patent: April 12, 2022
    Assignee: Nanya Technology Corporation
    Inventor: Tse-Yao Huang
  • Patent number: 11289373
    Abstract: A method includes the following steps. A seed layer is formed over a structure having at least one semiconductor die. A first patterned photoresist layer is formed over the seed layer, wherein the first patterned photoresist layer includes a first opening exposing a portion of the seed layer. A metallic wiring is formed in the first opening and on the exposed portion of the seed layer. A second patterned photoresist layer is formed on the first patterned photoresist layer and covers the metallic wiring, wherein the second patterned photoresist layer includes a second opening exposing a portion of the metallic wiring. A conductive via is formed in the second opening and on the exposed portion of the metallic wiring. The first patterned photoresist layer and the second patterned photoresist layer are removed. The metallic wiring and the conductive via are laterally wrapped around with an encapsulant.
    Type: Grant
    Filed: July 7, 2019
    Date of Patent: March 29, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Po-Yuan Teng, Bor-Rung Su, De-Yuan Lu, Hao-Yi Tsai, Tin-Hao Kuo, Tzung-Hui Lee, Tai-Min Chang
  • Patent number: 11289411
    Abstract: A substrate structure includes a wiring structure, a first bump pad, a second bump pad and a compensation structure. The wiring structure includes a plurality of redistribution layers. The first bump pad and the second bump pad are bonded to and electrically connected to the wiring structure. An amount of redistribution layers disposed under the first bump pad is greater than an amount of redistribution layers disposed under the second bump pad. The compensation structure is disposed under the second bump pad.
    Type: Grant
    Filed: July 29, 2020
    Date of Patent: March 29, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Syu-Tang Liu, Tsung-Tang Tsai, Huang-Hsien Chang, Ching-Ju Chen
  • Patent number: 11282817
    Abstract: A semiconductor device includes a first semiconductor die package. The first semiconductor package includes a molding compound, and a conductive element in the molding compound, wherein a top surface of the conductive element is above or co-planar with a top-most surface of the molding compound. The semiconductor device further includes a second semiconductor die package. The second semiconductor package includes a plurality of copper-containing contacts on a single metal pad, wherein each of the plurality of copper-containing contacts is bonded to the conductive element.
    Type: Grant
    Filed: January 28, 2020
    Date of Patent: March 22, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Feng Chen, Chun-Hung Lin, Han-Ping Pu, Ming-Da Cheng, Kai-Chiang Wu
  • Patent number: 11282808
    Abstract: An inertial sensor includes a support substrate, a sensor main body supported by the support substrate, and a bonding member that is located between the support substrate and the sensor main body and bonds the sensor main body to the support substrate. The sensor main body includes a substrate bonded to the support substrate via the bonding member and a capacitance-type sensor device provided at a side of the substrate opposite to the support substrate. The substrate has a side surface, a first principal surface facing the support substrate, and a recessed step section that is located between the side surface and the first principal surface and connects the side surface to the first principal surface. The bonding member extends along the first principal surface and the step section.
    Type: Grant
    Filed: April 24, 2020
    Date of Patent: March 22, 2022
    Inventor: Teruo Takizawa
  • Patent number: 11276632
    Abstract: A semiconductor package includes a semiconductor chip including a chip pad on a first surface thereof, an external pad electrically connected to the chip pad of the semiconductor chip, an external connection terminal covering the external pad, and an intermediate layer between the external pad and the external connection terminal, the intermediate layer including a third metal material that is different from a first metal material included in the external pad and a second metal material included in the external connection terminal.
    Type: Grant
    Filed: December 23, 2019
    Date of Patent: March 15, 2022
    Assignee: NEPES CO., LTD.
    Inventors: Gi Jo Jung, Chang Yong Jo, Young Mo Lee, Jung Sic Oh, Jong Ho Han
  • Patent number: 11270968
    Abstract: The purpose of the present invention is to provide an electronic circuit connection method and an electronic circuit capable of improving the reliability of electrical connection. A connection method for an electronic circuit 100 includes: a process of forming a first metal bumps 30 and a second metal bump 40, each of which has a cone shape; and a process of joining a first electrode pad 12 and a third electrode pad 22 by the first metal bump 30 and joining a second electrode pad 13 and a fourth electrode pad 23 by the second metal bump 40, wherein at least one region of between a first region 11a and a second region 11b in a first connection surface 11 and between a third region 21a and a fourth region 21b in a second connection surface 21 has a step 11c, and the first metal bump 30 and the second metal bump 40 have different heights so as to correct a height H1 of the step 11c.
    Type: Grant
    Filed: May 30, 2019
    Date of Patent: March 8, 2022
    Assignee: NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY
    Inventors: Masaru Hashino, Ying Ying Lim, Hiroshi Nakagawa, Masahiro Aoyagi, Katsuya Kikuchi
  • Patent number: 11269050
    Abstract: A radar system includes a first integrated radar circuit having a plurality of first transmission paths and a local oscillator configured to generate a local oscillator signal. The first integrated radar circuit has a first terminal configured to output an oscillation signal based on the local oscillator signal. The radar system includes a second integrated radar circuit having a second transmission path and a second terminal. The radar system includes a partially reflective element coupled to the first terminal via a first line section and to the second terminal via a second line section. The partially reflective element is configured to reflect back a first portion of the oscillation signal as a reflected signal via the first line section to the first terminal and to pass on a second portion of the oscillation signal as a forward signal via the second line section to the second terminal.
    Type: Grant
    Filed: September 20, 2019
    Date of Patent: March 8, 2022
    Inventors: Philipp Schmidt, Alexander Melzer, Andreas Och
  • Patent number: 11264992
    Abstract: A field-programmable-gate-array (FPGA) IC chip includes multiple first non-volatile memory cells in the FPGA IC chip, wherein the first non-volatile memory cells are configured to save multiple resulting values for a look-up table (LUT) of a programmable logic block of the FPGA IC chip, wherein the programmable logic block is configured to select, in accordance with its inputs, one from the resulting values into its output; and multiple second non-volatile memory cells in the FPGA IC chip, wherein the second non-volatile memory cells are configured to save multiple programming codes configured to control a switch of the FPGA IC chip.
    Type: Grant
    Filed: March 23, 2021
    Date of Patent: March 1, 2022
    Assignee: iCometrue Company Ltd.
    Inventors: Jin-Yuan Lee, Mou-Shiung Lin
  • Patent number: 11264342
    Abstract: Some embodiments relate to a semiconductor device package, which includes a substrate with a contact pad. A non-solder ball is coupled to the contact pad at a contact pad interface surface. A layer of solder is disposed over an outer surface of the non-solder ball, and has an inner surface and an outer surface which are generally concentric with the outer surface of the non-solder ball. An intermediate layer separates the non-solder ball and the layer of solder. The intermediate layer is distinct in composition from both the non-solder ball and the layer of solder. Sidewalls of the layer of solder are curved or sphere-like and terminate at a planar surface, which is disposed at a maximum height of the layer of solder as measured from the contact pad interface surface.
    Type: Grant
    Filed: January 3, 2020
    Date of Patent: March 1, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Chung-Shi Liu, Ming-Da Cheng, Mirng-Ji Lii, Meng-Tse Chen, Wei-Hung Lin
  • Patent number: 11227859
    Abstract: A device package and a method of forming the device package are described. The device package includes one or more dies disposed on a first substrate. The device packages further includes one or more interconnects vertically disposed on the first substrate, and a mold layer disposed over and around the first die, the one or more interconnects, and the first substrate. The device package has a second die disposed on a second substrate, wherein the first substrate is electrically coupled to the second substrate with the one or more interconnects, and wherein the one or more interconnects are directly disposed on at least one of a top surface of the first substrate and a bottom surface of the second substrate without an adhesive layer. The device package may include one or more interconnects having one or more different thicknesses or heights at different locations on the first substrate.
    Type: Grant
    Filed: September 30, 2017
    Date of Patent: January 18, 2022
    Assignee: Intel Corporation
    Inventors: Feras Eid, Johanna M. Swan, Shawna M. Liff
  • Patent number: 11211336
    Abstract: An integrated fan-out package includes an integrated circuit, a plurality of semiconductor devices, a first redistribution circuit structure, and an insulating encapsulation. The integrated circuit has an active surface and a rear surface opposite to the active surface. The semiconductor devices are electrically connected the integrated circuit. The first redistribution circuit structure is disposed between the integrated circuit and the semiconductor devices. The first redistribution circuit structure is electrically connected to the integrated circuit and the semiconductor devices respectively. The first redistribution circuit structure has a first surface, a second surface opposite to the first surface, and lateral sides between the first surface and the second surface. The insulating encapsulation encapsulates the integrated circuit and the semiconductor devices and covers the first surface and the second surface of the first redistribution circuit structure.
    Type: Grant
    Filed: November 1, 2019
    Date of Patent: December 28, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Chun-Hui Yu, Kuo-Chung Yee
  • Patent number: 11211318
    Abstract: A method includes receiving a first design for conductive bumps on a first surface of an interposer, the conductive bumps in the first design having a same cross-section area; grouping the conductive bumps in the first design into a first group of conductive bumps in a first region of the first surface and a second group of conductive bumps in a second region of the first surface, where a bump pattern density of the second region is lower than that of the first region; forming a second design by modifying the first design, where modifying the first design includes modifying a cross-section area of the second group of conductive bumps in the second region; and forming the conductive bumps on the first surface of the interposer in accordance with the second design, where after being formed, the first group of conductive bumps and the second group of conductive bumps have different cross-section areas.
    Type: Grant
    Filed: June 21, 2019
    Date of Patent: December 28, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ling-Wei Li, Cheng-Lin Huang, Min-Tar Liu, Fu-Kang Chiao, Matt Chou, Chun-Yen Lo, Che-Jung Chu, Wen-Ming Chen, Kuo-Chio Liu
  • Patent number: 11205640
    Abstract: Disclosed is a semiconductor package having a package-on-package (PoP) structure in which a signal region and a power region are formed separately. The semiconductor package includes a lower semiconductor package and an upper semiconductor package on the lower semiconductor package. The upper semiconductor package includes an upper package substrate, a memory chip on the upper package substrate, a wire that electrically connects the memory chip to the upper package substrate, a power connector on the upper semiconductor package, a signal connector on the bottom surface of the upper package substrate, and an upper package molding material.
    Type: Grant
    Filed: May 20, 2020
    Date of Patent: December 21, 2021
    Inventor: Mingi Hong
  • Patent number: 11195771
    Abstract: A substrate structure includes a substrate, an encapsulating layer and a redistribution structure. The substrate has a first surface. The encapsulating layer surrounds the substrate and has a first surface. The redistribution structure is disposed on the first surface of the substrate and the first surface of the encapsulating layer. A gap exists in elevation between the first surface of the substrate and the first surface of the encapsulating layer.
    Type: Grant
    Filed: December 5, 2019
    Date of Patent: December 7, 2021
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Hsu-Nan Fang
  • Patent number: 11195812
    Abstract: A method for fabricating an electronic package is provided. A plurality of packaging structures are provided, each of which having a carrier and at least one electronic component disposed on the carrier. The plurality of packaging structures are disposed on a supporting plate. An encapsulation layer is formed on the supporting plate and encapsulates the plurality of packaging structures. Even if there are various types of electronic packages of different specifications in the market, the molds that the encapsulation layer uses can still be developed for a supporting plate of a certain specification. Therefore, the fabrication cost of the electronic package is reduced.
    Type: Grant
    Filed: March 17, 2020
    Date of Patent: December 7, 2021
    Assignee: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Hsin-Yi Liao, Cheng-Kai Chang, Bo-Hao Ma, Chun-Chi Ke
  • Patent number: 11189545
    Abstract: A semiconductor device includes a plurality of first semiconductor dies, a first adhesive layer, a plurality of second semiconductor dies, a second adhesive layer, and a plurality of first metal bumps. The first semiconductor dies are embedded in a first photosensitive layer of a first group of wafers. The first adhesive layer is disposed between at least two of the first group of wafers to form a first structure. The second semiconductor dies are embedded in a second photosensitive layer of a second group of wafers. The second adhesive layer is disposed between at least two of the second group of wafers to form a second structure. The first metal bumps are disposed between the first structure and second structure, in which the first structure is connected to the second structure with the first metal bumps.
    Type: Grant
    Filed: June 20, 2019
    Date of Patent: November 30, 2021
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Chiang-Lin Shih, Pei-Jhen Wu
  • Patent number: 11183472
    Abstract: Even in a case where a pad becomes smaller, solder connection strength is improved. A semiconductor device includes a pad, a diffusion layer, and a melting layer. The pad included by the semiconductor device includes a concave portion on a surface at which solder connection is to be performed. The diffusion layer included by the semiconductor device is disposed at the concave portion and constituted with a metal which remains on the surface of the pad while diffusing into solder upon the solder connection. The melting layer included by the semiconductor device is disposed adjacent to the diffusion layer and constituted with a metal which diffuses and melts into the solder upon the solder connection.
    Type: Grant
    Filed: October 19, 2018
    Date of Patent: November 23, 2021
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventor: Takuya Nakamura
  • Patent number: 11171119
    Abstract: A semiconductor module includes a module substrate, a semiconductor package mounted on the module substrate, a first bonding wire connecting the module substrate to the semiconductor package, and a first molding member covering the first bonding wire. The semiconductor package includes a package substrate, a semiconductor chip mounted on the package substrate, a second bonding wire connecting the package substrate to the semiconductor chip, and a second molding member covering the semiconductor chip and the second bonding wire. The first and second bonding wires are each connected to one connection pad of the package substrate.
    Type: Grant
    Filed: November 26, 2019
    Date of Patent: November 9, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kyungseon Hwang, Wonyoung Kim, Jinchan Ahn
  • Patent number: 11171099
    Abstract: A semiconductor device includes a semiconductor wafer. A plurality of pillar bumps is formed over the semiconductor wafer. A solder is deposited over the pillar bumps. The semiconductor wafer is singulated into a plurality of semiconductor die after forming the pillar bumps while the semiconductor wafer is on a carrier. An encapsulant is deposited around the semiconductor die and pillar bumps while the semiconductor die remains on the carrier. The encapsulant covers an active surface of the semiconductor die between the pillar bumps.
    Type: Grant
    Filed: July 29, 2019
    Date of Patent: November 9, 2021
    Assignee: Semtech Corporation
    Inventors: Kok Khoon Ho, Jonathan Clark, John MacLeod
  • Patent number: 11171115
    Abstract: Described is a packaging technology to improve performance of an AI processing system. An IC package is provided which comprises: a substrate; a first die on the substrate, and a second die stacked over the first die. The first die includes memory and the second die includes computational logic. The first die comprises a ferroelectric RAM (FeRAM) having bit-cells. Each bit-cell comprises an access transistor and a capacitor including ferroelectric material. The access transistor is coupled to the ferroelectric material. The FeRAM can be FeDRAM or FeSRAM. The memory of the first die may store input data and weight factors. The computational logic of the second die is coupled to the memory of the first die. The second die is an inference die that applies fixed weights for a trained model to an input data to generate an output. In one example, the second die is a training die that enables learning of the weights.
    Type: Grant
    Filed: March 18, 2019
    Date of Patent: November 9, 2021
    Assignee: Kepler Computing Inc.
    Inventors: Sasikanth Manipatruni, Rajeev Kumar Dokania, Amrita Mathuriya, Ramamoorthy Ramesh
  • Patent number: 11171127
    Abstract: In one example, a semiconductor structure comprises a redistribution structure comprising a conductive structure, a cavity substrate on a top side of the redistribution structure and having a cavity and a pillar contacting the redistribution structure, an electronic component on the top surface of the redistribution structure and in the cavity, wherein the electronic component is electrically coupled with the conductive structure, and an encapsulant in the cavity and on the top side of the redistribution structure, contacting a lateral side of the electronic component, a lateral side of the cavity, and a lateral side of the pillar. Other examples and related methods are also disclosed herein.
    Type: Grant
    Filed: August 2, 2019
    Date of Patent: November 9, 2021
    Assignee: AMKOR TECHNOLOGY SINGAPORE HOLDING PTE. LTD.
    Inventors: Gi Tae Lim, Jae Yun Kim, Myung Jae Choi
  • Patent number: 11164805
    Abstract: A semiconductor package including a package substrate, a semiconductor chip on a top surface of the package substrate, a connection terminal between the package substrate and the semiconductor chip, the connection terminal connecting the package substrate to the semiconductor chip, a non-conductive film (NCF) between the package substrate and semiconductor chip, the NCF surrounding the connection terminal and bonding the semiconductor chip to the package substrate, and a side encapsulation material covering a side surface of the semiconductor chip, contacting the package substrate, and including a first portion between a bottom surface of the semiconductor chip and the top surface of the package substrate may be provided. At least a portion of the NCF includes a second portion that horizontally protrudes from the semiconductor chip when viewed, and a portion of the side encapsulation material is in contact with the bottom surface of the semiconductor chip.
    Type: Grant
    Filed: March 10, 2020
    Date of Patent: November 2, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Younglyong Kim, Taewon Yoo
  • Patent number: 11158551
    Abstract: A method to fabricate a modular die daisy chain design for wafer level chip scale package (WLCSP) board level reliability testing is described. A wafer is provided having pairs of solder balls electrically connected to each other by underlying metal pads. The wafer is singulated into dies of any of a plurality of sizes as required for testing. Thereafter one of the singulated dies is mounted to a test printed circuit board (PCB). The pairs of solder balls are electrically connected in a daisy chain on the test PCB.
    Type: Grant
    Filed: January 7, 2020
    Date of Patent: October 26, 2021
    Assignee: Dialog Semiconductor (UK) Limited
    Inventors: Duncan Barclay, Jesus Mennen Belonio, Jr., Edward Horsburgh
  • Patent number: 11145627
    Abstract: Provided is a semiconductor package including first to third semiconductor dies, first to third RDL layers, conductive vias and an encapsulant, and a manufacturing method thereof. The first RDL layer is on an active surface of the first semiconductor die. The second semiconductor die is on the first RDL layer and electrically connected thereto through first TSVs. The conductive vias are on the first RDL layer and around the second semiconductor die. The encapsulant encapsulates the second semiconductor die and the conductive vias. The second RDL layer is on the encapsulant. The third semiconductor die is on the second RDL layer and electrically connected thereto through second TSVs. The third RDL layer is on the third semiconductor die. The area of the second semiconductor die is smaller than that of the first semiconductor die. The area of the third semiconductor die is larger than that of the second semiconductor die.
    Type: Grant
    Filed: October 4, 2019
    Date of Patent: October 12, 2021
    Assignee: Winbond Electronics Corp.
    Inventor: Jin-Neng Wu
  • Patent number: 11134573
    Abstract: A printed wiring-board island relieves added complexity to a printed circuit board. The printed wiring-board island creates an island form factor in the printed circuit board. Coupling of a semiconductive device package to the printed wiring-board island includes a ball-grid array. The ball-grid array can at least partially penetrate the printed wiring-board island.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: September 28, 2021
    Assignee: Intel Corporation
    Inventors: Georg Seidemann, Sonja Koller, Bernd Waidhas
  • Patent number: 11127666
    Abstract: A semiconductor device has a semiconductor die mounted to a carrier. An encapsulant is deposited over the semiconductor die and carrier. The carrier is removed. A first insulating layer is formed over a portion of the encapsulant within an interconnect site outside a footprint of the semiconductor die. An opening is formed through the first insulating layer within the interconnect site to expose the encapsulant. The opening can be ring-shaped or vias around the interconnect site and within a central region of the interconnect site to expose the encapsulant. A first conductive layer is formed over the first insulating layer to follow a contour of the first insulating layer. A second conductive layer is formed over the first conductive layer and exposed encapsulant. A second insulating layer is formed over the second conductive layer. A bump is formed over the second conductive layer in the interconnect site.
    Type: Grant
    Filed: February 8, 2017
    Date of Patent: September 21, 2021
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: Yaojian Lin, Kang Chen, Jianmin Fang
  • Patent number: 11112841
    Abstract: Embodiments of the invention include a mmWave transceiver and methods of forming such devices. In an embodiment, the mmWave transceiver includes an RF module. The RF module may include a package substrate, a plurality of antennas formed on the package substrate, and a die attached to a surface of the package substrate. In an embodiment, the mmWave transceiver may also include a mainboard mounted to the RF module with one or more solder balls. In an embodiment, a thermal feature is embedded within the mainboard, and the thermal feature is separated from the die by a thermal interface material (TIM) layer. According to an embodiment, the thermal features are slugs and/or vias. In an embodiment, the die compresses the TIM layer resulting in a TIM layer with minimal thickness.
    Type: Grant
    Filed: April 1, 2017
    Date of Patent: September 7, 2021
    Assignee: Intel Corporation
    Inventors: Divya Mani, William J. Lambert, Shawna Liff, Sergio A. Chan Arguedas, Robert L. Sankman
  • Patent number: 11101261
    Abstract: A package includes a package component, which further includes a top surface and a metal pad at the top surface of the package component. The package further includes a non-reflowable electrical connector over and bonded to the metal pad, and a molding material over the package component. The non-reflowable electrical connector is molded in the molding material and in contact with the molding material. The non-reflowable electrical connector has a top surface lower than a top surface of the molding compound.
    Type: Grant
    Filed: August 5, 2019
    Date of Patent: August 24, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuei-Wei Huang, Chih-Wei Lin, Hsiu-Jen Lin, Wei-Hung Lin, Ming-Da Cheng, Chung-Shi Liu
  • Patent number: 11081460
    Abstract: A method of manufacturing a semiconductor device having a conductive substrate having a first surface, a second surface opposite the first surface, and a passivation material covering a portion of the first surface can include applying a seed layer of conductive material to the first surface of the conductive substrate and to the passivation material, the seed layer having a first face opposite the conductive substrate. The method can include forming a plurality of pillars comprising layers of first and second materials. The method can include etching the seed layer to undercut the seed layer between the conductive substrate and the first material of at least one of the pillars. In some embodiments, a cross-sectional area of the seed layer in contact with the passivation material between the first material and the conductive substrate is less than the cross-sectional area of the second material.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: August 3, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Suresh Yeruva, Owen R. Fay, Sameer S. Vadhavkar, Adriel Jebin Jacob Jebaraj, Wayne H. Huang
  • Patent number: 11081391
    Abstract: A semiconductor device includes a plurality of connectors and at least one insulating layer disposed over a semiconductor substrate. A molding layer extends around the plurality of connectors. A sidewall of the molding layer that is closest to a scribe line is offset from the scribe line.
    Type: Grant
    Filed: June 26, 2018
    Date of Patent: August 3, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ying-Ju Chen, Hsien-Wei Chen
  • Patent number: 11081384
    Abstract: A method includes producing a semiconductor arrangement having a semiconductor layer, a first insulation layer arranged on the semiconductor layer and facing a first surface of the semiconductor arrangement, and an insulating via extending in a vertical direction through the semiconductor layer as far as the first insulation layer, the insulating via surrounding a region of the semiconductor layer in a ring-shaped fashion. The method further includes permanently securing a first carrier to the first surface of the semiconductor arrangement.
    Type: Grant
    Filed: April 18, 2019
    Date of Patent: August 3, 2021
    Assignee: Infineon Technologies AG
    Inventors: Hermann Gruber, Joerg Busch
  • Patent number: 11066297
    Abstract: Microelectromechanical systems (MEMS) packages and methods of manufacture thereof are described. In an embodiment, a method of manufacturing a MEMS package may include attaching a MEMS structure having a capping structure thereon to a device wafer comprising a plurality of first devices formed therein to form a wafer level MEMS package; and singulating the device wafer having the MEMS structure attached thereto to form a plurality of chip scale MEMS packages.
    Type: Grant
    Filed: May 14, 2018
    Date of Patent: July 20, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Kuo-Chung Yee
  • Patent number: 11069642
    Abstract: A package structure includes a semiconductor die, a redistribution circuit structure, and conductive pads. The redistribution circuit structure is located on and electrically connected to the semiconductor die, the redistribution circuit structure includes a first contact pad having a first width and a second contact pad having a second width. The conductive pads are located on and electrically connected to the redistribution circuit structure through connecting to the first contact pad and the second contact pad, the redistribution circuit structure is located between the conductive pads and the semiconductor die. The first width of the first contact pad is less than a width of the conductive pads, and the second width of the second contact pad is substantially equal to or greater than the width of the conductive pads.
    Type: Grant
    Filed: May 13, 2019
    Date of Patent: July 20, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsung-Shu Lin, Hsuan-Ning Shih
  • Patent number: 11062976
    Abstract: An exemplary assembly includes a top circuit substrate; a bottom circuit assembly that underlays the top circuit substrate and is attached to the top circuit substrate by an adhesive layer as a stiffener, the adhesive layer, and a plurality of conductive balls. The top circuit substrate includes a plurality of upper vias that extend through the top circuit substrate. The bottom circuit assembly includes a plurality of lower vias that extend through the bottom circuit assembly. The adhesive layer includes internal connections that electrically connect the upper vias to the lower vias. The conductive balls are housed in the lower vias. The bottom circuit assembly has an elastic modulus at least six times the elastic modulus of the top circuit substrate, and has a coefficient of thermal expansion at least two times the coefficient of thermal expansion of the top circuit substrate.
    Type: Grant
    Filed: May 3, 2019
    Date of Patent: July 13, 2021
    Assignee: International Business Machines Corporation
    Inventors: Lei Shan, Daniel J. Friedman
  • Patent number: 11061193
    Abstract: A semiconductor package including: a chip having a first surface and a second surface; a mold configured to encapsulate the chip; a vertical conductive channel electrically connected to a pad formed on the second surface of the chip while passing through the mold; a wiring pattern electrically connected to a pad formed on the first surface of the chip and configured to perform electrical connection in the package; an optical device arranged on a surface of the semiconductor package to be electrically connected to the vertical conductive channel; and an external connection terminal configured to electrically connect the semiconductor package to the outside.
    Type: Grant
    Filed: April 3, 2020
    Date of Patent: July 13, 2021
    Assignee: Lipac Co., Ltd.
    Inventor: Sang Don Lee