Ball Shaped Patents (Class 257/738)
  • Patent number: 10332945
    Abstract: An organic light-emitting display apparatus includes a substrate; a common voltage line; a pixel including: a first area at which light is emitted and a contact area at which the common voltage line is electrically connected to the pixel; a via insulating layer including a contact via hole defined therein to expose a portion of the common voltage line; a pixel electrode in the first area of the pixel; a pixel-defining layer including a first opening defined therein to expose a portion of the pixel electrode; an intermediate layer on the exposed portion of the pixel electrode, the intermediate layer including an organic emission layer; and a counter electrode on the intermediate layer, the counter electrode in direct contact with the common voltage line at the contact via hole in the contact area.
    Type: Grant
    Filed: October 18, 2017
    Date of Patent: June 25, 2019
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventor: Jeeeun Kim
  • Patent number: 10332862
    Abstract: A semiconductor package structure includes a first substrate, at least one first semiconductor element and a second substrate. The first semiconductor element is attached to the first substrate. The second substrate defines a cavity and includes a plurality of thermal vias. One end of each of the thermal vias is exposed in the cavity, and the first semiconductor element is disposed within the cavity and thermally connected to the thermal vias.
    Type: Grant
    Filed: September 7, 2017
    Date of Patent: June 25, 2019
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Bo-Syun Chen, Tang-Yuan Chen, Yu-Chang Chen, Jin-Feng Yang, Chin-Li Kao, Meng-Kai Shih
  • Patent number: 10332855
    Abstract: A fan-out semiconductor package includes a first connection member having a through hole, a semiconductor chip in the through hole, having an active surface with a connection pad and an inactive surface on an opposing side. An encapsulant encapsulates at least a portion of the first connection member and the semiconductor chip. A second connection member is on the first connection member and the semiconductor chip. The first connection member and the second connection member each include a redistribution layer electrically connected to a connection pad of the semiconductor chip. The interface between the second connection member and the encapsulant is located on a different level from the level of the interface between the second connection member and a redistribution layer of the first connection member or the level of the interface between the second connection member and a connection pad of the semiconductor chip.
    Type: Grant
    Filed: March 7, 2017
    Date of Patent: June 25, 2019
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Doo Hwan Lee, Ju Hyeon Kim, Dae Kyu Ahn, Sung Won Jeong
  • Patent number: 10319729
    Abstract: Apparatuses and methods have been disclosed. One such apparatus includes strings of memory cells formed on a topside of a substrate. Support circuitry is formed on the backside of the substrate and coupled to the strings of memory cells through vertical interconnects in the substrate. The vertical interconnects can be transistors, such as surround substrate transistors and/or surround gate transistors.
    Type: Grant
    Filed: February 1, 2016
    Date of Patent: June 11, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Takehiro Hasegawa, Koji Sakui
  • Patent number: 10304785
    Abstract: Embodiments of the present disclosure are directed towards a package assembly for embedded die and associated techniques and configurations.
    Type: Grant
    Filed: June 19, 2018
    Date of Patent: May 28, 2019
    Assignee: Intel Corporation
    Inventor: Takashi Shuto
  • Patent number: 10297559
    Abstract: Provided are a semiconductor device and a semiconductor package including the same. The semiconductor device comprises a semiconductor chip body including a first chip pad on a top surface, a passivation film disposed on the semiconductor chip body and a first redistribution layer that is disposed between the passivation film and the semiconductor chip body with an opening to expose a first chip center pad region at least partially overlapping the first chip pad, a first redistribution center pad region connected to the first chip center pad region, and a first edge pad region spaced apart from the first redistribution center pad region, through the passivation film, wherein a top surface of the first chip center pad region and a top surface of the first redistribution center pad region are not disposed on the same plane.
    Type: Grant
    Filed: October 17, 2016
    Date of Patent: May 21, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Won-Young Kim, Sun-Won Kang, Jin-Chan Ahn
  • Patent number: 10282587
    Abstract: A sensing module substrate and a sensing module including the same are provided. The sensing module substrate includes a film substrate having a first surface and a second surface; sensing vias which penetrate the film substrate from the first surface to the second surface, each of the sensing vias being configured to be coupled to pixels of a semiconductor chip; and an interconnection pattern provided on at least one of the first surface and the second surface of the film substrate.
    Type: Grant
    Filed: December 30, 2016
    Date of Patent: May 7, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Inho Choi, Youngdoo Jung, Woonbae Kim, Jungwoo Kim, Ji-Yong Park, Kyoungsuk Yang, Jeong-Kyu Ha
  • Patent number: 10276424
    Abstract: Methods and apparatus for wafer level packaging are described herein. According to one embodiment, a method comprises depositing an adhesive layer atop a carrier, placing at least a portion of a substrate pre-fabricated with a plurality of die cavities and a plurality of through vias atop the laminate, inserting a die into each of the die cavities, encapsulating the die and the substrate and debonding and removing the laminate and the carrier from the encapsulated die and substrate. Another embodiment provides an apparatus comprising a substrate, a plurality of die cavities formed through the substrate and a plurality of conductive through vias disposed through the substrate and arranged about the perimeter of each die cavity, wherein a top surface of the substrate is exposed for application of an encapsulating layer and a bottom surface of the substrate is exposed for placement on an adhesive layer.
    Type: Grant
    Filed: June 30, 2017
    Date of Patent: April 30, 2019
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Guan Huei See, Yu Gu, Arvind Sundarrajan
  • Patent number: 10276548
    Abstract: An embodiment package includes a first package. The first package includes a first integrated circuit die, an encapsulant around the first integrated circuit die, and redistribution layers over the encapsulant and the first integrated circuit die. The package also includes a second package bonded to the first package by a plurality of functional connectors. The functional connectors and the redistribution layers electrically connect a second integrated circuit die of the second package to the first integrated circuit die. The package also includes a plurality of dummy connectors disposed between the first package and the second package. One end of each of the plurality of dummy connectors facing the first package is physically separated from the first package.
    Type: Grant
    Filed: August 4, 2017
    Date of Patent: April 30, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Shien Chen, Hsiu-Jen Lin, Ming-Chih Yew, Ming-Da Cheng, Yi-Jen Lai, Yu-Tse Su, Sey-Ping Sun, Yang-Che Chen
  • Patent number: 10269757
    Abstract: An integrated circuit includes a substrate and at least one chip. Each chip is disposed over the substrate or the other chip. Solder bumps are disposed between the substrate and the at least one chip. An insulating film is disposed around the solder bumps and provides electrical insulation for the solder bumps except areas for interconnections. A thermally conductive underfill is disposed between the substrate, the at least one chip, and the solder bumps.
    Type: Grant
    Filed: January 6, 2016
    Date of Patent: April 23, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Tien-I Bao
  • Patent number: 10262699
    Abstract: A memory device includes a memory cell array having a plurality of memory cell groups with a corresponding plurality of independent channels, and the device and an operating method thereof perform an internal data processing operation for the memory cell groups. The memory device includes an internal command generator configured to generate one or more internal commands in order to perform an internal data processing operation in response to a reception of a command, and an internal common bus for a common internal processing channel which is disposed to be shared by the plurality of memory cell groups and configured to form a transmission path of data between the plurality of memory cell groups when the internal data processing operation is performed.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: April 16, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Reum Oh, Je-Min Ryu, Pavan Kumar Kasibhatla
  • Patent number: 10261249
    Abstract: An optical module includes a first board that includes a recessed portion and a first conductor layer, a second board accommodated in the recessed portion and includes an optical waveguide and a second conductor layer, a semiconductor element installed across the first board and the second board and coupled to the first conductor layer and the second conductor layer, and a first bonding material disposed between a sidewall and a bottom surface of the recessed portion and the second board so as to bond the first board and the second board to each other.
    Type: Grant
    Filed: October 17, 2017
    Date of Patent: April 16, 2019
    Assignee: FUJITSU LIMITED
    Inventors: Norio Kainuma, Naoaki Nakamura, Kenji Fukuzono
  • Patent number: 10256210
    Abstract: A semiconductor package structure has a first electronic component on an insulating layer, a dielectric layer on the insulating layer and surrounding the first electronic component, a second electronic component stacked on the first electronic component, wherein an active surface of the first electronic component faces an active surface of the second electronic component, a molding compound on the first electronic component and surrounding the second electronic component, a third electronic component stacked on the second electronic component and the molding compound.
    Type: Grant
    Filed: September 6, 2017
    Date of Patent: April 9, 2019
    Assignee: MEDIATEK INC.
    Inventors: Tzu-Hung Lin, Ching-Wen Hsiao, I-Hsuan Peng
  • Patent number: 10249586
    Abstract: Embodiments are directed to a method of forming a semiconductor chip package and resulting structures having a mixed under-bump metallization (UBM) size and pitch on a single die. A first set of UBMs having a first total plateable surface area is formed on a first region of a die. A second set of UBMs having an equal total plateable surface area is formed on a second region of the die. A solder bump having a calculated solder height is applied to a plateable surface of each UBM. The solder height is calculated such that a volume of solder in the first region is equal to a volume of solder in the second region.
    Type: Grant
    Filed: September 21, 2017
    Date of Patent: April 2, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Charles L. Arvin, Christopher D. Muzzy
  • Patent number: 10240050
    Abstract: A method of producing an article is described. The method includes (a) providing a substrate comprising an etchable surface layer; (b) coating the etchable surface layer with a composition comprising a non-volatile, etch-resistant component in a volatile liquid carrier; and (c) drying the composition to remove the liquid carrier, whereupon the non-volatile, etch-resistant component self-assembles to form etch-resistant traces on the etchable surface layer. The liquid carrier is in the form of an emulsion comprising a continuous phase and a second phase in the form of domains dispersed in the continuous phase.
    Type: Grant
    Filed: September 19, 2012
    Date of Patent: March 26, 2019
    Assignee: Clearview Films Ltd.
    Inventors: Arkady Garbar, Eric L. Granstrom, Joseph Masrud
  • Patent number: 10217873
    Abstract: A semiconductor device has a first semiconductor die including an active region formed on a surface of the first semiconductor die. The active region of the first semiconductor die can include a sensor. An encapsulant is deposited over the first semiconductor die. A conductive layer is formed over the encapsulant and first semiconductor die. An insulating layer can be formed over the first semiconductor die. An opening is formed in the insulating layer over the active region. A transmissive layer is formed over the first semiconductor die including the active region. The transmissive layer includes an optical dielectric material or an optical transparent or translucent material. The active region is responsive to an external stimulus passing through the transmissive layer. A plurality of bumps is formed through the encapsulant and electrically connected to the conductive layer. A second semiconductor die is disposed adjacent to the first semiconductor die.
    Type: Grant
    Filed: December 29, 2016
    Date of Patent: February 26, 2019
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: Byung Joon Han, Il Kwon Shim, Heap Hoe Kuan
  • Patent number: 10186487
    Abstract: A semiconductor device includes a first chip having a through via, a second chip having a first terminal that is electrically connected to the through via, and a substrate having a second terminal disposed on a first surface thereof and electrically connected to the first terminal. When viewed along a straight line that intersects a center axis that is perpendicular to the first surface and intersects a center point of the substrate, the first terminal is disposed further towards the center axis than the second terminal and the through via is disposed further towards the center axis than the first terminal.
    Type: Grant
    Filed: August 28, 2017
    Date of Patent: January 22, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Kazushige Kawasaki, Mikihiko Ito, Masaru Koyanagi
  • Patent number: 10186480
    Abstract: A stacked-chip apparatus includes a package substrate and an interposer with a chip stack disposed with a standoff that matches the interposer. A package-on-package stacked-chip apparatus includes a top package disposed on the interposer.
    Type: Grant
    Filed: January 14, 2013
    Date of Patent: January 22, 2019
    Assignee: INTEL CORPORATION
    Inventors: Sriram Muthukumar, Charles A. Gealer
  • Patent number: 10177073
    Abstract: Disclosed herein are a device having an embedded heat spreader and method for forming the same. A carrier substrate may comprise a carrier, an adhesive layer, a base film layer, and a seed layer. A patterned mask is formed with a heat spreader opening and via openings. Vias and a heat spreader may be formed in the pattern mask openings at the same time using a plating process and a die attached to the head spreader by a die attachment layer. A molding compound is applied over the die and heat spreader so that the heat spreader is disposed at the second side of the molded substrate. A first RDL may have a plurality of mounting pads and a plurality of conductive lines is formed on the molded substrate, the mounting pads may have a bond pitch greater than the bond pitch of the die contact pads.
    Type: Grant
    Filed: July 3, 2017
    Date of Patent: January 8, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei Sen Chang, Tsung-Hsien Chiang, Yen-Chang Hu, Ching-Wen Hsiao
  • Patent number: 10163876
    Abstract: A method of manufacturing a structure includes: providing a substrate; forming an adhesive layer over the substrate; forming an interconnect layer comprising a metal line and a metal via over the adhesive layer; forming a plurality of conductive pads over the interconnect layer; forming conductive pillars over the interconnect layer; disposing a first semiconductor die over the conductive pads, the first semiconductor die being spaced apart from the conductive pillars; bonding a second semiconductor die with the conductive pillars; and removing the substrate and the adhesive layer to expose a conductive portion of the interconnect layer.
    Type: Grant
    Filed: May 23, 2018
    Date of Patent: December 25, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Shin-Puu Jeng, Jui-Pin Hung, Feng-Cheng Hsu
  • Patent number: 10163866
    Abstract: A semiconductor device and method that utilize a surface device are provided. In an embodiment a fuse line comprises an underbump metallization which has two separate, electrically isolated parts. The two parts are bridged by an external connector, such as a solder ball in order to electrically connect the surface device. When, after testing, the surface device is determined to be defective, the fuse line may be disconnected by removing the external connector from the two separate parts, electrically isolating the surface device. In another embodiment the surface is located beneath a package within an integrated fan out package or is part of a multi-fan out package.
    Type: Grant
    Filed: September 27, 2017
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsien-Wei Chen, Ying-Ju Chen, An-Jhih Su, Jie Chen
  • Patent number: 10157828
    Abstract: A chip package structure includes a semiconductor component, a plurality of conductive pillars, an encapsulant and a redistribution layer. The semiconductor component includes a plurality of pads. The conductive pillars are disposed on the pads, wherein each of the conductive pillars is a solid cylinder including a top surface and a bottom surface, and a diameter of the top surface is substantially the same as a diameter of the bottom surface. The encapsulant encapsulates the semiconductor component and the conductive pillars, wherein the encapsulant exposes the top surface of each of the conductive pillars. The redistribution layer is disposed on the encapsulant and electrically connected to the conductive pillars.
    Type: Grant
    Filed: May 19, 2017
    Date of Patent: December 18, 2018
    Assignee: Powertech Technology Inc.
    Inventors: Hung-Hsin Hsu, Nan-Chun Lin
  • Patent number: 10157824
    Abstract: A device comprising a semiconductor die, a package substrate coupled to the semiconductor die, and an encapsulation layer that at least partially encapsulates the semiconductor die. The package substrate includes at least one stacked via. The at least one stacked via includes a first via and a second via coupled to the first via. The second via includes a seed layer coupled to the first via. The second via includes a different shape than the first via. The package substrate includes a prepreg layer. The package substrate includes a first pad coupled to the first via, and a second pad coupled to the second via.
    Type: Grant
    Filed: August 16, 2017
    Date of Patent: December 18, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Kuiwon Kang, Houssam Jomaa, Layal Rouhana, Seongryul Choi
  • Patent number: 10157813
    Abstract: A package includes a substrate having a conductive layer, and the conductive layer comprises an exposed portion. A die stack is disposed over the substrate and electrically connected to the conductive layer. A high thermal conductivity material is disposed over the substrate and contacting the exposed portion of the conductive layer. The package further includes a contour ring over and contacting the high thermal conductivity material.
    Type: Grant
    Filed: August 14, 2017
    Date of Patent: December 18, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wensen Hung, Szu-Po Huang, Hsiang-Fan Lee, Kim Hong Chen, Chi-Hsi Wu, Shin-Puu Jeng
  • Patent number: 10157850
    Abstract: A semiconductor package and a manufacturing method for the semiconductor package are provided. The semiconductor package has at least one die, conductive balls, and a molding compound. The at least one die and conductive balls are molded in a molding compound. Each of the conductive balls has a planar end portion and a non-planar end portion opposite to the planar end portion. A surface of the planar end portion of each of the conductive balls is substantially coplanar and levelled with a surface of the molding compound and a surface of the at least one die, and the non-planar end portion of each of the conductive balls protrudes from the molding compound.
    Type: Grant
    Filed: July 28, 2017
    Date of Patent: December 18, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Wei Wu, Jing-Cheng Lin, Szu-Wei Lu, Ying-Ching Shih
  • Patent number: 10157854
    Abstract: A package includes a device die, a molding material encircling the device die, wherein a top surface of the molding material is substantially level with a top surface of the device die, and a bottom dielectric layer over the device die and the molding material. A plurality of redistribution lines (RDLs) extends into the bottom dielectric layer and electrically coupling to the device die. A top polymer layer is over the bottom dielectric layer, with a trench ring penetrating through the top polymer layer. The trench ring is adjacent to edges of the package. The package further includes Under-Bump Metallurgies (UBMs) extending into the top polymer layer.
    Type: Grant
    Filed: March 29, 2018
    Date of Patent: December 18, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jie Chen, Hsien-Wei Chen
  • Patent number: 10154591
    Abstract: Passive device assembly for accurate ground plane control is disclosed. A passive device assembly includes a device substrate conductively coupled to a ground plane separation control substrate. A passive device disposed on a lower surface of the device substrate is separated from an embedded ground plane mounted on a lower surface of the ground plane separation control substrate by a separation distance. The separation distance is accurately controlled to minimize undesirable interference that may occur to the passive device. The separation distance is provided inside the passive device assembly. Conductive mounting pads are disposed on the lower surface of the ground plane separation control substrate to support accurate alignment of the passive device assembly on a circuit board. By providing sufficient separation distance inside the passive device assembly, the passive device assembly can be precisely mounted onto any circuit board regardless of specific design and layout of the circuit board.
    Type: Grant
    Filed: February 14, 2018
    Date of Patent: December 11, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Chengjie Zuo, David Francis Berdy, Daeik Daniel Kim, Changhan Hobie Yun, Mario Francisco Velez, Jonghae Kim
  • Patent number: 10147615
    Abstract: A method for fabricating a package structure is provided, which includes the steps of: forming a first insulating layer on a carrier; forming a dielectric body on the first insulating layer, wherein the dielectric body has a first surface formed on the first insulating layer and a second surface opposite to the first surface, and a circuit layer and a plurality of conductive posts formed on the circuit layer are embedded in the dielectric body; forming a second insulating layer on the second surface of the dielectric body, wherein the glass transition temperature of the first insulating layer and/or the second insulating layer is greater than 250° C.; and removing the carrier. Since the glass transition temperature of the first or second insulating layer is greater than that of the dielectric body, the package structure has a preferred strength to avoid warping, thereby dispensing with a support member.
    Type: Grant
    Filed: February 23, 2017
    Date of Patent: December 4, 2018
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventor: Yu-Cheng Pai
  • Patent number: 10147706
    Abstract: A multi-chip package includes a package substrate including a first substrate pad, a first group of semiconductor chips stacked on the package substrate, each of the first group of the semiconductor chips including bonding pads, first stud bumps arranged on the bonding pads of the first group of the semiconductor chips except for a lowermost semiconductor chip in the first group, a first conductive wire downwardly extended from the bonding pad of the lowermost semiconductor chip in the first group and connected to the first substrate pad, and a second conductive wire upwardly extended from the bonding pad of the lowermost semiconductor chip in the first group and sequentially connected to the first stud bumps.
    Type: Grant
    Filed: June 15, 2017
    Date of Patent: December 4, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Won-Gil Han, Byong-Joo Kim, Yong-Je Lee, Jae-Heung Lee, Seung-Weon Ha
  • Patent number: 10141280
    Abstract: Structures and formation methods of a package structure are provided. The package structure includes a semiconductor die and a substrate bonded to the semiconductor die through a first bonding structure and a second bonding structure therebetween. The first bonding structure and the second bonding structure are next to each other and the second bonding structure is wider than the first bonding structure. The first bonding structure has a first under bump metallurgy (UBM) structure and a first solder bump thereon, and the second bonding structure has a second UBM structure and a second solder bump thereon. The second UBM structure has a maximum width larger than that of the first UBM structure, and the second solder bump has a maximum width larger than that of the first solder bump.
    Type: Grant
    Filed: February 4, 2015
    Date of Patent: November 27, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Hsien-Wei Chen
  • Patent number: 10134699
    Abstract: An integrated circuit structure includes a substrate, a PPI over the substrate, a solder region over and electrically coupled to a portion of the PPI, and a molding compound molding a lower portion of the solder region therein. A top surface of the molding compound is level with or lower than a maximum-diameter plane, wherein the maximum-diameter plane is parallel to a major surface of the substrate, and the maximum-diameter of the solder region is in the maximum-diameter plane.
    Type: Grant
    Filed: January 16, 2017
    Date of Patent: November 20, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Hsiang Hu, Wei-Yu Chen, Ming-Da Cheng, Hung-Jui Kuo, Chung-Shi Liu
  • Patent number: 10128170
    Abstract: Conductive clip connection arrangements for semiconductor packages are disclosed. Some examples provide electrically conductive clip connection arrangements for semiconductor packages that improve electrical performance and fabrication reliability while maintaining compatibility with existing quality control processes. Some examples provide innovative conductive clip structures and die pad arrangements that broaden the range of options available for tailoring the physical configurations of one or more of the constituent conductive clips and/or die pads to achieve specific electrical performance targets.
    Type: Grant
    Filed: January 9, 2017
    Date of Patent: November 13, 2018
    Assignee: SILANNA ASIA PTE LTD
    Inventors: Stuart B. Molin, Laxminarayan Sharma
  • Patent number: 10128208
    Abstract: In some embodiments, a package substrate for a semiconductor device includes a substrate core and a material layer disposed over the substrate core. The package substrate includes a spot-faced aperture disposed in the substrate core and the material layer.
    Type: Grant
    Filed: March 12, 2018
    Date of Patent: November 13, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Hao-Cheng Hou, Yu-Feng Chen, Jung Wei Cheng, Yu-Min Liang, Tsung-Ding Wang
  • Patent number: 10115686
    Abstract: A method of fabricating a semiconductor structure includes: forming a conductive layer on a first insulating layer; etching a portion of the conductive layer to expose a portion of the first insulating layer; deforming a surface of the portion of the first insulating layer to form a rough surface of the first insulating layer; and removing a residue of the conductive layer on the rough surface of the first insulating layer.
    Type: Grant
    Filed: November 3, 2016
    Date of Patent: October 30, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Wei-Li Huang, Jheng-Jie Wong, Hsiang-Sheng Su, Tsung-Lung Huang, Kuo-Chio Liu, Hsin-Chieh Huang, De-Dui Marvin Liao, Chin-Yu Ku, Chen-Shien Chen
  • Patent number: 10115695
    Abstract: A solid-state imaging device encompasses a detector substrate having a first main-surface, on which a plurality of first lands are arranged in a matrix, and a signal-circuit substrate having a second main-surface, on which plurality of second lands are arranged so as to face the arrangement of the first lands. A plurality of tubular bumps, each of which having a flattened plane pattern, and is provided between each of the first lands and each of the second lands. The tubular bumps respectively have major-axis directions to define inclined angles, and are arranged in the matrix such that the inclined angles differ depending on locations of the plurality of tubular bumps.
    Type: Grant
    Filed: December 22, 2017
    Date of Patent: October 30, 2018
    Assignee: TOHOKU-MICROTEC CO., LTD
    Inventor: Makoto Motoyoshi
  • Patent number: 10115703
    Abstract: A semiconductor device includes a first semiconductor substrate, a second semiconductor substrate, a first metal layer located on the first semiconductor substrate, a second metal layer located on the second semiconductor substrate, a third metal layer, a first alloy layer, and a second alloy layer. The third metal layer extends between the first metal layer and the second metal layer. The first alloy layer comprises components of the first and third metal layers, and is provided between the first metal layer and the third metal layer. The second alloy layer comprises components of the second and third metal layers, and is provided between the second metal layer and the third metal layer. At least one of the first metal the second metal layers projects into the third metal layer at a circumferential edge portion thereof.
    Type: Grant
    Filed: March 3, 2016
    Date of Patent: October 30, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Tatsuo Migita, Koji Ogiso
  • Patent number: 10109572
    Abstract: A package structure is provided, which includes: a dielectric layer having opposite first and second surfaces; a first circuit layer embedded in the dielectric layer and having a surface exposed from the first surface of the dielectric layer; a plurality of conductive posts embedded in the dielectric layer and electrically connected to the first circuit layer and having one ends exposed from the second surface of the dielectric layer; a second circuit layer formed on the second surface of the dielectric layer and electrically connected the ends of the conductive posts exposed from the second surface of the dielectric layer; and a plurality of protruding elements formed on the surface of the first circuit layer exposed from the first surface of the dielectric layer, thereby providing a large contact area so as to strengthen bonding between a semiconductor chip and the first circuit layer of the package structure.
    Type: Grant
    Filed: December 19, 2016
    Date of Patent: October 23, 2018
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventor: Wei-Chung Hsiao
  • Patent number: 10090375
    Abstract: The invention provides a semiconductor structure. The semiconductor structure includes a substrate. A first passivation layer is disposed on the substrate. A conductive pad is disposed on the first passivation layer. A second passivation layer is disposed on the first passivation layer. A conductive structure is disposed on the conductive pad, and a passive device is also disposed on the conductive pad, wherein the passive device has a first portion located above the second passivation layer and a second portion passing through the second passivation layer. A solderability preservative film covers the first portion of the passive device, and an under bump metallurgy (UBM) layer covers the second portion of the passive device and a portion of the conductive structure.
    Type: Grant
    Filed: March 6, 2017
    Date of Patent: October 2, 2018
    Assignee: MEDIATEK INC.
    Inventors: Tzu-Hung Lin, Cheng-Chou Hung
  • Patent number: 10090278
    Abstract: A semiconductor package includes a plurality of semiconductor chips on a substrate. The semiconductor chips include a first semiconductor chip, a second semiconductor chip, and a third semiconductor chip that are sequentially stacked on the substrate. The semiconductor package further includes a plurality of non-conductive layers between the substrate and the first semiconductor chip and between adjacent semiconductor chips among the semiconductor chips. The semiconductor chips include smaller widths as a distance from the substrate increases. Each of the non-conductive layers includes an extension protruding outward from a side surface of an overlying one of the semiconductor chips.
    Type: Grant
    Filed: December 29, 2016
    Date of Patent: October 2, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-Sick Park, Geol Nam, Tae Hong Min, Jihwan Hwang
  • Patent number: 10079265
    Abstract: A display panel including a backplane, a first bonding layer, a plurality of micro light-emitting diodes, a first insulation layer, and a second bonding layer is provided. The first bonding layer is disposed on the backplane. The micro light-emitting diodes are disposed on the first bonding layer and are electrically connected to the first bonding layer. The first insulation layer is located between any adjacent two of the micro light-emitting diodes. The first insulation layer has a concave-convex surface. The second bonding layer is disposed on the micro light-emitting diodes and the first insulation layer and is electrically connected to the micro light-emitting diodes. A micro light-emitting diode apparatus including a substrate, a plurality of micro light-emitting diodes, and a first insulation layer is provided. The first insulation layer is located between any adjacent two of the micro light-emitting diodes. The first insulation layer has a concave-convex surface.
    Type: Grant
    Filed: July 25, 2017
    Date of Patent: September 18, 2018
    Assignee: PlayNitride Inc.
    Inventors: Chih-Ling Wu, Yu-Hung Lai, Yi-Min Su, Yu-Yun Lo, Tzu-Yang Lin
  • Patent number: 10049990
    Abstract: An integrated circuit structure includes a substrate, a metal pad over the substrate, a passivation layer having a portion over the metal pad, and a polymer layer over the passivation layer. A Post-Passivation Interconnect (PPI) has a portion over the polymer layer, wherein the PPI is electrically coupled to the metal pad. The integrated circuit structure further includes a first solder region over and electrically coupled to a portion of the PPI, a second solder region neighboring the first solder region, a first coating material on a surface of the first solder region, and a second coating material on a surface of the second solder region. The first coating material and the second coating material encircle the first solder region and the second solder region, respectively. The first coating material is spaced apart from the second coating material.
    Type: Grant
    Filed: March 7, 2014
    Date of Patent: August 14, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Chun Miao, Shih-Wei Liang, Kai-Chiang Wu
  • Patent number: 10043757
    Abstract: A semiconductor package structure and a method of fabricating the same are provided. The semiconductor package structure includes a package body having opposing first and second surfaces; a plurality of first conductive pads and a plurality of second conductive pads formed on the first surface of the package body; a semiconductor component embedded in the package body and electrically connected to the first conductive pads; and a plurality of conductive elements embedded in the package body, each of the conductive elements having a first end electrically connected to a corresponding one of the second conductive pads and a second end opposing the first end and exposed from the second surface of the package body. Since the semiconductor component is embedded in the package body, the thickness of the semiconductor package structure is reduced.
    Type: Grant
    Filed: May 10, 2015
    Date of Patent: August 7, 2018
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Yu-Cheng Pai, Wei-Chung Hsiao, Shih-Chao Chiu, Chun-Hsien Lin, Ming-Chen Sun, Tzu-Chieh Shen, Chia-Cheng Chen
  • Patent number: 10043740
    Abstract: Semiconductor packages with interconnects having passivation thereon is disclosed. The passivation layer may be any suitable dielectric material that may overlie a build-up dielectric layer and metal traces of an interconnect layer in a semiconductor package. Via holes may be formed in the build-up dielectric and the passivation layer may be removed from the bottom of the via hole. By removing the passivation layer at the bottom of the via hole, any residual build-up dielectric may also be removed from the bottom of the via hole. Thus removal of the residual build-up dielectric may not require a desmear process that would otherwise roughen metal and/or dielectric surfaces. The resulting smoother metal and/or dielectric surfaces enabled by the use of the passivation layer may allow greater process latitude and/or flexibility to fabricate relatively smaller dimensional interconnect features and/or relatively improved signaling frequency and integrity.
    Type: Grant
    Filed: July 12, 2016
    Date of Patent: August 7, 2018
    Assignee: Intel Coporation
    Inventors: Sri Ranga Sai Boyapati, Rahul N. Manepalli, Dilan Seneviratne, Srinivas V. Pietambaram, Kristof Darmawikarta, Robert Alan May, Islam A. Salama
  • Patent number: 10037975
    Abstract: A semiconductor device package including a first encapsulation layer, a redistribution layer disposed on the first encapsulation layer, a first die disposed on the redistribution layer, a second encapsulation layer covering the first die and the redistribution layer, and an electrical connection terminal electrically connected to the redistribution layer. The first encapsulation layer has a first surface and a second surface different from the first surface. The first encapsulation layer surrounds a portion of the electrical connection terminal and exposes the electrical connection terminal.
    Type: Grant
    Filed: August 11, 2017
    Date of Patent: July 31, 2018
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Wei-Ming Hsieh, Yu-Pin Tsai, Man-Wen Tseng
  • Patent number: 10037962
    Abstract: A package includes a first package component, a second package component over the first package component, and a solder region bonding the first package component to the second package component. At least one ball-height control stud separates the first package component and the second package component from each other, and defines a standoff distance between the first package component and the second package component.
    Type: Grant
    Filed: May 2, 2017
    Date of Patent: July 31, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsung-Yuan Yu, Hsien-Wei Chen, Jie Chen
  • Patent number: 10032719
    Abstract: A method of forming a semiconductor structure comprises forming pools of acidic or basic material in a substrate structure. A resist is formed over the pools of acidic or basic material and the substrate structure. The acidic or basic material is diffused from the pools into portions of the resist proximal to the pools more than into portions of the resist distal to the pools. Then, the resist is exposed to a developer to remove a greater amount of the resist portions proximal to the pools compared to the resist portions distal to the pools to form openings in the resist. The openings have wider portions proximal to the substrate structure and narrower portions distal to the substrate structure. The method may further comprise forming features in the openings of the resist. The features have wider portions proximal to the substrate structure and narrower portions distal to the substrate structure.
    Type: Grant
    Filed: May 26, 2017
    Date of Patent: July 24, 2018
    Assignee: Micron Technology Inc.
    Inventors: Adam L. Olson, Kaveri Jain, Lijing Gou, William R. Brown, Ho Seop Eom, Xue (Gloria) Chen, Anton J. deVilliers
  • Patent number: 10032662
    Abstract: Packaged semiconductor devices and methods of packaging thereof are disclosed. In some embodiments, a packaged semiconductor device includes a first device and a second device coupled to the first device. The second device includes an integrated circuit die covered by a molding compound. An over-mold structure is disposed over the second device.
    Type: Grant
    Filed: October 8, 2014
    Date of Patent: July 24, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Shu-Hang Liao, Ying-Ching Shih, Szu-Wei Lu, Jing-Cheng Lin
  • Patent number: 10032703
    Abstract: Package-on-package systems for packaging semiconductor devices. In one embodiment, a package-on-package system comprises a first semiconductor package device and a second semiconductor package device. The first package device includes a base substrate including a first side having a die-attach region and a peripheral region, a first semiconductor die attached to the base substrate at the die-attach region, wherein the first semiconductor die has a front side facing the first side of the base substrate and a backside spaced apart from the first side of the base substrate by a first distance, and a high density interconnect array in the perimeter region of the base substrate outside of the die-attach region. The interconnect array has a plurality of interconnects that extend from the first side of the base substrate by a second distance greater than the first distance. The second semiconductor device package is electrically coupled corresponding individual interconnects.
    Type: Grant
    Filed: August 5, 2016
    Date of Patent: July 24, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Owen R. Fay, Jack E. Murray
  • Patent number: 10032697
    Abstract: An electronic component package may include: a redistribution layer including a first insulating layer, a first conductive pattern disposed on the first insulating layer, and a first via connected to the first conductive pattern while penetrating through the first insulating layer; an electronic component disposed on the redistribution layer; and an encapsulant encapsulating the electronic component. The first via has a horizontal cross-sectional shape in which a distance between first and second edge points of the first via in a first direction passing through the center of the first via and the first and second edge points thereof is shorter than that between third and fourth edge points of the first via in a second direction perpendicular to the first direction and passing through the center of the first via and the third and fourth points thereof.
    Type: Grant
    Filed: July 6, 2016
    Date of Patent: July 24, 2018
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Han Kim, Young Gwan Ko, Kang Heon Hur, Kyung Moon Jung, Sung Han Kim
  • Patent number: 10008470
    Abstract: A method for manufacturing an embedded chip package is provided. The method may include: forming electrically conductive lines over a substrate; placing the substrate next to a chip arrangement comprising a chip, the chip comprising one or more contact pads, wherein one or more of the electrically conductive lines are arranged proximate to a side wall of the chip; and forming one or more electrical interconnects over the chip arrangement to electrically connect at least one electrically conductive line to at least one contact pad.
    Type: Grant
    Filed: June 21, 2017
    Date of Patent: June 26, 2018
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Gottfried Beer, Walter Hartner