Ball Shaped Patents (Class 257/738)
  • Patent number: 10707257
    Abstract: According to an aspect, a multi-chip packaging structure includes a first substrate having a first surface and a second surface, where the first substrate has a conductive layer portion. The multi-chip packaging structure includes an image sensor device coupled to the first surface of the first substrate, a first device coupled to the second surface of the first substrate, and a second substrate disposed apart from the first substrate, where the second substrate has a conductive layer portion. The conductive layer portion of the first substrate is communicatively connected to the conductive layer portion of the second substrate. The first device is disposed between the first substrate and the second substrate. The multi-chip packaging structure includes a second device coupled to the second substrate, and a third device coupled to the first substrate or the second substrate.
    Type: Grant
    Filed: August 14, 2018
    Date of Patent: July 7, 2020
    Assignee: Semiconductor Components Industries, LLC
    Inventor: Yu-Te Hsieh
  • Patent number: 10707150
    Abstract: A semiconductor device has a semiconductor package and an interposer disposed over the semiconductor package. The semiconductor package has a first semiconductor die and a modular interconnect unit disposed in a peripheral region around the first semiconductor die. A second semiconductor die is disposed over the interposer opposite the semiconductor package. An interconnect structure is formed between the interposer and the modular interconnect unit. The interconnect structure is a conductive pillar or stud bump. The modular interconnect unit has a core substrate and a plurality of vertical interconnects formed through the core substrate. A build-up interconnect structure is formed over the first semiconductor die and modular interconnect unit. The vertical interconnects of the modular interconnect unit are exposed by laser direct ablation. An underfill is deposited between the interposer and semiconductor package.
    Type: Grant
    Filed: July 9, 2018
    Date of Patent: July 7, 2020
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: Il Kwon Shim, Yaojian Lin, Pandi C. Marimuthu, Kang Chen, Yu Gu
  • Patent number: 10692832
    Abstract: A method for forming a semiconductor structure includes: providing a semiconductor substrate having a first pad and a second pad on a top surface of the semiconductor substrate; providing a circuit board having an active pad and a non-metallic surface; providing a first solder ball and a second solder ball on the active pad and the non-metallic surface respectively; attaching the first pad and the second pad on the first solder ball and the second solder ball respectively; and reflowing the first solder ball and the second solder ball to form a first bump wetted on the active pad and a second bump not wetted on the non-metallic surface.
    Type: Grant
    Filed: June 25, 2018
    Date of Patent: June 23, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chun-Lin Lu, Kai-Chiang Wu
  • Patent number: 10692813
    Abstract: A semiconductor device including an integrated circuit, a dielectric layer, a plurality of connecting terminals and at least one dummy conductor is provided. The integrated circuit has a plurality of connecting pads, and the dielectric layer is disposed thereon and partially exposes the plurality of the connecting pads by a plurality of openings defined therein. The plurality of the connecting terminals is disposed on the plurality of the connecting pads exposed by the plurality of the openings. The at least one dummy conductor is disposed on the dielectric layer and electrically isolated from the integrated circuit. A substantial topology variation is between the plurality of the connecting terminals and the at least one dummy conductor. A semiconductor package having the semiconductor device is also provided.
    Type: Grant
    Filed: January 5, 2017
    Date of Patent: June 23, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Feng-Cheng Hsu, Shin-Puu Jeng
  • Patent number: 10672737
    Abstract: Provided is a 3DIC structure includes a wafer, a die and a dielectric layer. The die is over and bonded to the wafer. The dielectric layer is over the wafer and aside the die, covering sidewalls of the die. A total thickness variation (TTV) of the die is less than 0.8 ?m.
    Type: Grant
    Filed: January 19, 2018
    Date of Patent: June 2, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yi-Hsiu Chen, Ebin Liao, Hong-Ye Shih, Wen-Chih Chiou, Jia-Ling Ko
  • Patent number: 10662056
    Abstract: A semiconductor device has a first semiconductor die and a modular interconnect structure adjacent to the first semiconductor die. An encapsulant is deposited over the first semiconductor die and modular interconnect structure as a reconstituted panel. An interconnect structure is formed over the first semiconductor die and modular interconnect structure. An active area of the first semiconductor die remains devoid of the interconnect structure. A second semiconductor die is mounted over the first semiconductor die with an active surface of the second semiconductor die oriented toward an active surface of the first semiconductor die. The reconstituted panel is singulated before or after mounting the second semiconductor die. The first or second semiconductor die includes a microelectromechanical system (MEMS). The second semiconductor die includes an encapsulant and an interconnect structure formed over the second semiconductor die.
    Type: Grant
    Filed: October 24, 2018
    Date of Patent: May 26, 2020
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: Yaojian Lin, Won Kyoung Choi, Kang Chen, Ivan Micallef
  • Patent number: 10665473
    Abstract: A package structure including a semiconductor die, a redistribution layer and a plurality of conductive elements is provided. At least one joint of the joints in the redistribution layer or on the semiconductor die is connected with the conductive element for electrically connecting the redistribution layer, the semiconductor die and the conductive elements.
    Type: Grant
    Filed: November 8, 2017
    Date of Patent: May 26, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chia-Hsiang Lin, Feng-Cheng Hsu, Shuo-Mao Chen, Shin-Puu Jeng, Arunima Banerjee
  • Patent number: 10658316
    Abstract: According to an aspect of the present disclosure, a semiconductor device is provided that includes a substrate, at least one bond pad, a passivation layer and a NBLoK layer. The bond pad is formed over the substrate. The passivation layer is deposited over the substrate and has an opening defined by end portions of the passivation layer over the bond pad. The NBLoK layer is covering the end portions of the passivation layer.
    Type: Grant
    Filed: October 2, 2018
    Date of Patent: May 19, 2020
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Xiaodong Li, Juan Boon Tan, Ramasamy Chockalingam
  • Patent number: 10636721
    Abstract: A semiconductor package includes a substrate including an antenna; a heating element disposed on a first surface of the substrate and connected to the antenna; a heat radiating part coupled to the heating element; and a signal transfer part disposed on the first surface of the substrate and configured to electrically connect the substrate to a main substrate. The heat radiating part may include a heat transfer part connected to the heating element and heat radiating terminals connecting the heat transfer part and the main substrate to each other.
    Type: Grant
    Filed: December 6, 2017
    Date of Patent: April 28, 2020
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Tae Hyun Kim, Jung Hyun Lim, Seung Goo Jang, Eun Kyoung Kim, Se Min Jin
  • Patent number: 10629507
    Abstract: A system in package is described comprising a substrate having a top side and a bottom side, having redistribution layers therein, and having a cavity extending partially into the top side of the substrate. At least one passive component is mounted on the top side of the substrate and into the cavity and embedded in a first molding compound. At least one silicon die is mounted on the bottom side of the substrate and embedded in a second molding compound wherein electrical connections are made between the at least one silicon die and the at least one passive component through the redistribution layers. Solder balls are mounted through openings in the second molding compound to the redistribution layers wherein the solder balls provide package output.
    Type: Grant
    Filed: November 23, 2018
    Date of Patent: April 21, 2020
    Assignee: Dialog Semiconductor (UK) Limited
    Inventors: Che-Han Jerry Li, Jesus Mennen Belonio, Jr., Ernesto Gutierrez, III, Shou Cheng Eric Hu
  • Patent number: 10622320
    Abstract: A semiconductor package may include a semiconductor chip; a molding portion configured to surround at least a side surface of the semiconductor chip; a passivation layer including a contact plug connected to the semiconductor chip and having a narrowing width further away from the semiconductor chip in a vertical direction, below the semiconductor chip; and a redistribution layer portion electrically connecting the semiconductor chip with an external connection terminal, below the passivation layer.
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: April 14, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jong-youn Kim, Seok-hyun Lee, Youn-ji Min, Kyoung-lim Suk, Seok-won Lee
  • Patent number: 10608158
    Abstract: A technique relates to a structure. An under-bump-metallization (UBM) structure includes a first region and a second region. The first and second regions are laterally positioned in the UBM structure. The first region includes a superconducting material. A substrate opposes the UBM structure. A superconducting solder material joins the first region to the substrate and the second region to the substrate.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: March 31, 2020
    Assignee: International Business Machines Corporation
    Inventors: David W. Abraham, John M. Cotte, Eric P. Lewandowski
  • Patent number: 10606316
    Abstract: A flexible electronic device that includes a flexible substrate having an upper surface and a lower surface and interconnects extending between the upper surface and the lower surface; a flexible display mounted directly to the upper surface of the flexible substrate such that the flexible display is electrically connected to the flexible substrate; a first encapsulant mounted to the upper surface of the flexible substrate such that the flexible display is at least partially embedded within the first encapsulant; an electronic component mounted to a lower surface of the flexible substrate such that the electronic component is electrically connected to the flexible substrate; a second encapsulant mounted to the lower surface of the flexible substrate such that the electronic component is at least partially embedded within the second encapsulant; a flexible casing that surrounds the electronic component and the second encapsulant.
    Type: Grant
    Filed: December 10, 2015
    Date of Patent: March 31, 2020
    Assignee: Intel Corporation
    Inventors: Jackson Chung Peng Kong, Kooi Chi Ooi, Bok Eng Cheah, Eng Huat Goh
  • Patent number: 10600932
    Abstract: A manufacturing method of an optoelectronic semiconductor device includes: providing a matrix substrate, which comprises a substrate and a matrix circuit disposed on the substrate; transferring a plurality of micro-sized optoelectronic semiconductor elements from a temporary substrate to the matrix substrate, wherein the micro-sized optoelectronic semiconductor elements are separately disposed on the matrix substrate, and at least one electrode of each micro-sized optoelectronic semiconductor element is electrically connected with the matrix circuit; forming a protective layer completely covering the micro-sized optoelectronic semiconductor elements, wherein the height of the protective layer is greater than the height of the micro-sized optoelectronic semiconductor elements; and grinding the protective layer until a residual on a back surface of each micro-sized optoelectronic semiconductor element and the back surface are removed to expose a new surface.
    Type: Grant
    Filed: March 4, 2019
    Date of Patent: March 24, 2020
    Assignee: ULTRA DISPLAY TECHNOLOGY CORP.
    Inventor: Hsien-Te Chen
  • Patent number: 10593641
    Abstract: A packaging method and a package structure of a fan-out chip are disclosed. The package structure comprises a first chip with bumps and a second chip without bumps, a first dielectric layer formed on a surface of the second chip and through-holes fabricated in the first dielectric layer; a plastic package material; a second dielectric layer; a metal redistribution layer for interconnecting within and between the first chip and the second chip; under bump metallization layers and micro-bumps. By fabricating the dielectric layers with the through-holes on the surfaces of the first chip and the second chip, exposing the bumps of the first chip and metal pads of the second chip and subsequently fabricating the metal redistribution layer, the interconnections within and between the first chip and the second chip are achieved and thereby the integrated package of the first chip and the second chip is achieved.
    Type: Grant
    Filed: May 20, 2016
    Date of Patent: March 17, 2020
    Assignee: SJ SEMICONDUCTOR (JIANGYIN) CORPORATION
    Inventors: Yuedong Qiu, Chengchung Lin
  • Patent number: 10588214
    Abstract: A stacked structure includes a circuit board, an electronic component, metallic cores, and insulating cladding layers. The circuit board includes first bonding pads. The electronic component includes second bonding pads that are opposite to the first bonding pads. Each metallic core is connected to a corresponding first bonding pad and a corresponding second bonding pad. The metallic cores have a curved surface interposed between the corresponding first bonding pad and the corresponding second bonding pad. The insulating cladding layers are separated from each other and cover the curved surfaces of the metallic cores.
    Type: Grant
    Filed: August 18, 2019
    Date of Patent: March 10, 2020
    Assignee: UNIMICRON TECHNOLOGY CORP.
    Inventors: Tzyy-Jang Tseng, Kai-Ming Yang, Pu-Ju Lin, Cheng-Ta Ko, Yu-Hua Chen
  • Patent number: 10580950
    Abstract: Disclosed herein is a light emitting device manufactured by separating a growth substrate in a wafer level. The light emitting device includes: a base; a light emitting structure disposed on the base; and a plurality of second contact electrodes disposed between the base and the light emitting structure, wherein the base includes at least two bulk electrodes electrically connected to the light emitting structure and an insulation support disposed between the bulk electrodes and enclosing the bulk electrodes, the insulation support and the bulk electrodes each including concave parts and convex parts engaged with each other on surfaces facing each other, and the convex parts including a section in which a width thereof is changed in a protrusion direction.
    Type: Grant
    Filed: April 16, 2018
    Date of Patent: March 3, 2020
    Assignee: SEOUL VIOSYS CO., LTD.
    Inventors: Jong Hyeon Chae, Chang Yeon Kim, Sung Su Son, Dae Woong Suh
  • Patent number: 10573580
    Abstract: Apparatus and method associated with surface structures of compute component packages are disclosed herein. In embodiments, an apparatus may include a plurality of structures provided on a surface of a compute component package, wherein the plurality of structures are to be used to attach and electrically couple the compute component package to another device, and wherein a structure of the plurality of structures includes first and second portions, the second portion disposed further from the surface than the first portion, and the first portion to comprise a material different from the second portion.
    Type: Grant
    Filed: March 31, 2017
    Date of Patent: February 25, 2020
    Assignee: Intel Corporation
    Inventors: Srinivasa R. Aravamudhan, Christopher D. Combs
  • Patent number: 10559547
    Abstract: A semiconductor chip includes a semiconductor substrate having a main surface, first and second electrodes, a first insulating layer, and first and second bumps. The first and second electrodes are formed above the main surface of the semiconductor substrate. The first insulating layer is formed above a first portion of the first electrode. The first bump is formed above a second portion of the first electrode and above the first insulating layer and is electrically connected to the first electrode. The second bump is formed above the second electrode. The area of the second bump is larger than that of the first bump in a plan view of the main surface of the semiconductor substrate. The first insulating layer adjusts the distance from the main surface of the semiconductor substrate to the top surface of the first bump in a direction normal to the main surface.
    Type: Grant
    Filed: June 12, 2018
    Date of Patent: February 11, 2020
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Masahiro Shibata, Daisuke Tokuda, Atsushi Kurokawa, Hiroaki Tokuya, Yasunari Umemoto
  • Patent number: 10546828
    Abstract: Embodiments relate to an apparatus for rework of a BGA package. Memory shape material is placed adjacent to a plurality of solder joints of the package. Stimulation is applied to the material, with the stimulation causing the material to change from a non-stimulated shape to a stimulated shape. This stimulation causes an expansion of the material. As the material expands, it exerts a tensile force on the BGA package and an adjacently positioned carrier, causing a separation of the two components, while mitigating collateral heat of adjacently positioned components.
    Type: Grant
    Filed: February 27, 2018
    Date of Patent: January 28, 2020
    Assignee: International Business Machines Corporation
    Inventors: Eric V. Kline, Arvind K. Sinha
  • Patent number: 10541198
    Abstract: A method of manufacturing a semiconductor package includes: (a) providing a carrier; (b) disposing a dielectric layer and a conductive pad on the carrier; (c) disposing a redistribution layer on the dielectric layer to electrically connect to the conductive pad; (d) connecting a die to the redistribution layer; (e) removing at least a portion of the carrier to expose the conductive pad; and (f) disposing an electrical contact to electrically connect to the conductive pad.
    Type: Grant
    Filed: January 30, 2018
    Date of Patent: January 21, 2020
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Chien Lin Chang Chien, Chin-Li Kao, Chang Chi Lee, Chih-Pin Hung
  • Patent number: 10541154
    Abstract: A method of forming a semiconductor package includes providing a substrate, wherein the substrate has at least one chip attached on an upper surface of the substrate. An insulating barrier layer is deposited above the substrate, wherein the at least one chip is at least partially embedded within the insulating barrier layer. A thermally conductive layer is formed over the insulating barrier layer to at least partially encapsulate the at least one chip.
    Type: Grant
    Filed: January 30, 2017
    Date of Patent: January 21, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chun-Hao Tseng, Ying-Hao Kuo, Kuo-Chung Yee
  • Patent number: 10541220
    Abstract: Described examples provide integrated circuits and methods, including forming a conductive seed layer at least partially above a conductive feature of a wafer, forming a conductive structure on at least a portion of the conductive seed layer, performing a printing process that forms a polymer material on a side of the wafer proximate a side of the conductive structure, curing the deposited polymer material, and attaching a solder ball structure to a side of the conductive structure.
    Type: Grant
    Filed: August 2, 2018
    Date of Patent: January 21, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Daiki Komatsu, Makoto Shibuya, Yi Yan, Hau Nguyen, Luu Thanh Nguyen, Anindya Poddar
  • Patent number: 10535536
    Abstract: A wafer level fan out package includes a semiconductor die having a first surface, a second surface, and a third surface. A stiffener is disposed on the third surface of the semiconductor die. A conductive via passes through the stiffener. First and second electrically conductive patterns electrically connected to the conductive via are disposed on the first and second surfaces of the semiconductor die and stiffener. Solder balls are electrically connected to the first or second electrically conductive patterns.
    Type: Grant
    Filed: March 5, 2019
    Date of Patent: January 14, 2020
    Assignee: Amkor Technology, Inc.
    Inventors: Jin Young Kim, Doo Hyun Park, Seung Jae Lee
  • Patent number: 10529698
    Abstract: An embodiment is a package including a first package structure. The first package structure includes a first integrated circuit die having an active side and a back-side, the active side comprising die connectors, a first electrical connector adjacent the first integrated circuit die, an encapsulant laterally encapsulating the first integrated circuit die and the first electrical connector, a first redistribution structure on and electrically connected to the die connectors of the first integrated circuit die and the first electrical connector, and thermal elements on the back-side of the first integrated circuit die. The package further includes a second package structure bonded to the first electrical connector and the thermal elements with a first set of conductive connectors.
    Type: Grant
    Filed: September 1, 2017
    Date of Patent: January 7, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Der-Chyang Yeh, Han-Ping Pu
  • Patent number: 10522451
    Abstract: A fan-out semiconductor package includes: a first connection member having a through-hole; a semiconductor chip disposed in the through-hole of the first connection member and having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface; an encapsulant encapsulating at least portions of the first connection member and the inactive surface of the semiconductor chip; a second connection member disposed on the first connection member and the active surface of the semiconductor chip; and a heat dissipation layer embedded in the encapsulant so that one surface thereof is exposed. The first connection member and the second connection member include, respectively, redistribution layers electrically connected to the connection pads of the semiconductor chip.
    Type: Grant
    Filed: July 13, 2018
    Date of Patent: December 31, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Da Hee Kim, Young Gwan Ko, Sung Won Jeong
  • Patent number: 10515825
    Abstract: A method for manufacturing a semiconductor device and a semiconductor device produced thereby. For example and without limitation, various aspects of this disclosure provide methods for manufacturing a semiconductor device, and semiconductor devices produced thereby, that comprise forming an interposer including a reinforcement layer.
    Type: Grant
    Filed: September 18, 2018
    Date of Patent: December 24, 2019
    Assignee: Amkor Technology, Inc.
    Inventors: Jong Sik Paek, Doo Hyun Park, Seong Min Seo, Sung Geun Kang, Yong Song, Wang Gu Lee, Eun Young Lee, Seo Yeon Ahn, Pil Je Sung
  • Patent number: 10514535
    Abstract: An image pickup unit of an embodiment includes: a first substrate on which an image pickup device is mounted; a first intermediate wiring board including a first wire, one end of the first wire electrically connected to the first substrate, the other end of the first wire including a first electrode pad; a second substrate on which an electronic component is mounted; and a second intermediate wiring board including a second wire, one end of the second wire electrically connected to the second substrate, and the other end of the second wire including a second electrode pad, wherein the first electrode pad and the second electrode pad coming into close contact and fixed in an electrically connected state are bent and deformed.
    Type: Grant
    Filed: January 10, 2017
    Date of Patent: December 24, 2019
    Assignee: OLYMPUS CORPORATION
    Inventor: Takuro Suyama
  • Patent number: 10510647
    Abstract: A semiconductor package includes an organic interposer, a semiconductor chip, a passivation layer, and an underbump metallurgy (UBM) layer. The organic interposer includes insulating layers and wiring layers disposed on the insulating layers. The semiconductor chip is disposed on one surface of the organic interposer. The passivation layer is disposed on another surface of the organic interposer opposing the one surface on which the semiconductor chip is disposed, and has openings extending to portions of the wiring layer. The UBM layer includes UBM pads disposed on the passivation layer and UBM vias disposed in the openings and connecting the UBM pads and the wiring layer to each other. At least one groove portion is disposed in an outer circumferential surface of the UBM pad.
    Type: Grant
    Filed: April 2, 2018
    Date of Patent: December 17, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Jee Ae Heo
  • Patent number: 10510734
    Abstract: An embodiment package includes a first package. The first package includes a first integrated circuit die, an encapsulant around the first integrated circuit die, and redistribution layers over the encapsulant and the first integrated circuit die. The package also includes a second package bonded to the first package by a plurality of functional connectors. The functional connectors and the redistribution layers electrically connect a second integrated circuit die of the second package to the first integrated circuit die. The package also includes a plurality of dummy connectors disposed between the first package and the second package. One end of each of the plurality of dummy connectors facing the first package is physically separated from the first package.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: December 17, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Shien Chen, Hsiu-Jen Lin, Ming-Chih Yew, Ming-Da Cheng, Yi-Jen Lai, Yu-Tse Su, Sey-Ping Sun, Yang-Che Chen
  • Patent number: 10510631
    Abstract: A package structure and a method of manufacturing the same are provided. The package structure includes a die, a redistribution layer (RDL) structure, a through integrated fan-out via (TIV) and a first connector. The RDL structure is connected to the die and includes a plurality of RDLs. The TIV is aside the die and penetrates through the RDL structure. The first connector is in electrical contact with the TIV and electrically connected to the die. The TIV is in electrical contact with the RDLs of the RDL structure.
    Type: Grant
    Filed: September 18, 2017
    Date of Patent: December 17, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Hsuan Tai, Chih-Hua Chen, Hao-Yi Tsai, Yu-Chih Huang, Chia-Hung Liu, Ting-Ting Kuo
  • Patent number: 10510648
    Abstract: A method comprises embedding a semiconductor structure in a molding compound layer, depositing a plurality of photo-sensitive material layers over the molding compound layer, developing the plurality of photo-sensitive material layers to form a plurality of openings, wherein a first portion and a second portion of an opening of the plurality of openings are formed in different photo-sensitive material layers and filling the first portion and the second portion of the opening with a conductive material to form a first via in the first portion and a first redistribution layer in the second portion.
    Type: Grant
    Filed: December 18, 2018
    Date of Patent: December 17, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tzu-Wei Chiu, Sao-Ling Chiu
  • Patent number: 10504863
    Abstract: BGA packages with a spatially varied ball height, molds and techniques to form such packages. A template or mold with cavities may be pre-fabricated to hold solder paste material applied to the mold, for example with a solder paste printing process. The depth and/or diameter of the cavities may be predetermined as a function of spatial position within the mold working surface area. Mold cavity dimensions may be specified corresponding to package position to account for one or more pre-existing or expected spatial variations in the package, such as a package-level warpage measurement. Any number of different ball heights may be provided. The molds may be employed in a standardize process that need not be modified with each change in the mold.
    Type: Grant
    Filed: November 21, 2018
    Date of Patent: December 10, 2019
    Assignee: Intel Corporation
    Inventors: Eric J. Li, Jimin Yao, Shawna M. Liff
  • Patent number: 10504874
    Abstract: Semiconductor package structures and methods of forming the same are provided. An interposer is bonded to a printed circuit board (PCB) or package substrate through first solder bumps disposed on a first side of the interposer. The first solder bumps have a first pitch. A plurality of semiconductor chips are formed, and each of the semiconductor chips is bonded to a second side of the interposer through second solder bumps. The second solder bumps have a second pitch that is less than the first pitch. Each of the semiconductor chips includes a substrate with one or more transistors or integrated circuits formed thereon.
    Type: Grant
    Filed: August 1, 2016
    Date of Patent: December 10, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Chan-Hong Chern, Mark Chen
  • Patent number: 10490506
    Abstract: A packaged chip, including a package structure, a redistribution structure, and a carrier, where the package structure includes a first chip and a second chip adjacent to the first chip. The redistribution structure is configured to electrically connect the first chip and the carrier, and is configured to electrically connect the second chip and the carrier. The redistribution structure includes a main body made of an insulating material and a bump solder array welded to a lower surface of the main body. A metal redistribution wire group and a metal interconnection wire group that has a curve or bend design are disposed in the main body. An upper surface of the main body of the redistribution structure adheres to a lower surface of the first chip and a lower surface of the second chip. The redistribution structure is welded to an upper surface of the carrier.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: November 26, 2019
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Chih Chiang Ma, Jyh Rong Lin, Xiaodong Zhang
  • Patent number: 10483241
    Abstract: A semiconductor device assembly includes a substrate and a die coupled to the substrate, the die including a first contact pad electrically coupled to a first circuit on the die including an active circuit element, a first TSV electrically coupling the first contact pad to a first backside contact pad, and a second contact pad electrically coupled to a second circuit including only passive circuit elements. The substrate includes a substrate contact electrically coupled to the first and second contact pads. The assembly can further include a second die including a third contact pad electrically coupled to a third circuit including a second active circuit element, and a fourth contact pad electrically coupled to a fourth circuit on the second die including only passive circuit elements. The substrate contact can be electrically coupled to the third contact pad, but electrically disconnected from the fourth contact pad.
    Type: Grant
    Filed: June 27, 2018
    Date of Patent: November 19, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Kevin G. Duesman, James E. Davis, Warren L. Boyer
  • Patent number: 10475747
    Abstract: An integrated fan-out package includes an integrated circuit, a plurality of semiconductor devices, a first redistribution circuit structure, and an insulating encapsulation. The integrated circuit has an active surface and a rear surface opposite to the active surface. The semiconductor devices are electrically connected the integrated circuit. The first redistribution circuit structure is disposed between the integrated circuit and the semiconductor devices. The first redistribution circuit structure is electrically connected to the integrated circuit and the semiconductor devices respectively. The first redistribution circuit structure has a first surface, a second surface opposite to the first surface, and lateral sides between the first surface and the second surface. The insulating encapsulation encapsulates the integrated circuit and the semiconductor devices and covers the first surface and the second surface of the first redistribution circuit structure.
    Type: Grant
    Filed: August 14, 2017
    Date of Patent: November 12, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chen-Hua Yu, Chun-Hui Yu, Kuo-Chung Yee
  • Patent number: 10475760
    Abstract: A semiconductor device includes a substrate including a surface, a plurality of pads disposing on the surface of the substrate, the plurality of pads includes a non-solder mask defined (NSMD) pad and a solder mask defined (SMD) pad, and the NSMD pad is arranged at a predetermined location. Further, a method of manufacturing a semiconductor device includes providing a substrate, disposing a plurality of pads on a surface of the substrate, disposing a solder mask over the surface of the substrate and the plurality of pads, forming a first recess in the solder mask to surround one of the plurality of pads, and forming a second recess in the solder mask and above one of the plurality of pads.
    Type: Grant
    Filed: November 27, 2017
    Date of Patent: November 12, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Jie Chen, Ying-Ju Chen, Hsien-Wei Chen, Tsung-Yuan Yu
  • Patent number: 10453788
    Abstract: A fan-out semiconductor package includes: a frame including insulating layers, wiring layers disposed on the insulating layers, and connection via layers penetrating through the insulating layers and electrically connecting the wiring layers to each other, and having a recess portion; a semiconductor chip having connection pads and disposed in the recess portion so that an inactive surface is connected to the stopper layer; an encapsulant covering at least portions of the semiconductor chip and filling at least portions of the recess portion; and a connection member disposed on the frame and an active surface of the semiconductor chip and including one or more redistribution layers electrically connecting the wiring layers and the connection pads to each other, in which the recess portion includes walls having different inclined angles.
    Type: Grant
    Filed: May 24, 2018
    Date of Patent: October 22, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jeong II Lee, Jeong Ho Lee, Jin Su Kim, Bong Ju Cho
  • Patent number: 10454048
    Abstract: Disclosed is a flexible display device in which a flexible film is first patterned and in a subsequent process of removing a glass substrate, a structure around the flexible film is removed therewith by external physical force, in order to make the device slim. In the flexible display device, the edge structure of the flexible film may be changed to minimize the generation of particles on the cut plane of the flexible film, thereby preventing damage to the periphery of the flexible film.
    Type: Grant
    Filed: August 30, 2017
    Date of Patent: October 22, 2019
    Assignee: LG Display Co., Ltd.
    Inventor: Hae-Yeon Jeong
  • Patent number: 10446524
    Abstract: A packaged module for use in a wireless communication device has a substrate supporting a crystal and a first die that includes at least a microprocessor and one or more of radio frequency transmitter circuitry and radio frequency receiver circuitry. The first die is disposed between the crystal and the substrate. An overmold encloses the first die and the crystal. The substrate also supports a second die that includes at least a power amplifier for amplifying a radio frequency input signal, where the second die is disposed on an opposite side of the substrate from the first die and the crystal.
    Type: Grant
    Filed: July 27, 2018
    Date of Patent: October 15, 2019
    Assignee: Skyworks Solutions, Inc.
    Inventors: Darren Roger Frenette, George Khoury, Leslie Paul Wallis
  • Patent number: 10440826
    Abstract: A semiconductor device includes a mounting substrate including an interface, which is connectable with a host, a surface-mounted component mounted on the mounting substrate and having first and second electrode groups, a first solder portion that is positioned between a first electrode in the first electrode group and the mounting substrate to electrically connect the first electrode and the mounting substrate, and a second solder portion that is positioned between a second electrode in the second electrode group and the mounting substrate to electrically connect the second electrode and the mounting substrate. The second solder portion has a larger contact area with the mounting substrate than the first solder portion. The second solder portion is positioned between at least one additional second electrode in the second electrode group to electrically connect the at least one additional second electrode and the mounting substrate.
    Type: Grant
    Filed: September 4, 2017
    Date of Patent: October 8, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Daisuke Kimura
  • Patent number: 10431561
    Abstract: A pre-conductive array disposed on a target circuit substrate comprises a plurality of conductive electrode groups disposed on the target circuit substrate, and at least a conductive particle dispose on each of conductive electrodes of a part or all of the conductive electrode groups. The at least a conductive particle and the corresponding conductive electrode form a pre-conductive structure, and the pre-conductive structures form the pre-conductive array.
    Type: Grant
    Filed: September 20, 2018
    Date of Patent: October 1, 2019
    Assignee: ULTRA DISPLAY TECHNOLOGY CORP.
    Inventor: Hsien-Te Chen
  • Patent number: 10424525
    Abstract: An assembly is provided including one or more semiconductor dice attached on a substrate, the semiconductor die provided with electrically-conductive stud bumps opposite the substrate. The stud bumps embedded in a molding compound molded thereon are exposed to grinding thus leveling the molding compound to expose the distal ends of the stud bumps at a surface of the molding compound. Recessed electrically-conductive lines extending over said surface of the molding compound with electrically-conductive lands over the distal ends of the stud bumps. A further molding compound is provided to cover the recessed electrically-conductive lines and surrounding the electrically-conductive lands.
    Type: Grant
    Filed: May 23, 2018
    Date of Patent: September 24, 2019
    Assignee: STMicroelectronics S.r.l.
    Inventor: Federico Giovanni Ziglioli
  • Patent number: 10418339
    Abstract: The present disclosure relates to a method for bonding semiconductor components. A semiconductor component comprising microbumps on a planar bonding surface is prepared for bonding by applying a photosensitive polymer layer on the bonding surface. The average thickness of the initial polymer layer in between the microbumps is similar to the average height of the microbumps. In a lithography process, the polymer is removed from the upper surface of the microbumps and from areas around the microbumps. The polymer is heated to a temperature at which the polymer flows, resulting in a polymer layer that closely adjoins the microbumps, without exceeding the microbump height. The closely adjoining polymer layer may have a degree of planarity substantially similar to a planarized layer.
    Type: Grant
    Filed: June 27, 2018
    Date of Patent: September 17, 2019
    Assignee: IMEC VZW
    Inventors: Fabrice Duval, Fumihiro Inoue
  • Patent number: 10410685
    Abstract: A memory device includes a memory cell array having a plurality of memory cell groups with a corresponding plurality of independent channels, and the device and an operating method thereof perform an internal data processing operation for the memory cell groups. The memory device includes an internal command generator configured to generate one or more internal commands in order to perform an internal data processing operation in response to a reception of a command, and an internal common bus for a common internal processing channel which is disposed to be shared by the plurality of memory cell groups and configured to form a transmission path of data between the plurality of memory cell groups when the internal data processing operation is performed.
    Type: Grant
    Filed: March 5, 2019
    Date of Patent: September 10, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Reum Oh, Je-Min Ryu, Pavan Kumar Kasibhatla
  • Patent number: 10412838
    Abstract: There is provided a conductive particle including a core particle containing a resin material, and a surface layer that covers a surface of the core particle and contains a solder material, in which a melting point of the solder material is equal to or lower than a softening point of the resin material.
    Type: Grant
    Filed: May 1, 2017
    Date of Patent: September 10, 2019
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Arata Kishi, Hiroki Maruo
  • Patent number: 10410963
    Abstract: An electric device includes a first structure, a second structure, and a deformed layer. The deformed layer includes a dielectric matrix and electrically conductive elements formed therein. The deformed layer is arranged to electrically couple the first structure with the second structure.
    Type: Grant
    Filed: June 7, 2018
    Date of Patent: September 10, 2019
    Assignee: AT&S Austria Technologie & Systemtechnik Aktiengesellschaft
    Inventors: Gerald Weis, Hannes Voraberger
  • Patent number: 10403674
    Abstract: Device and method of forming the devices are disclosed. The method includes providing a substrate prepared with transistor and sensor regions. The substrate is processed by forming a lower sensor cavity in the substrate, filling the lower sensor cavity with a sacrificial material, forming a dielectric membrane in the sensor region, forming a transistor in the transistor region and forming a micro-electrical mechanical system (MEMS) component on the dielectric membrane in the sensor region. The method continues by forming a back-end-of-line (BEOL) dielectric having a plurality of interlayer dielectric (ILD) layers with metal and via levels disposed on the substrate for interconnecting the components of the device. The metal lines in the metal levels are configured to define an upper sensor cavity over the lower sensor cavity, and metal lines of a first metal level of the BEOL dielectric are configured to define a geometry of the MEMS component.
    Type: Grant
    Filed: July 12, 2017
    Date of Patent: September 3, 2019
    Assignee: Meridian Innovation Pte Ltd
    Inventors: Piotr Kropelnicki, Ilker Ender Ocak, Paul Simon Pontin
  • Patent number: 10396036
    Abstract: A vertically ground isolated package device can include (1) ground shielding attachment structures and shadow voiding for data signal contacts; (2) vertical ground shielding structures and shield fencing of vertical data signal interconnects; and (3) ground shielding for an electro-optical module connector of the package device. These reduce cross talk between data signal contacts, attachment structures and vertical “signal” interconnects of the package device. The ground shielding attachment structures may include patterns of solder bumps and/or surface contacts. The shadow voiding may be surrounding voids in ground planes that are larger than the data signal solder bumps. The vertical ground shielding structures may include patterns of ground shield interconnects between the vertical data signal interconnects: The shield fencing may include patterns of ground plated through holes (PTH) and micro-vias (uVia).
    Type: Grant
    Filed: December 26, 2015
    Date of Patent: August 27, 2019
    Assignee: Intel Corporation
    Inventors: Yu Amos Zhang, Zhiguo Qian, Kemal Aygun, Yidnekachew S. Mekonnen, Gregorio R. Murtagian, Sanka Ganesan, Eduard Roytman, Jeff C. Morriss