Bump Leads Patents (Class 257/737)
  • Patent number: 10319655
    Abstract: A device includes a bottom package component that includes a bottom die, and a dam over a top surface of the bottom die. The dam has a plurality of sides forming a partial ring, with an air gap surrounded by the plurality of side portions. The air gap overlaps the bottom die. A top package component is bonded to the bottom package component, wherein the air gap separates a bottom surface of the top package component from the bottom die.
    Type: Grant
    Filed: May 2, 2017
    Date of Patent: June 11, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Tsung-Ding Wang, Chen-Shien Chen, Chung-Shi Liu, Jiun Yi Wu
  • Patent number: 10319694
    Abstract: A semiconductor device according to some examples of the disclosure may include a package substrate, a semiconductor die coupled to one side of the package substrate with a first set of contacts on an active side of the semiconductor die and coupled to a plurality of solder prints with a second set of contacts on a back side of the semiconductor die. The semiconductor die may include a plurality of vias connecting the first set of contacts to the second set of contacts and configured to allow heat to be transferred from the active side of the die to the plurality of solder prints for a shorter heat dissipation path.
    Type: Grant
    Filed: August 10, 2016
    Date of Patent: June 11, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Daniel Daeik Kim, Jie Fu, Manuel Aldrete, Jonghae Kim, Changhan Hobie Yun, David Francis Berdy, Chengjie Zuo, Mario Francisco Velez
  • Patent number: 10319608
    Abstract: A package structure can include: (i) a substrate having opposite first and second surfaces; (ii) a die having opposite active and back surfaces, where the die is arranged above the first surface of the substrate, the back surface of the die is adjacent to the first surface of the substrate; (iii) pads arranged on the active surface of the die; (iv) a first encapsulator configured to encapsulate the die; (v) an interconnection structure configured to electrically connect to the pads through the first encapsulator; (vi) a second encapsulator configured to encapsulate the interconnection structure; and (vii) a redistribution structure configured to electrically connect to the interconnection structure and to provide external electrical connectivity.
    Type: Grant
    Filed: June 8, 2016
    Date of Patent: June 11, 2019
    Assignee: Silergy Semiconductor Technology (Hangzhou) LTD
    Inventor: Xiaochun Tan
  • Patent number: 10308504
    Abstract: A method of manufacturing and using micro assembler systems are described. A method of manufacturing includes disposing a first plurality of electrodes above a first zone of the substrate, wherein the first plurality of electrodes has a first range of spacing. The method further includes disposing a second plurality of electrodes above a second zone of the substrate, wherein the second plurality of electrodes has a second range of spacing that is less than the first range of spacing. A method of using micro assembler systems includes disposing a mobile particle at least partially submersed in an assembly medium above a substrate, a first plurality of electrodes and a second plurality of electrodes. The method further includes conducting a field through individual electrodes of the first plurality of electrodes and the second plurality of electrodes to generate electrophoretic forces or dielectrophoretic forces on the mobile particle.
    Type: Grant
    Filed: March 31, 2017
    Date of Patent: June 4, 2019
    Assignee: Palo Alto Research Center Incorporated
    Inventors: Jeng Ping Lu, Eugene M. Chow, David K. Biegelsen, Sourobh Raychaudhuri
  • Patent number: 10312220
    Abstract: A semiconductor package structure and a method for making a semiconductor package. As non-limiting examples, various aspects of this disclosure provide various semiconductor package structures, and methods for making thereof, that comprise a connect die that routes electrical signals between a plurality of other semiconductor die.
    Type: Grant
    Filed: September 18, 2017
    Date of Patent: June 4, 2019
    Assignee: Amkor Technology, Inc.
    Inventors: David Hiner, Michael Kelly, Ronald Huemoeller
  • Patent number: 10305008
    Abstract: A semiconductor module includes: one or more semiconductor elements; a wiring substrate having a first surface on which the one or more semiconductor elements are mounted, the wiring substrate being electrically connected to the one or more semiconductor elements; a heat sink on which the wiring substrate is mounted, the heat sink facing a second surface of the wiring substrate on a reverse side of the first surface; a binder which is formed in a die pad area on the heat sink so as to be present between the wiring substrate and the heat sink, and bonds the wiring substrate and the heat sink; and a support which is formed in a peripheral part of the die pad area on the heat sink, and fixes the wiring substrate to the heat sink by being in contact with a peripheral part of the second surface of the wiring substrate.
    Type: Grant
    Filed: October 18, 2017
    Date of Patent: May 28, 2019
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Takeshi Kawabata, Kiyomi Hagihara, Satoshi Kanai, Takashi Yui
  • Patent number: 10303311
    Abstract: Provided are a touch-panel that is capable of reliably electrically connecting a terminal-portion and a flexible-printed-circuit board even in a case in which a groove formed in a resin layer is not completely filled with a conductive material in the terminal-portion and a method for manufacturing the touch-panel. A touch-panel includes a plurality of first terminal-portions that are provided so as to correspond to a plurality of first detection electrodes. The first terminal-portion includes a first resin layer that is provided on a first substrate and has a first terminal groove formed therein and a first conductive material that fills the first terminal groove. First conductive connection portions each of which comes into contact with the first conductive material of the first terminal-portion and covers at least a portion of the outer surface of the first resin layer are provided in a plurality of first terminal portions so as to be separated from each other.
    Type: Grant
    Filed: October 5, 2016
    Date of Patent: May 28, 2019
    Assignee: FUJIFILM Corporation
    Inventors: Masaya Nakayama, Hiroyuki Kobayashi
  • Patent number: 10306772
    Abstract: An adhesive film including a substrate film and an adhesive agent layer formed thereon is adhered to the back surface side of a mounting region of a flexible substrate, and an electronic component is mounted on the front surface side. An adhesive agent in the adhesive agent layer contains silica fine particles having a primary particle diameter of less than 100 nm, and the adhesive agent layer has a shear storage elastic modulus at 160° C. of 0.15 MPa or more. When the anisotropic conductive film is disposed on the mounting region and the electronic component is mounted on the anisotropic conductive film by heating and pressing, the adhesive agent is not pushed out to a large extent, and conductive particles sandwiched between a bump on the electronic component and the electrode are pressed and squashed, improving an electrical connection between the electronic component and the electrode.
    Type: Grant
    Filed: September 19, 2016
    Date of Patent: May 28, 2019
    Assignee: DEXERIALS CORPORATION
    Inventor: Takayuki Matsushima
  • Patent number: 10297560
    Abstract: A semiconductor device and method of manufacturing is provided, whereby a support structure is utilized to provide additional support for a conductive element in order to eliminate or reduce the formation of a defective surface such that the conductive element may be formed to have a thinner structure without suffering deleterious structures.
    Type: Grant
    Filed: January 15, 2018
    Date of Patent: May 21, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Ming-Che Ho, Hung-Jui Kuo, Yi-Wen Wu, Tzung-Hui Lee
  • Patent number: 10297561
    Abstract: Semiconductor dies having interconnect structures formed thereon, and associated systems and methods, are disclosed herein. In one embodiment, an interconnect structure includes a conductive material electrically coupled to an electrically conductive contact of a semiconductor die. The conductive material includes a first portion vertically aligned with the conductive contact, and a second portion that extends laterally away from the conductive contact. A solder material is disposed on the second portion of the interconnect structure such that the solder material is at least partially laterally offset from the conductive contact of the semiconductor die. In some embodiments, an interconnect structure can further include a containment layer that prevents wicking or other undesirable movement of the solder material during a reflow process.
    Type: Grant
    Filed: December 22, 2017
    Date of Patent: May 21, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Kyle S. Mayer, Owen R. Fay
  • Patent number: 10297577
    Abstract: Semiconductor device assemblies with heat transfer structures formed from semiconductor materials are disclosed herein. In one embodiment, a semiconductor device assembly can include a thermal transfer structure formed from a semiconductor substrate. The thermal transfer structure includes an inner region, an outer region projecting from the inner region, and a cavity defined in the outer region by the inner and outer regions. The semiconductor device assembly further includes a stack of first semiconductor dies in the cavity, and a second semiconductor die attached to the outer region of the thermal transfer structure and enclosing the stack of first semiconductor dies within the cavity.
    Type: Grant
    Filed: September 1, 2017
    Date of Patent: May 21, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Sameer S. Vadhavkar, Jaspreet S. Gandhi, James M. Derderian
  • Patent number: 10297563
    Abstract: Techniques and mechanisms for providing effective connectivity with surface level microbumps on an integrated circuit package substrate. In an embodiment, different metals are variously electroplated to form a microbump which extends through a surface-level dielectric of a substrate to a seed layer including copper. The microbump includes nickel and tin, wherein the nickel aids in mitigating an absorption of seed layer copper. In another embodiment, the microbump has a mass fraction of tin, or a mass fraction of nickel, that is different in various regions along a height of the microbump.
    Type: Grant
    Filed: September 15, 2016
    Date of Patent: May 21, 2019
    Assignee: Intel Corporation
    Inventors: Rahul Jain, Kyu Oh Lee, Amanda E. Schuckman, Steve S. Cho
  • Patent number: 10290571
    Abstract: A method includes forming a plurality of dielectric layers, forming a plurality of redistribution lines in the plurality of dielectric layers, forming stacked vias in the plurality of dielectric layers with the stacked vias forming a continuous electrical connection penetrating through the plurality of dielectric layers, forming a dielectric layer over the stacked vias and the plurality of dielectric layers, forming a plurality of bond pads in the dielectric layer, and bonding a device die to the dielectric layer and a first portion of the plurality of bond pads through hybrid bonding.
    Type: Grant
    Filed: September 18, 2017
    Date of Patent: May 14, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Sung-Feng Yeh, Ming-Fa Chen, Hsien-Wei Chen
  • Patent number: 10290596
    Abstract: A method of making a semiconductor device includes depositing a dielectric layer over a conductive pad using a first deposition process. The method further includes depositing a first passivation layer directly over the dielectric layer using a high density plasma chemical vapor deposition (HDPCVD). The first deposition process is different from HDPCVD. A thickness of the dielectric layer is sufficient to prevent charges generated by depositing the first passivation layer from reaching the conductive pad.
    Type: Grant
    Filed: June 8, 2017
    Date of Patent: May 14, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Lung Shih, Chao-Keng Li, Alan Kuo, C. C. Chang, Yi-An Lin
  • Patent number: 10283376
    Abstract: A chip encapsulating method includes: fixing a plurality of wafers to a first panel level substrate, the wafer including a plurality of chips; forming a re-distribution layer on the wafer for each of the chips; forming each individual chip and the re-distribution layer connected to the chip by cutting; fixing the chip and the re-distribution layer connected thereto to a second panel level substrate; and encapsulating the chip to form an encapsulating layer. A chip encapsulating structure is prepared by the above described chip encapsulating method.
    Type: Grant
    Filed: April 12, 2018
    Date of Patent: May 7, 2019
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., BEIJING BOE DISPLAY TECHNOLOGY CO., LTD.
    Inventors: Lianjie Qu, Yun Qiu, Dan Wang, Hebin Zhao
  • Patent number: 10276402
    Abstract: A semiconductor package has a first redistribution layer, a first die, a second redistribution layer, and a surface coating layer. The first die is encapsulated within a molding material and disposed on and electrically connected to the first redistribution layer. The second redistribution layer is disposed on the molding material, on the first die, and electrically connected to the first die. The second redistribution layer has a topmost metallization layer having at least one contact pad, and the at least one contact pad includes a concave portion. The surface coating layer covers a portion of the topmost metallization layer and exposes the concave portion of the at least one contact pad. A manufacturing process is also provided.
    Type: Grant
    Filed: May 6, 2016
    Date of Patent: April 30, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yu-Feng Chen, Chih-Hua Chen, Chen-Hua Yu, Chung-Shi Liu, Hung-Jui Kuo, Hui-Jung Tsai, Hao-Yi Tsai
  • Patent number: 10276509
    Abstract: A method for fabricating an integrated fan-out package is provided. The method includes the following steps. A plurality of conductive posts are placed in apertures of a substrate. A carrier having an adhesive thereon is provided. The conductive posts are transferred to the carrier in a standing orientation by adhering the conductive posts in the apertures to the adhesive. An integrated circuit component is mounted onto the adhesive having the conductive posts adhered thereon. An insulating encapsulation is formed to encapsulate the integrated circuit component and the conductive posts. A redistribution circuit structure is formed on the insulating encapsulation, the integrated circuit component, and the conductive posts, wherein the redistribution circuit structure is electrically connected to the integrated circuit component and the conductive posts. The carrier is removed. At least parts of the adhesive are removed (e.g. patterned or entirely removed) to expose surfaces of the conductive posts.
    Type: Grant
    Filed: November 30, 2017
    Date of Patent: April 30, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Hao Chang, Hsin-Hung Liao, Hao-Yi Tsai, Chien-Ling Hwang, Wei-Sen Chang, Tsung-Hsien Chiang, Tin-Hao Kuo
  • Patent number: 10276551
    Abstract: A semiconductor device package includes a redistribution structure, a first semiconductor device, a plurality of second semiconductor devices, at least one warpage adjusting component, and an encapsulating material. The first semiconductor device is disposed on the redistribution structure. The second semiconductor devices are disposed on the redistribution structure and surround the first semiconductor device. The at least one warpage adjusting component is disposed on at least one of the second semiconductor devices. The encapsulating material encapsulates the first semiconductor device, the second semiconductor devices and the warpage adjusting component, wherein a Young's modulus of the warpage adjusting component is greater than or equal to a Young's modulus of the encapsulating material, and a coefficient of thermal expansion (CTE) of the warpage adjusting component is smaller than a CTE of the encapsulating material.
    Type: Grant
    Filed: December 27, 2017
    Date of Patent: April 30, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Po-Yao Lin, Cheng-Yi Hong, Feng-Cheng Hsu, Shuo-Mao Chen, Shin-Puu Jeng, Shu-Shen Yeh, Kuang-Chun Lee
  • Patent number: 10276516
    Abstract: Some embodiments relate to a semiconductor package. The semiconductor package includes a redistribution layer (RDL) including a first metal layer and a second metal layer. The second metal layer is stacked over the first metal layer and is coupled to the first metal layer through a via. A first semiconductor die is disposed over the RDL. The first semiconductor die includes a plurality of contact pads electrically coupled to the RDL, and the RDL enables fan-out connection of the first semiconductor die. A second semiconductor die is disposed over the first semiconductor die and over the RDL. The second semiconductor die is bonded to the RDL by a plurality of conductive bump structures.
    Type: Grant
    Filed: April 30, 2018
    Date of Patent: April 30, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jing-Cheng Lin, Chin-Chuan Chang, Jui-Pin Hung
  • Patent number: 10276533
    Abstract: A semiconductor device includes a semiconductor chip including a semiconductor substrate, an element formed in an element forming region of the semiconductor substrate, and a through-via penetrating across a front surface and a rear surface of the semiconductor substrate while avoiding the element forming region of the semiconductor substrate to form a conductive path between the front surface and the rear surface; a circuit component mounted on a circuit component connection surface at the same side as the front surface of the semiconductor substrate of the semiconductor chip; and an external connection members formed on the rear surface of the semiconductor substrate.
    Type: Grant
    Filed: May 3, 2018
    Date of Patent: April 30, 2019
    Assignee: Rohm Co., Ltd.
    Inventor: Kiyotaka Umemoto
  • Patent number: 10276668
    Abstract: A semiconductor device including a plurality of lower electrodes on a substrate, the plurality of lower electrodes in a first direction and a second direction perpendicular to the first direction to form rows and columns, a support structure having a flat panel form, the support structure connecting and supporting the plurality of lower electrodes, the support structure including a plurality of open areas defined therein, the support structure including two different shapes in an alternating manner may be provided. The plurality of open areas may have a same shape and partially expose sides of all the plurality of lower electrodes.
    Type: Grant
    Filed: November 1, 2017
    Date of Patent: April 30, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Ji-hoon Kim
  • Patent number: 10276421
    Abstract: An integrated fan-out package including a die, an insulating encapsulation, a filler, and a redistribution circuit structure is provided. The insulating encapsulation encapsulates sidewalls of the die, and the insulating encapsulation includes a recess on a top surface thereof. The filler covers the top surface of the insulating encapsulation and is being at least partially filled in the recess. The redistribution circuit structure covers an active surface of the die and the filler while being electrically connected to the die. The redistribution structure includes a dielectric layer covering the die and the filler. In addition, a method of manufacturing integrated fan-out packages is also provided.
    Type: Grant
    Filed: May 5, 2016
    Date of Patent: April 30, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Sih-Hao Liao, Hung-Jui Kuo, Yu-Hsiang Hu
  • Patent number: 10269759
    Abstract: A bump-on-trace (BOT) interconnection in a package and methods of making the BOT interconnection are provided. An embodiment BOT interconnection comprises a landing trace including a distal end, a conductive pillar extending at least to the distal end of the landing trace; and a solder feature electrically coupling the landing trace and the conductive pillar. In an embodiment, the conductive pillar overhangs the end surface of the landing trace. In another embodiment, the landing trace includes one or more recesses for trapping the solder feature after reflow. Therefore, a wetting area available to the solder feature is increased while permitting the bump pitch of the package to remain small.
    Type: Grant
    Filed: March 10, 2017
    Date of Patent: April 23, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yen-Liang Lin, Chen-Shien Chen, Tin-Hao Kuo
  • Patent number: 10269717
    Abstract: Structures and formation methods of a chip package are provided. The chip package includes a semiconductor die and a package layer partially or completely encapsulating the semiconductor die. The chip package also includes a polymer layer over the semiconductor die and the package layer. The chip package further includes a dielectric layer over the polymer layer. The dielectric layer is substantially made of a semiconductor oxide material. In addition, the chip package includes a conductive feature in the dielectric layer electrically connected to a conductive pad of the semiconductor die.
    Type: Grant
    Filed: July 17, 2017
    Date of Patent: April 23, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chen-Hua Yu, Wen-Chih Chiou
  • Patent number: 10262965
    Abstract: A display device includes: a flexible substrate having a display area for displaying an image and a peripheral area outside the display area; a first pad electrode in the peripheral area of the flexible substrate; and a driver connected to the first pad electrode. The driver includes: a circuit board including a driving circuit; a second pad electrode on one side of the circuit board and facing the first pad electrode; a convex structure on one side of the second pad electrode and having an oval cross-section; and a bump electrode on one side of the convex structure and connected to the first pad electrode. The bump electrode includes a column covering the convex structure and a convex portion extending from one side of the column and protruding to the first pad electrode.
    Type: Grant
    Filed: June 7, 2017
    Date of Patent: April 16, 2019
    Assignee: Samsung Display Co., Ltd.
    Inventors: Seung-Soo Ryu, Jeong Do Yang, Jung Yun Jo
  • Patent number: 10262959
    Abstract: In accordance with an embodiment of the present invention, a method of forming a semiconductor device includes forming a contact layer over a first major surface of a substrate. The substrate includes device regions separated by kerf regions. The contact layer is disposed in the kerf region and the device regions. A structured solder layer is formed over the device regions. The contact layer is exposed at the kerf region after forming the structured solder layer. The contact layer and the substrate in the kerf regions are diced.
    Type: Grant
    Filed: October 17, 2016
    Date of Patent: April 16, 2019
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Evelyn Napetschnig, Ulrike Fastner, Alexander Heinrich, Thomas Fischer
  • Patent number: 10262940
    Abstract: An electric connector includes a metal interconnect, a first vertical element and a second vertical element. The metal interconnect includes a plurality of horizontal elements. The first vertical element physically connects to a top surface of each of the horizontal elements. The second vertical element physically connects to a bottom surface of each of the horizontal elements, and the second vertical element misaligns the first vertical element. The present invention also provides an electric connector including a first vertical element and a second vertical element. The first vertical element physically connects to a top surface of a horizontal element. The second vertical element physically connects to a bottom surface of the horizontal element, and the second vertical element misaligns the first vertical element, wherein the first vertical element or the horizontal element is burned out before the second vertical element is burned out while a voltage is applied.
    Type: Grant
    Filed: August 3, 2017
    Date of Patent: April 16, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Jhih-Ming Wang, Li-Cih Wang, Tien-Hao Tang
  • Patent number: 10263153
    Abstract: A light-emitting diode (LED) display array, a manufacturing method thereof and a wearable device are provided. The LED display array comprises a first substrate and a second substrate arranged oppositely to each other. At least one pixel unit is formed on a surface of the first substrate facing the second substrate. At least one drive unit is formed on a surface of the second substrate facing the first substrate. Each pixel unit on the first substrate corresponds to a drive unit on the second substrate. A metal block is formed between each pixel unit and the drive unit corresponding to the pixel unit. The pixel unit is electrically connected with the drive unit corresponding to the pixel unit through the metal block.
    Type: Grant
    Filed: May 25, 2017
    Date of Patent: April 16, 2019
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventor: Bo Zhang
  • Patent number: 10262958
    Abstract: A method includes forming a passivation layer over a portion of a metal pad, forming a polymer layer over the passivation layer, and exposing the polymer layer using a photolithography mask. The photolithography mask has an opaque portion, a transparent portion, and a partial transparent portion. The exposed polymer layer is developed to form an opening, wherein the metal pad is exposed through the opening. A Post-Passivation Interconnect (PPI) is formed over the polymer layer, wherein the PPI includes a portion extending into the opening to connect to the metal pad.
    Type: Grant
    Filed: April 4, 2018
    Date of Patent: April 16, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ching-Jung Yang, Hsien-Wei Chen, Hsien-Ming Tu, Chang-Pin Huang, Yu-Chia Lai, Tung-Liang Shao
  • Patent number: 10262972
    Abstract: A semiconductor package may include a first chip stack including first chips which are stacked on a package substrate. The semiconductor package may include a second chip stack including second chips which are stacked on the package substrate. The semiconductor package may include a third chip disposed on the first and second chip stacks.
    Type: Grant
    Filed: December 1, 2017
    Date of Patent: April 16, 2019
    Assignee: SK hynix Inc.
    Inventors: Seung Yeop Lee, Jin Kyoung Park
  • Patent number: 10256209
    Abstract: A component-mounted resin substrate includes a thermoplastic resin substrate and an electronic component. The resin substrate includes a surface including a mounting land conductor and a reinforcing resin member. A bump of the electronic component is joined to the mounting land conductor by ultrasonic joining. The reinforcing resin member is in contact with a side surface of the mounting land conductor and has a height smaller than a height of the mounting land conductor.
    Type: Grant
    Filed: March 19, 2018
    Date of Patent: April 9, 2019
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Keisuke Ikeno, Kuniaki Yosui
  • Patent number: 10256114
    Abstract: A semiconductor device having one or more tiered pillars and methods of manufacturing such a semiconductor device are disclosed. The semiconductor device may include redistribution layers, a semiconductor die, and a plurality of interconnection structures that operatively couple a bottom surface of the semiconductor die to the redistribution layers. The semiconductor device may further include one or more conductive pillars about a periphery of the semiconductor die. The one or more conductive pillars may be electrically connected to the redistribution layers and may each comprise a plurality of stacked tiers.
    Type: Grant
    Filed: March 23, 2017
    Date of Patent: April 9, 2019
    Assignee: AMKOR TECHNOLOGY, INC.
    Inventors: Ronald Patrick Huemoeller, Michael G. Kelly, Curtis Zwenger
  • Patent number: 10249589
    Abstract: The semiconductor device includes: a semiconductor substrate; a conductor layer formed over the semiconductor substrate and having an upper surface and a lower surface; a conductive pillar formed on the upper surface of the conductor layer and having an upper surface, a lower surface, and a sidewall; a protection film covering the upper surface of the conductor layer and having an opening which exposes the upper surface and the sidewall of the conductive pillar; and a protection film covering the sidewall of the conductive pillar. Then, in plan view, the opening of the protection film is wider than the upper surface of the conductive pillar and exposes an entire region of an upper surface of the conductive pillar.
    Type: Grant
    Filed: April 28, 2017
    Date of Patent: April 2, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Akira Yajima, Yoshiaki Yamada
  • Patent number: 10242942
    Abstract: Embodiments of the present disclosure are directed towards techniques and configurations for designing and assembling a die capable of being adapted to a number of different packaging configurations. In one embodiment an integrated circuit (IC) die may include a semiconductor substrate. The die may also include an electrically insulative material disposed on the semiconductor substrate; a plurality of electrical routing features disposed in the electrically insulative material to route electrical signals through the electrically insulative material; and a plurality of metal features disposed in a surface of the electrically insulative material. In embodiments, the plurality of metal features may be electrically coupled with the plurality of electrical routing features. In addition, the plurality of metal features may have an input/output (I/O) density designed to enable the die to be integrated with a plurality of different package configurations. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: April 25, 2014
    Date of Patent: March 26, 2019
    Assignee: INTEL CORPORATION
    Inventors: Mathew J. Manusharow, Dustin P. Wood, Debendra Mallik
  • Patent number: 10242797
    Abstract: A multilayer-ceramic-capacitor mounting structure includes a circuit board and a multilayer ceramic capacitor. First and second external electrodes include first and second conductive resin layers on surfaces of first and second base electrode layers, respectively. The circuit board includes a copper plate on a surface of a core, disposed as a wiring pattern, and including a predetermined thickness, and signal electrodes disposed on a surface of the copper plate. The first and second external electrodes are each electrically connected to the signal electrodes of the copper plate.
    Type: Grant
    Filed: April 10, 2017
    Date of Patent: March 26, 2019
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Yosuke Terashita
  • Patent number: 10229894
    Abstract: A semiconductor process includes: applying an encapsulation material on an upper surface of a first substrate to encapsulate a die and first conductive parts, wherein the encapsulation material is a B-stage adhesive; forming a plurality of openings on the encapsulation material to expose the first conductive parts; pressing a second substrate onto the encapsulation material to adhere a lower surface of the second substrate to the encapsulation material, wherein the second substrate includes second conductive parts, and each of the first conductive parts contacts a corresponding one of the second conductive parts; and heating to fuse the first conductive parts and the corresponding second conductive parts to form a plurality of interconnection elements and solidify the encapsulation material to form a C-stage adhesive.
    Type: Grant
    Filed: April 18, 2018
    Date of Patent: March 12, 2019
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Shih-Ming Huang, Chun-Hung Lin, Yi-Ting Chen, Wen-Hsin Lin, Shih-Wei Chan, Yung-Hsing Chang
  • Patent number: 10224293
    Abstract: A package structure and method for forming the same are provided. The package structure includes a substrate and a semiconductor die formed over the substrate. The package structure also includes a package layer covering the semiconductor die and a conductive structure formed in the package layer. The package structure includes a first insulating layer formed on the conductive structure, and the first insulating layer includes monovalent metal oxide. A second insulating layer is formed between the first insulating layer and the package layer. The second insulating layer includes monovalent metal oxide, and a weight ratio of the monovalent metal oxide in the second insulating layer is greater than a weight ratio of the monovalent metal oxide in first insulating layer.
    Type: Grant
    Filed: April 24, 2017
    Date of Patent: March 5, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Jing-Cheng Lin, Tsei-Chung Fu
  • Patent number: 10224272
    Abstract: A semiconductor package includes a substrate, a rewiring layer, a plurality of semiconductor chip stack structures, and a second semiconductor chip. The rewiring layer is disposed on an upper surface of the substrate. The rewiring layer includes a concave portion. The semiconductor chip stack structures include a plurality of first semiconductor chips. The first semiconductor chips are disposed on the rewiring layer. The first semiconductor chips are spaced apart from each other in a horizontal direction. The second semiconductor chip is disposed within the concave portion. The second semiconductor chip is configured to electrically connect each of the plurality of semiconductor chip stack structures to each other.
    Type: Grant
    Filed: June 11, 2018
    Date of Patent: March 5, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ji-Hwang Kim, Jong-Bo Shim, Cha-Jea Jo, Won-Il Lee
  • Patent number: 10224313
    Abstract: Interconnect structures with intermetallic palladium joints are disclosed herein. In one embodiment, a method of forming an interconnect structure includes depositing a first conductive material comprising nickel on a first conductive surface of a first die, and depositing a second conductive material comprising nickel on a second conductive surface of a second die spaced apart from the first surface. The method further includes depositing a third conductive material on the second conductive material, and thermally compressing tin/solder between the first and third conductive materials to form an intermetallic palladium joint that extends between the first conductive material and the second conductive material such that one end of the intermetallic palladium joint is bonded directly to the first conductive material and an opposite end of the intermetallic palladium joint is bonded directly to the second conductive material.
    Type: Grant
    Filed: February 26, 2018
    Date of Patent: March 5, 2019
    Assignee: MICRON TECHNOLOGY, INC.
    Inventor: Jaspreet S. Gandhi
  • Patent number: 10224300
    Abstract: A pad structure adapted to be disposed on a first package substrate and electrically connected to conductive contacts of a second package substrate includes a first conductive pad having a first top surface, a second conductive pad, a first leveling conductor and a second leveling conductor. The second conductive pad disposed aside the first conductive pad has a second top surface non-coplanar with the first top surface. The first leveling conductor disposed on the first conductive pad has a first leveling surface opposite to the first top surface. The second leveling conductor disposed on the second conductive pad and having a second leveling surface opposite to the second top surface is coplanar with the first leveling surface. The conductive contacts of the second package substrate are disposed on the first leveling conductor and the second leveling conductor. A manufacturing method of a pad structure is also provided.
    Type: Grant
    Filed: August 2, 2017
    Date of Patent: March 5, 2019
    Inventor: Dyi-Chung Hu
  • Patent number: 10222698
    Abstract: A printable component includes a component substrate and one or more electrical conductors. One or more electrically conductive connection posts protrudes from the component substrate to form an exposed electrical contact. Each connection post is electrically connected to at least one of the electrical conductors and one or more wicking posts protrude from the component substrate. The wicking post can be insulating. In certain embodiments, a printable component source wafer comprises a source wafer, a plurality of sacrificial portions separated by anchor portions formed in a sacrificial layer of the source wafer, and a plurality of printable components. Each printable component is disposed over a corresponding sacrificial portion and connected to an anchor portion by a tether. A destination substrate structure comprises a destination substrate having one or more electrically conductive contact pads, an adhesive layer disposed on the destination substrate, and one or more printable components.
    Type: Grant
    Filed: July 27, 2017
    Date of Patent: March 5, 2019
    Assignee: X-Celeprint Limited
    Inventors: Carl Prevatte, Christopher Bower, Matthew Meitl
  • Patent number: 10204542
    Abstract: The present disclosure proposes a display and a display panel driving device. The display panel driving device includes a source driver chip having source driver signal output ports, a leads, each lead connected to one of the source driver signal output ports, and a multiplexer connected to the leads. The multiplexer is configured to transmit the source driver signal output by each of the leads to data lines on the display panel, and configured to adjust the strength of the source driver signal output by each of leads if the strength is not unanimous so that the source driver signals with a single strength enters the data lines. The display includes a display panel and the display panel driving device. Display uniformity of images shown on the panel is improved.
    Type: Grant
    Filed: July 20, 2016
    Date of Patent: February 12, 2019
    Assignee: Wuhan China Star Optoelectronics Technology Co., Ltd
    Inventor: Zhenzhou Xing
  • Patent number: 10205053
    Abstract: There are provided a semiconductor structure exhibiting excellent crystallinity by preventing the occurrence of a strain, and a semiconductor device. The semiconductor structure comprises a substrate, a bridging portion bridged to the substrate, a semiconductor layer formed on the bridging portion, a void defined by the substrate and the bridging portion. The bridging portion has a plurality of through holes. The through holes are blocked with the semiconductor layer. Therefore, the semiconductor layer does not have a through hole.
    Type: Grant
    Filed: December 11, 2017
    Date of Patent: February 12, 2019
    Assignee: TOYODA GOSEI CO., LTD.
    Inventor: Koji Okuno
  • Patent number: 10204851
    Abstract: Electronic assemblies and methods including the formation of interconnect structures are described. In one embodiment an apparatus includes semiconductor die and a first metal bump on the die, the first metal bump including a surface having a first part and a second part. The apparatus also includes a solder resistant coating covering the first part of the surface and leaving the second part of the surface uncovered. Other embodiments are described and claimed.
    Type: Grant
    Filed: February 20, 2018
    Date of Patent: February 12, 2019
    Assignee: INTEL CORPORATION
    Inventors: Sanka Ganesan, Zhiguo Qian, Robert L. Sankman, Krishna Srinivasan, Zhaohui Zhu
  • Patent number: 10204926
    Abstract: A display device that is resistant to erosion caused by moisture infiltration is provided. In the display device, a driver circuit unit includes a driver chip and a film pad on which the driver chip is mounted. A display panel of the display device includes a panel pad bonded to the film pad. The panel pad includes first conductive lines electrically connected to signal lines disposed in an active area of the display panel, second conductive lines in contact with the first conductive lines, third conductive lines in contact with the second conductive lines, and a conductive film connecting the third conductive lines to the film pad. A contact area between the first conductive lines and the second conductive lines overlaps at least a portion of an area of the conductive film.
    Type: Grant
    Filed: August 26, 2016
    Date of Patent: February 12, 2019
    Assignee: LG DISPLAY CO., LTD.
    Inventor: HeeDong Choi
  • Patent number: 10200010
    Abstract: An elastic wave filter device includes a transmission filter chip, a reception filter chip, and a mounting terminal. The transmission filter chip includes a piezoelectric substrate and an IDT electrode provided on a principal surface of the piezoelectric substrate. The reception filter chip includes a piezoelectric substrate and an IDT electrode provided on a principal surface of the piezoelectric substrate. The transmission filter chip and the reception filter chip are laminated to provide sealed spaces above the IDT electrodes. The mounting terminal is disposed on a side of the reception filter chip opposite to the transmission filter chip side. The elastic wave filter device is mounted such that the reception filter chip faces a mounting surface.
    Type: Grant
    Filed: June 17, 2016
    Date of Patent: February 5, 2019
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Takashi Iwamoto
  • Patent number: 10199345
    Abstract: A substrate structure is provided, which includes: a substrate body having a plurality of conductive pads; an insulating layer formed on the substrate body and exposing the conductive pads; a plurality of conductive vias formed in the insulating layer and electrically connected to the conductive pads; a plurality of circuits formed on the conductive vias and in the insulating layer, wherein the circuits are greater in width than the conductive vias; and a plurality of conductive posts formed on the circuits and the insulating layer, wherein each of the conductive posts has a width greater than or equal to that of each of the circuits. The conductive vias, the circuits and the conductive posts are integrally formed. As such, micro-chips or fine-pitch conductive pads can be electrically connected to the substrate structure in a flip-chip manner.
    Type: Grant
    Filed: January 10, 2018
    Date of Patent: February 5, 2019
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Hsin-Ta Lin, Ching-Wen Chiang
  • Patent number: 10192837
    Abstract: A wafer-level chip-scale package (WLCSP) includes an integrated circuit (IC) chip, and die bonding pads with a redistribution layer (RDL) having multiple via structures located directly below the footprint of a solder ball placed on the bonding pad. The via structures electrically connect the solder ball to a top metal layer of the IC chip. The RDL may extend beyond the solder ball's footprint and have additional vias that connect to the top metal layer, including vias located under and connected to other solder balls. The bonding pads have a low R-on resistance and are not susceptible to thermal-induced cracking.
    Type: Grant
    Filed: December 20, 2017
    Date of Patent: January 29, 2019
    Assignee: NXP B.V.
    Inventors: Chung Hsiung Ho, Wayne Hsiao, Richard Te Gan, James Raymond Spehar
  • Patent number: 10192812
    Abstract: A semiconductor chip, a display device or an electronic device includes a substrate, one or more conductive pads disposed on the substrate, and one or more bumps electrically connected to the one or more conductive pads, in which the one or more bumps includes a metal core, a polymer layer disposed over a surface of the metal core, and a conductive coating layer disposed over a surface of the polymer layer and electrically connected to the one or more conductive pads.
    Type: Grant
    Filed: July 25, 2017
    Date of Patent: January 29, 2019
    Assignee: Samsung Display Co., Ltd.
    Inventors: Byoung Yong Kim, Jeong Ho Hwang
  • Patent number: 10184975
    Abstract: A printed board with a wiring pattern for detecting deterioration includes an insulating substrate, a wiring pattern group that is formed on the insulating substrate and includes a wiring pattern for detecting deterioration; and a solder resist covering the wiring pattern group, in which the board has a thin film section, and a thick film section in which a thickness of the solder resist is larger than the thin film section, and the wiring pattern for detecting deterioration is formed in the thin film section whose entire surrounding area or partial surrounding area is surrounded by the thick film section.
    Type: Grant
    Filed: September 28, 2015
    Date of Patent: January 22, 2019
    Assignee: FANUC CORPORATION
    Inventors: Yuichi Okouchi, Norihiro Saido