Bump Leads Patents (Class 257/737)
  • Patent number: 11367688
    Abstract: A semiconductor package includes a first package substrate, a first semiconductor chip on the first package substrate, a molding layer covering side walls of the first semiconductor chip and including through holes, an interposer on the first semiconductor chip and the molding layer, conductive connectors in the through holes of the molding layer and connected to the first package substrate and the interposer, and an insulating filler including a first portion that fills the through holes of the molding layer so as to surround side walls of the conductive connectors.
    Type: Grant
    Filed: November 5, 2020
    Date of Patent: June 21, 2022
    Inventors: Choongbin Yim, Jungwoo Kim, Jihwang Kim, Jongbo Shim, Kyoungsei Choi
  • Patent number: 11367715
    Abstract: A photorelay of an embodiment includes a polyimide substrate having a first surface and a second surface on an opposite side of the polyimide substrate from the first surface, the polyimide substrate having a thickness equal to or more than 10 ?m and equal to or less than 120 ?m, an input terminal provided on the second surface, an output terminal provided on the second surface, a light receiving element provided on the first surface, a light emitting element provided on the light receiving element, and a MOSFET provided on the first surface.
    Type: Grant
    Filed: September 4, 2020
    Date of Patent: June 21, 2022
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventor: Tatsuo Tonedachi
  • Patent number: 11362055
    Abstract: The semiconductor package has a metal layer, a first dielectric layer formed on a metal layer, and an opening formed through the first dielectric layer to expose a part of the metal layer. The bump structure has an under bump metallurgy (hereinafter UBM), a first buffer layer and a metal bump. The UBM is formed on the first part of the metal layer, a sidewall of the opening and a top surface of the first dielectric layer. The first buffer layer is formed between a part of the UBM corresponding to the top surface of the first dielectric layer and the top surface of the first dielectric layer. The metal bump is formed on the UBM. Therefore, the first buffer layer effectively absorbs a thermal stress to avoid cracks generated in the bump structure after the bonding step.
    Type: Grant
    Filed: November 12, 2020
    Date of Patent: June 14, 2022
    Assignee: Powertech Technology Inc.
    Inventors: Chih-Yen Su, Chun-Te Lin
  • Patent number: 11362054
    Abstract: A semiconductor package includes a chip including a pad; a first insulation pattern on the chip and exposing the pad; a redistribution layer (RDL) on an upper surface of the first insulation pattern and connected to the pad; a second insulation pattern on the upper surface of the first insulation pattern and including an opening exposing a ball land of the RDL and a patterned portion in the opening; an under bump metal (UBM) on upper surfaces of the second insulation pattern and patterned portion and filling the opening, the UBM including a first locking hole exposing an edge of an upper surface of the ball land; and a conductive ball on an upper surface of the UBM and including a first locking portion in the first locking hole. The first locking hole may be about 10% to about 50% of the area of the UBM upper surface.
    Type: Grant
    Filed: July 8, 2020
    Date of Patent: June 14, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyunsoo Chung, Taewon Yoo, Myungkee Chung
  • Patent number: 11362046
    Abstract: Some embodiments relate to a semiconductor package. The package includes a redistribution layer (RDL), and a first semiconductor die disposed over the RDL. The first semiconductor die includes a plurality of contact pads electrically coupled to the RDL. The RDL enables fan-out connection of the first semiconductor die. A die package is disposed over the first semiconductor die and over the RDL. The die package is coupled to a first surface of the RDL by a plurality of conductive bump structures. The plurality of conductive bump structures laterally surround the plurality of contact pads and have uppermost surfaces that are level with an uppermost surface of the first semiconductor die.
    Type: Grant
    Filed: May 29, 2020
    Date of Patent: June 14, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jing-Cheng Lin, Chin-Chuan Chang, Jui-Pin Hung
  • Patent number: 11355428
    Abstract: A semiconductor package includes an interconnect structure including a redistribution structure, an insulating layer over the redistribution structure, and conductive pillars on the insulating layer, wherein the conductive pillars are connected to the redistribution structure, wherein the interconnect structure is free of active devices, a routing substrate including a routing layer over a core substrate, wherein the interconnect structure is bonded to the routing substrate by solder joints, wherein each of the solder joints bonds a conductive pillar of the conductive pillars to the routing layer, an underfill surrounding the conductive pillars and the solder joints, and a semiconductor device including a semiconductor die connected to a routing structure, wherein the routing structure is bonded to an opposite side of the interconnect structure as the routing substrate.
    Type: Grant
    Filed: February 7, 2020
    Date of Patent: June 7, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jiun Yi Wu, Chen-Hua Yu, Chung-Shi Liu
  • Patent number: 11355341
    Abstract: A first semiconductor substrate contains a first semiconductor material, such as silicon. A second semiconductor substrate containing a second semiconductor material, such as gallium nitride or aluminum gallium nitride, is formed on the first semiconductor substrate. The first semiconductor substrate and second semiconductor substrate are singulated to provide a semiconductor die including a portion of the second semiconductor material supported by a portion of the first semiconductor material. The semiconductor die is disposed over a die attach area of an interconnect structure. The interconnect structure has a conductive layer and optional active region. An underfill material is deposited between the semiconductor die and die attach area of the interconnect structure. The first semiconductor material is removed from the semiconductor die and the interconnect structure is singulated to separate the semiconductor die. The first semiconductor material can be removed post interconnect structure singulation.
    Type: Grant
    Filed: April 29, 2020
    Date of Patent: June 7, 2022
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Gordon M. Grivna, Stephen St. Germain
  • Patent number: 11342267
    Abstract: A semiconductor package structure includes a first semiconductor die and a second semiconductor die neighboring the first semiconductor die. The first semiconductor die includes a first edge, a second edge opposite the first edge, and a first metal layer exposed from the second edge. The second semiconductor includes a third edge neighboring the second edge of the first semiconductor die, a fourth edge opposite the third edge, and a second metal layer exposed from the third edge. The first metal layer of the first semiconductor die is electrically connected to the second metal layer of the second semiconductor die.
    Type: Grant
    Filed: October 23, 2019
    Date of Patent: May 24, 2022
    Assignee: MediaTek Inc.
    Inventors: Po-Hao Chang, Yi-Jou Lin, Hung-Chuan Chen
  • Patent number: 11342291
    Abstract: A semiconductor package includes a semiconductor substrate, an interconnect structure disposed over the substrate, a first passivation layer disposed over an interconnect structure, a contact pad disposed over the first passivation layer, a dummy pattern disposed around the contact pad and over the first passivation layer, and a second passivation layer overlaying the dummy pattern and the contact pad.
    Type: Grant
    Filed: May 6, 2020
    Date of Patent: May 24, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Yao-Chun Chuang, Hong-Seng Shue, Chen-Nan Chiu, Li-Huan Chu, Mirng-Ji Lii
  • Patent number: 11342308
    Abstract: A semiconductor device is provided with a first semiconductor chip and a second semiconductor chip that are arranged so as to oppose each other. The first semiconductor chip has a first connecting portion provided in a first hole portion, and the second semiconductor chip has an electrically conductive second connecting portion that is composed of a concave metal film formed on the front surface of a second electrode portion, the side surface of a second hole portion, and the front surface of a second protective film. The first electrode portion and the second electrode portion are electrically connected via the first connecting portion and the second connecting portion.
    Type: Grant
    Filed: April 4, 2018
    Date of Patent: May 24, 2022
    Assignee: SHARP KABUSHIKI KAISHA
    Inventor: Keiichi Sawai
  • Patent number: 11335610
    Abstract: Provided is a semiconductor structure including a pad disposed over and electrically connected to an interconnect structure, wherein the pad has a probe mark, and the probe mark has a concave surface; a protective layer conformally covering the pad and the probe mark; and a bonding structure disposed over the protective layer, wherein the bonding structure includes: a bonding dielectric layer includes a first bonding dielectric material and a second bonding dielectric material on the first bonding dielectric material; a first bonding metal layer including a via plug and a metal feature, wherein the via plug penetrates through the first bonding dielectric material and the protective layer to electrically connect to the pad having the probe mark, the metal feature is located on the via plug and the first bonding dielectric material, and the metal feature is laterally surrounded by the second bonding dielectric material.
    Type: Grant
    Filed: December 24, 2020
    Date of Patent: May 17, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsien-Wei Chen, Ching-Jung Yang, Jie Chen
  • Patent number: 11335655
    Abstract: A package structure include a ground plate, a semiconductor die, a molding compound, and an antenna element. The semiconductor die is located over the ground plate. The molding compound is located over the semiconductor die. The antenna element is located in the molding compound and overlaps with the ground plate along a stacking direction of the ground plate, the semiconductor die and the molding compound. The antenna element has a first side levelled with a first surface of the molding compound, and the ground plate is located between the semiconductor die and the antenna element.
    Type: Grant
    Filed: December 14, 2020
    Date of Patent: May 17, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Albert Wan, Chao-Wen Shih, Shou-Zen Chang, Nan-Chin Chuang
  • Patent number: 11322465
    Abstract: A method may include forming a metal pattern in a metal layer of a fabricated integrated circuit device and under a target bump of the fabricated integrated circuit device, wherein the metal pattern has an inner shape and an outer field such that a void space in the metal layer is created between the inner shape and the outer field and approximately centering the void space on an outline of an under-bump metal formed under the target bump with a keepout distance from the inner shape and the outer field on either side of the outline such that the metal minimizes local variations in mechanical stress on underlying structures within the fabricated integrated circuit device.
    Type: Grant
    Filed: June 9, 2020
    Date of Patent: May 3, 2022
    Assignee: Cirrus Logic, Inc.
    Inventors: Kathryn R. Holland, Marc L. Tarabbia, Yaoyu Pang, Alexander Barr
  • Patent number: 11322446
    Abstract: A system-in-package includes a redistributed line (RDL) structure, a first semiconductor chip, a second semiconductor chip, and a bridge die. The RDL structure includes a first RDL pattern to which a first chip pad of the first semiconductor chip is electrically connected. The second semiconductor chip is stacked on the first semiconductor chip such that the second semiconductor chip protrudes past a side surface of the first semiconductor chip, wherein a second chip pad disposed on the protrusion is electrically connected to the first RDL pattern through the bridge die.
    Type: Grant
    Filed: October 28, 2019
    Date of Patent: May 3, 2022
    Assignee: SK hynix Inc.
    Inventors: Jong Hoon Kim, Ki Jun Sung, Ki Bum Kim
  • Patent number: 11322539
    Abstract: There is provided a semiconductor device including: a plurality of bumps on a first semiconductor substrate; and a lens material in a region other than the plurality of bumps on the first semiconductor substrate, wherein a distance between a side of a bump closest to the lens material and a side of the lens material closest to the bump is greater than twice a diameter of the bump closest to the lens material, and wherein the distance between the side of the bump closest to the lens material and the side of the lens material closest to the bump is greater a minimum pitch of the bumps.
    Type: Grant
    Filed: June 3, 2020
    Date of Patent: May 3, 2022
    Assignee: SONY CORPORATION
    Inventors: Jun Ogi, Junichiro Fujimagari, Susumu Inoue, Atsushi Fujiwara
  • Patent number: 11322419
    Abstract: A method includes forming a polymer layer covering a metal via in a wafer, grooving the wafer to form a trench, wherein the trench extends from a top surface of the polymer layer into the wafer, and performing a die-saw on the wafer to separate the wafer into a plurality of device dies. A kerf passes through the trench. One of the device dies is placed over a carrier. An encapsulating material is dispensed over and around the device die. The method further includes pressing and curing the encapsulating material. After the encapsulating material is cured, a sidewall of the polymer layer is tilted. A planarization is performed on the encapsulating material until the polymer layer and the metal via are exposed. A redistribution line is formed over and electrically coupled to the metal via.
    Type: Grant
    Filed: August 3, 2020
    Date of Patent: May 3, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Yen Chiu, Hsin-Chieh Huang, Ching Fu Chang
  • Patent number: 11315897
    Abstract: A semiconductor package includes: a semiconductor element; a substrate provided with the semiconductor element on a first surface of the substrate, the substrate including a first wiring partially exposed on a second surface of the substrate opposite to the first surface; a first structure formed of an insulating film, or an insulating film and a metal portion, the first structure surrounding an exposed portion of the first wiring, the first structure having asymmetric height and angle; and a first electrode provided on the exposed portion of the first wiring.
    Type: Grant
    Filed: August 25, 2020
    Date of Patent: April 26, 2022
    Assignee: KIOXIA CORPORATION
    Inventor: Satoru Takaku
  • Patent number: 11309219
    Abstract: A method for manufacturing a semiconductor device of an embodiment includes: dividing a semiconductor wafer including a plurality of chip areas each having a columnar electrode and dicing areas, along the dicing areas to form a plurality of semiconductor chips; sticking a first resin film on the plurality of semiconductor chips while filling parts of the first resin film in gaps each present between adjacent ones of the plurality of semiconductor chips; forming trenches narrower in width than the gaps in the first resin film filled in the gaps; and sequentially picking up the plurality of semiconductor chips each having the first resin film, and mounting the picked semiconductor chip on a substrate.
    Type: Grant
    Filed: March 5, 2020
    Date of Patent: April 19, 2022
    Assignee: Kioxia Corporation
    Inventors: Akira Tomono, Keisuke Tokubuchi, Takanobu Ono
  • Patent number: 11310911
    Abstract: An integrated circuit (IC) package is described. The IC package includes a metallization structure. The IC package also includes a first die in a package substrate layer. The package substrate includes a first surface and a second surface, opposite the first surface. The second surface of the package substrate layer is on the metallization structure. The IC package further includes a second die on the first surface of the package substrate layer and on the first die. The IC package also includes through vias in the package substrate layer to couple pads of the second die to metal routing layers at a first surface of the metallization structure. The IC package further includes package bumps on a second surface of the metallization structure, opposite the first surface, and coupled to the pads of the second die through the metal routing layers.
    Type: Grant
    Filed: July 14, 2020
    Date of Patent: April 19, 2022
    Assignee: QUALCOMM Incorporated
    Inventors: Stanley Seungchul Song, Jonghae Kim, Periannan Chidambaram
  • Patent number: 11302608
    Abstract: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a first die, a first conductive feature positioned in the first die, a second die positioned on the first die, a first mask layer positioned on the second die, a second mask layer positioned on the first mask layer, a conductive filler layer positioned penetrating the second mask layer, the first mask layer, and the second die, extending to the first die, and contacting the first conductive feature, isolation layers positioned between the conductive filler layer and the first die, between the conductive filler layer and the second die, and between the conductive filler layer and the first mask layer, and protection layers positioned between the conductive filler layer and the second mask layer and between the conductive filler layer and the first mask layer, and covering upper portions of the isolation layers.
    Type: Grant
    Filed: June 22, 2020
    Date of Patent: April 12, 2022
    Assignee: Nanya Technology Corporation
    Inventors: Tse-Yao Huang, Shing-Yih Shih
  • Patent number: 11289436
    Abstract: Embodiments of molded packages and corresponding methods of manufacture are provided. In an embodiment of a molded package, the molded package includes a laser-activatable mold compound having a plurality of laser-activated regions which are plated with an electrically conductive material to form metal pads and/or metal traces at a first side of the laser-activatable mold compound. A semiconductor die embedded in the laser-activatable mold compound has a plurality of die pads. An interconnect electrically connects the plurality of die pads of the semiconductor die to the metal pads and/or metal traces at the first side of the laser-activatable mold compound.
    Type: Grant
    Filed: May 28, 2020
    Date of Patent: March 29, 2022
    Assignee: Infineon Technologies Austria AG
    Inventors: Chee Hong Lee, Kok Yau Chua, Chii Shang Hong, Swee Kah Lee, Chee Yang Ng, Klaus Schiess
  • Patent number: 11289404
    Abstract: A through via comprising sidewalls having first scallops in a first region and second scallops in a second region and a method of forming the same are disclosed. In an embodiment, a semiconductor device includes a first substrate; and a through via extending through the substrate, the substrate including a first plurality of scallops adjacent the through via in a first region of the substrate and a second plurality of scallops adjacent the through via in a second region of the substrate, each of the scallops of the first plurality of scallops having a first depth, each of the scallops of the second plurality of scallops having a second depth, the first depth being greater than the second depth.
    Type: Grant
    Filed: January 17, 2020
    Date of Patent: March 29, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsu-Lun Liu, Wen-Hsiung Lu, Ming-Da Cheng, Chen-En Yen, Cheng-Lung Yang, Kuanchih Huang
  • Patent number: 11289453
    Abstract: A package comprising a substrate, an integrated device, and an interconnect structure. The substrate includes a first surface and a second surface. The substrate further includes a plurality of interconnects for providing at least one electrical connection to a board. The integrated device is coupled to the first surface of the substrate. The interconnect structure is coupled to the first surface of the substrate. The integrated device, the interconnect structure and the substrate are coupled together in such a way that when a first electrical signal travels between the integrated device and the board, the first electrical signal travels through at least the substrate, then through the interconnect structure and back through the substrate.
    Type: Grant
    Filed: February 27, 2020
    Date of Patent: March 29, 2022
    Assignee: QUALCOMM Incorporated
    Inventors: Aniket Patil, Zhijie Wang, Hong Bok We
  • Patent number: 11289442
    Abstract: A gold-coated silver bonding wire includes: a core material containing silver as a main component; and a coating layer provided on a surface of the core material and containing gold as a main component. The gold-coated silver bonding wire contains gold in a range of not less than 2 mass % nor more than 7 mass %, and at least one sulfur group element selected from the group consisting of sulfur, selenium, and tellurium in a range of not less than 1 mass ppm nor more than 80 mass ppm, with respect to a total content of the bonding wire.
    Type: Grant
    Filed: May 8, 2020
    Date of Patent: March 29, 2022
    Assignee: Tanaka Denshi Kogyo K.K.
    Inventors: Yuki Antoku, Shota Kawano, Yusuke Sakita
  • Patent number: 11282778
    Abstract: A semiconductor device package includes a redistribution structure, a conductive substrate stacked on the redistribution structure and an encapsulant encapsulating the redistribution structure and the conductive substrate. The encapsulant encapsulates a side surface of the conductive substrate. A method for manufacturing an electronic device package includes: providing a carrier, forming a redistribution structure on the carrier, mounting a conductive substrate on a first surface of the redistribution structure, forming a first encapsulant to encapsulate the first surface of the redistribution structure and a side surface of the conductive substrate, and removing the carrier.
    Type: Grant
    Filed: December 4, 2019
    Date of Patent: March 22, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Hsu-Nan Fang
  • Patent number: 11282825
    Abstract: A structure including a wiring substrate, an interposer disposed on and electrically connected to the wiring substrate, a semiconductor die disposed on and electrically connected to the interposer, a first insulating encapsulation disposed on the interposer, a second insulating encapsulation disposed on the wiring substrate, and a lid is provided. The semiconductor die is laterally encapsulated by the first insulating encapsulation. The semiconductor die and the first insulating encapsulation are laterally encapsulated by the second insulating encapsulation. A top surface of the first insulating encapsulation is substantially leveled with a top surface of the second insulating encapsulation and a surface of the semiconductor die. The lid is disposed on the semiconductor die, the first insulating encapsulation and the second insulating encapsulation.
    Type: Grant
    Filed: May 19, 2020
    Date of Patent: March 22, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsung-Shu Lin, Tsung-Yu Chen, Wensen Hung
  • Patent number: 11282814
    Abstract: A semiconductor device assembly can include a substrate including a plurality of external connections. The assembly can include a first individual module and a first bond pad. The first individual module can be disposed on the substrate such that the first side of the first individual module faces the substrate. In some embodiments, the first individual module electrically is coupled to an external connection of the substrate via the first bond pad. The assembly can include a second individual module comprising a plurality of lateral sides. The second individual module can be disposed over the first individual module. In some embodiments, a first lateral side of the second individual module includes a first step forming a first overhang portion and a first recess. In some embodiments, the first bond pad is vertically aligned with the first recess of the second individual module.
    Type: Grant
    Filed: December 27, 2019
    Date of Patent: March 22, 2022
    Assignee: Micron Technology, Inc.
    Inventor: Blaine J. Thurgood
  • Patent number: 11282773
    Abstract: An electrical device includes an electrically insulating body having an insulating body surface and a conductive pad array, a small conductive pad arranged on the insulating body surface and within the conductive pad array, and an enlarged conductive pad. The enlarged conductive pad is arranged on the insulating body and within the conductive pad array, wherein the enlarged conductive pad is spaced apart from the small conductive pad and is larger than the small conductive pad. C4 assemblies and methods of making C4 assemblies including the electrical device are also described.
    Type: Grant
    Filed: April 10, 2020
    Date of Patent: March 22, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Krishna R. Tunga, Thomas Weiss, Charles Leon Arvin, Bhupender Singh, Brian W. Quinlan
  • Patent number: 11264368
    Abstract: Various embodiments of the present disclosure are directed towards an integrated chip (IC). The IC includes a first dielectric structure having first inner sidewalls over an interlayer dielectric (ILD) structure. A second dielectric structure is over the first dielectric structure, where the first inner sidewalls are between second inner sidewalls of the second dielectric structure. A sidewall barrier structure is over the first dielectric structure and extends vertically along the second inner sidewalls. A lower bumping structure is between the second inner sidewalls and extends vertically along the first inner sidewalls and vertically along third inner sidewalls of the sidewall barrier structure. An upper bumping structure is over both the lower bumping structure and the sidewall barrier structure and between the second inner sidewalls, where an uppermost point of the upper bumping structure is at or below an uppermost point of the second dielectric structure.
    Type: Grant
    Filed: April 7, 2020
    Date of Patent: March 1, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ching-Sheng Chu, Chern-Yow Hsu
  • Patent number: 11264331
    Abstract: The present disclosure relates to methods and apparatus for forming a thin-form-factor semiconductor package. In one embodiment, a glass or silicon substrate is structured by micro-blasting or laser ablation to form structures for formation of interconnections therethrough. The substrate is thereafter utilized as a frame for forming a semiconductor package with embedded dies therein.
    Type: Grant
    Filed: November 18, 2019
    Date of Patent: March 1, 2022
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Han-Wen Chen, Steven Verhaverbeke, Giback Park, Giorgio Cellere, Diego Tonini, Vincent Dicaprio, Kyuil Cho
  • Patent number: 11257774
    Abstract: Structures, methods and devices are disclosed, related to improved stack structures in electronic devices. In some embodiments, a stack structure includes a pad implemented on a substrate, the pad including a polymer layer having a side that forms an interface with another layer of the pad, the pad further including an upper metal layer over the interface, the upper metal layer having an upper surface. In some embodiments, the stack structure also includes a passivation layer implemented over the upper metal layer, the passivation layer including a pattern configured to provide a compressive force on the upper metal layer to thereby reduce the likelihood of delamination at the interface, the pattern defining a plurality of openings to expose the upper surface of the upper metal layer.
    Type: Grant
    Filed: August 28, 2015
    Date of Patent: February 22, 2022
    Assignee: Skyworks Solutions, Inc.
    Inventors: Jiro Yota, Dogan Gunes
  • Patent number: 11257787
    Abstract: A package structure includes at least one semiconductor die, an insulating encapsulant, an isolation layer and a redistribution layer. The at least one first semiconductor die has a semiconductor substrate and a conductive post disposed on the semiconductor substrate. The insulating encapsulant is partially encapsulating the first semiconductor die, wherein the conductive post has a first portion surrounded by the insulating encapsulant and a second portion that protrudes out from the insulating encapsulant. The isolation layer is disposed on the insulating encapsulant and surrounding the second portion of the conductive post. The redistribution layer is disposed on the first semiconductor die and the isolation layer, wherein the redistribution layer is electrically connected to the conductive post of the first semiconductor die.
    Type: Grant
    Filed: May 18, 2020
    Date of Patent: February 22, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsien-Wei Chen, Ming-Fa Chen, Sung-Feng Yeh
  • Patent number: 11244915
    Abstract: A semiconductor device is provided that includes a dielectric layer, a bond pad, a passivation layer and a planar barrier. The bond pad is positioned in the dielectric layer. The passivation layer is positioned over the dielectric layer and has an opening over the bond pad. The planar barrier is positioned on the bond pad.
    Type: Grant
    Filed: October 31, 2019
    Date of Patent: February 8, 2022
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Ramasamy Chockalingam, Juan Boon Tan, Chee Kong Leong, Ranjan Rajoo, Xuesong Rao, Xiaodong Li
  • Patent number: 11239329
    Abstract: According to an aspect of the present disclosure, a semiconductor device includes a semiconductor substrate, a lower electrode provided on the semiconductor substrate, an insulating film that is provided on the semiconductor substrate and surrounds the lower electrode and a metal film that is provided on the lower electrode and includes a convex portion on an upper surface thereof, wherein the convex portion includes a first portion extending in a first direction parallel to an upper surface of the semiconductor substrate, and a second portion extending in a second direction that is parallel to the upper surface of the semiconductor substrate and intersects the first direction, and the metal film is thinner than the insulating film.
    Type: Grant
    Filed: February 5, 2020
    Date of Patent: February 1, 2022
    Assignee: Mitsubishi Electric Corporation
    Inventors: Shinya Soneda, Tetsuya Nitta, Kenji Harada
  • Patent number: 11239164
    Abstract: A semiconductor device includes a first metal plug and an etch stop layer disposed over a semiconductor substrate. The first metal plug has an upper portion protruding from a top surface of the etch stop layer, and a top surface of the upper portion is rounded. The semiconductor device also includes a second metal plug disposed over the first metal plug. The second metal plug is in direct contact with a first sidewall of the upper portion of the first metal plug and the top surface of the etch stop layer.
    Type: Grant
    Filed: February 26, 2020
    Date of Patent: February 1, 2022
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Chun-Heng Wu
  • Patent number: 11239209
    Abstract: A memory device includes a first memory block defined in a first wafer; and a second memory block defined in a second wafer that is disposed in a vertical direction with respect to the first wafer. A size of the first memory block is smaller than a size of the second memory block.
    Type: Grant
    Filed: October 22, 2020
    Date of Patent: February 1, 2022
    Assignee: SK hynix Inc.
    Inventors: Sung Lae Oh, Ki Soo Kim, Sang Woo Park, Dong Hyuk Chae
  • Patent number: 11233033
    Abstract: A semiconductor package includes a package substrate, a base module disposed on the package substrate and configured to include an intermediate chip, bonding wires connecting the intermediate chip to the package substrate, a lower-left chip disposed between the base module and the package substrate, and an upper-left chip disposed on the base module. The base module further includes an encapsulant encapsulating the intermediate chip, through vias electrically connected to the upper-left chip, and redistributed lines (RDLs) connecting the intermediate chip to the through vias and extending to provide connection parts which are spaced apart from the through vias and are connected to the lower-left chip.
    Type: Grant
    Filed: June 11, 2020
    Date of Patent: January 25, 2022
    Assignee: SK hynix Inc.
    Inventor: Won Duck Jung
  • Patent number: 11232957
    Abstract: The present disclosure provides a chip packaging method and a chip package structure. The chip packaging method comprises: forming wafer conductive traces on a wafer active surface of a wafer; forming a protective layer having material properties on the wafer conductive traces; cutting the wafer to obtain a die and adhering the die onto a carrier; forming a molding layer encapsulating the die and having material properties; stripping off the carrier; and forming a panel-level conductive layer and a dielectric layer. The chip packaging method reduces or eliminates warpage in the panel packaging process, lowers a requirement on an accuracy of aligning the die on the panel, reduces a difficulty in the panel packaging process, and makes the packaged chip structure more durable, and thus the present disclosure is especially suitable for large panel-level package and package of a thin chip with a large electric flux.
    Type: Grant
    Filed: March 2, 2020
    Date of Patent: January 25, 2022
    Assignee: PEP INOVATION PTE. LTD.
    Inventor: Jimmy Chew
  • Patent number: 11233021
    Abstract: An array substrate, a display panel, and a display device. The array substrate includes a substrate. The substrate has a display area and a non-display area adjacent to the display area, and the non-display area of the substrate has a first notch away from an end of the display area. A first edge of the first notch disposed near the display area of the substrate is provided with a binding area. The display device has a narrow border and a high screen ratio.
    Type: Grant
    Filed: April 29, 2019
    Date of Patent: January 25, 2022
    Assignee: WUHAN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Yantao Lu, Guanghui Liu, Chao Wang
  • Patent number: 11234324
    Abstract: A circuit board structure includes a first dielectric layer, at least one first circuit layer, a second dielectric layer, and an insulating protection layer. The first circuit layer is mounted on the first dielectric layer, and includes at least one first circuit. The second dielectric layer is mounted on the first circuit layer, and includes at least one thermally conductive bump and at least one electrically conductive bump. The electrically conductive bump is electrically connected to the first circuit. The insulating protection layer is mounted on the second dielectric layer. The thermally conductive bump directly contacts the glass substrate. When lasering is applied to cut the glass substrate for de-bonding, the lasering heat energy can be absorbed and dissipated by the thermally conductive bump, resolving the problem of circuit de-bonding and raising the process yield. In addition, a manufacturing method of the circuit board structure is provided.
    Type: Grant
    Filed: February 9, 2021
    Date of Patent: January 25, 2022
    Assignee: UNIMICRON TECHNOLOGY CORP.
    Inventors: Ping-Che Yang, Tsun-Sheng Chou, Yan-Jia Peng
  • Patent number: 11233028
    Abstract: The present disclosure provides a chip packaging method and a chip structure. The chip packaging method comprises: providing a wafer, and forming a protective layer on a wafer active surface of the wafer; cutting and separating the wafer to form a die; providing a metal structure, the metal structure including at least one metal unit; adhering the die and the metal structure onto a carrier; and forming a molding layer. The chip structure comprises: at least one die; a protective layer; a metal unit, the metal unit including at least one metal feature; and a molding layer, encapsulating the at least one die and the metal unit, and the chip structure is connected with an external circuit through the at least one metal feature.
    Type: Grant
    Filed: March 2, 2020
    Date of Patent: January 25, 2022
    Assignee: PEP INOVATION PTE. LTD.
    Inventor: Jimmy Chew
  • Patent number: 11233032
    Abstract: Embodiments of mechanisms for forming a package are provided. The package includes a substrate and a contact pad formed on the substrate. The package also includes a conductive pillar bonded to the contact pad through solder formed between the conductive pillar and the contact pad. The solder is in direct contact with the conductive pillar.
    Type: Grant
    Filed: December 4, 2019
    Date of Patent: January 25, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yeong-Jyh Lin, Hsin-Hung Liao, Chien-Ling Hwang, Bor-Ping Jang, Hsiao-Chung Liang, Chung-Shi Liu
  • Patent number: 11226709
    Abstract: A touch substrate for a touch screen includes a touch layer. The touch layer includes a first electrode and a second electrode. The first electrode includes a first protrusion and a first dummy electrode. The second electrode includes a second protrusion and a second dummy electrode. Adjacent two first protrusions or adjacent two second protrusions are spaced apart by a size of at least one sub-pixel.
    Type: Grant
    Filed: March 13, 2020
    Date of Patent: January 18, 2022
    Inventors: Yichao Deng, Jian Ye
  • Patent number: 11227848
    Abstract: A chip package array including a plurality of chip packages is provided. The chip packages are suitable for array arrangement to form the chip package array. Each of the chip packages includes a redistribution structure, a supporting structure, a chip, and an encapsulated material. The supporting structure is disposed on the redistribution structure and has an opening. The chip is disposed on the redistribution structure and located in the opening. The encapsulated material is located between the opening and the chip, wherein the encapsulated material is filled between the opening and the chip, and the chip and the supporting structure are respectively connected to the redistribution structure.
    Type: Grant
    Filed: June 29, 2017
    Date of Patent: January 18, 2022
    Assignee: VIA Alliance Semiconductor Co., Ltd.
    Inventors: Wen-Yuan Chang, Wei-Cheng Chen, Hsueh-Chung Shelton Lu
  • Patent number: 11227837
    Abstract: In an embodiment, a structure includes: a first integrated circuit die including first die connectors; a first dielectric layer on the first die connectors; first conductive vias extending through the first dielectric layer, the first conductive vias connected to a first subset of the first die connectors; a second integrated circuit die bonded to a second subset of the first die connectors with first reflowable connectors; a first encapsulant surrounding the second integrated circuit die and the first conductive vias, the first encapsulant and the first integrated circuit die being laterally coterminous; second conductive vias adjacent the first integrated circuit die; a second encapsulant surrounding the second conductive vias, the first encapsulant, and the first integrated circuit die; and a first redistribution structure including first redistribution lines, the first redistribution lines connected to the first conductive vias and the second conductive vias.
    Type: Grant
    Filed: May 6, 2020
    Date of Patent: January 18, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Jen-Fu Liu, Ming Hung Tseng, Tsung-Hsien Chiang, Yen-Liang Lin, Tzu-Sung Huang
  • Patent number: 11227838
    Abstract: A multichip package includes: a chip package comprising a first IC chip, a polymer layer in a space beyond and extending from a sidewall of the first IC chip, a through package via in the polymer layer, an interconnection scheme under the first IC chip, polymer layer and through package via, and a metal bump under the interconnection scheme and at a bottom of the chip package, wherein the first IC chip comprises memory cells for storing data therein associated with resulting values for a look-up table (LUT) and a selection circuit comprising a first input data set for a logic operation and a second input data set associated with the data stored in the memory cells, wherein the selection circuit selects, in accordance with the first input data set, data from the second input data set as an output data for the logic operation; and a second IC chip over the chip package, wherein the second IC chip couples to the first IC chip through, in sequence, the through package via and interconnection scheme, wherein the s
    Type: Grant
    Filed: November 4, 2020
    Date of Patent: January 18, 2022
    Assignee: iCometrue Company Ltd.
    Inventors: Mou-Shiung Lin, Jin-Yuan Lee
  • Patent number: 11217535
    Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate, a first die coupled to the package substrate with first interconnects, and a second die coupled to the first die with second interconnects, wherein the second die is coupled to the package substrate with third interconnects, a communication network is at least partially included in the first die and at least partially included in the second die, and the communication network includes a communication pathway between the first die and the second die.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: January 4, 2022
    Assignee: Intel Corporation
    Inventors: Adel A. Elsherbini, Amr Elshazly, Arun Chandrasekhar, Shawna M. Liff, Johanna M. Swan
  • Patent number: 11211459
    Abstract: An auxiliary carrier and a silicon carbide substrate are provided. The silicon carbide substrate includes an idle layer and a device layer between a main surface at a front side of the silicon carbide substrate and the idle layer. The device layer includes a plurality of laterally separated device regions. Each device region extends from the main surface to the idle layer. The auxiliary carrier is structurally connected with the silicon carbide substrate at the front side. The idle layer is removed. A mold structure is formed that fills a grid-shaped groove that laterally separates the device regions. The device regions are separated, and parts of the mold structure form frame structures laterally surrounding the device regions.
    Type: Grant
    Filed: December 16, 2019
    Date of Patent: December 28, 2021
    Assignee: Infineon Technologies AG
    Inventors: Andre Brockmeier, Guenter Denifl, Ronny Kern, Michael Knabl, Matteo Piccin, Francisco Javier Santos Rodriguez
  • Patent number: 11211348
    Abstract: A first wafer, a method of fabricating thereof and a wafer stack are disclosed. The first wafer includes a first substrate, a first dielectric layer on the first substrate, first metal layers embedded in the first dielectric layer, first switching holes extending partially through the first dielectric layer and exposing the first metal layers, a first interconnection layer filling up the first switching holes and electrically connected to the first metal layers, a first insulating layer residing on surfaces of both the first dielectric layer and the first interconnection layer, first contact holes extending through the first insulating layer and exposing the first interconnection layer, and a second interconnection layer filling up the first contact holes and electrically connected to the first interconnection layer. Filling the first contact holes and the first switching holes with different interconnection layers reduces the difficulty in fabricating interconnection structures for the first metal layers.
    Type: Grant
    Filed: November 19, 2019
    Date of Patent: December 28, 2021
    Assignee: WUHAN XINXIN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Xing Hu
  • Patent number: RE49045
    Abstract: Package on package (PoP) devices and methods of packaging semiconductor dies are disclosed. A PoP device includes a first packaged die and a second packaged die coupled to the first packaged die. Metal stud bumps are disposed between the first packaged die and the second packaged die. The metal stud bumps include a bump region and a tail region coupled to the bump region. The metal stud bumps are embedded in solder joints.
    Type: Grant
    Filed: August 7, 2017
    Date of Patent: April 19, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Chien-Hsun Lee, Yung Ching Chen