Bump Leads Patents (Class 257/737)
  • Patent number: 11031431
    Abstract: A semiconductor device including a plurality of substrates that is stacked, each of the substrates including a semiconductor substrate and a multi-layered wiring layer stacked on the semiconductor substrate, the semiconductor substrate having a circuit with a predetermined function formed thereon. Bonding surfaces between two substrates among the plurality of substrates have an electrode junction structure in which electrodes formed on the respective bonding surfaces are joined in direct contact with each other, the electrode junction structure being a structure for electrical connection between the two substrates.
    Type: Grant
    Filed: February 15, 2018
    Date of Patent: June 8, 2021
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Nobutoshi Fujii, Yoshiya Hagimoto
  • Patent number: 11024594
    Abstract: According to an exemplary embodiment, a substrate having a first area and a second area is provided. The substrate includes a plurality of pads. Each of the pads has a pad size. The pad size in the first area is larger than the pad size in the second area.
    Type: Grant
    Filed: November 26, 2018
    Date of Patent: June 1, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Wei-Hung Lin, Hsiu-Jen Lin, Ming-Da Cheng, Yu-Min Liang, Chen-Shien Chen, Chung-Shi Liu
  • Patent number: 11024757
    Abstract: In the semiconductor device, a first package is provided with a first substrate under which a semiconductor chip configured to output a signal and a first wiring electrically connected to the semiconductor chip are arranged. A second package is provided with a second substrate above which a processing circuit configured to process the output signal, a second wiring electrically connected to the processing circuit, and an encapsulant configured to seal the processing circuit are arranged, the semiconductor chip and the encapsulant being arranged to face each other in a non-contact manner. A connection portion electrically connects the first wiring and the second wiring.
    Type: Grant
    Filed: November 30, 2016
    Date of Patent: June 1, 2021
    Assignee: SONY CORPORATION
    Inventor: Makoto Murai
  • Patent number: 11024568
    Abstract: A semiconductor package is provided. The semiconductor package includes a first substrate, a first semiconductor chip arranged on the first substrate, a first group of at least one solder ball arranged on a side surface of the first semiconductor chip, an interposer arranged on the first semiconductor chip and the first substrate and being in contact with the first group of at least one solder ball, and an adhesive layer arranged between the first semiconductor chip and the interposer and configured to expose at least a portion of un upper surface of the first semiconductor chip, wherein a first height from an upper surface of the first substrate to the upper surface of the first semiconductor chip is greater than a second height of the first group of at least one solder ball.
    Type: Grant
    Filed: April 23, 2019
    Date of Patent: June 1, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Shle Ge Lee, Young Bae Kim
  • Patent number: 11024575
    Abstract: A semiconductor device includes a semiconductor substrate, a conductive pad disposed on the semiconductor substrate, and a pillar pattern disposed on the conductive pad. The semiconductor device further includes a solder seed pattern disposed on the pillar pattern, and a solder portion disposed on the pillar pattern and the solder seed pattern. A first width of the solder seed pattern is less than a second width of a top surface of the pillar pattern.
    Type: Grant
    Filed: May 17, 2019
    Date of Patent: June 1, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jinkuk Bae, Hyunsoo Chung, Inyoung Lee, Donghyeon Jang
  • Patent number: 11024608
    Abstract: An exemplary micro-device and substrate structure includes a destination substrate and one or more contact pads disposed thereon, a micro-device disposed on or over the destination substrate, and a layer of cured adhesive disposed on the destination substrate. The micro-device comprises at least one electrical contact. The at least one electrical contact is in direct electrical contact with the one or more contact pads. The adhesive layer adheres the micro-device to the destination substrate and is in contact with the one or more contact pads. An exemplary method of making a micro-device and substrate structure includes providing a destination substrate and one or more contact pads disposed thereon, coating a layer of curable adhesive, disposing a micro-device comprising at least one electrical contact on the layer and curing the layer thereby directly electrically contacting the at least one electrical contact with the one or more contact pads.
    Type: Grant
    Filed: July 18, 2018
    Date of Patent: June 1, 2021
    Assignee: X Display Company Technology Limited
    Inventors: Matthew Meitl, Brook Raymond, Ronald S. Cok, Christopher Andrew Bower, Salvatore Bonafede, Erich Radauscher, Carl Ray Prevatte, Jr., António José Marques Trindade, Tanya Yvette Moore
  • Patent number: 11018106
    Abstract: A semiconductor device includes a first substrate including a plurality of first pads disposed on a first surface of the first substrate, a second substrate including a plurality of second pads disposed on a second surface of the substrate, a plurality of conductive bumps bonded the plurality of first pads with the plurality of second pads correspondingly, a solder bracing material disposed on the first surface and surrounded the plurality of conductive bumps, an underfill material surrounded the plurality of conductive bumps and disposed between the solder bracing material and the second surface, and a rough interface between the solder bracing material and the underfill material. The rough interface includes a plurality of protruded portions and a plurality of recessed portions.
    Type: Grant
    Filed: June 20, 2018
    Date of Patent: May 25, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Jing-Cheng Lin, Feng-Cheng Hsu
  • Patent number: 11018108
    Abstract: A semiconductor package includes: a redistribution substrate; a semiconductor chip on the redistribution substrate; and an external terminal on a bottom surface of the redistribution substrate, wherein the redistribution substrate comprises: a first insulating layer including a first opening; a second insulating layer on the first insulating layer and including a second opening, wherein the second opening is positioned in the first opening in a plan view; a first barrier metal layer disposed along a sidewall of the first opening and along a sidewall of the second opening; a first redistribution conductive pattern on the first barrier metal layer; a third insulating layer on a bottom surface of the first insulating layer; and a pad penetrating the third insulating layer and electrically connecting to the first redistribution conductive pattern, wherein the external terminal is provided on the pad, wherein the second insulating layer at least partially covers a chip pad of the semiconductor chip, and the second
    Type: Grant
    Filed: June 28, 2020
    Date of Patent: May 25, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Youn Ji Min, Seokhyun Lee, Jongyoun Kim, Kyoung Lim Suk, SeokWon Lee
  • Patent number: 11018091
    Abstract: A package includes a device die, a molding material encircling the device die, wherein a top surface of the molding material is substantially level with a top surface of the device die, and a bottom dielectric layer over the device die and the molding material. A plurality of redistribution lines (RDLs) extends into the bottom dielectric layer and electrically coupling to the device die. A top polymer layer is over the bottom dielectric layer, with a trench ring penetrating through the top polymer layer. The trench ring is adjacent to edges of the package. The package further includes Under-Bump Metallurgies (UBMs) extending into the top polymer layer.
    Type: Grant
    Filed: December 5, 2019
    Date of Patent: May 25, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jie Chen, Hsien-Wei Chen
  • Patent number: 11018115
    Abstract: A semiconductor package includes a package substrate, a plurality of semiconductor devices stacked on the package substrate, a plurality of underfill fillets disposed between the plurality of semiconductor devices and between the package substrate and the plurality of semiconductor devices, and a molding resin at least partially surrounding the plurality of semiconductor devices and the plurality of underfill fillets. The plurality of underfill fillets include a plurality of protrusions that protrude from spaces between each of the plurality of semiconductor devices or between the package substrate and each of the plurality of semiconductor devices. At least two neighboring underfill fillet protrusions of the plurality of protrusions form one continuous structure without an interface therebetween.
    Type: Grant
    Filed: March 19, 2020
    Date of Patent: May 25, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ji-Hwan Hwang, Sang-Sick Park, Tae-Hong Min, Geol Nam
  • Patent number: 11018220
    Abstract: Structures and methods for isolating semiconductor devices and improving device reliability under harsh environmental conditions are described. An isolation region may be formed by ion implantation in a region of semiconductor surrounding a device. The implantation region may extend into streets of a wafer. A passivation layer may be deposited over the implantation region and extend further into the streets than the isolation region to protect the isolation region from environmental conditions that may adversely affect the isolation region.
    Type: Grant
    Filed: April 19, 2018
    Date of Patent: May 25, 2021
    Assignee: MACOM TECHNOLOGY SOLUTIONS HOLDINGS, INC.
    Inventors: Allen W. Hanson, Wayne Mack Struble, John Claassen Roberts
  • Patent number: 11011484
    Abstract: A semiconductor device includes a first substrate and a second substrate that is stacked on a first surface of the first substrate in a stacking direction and includes a second surface facing the first surface. A plurality of first terminals is provided on the first surface of the first substrate. A plurality of second terminals is provided on the second surface of the second substrate. A plurality of metallic portions is respectively provided between the plurality of first terminals and the plurality of second terminals. In a cross-section substantially perpendicular to the stacking direction, at least one of (i) each of the plurality of first terminals or (ii) each of the plurality of second terminals (a) includes a recessed portion in a first direction toward an adjacent first terminal or second terminal or (b) includes a projecting portion in a second direction intersecting with the first direction.
    Type: Grant
    Filed: February 24, 2020
    Date of Patent: May 18, 2021
    Assignee: KIOXIA CORPORATION
    Inventor: Hiroyuki Wakioka
  • Patent number: 11011406
    Abstract: The invention relates to a method of processing a substrate. The substrate has one side and a side opposite to the one side. The substrate has, on the one side or on the side opposite to the one side, at least one recess. The method comprises providing a protective film and applying the protective film to the side of the substrate having the at least one recess so that at least a central area of a front surface of the protective film is in direct contact with the side of the substrate having the at least one recess. The method further comprises applying pressure to the protective film so that the protective film enters into the at least one recess along at least part of a depth of the recess, and processing the one side of the substrate and/or the side of the substrate opposite to the one side.
    Type: Grant
    Filed: August 16, 2019
    Date of Patent: May 18, 2021
    Assignee: DISCO CORPORATION
    Inventors: Karl Heinz Priewasser, Kensuke Nagaoka
  • Patent number: 11004741
    Abstract: An interconnect structure for an integrated circuit, such as a three dimensional integrated circuit (3DIC), and a method of forming the same is provided. An example interconnect structure includes a substrate, a through via extending through the substrate, and a liner disposed between the substrate and the through via. The substrate includes a tapered profile portion. The tapered profile portion abuts the liner.
    Type: Grant
    Filed: December 23, 2019
    Date of Patent: May 11, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jiung Wu, Kuan-Liang Lai, Ming-Tsu Chung, Hong-Ye Shih, Ku-Feng Yang, Tsang-Jiuh Wu, Wen-Chih Chiou, Shin-Puu Jeng, Chen-Hua Yu
  • Patent number: 11004697
    Abstract: A semiconductor device includes a substrate including traces, wherein the traces protrude above a top surface of the substrate; a prefill material over the substrate and between the traces, wherein the prefill material directly contacts peripheral surfaces of the traces; a die attached over the substrate; and a wafer-level underfill between the prefill material and the die.
    Type: Grant
    Filed: June 10, 2019
    Date of Patent: May 11, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Shijian Luo, Jonathan S. Hacker
  • Patent number: 11004821
    Abstract: A wire bonding method comprises: preparing a wire bonding apparatus; a step of forming a free air ball; a first height measuring step of measuring the height of a first electrode by detecting whether the free air ball is grounded to the first electrode; a second height measuring step of measuring the height of a second electrode by detecting whether the free air ball is grounded to the second electrode; a first bonding step of controlling the height of a bonding tool based on the measurement result in the first height measuring step, and bonding the free air ball to the first electrode; and a second bonding step of controlling the height of the bonding tool based on the measurement result in the second height measuring step, and bonding a wire to the second electrode to connect the first and the second electrodes. Thus, electrodes can be correctly bonded.
    Type: Grant
    Filed: August 22, 2017
    Date of Patent: May 11, 2021
    Assignee: SHINKAWA LTD.
    Inventors: Yusuke Maruya, Yuki Sekine
  • Patent number: 10998267
    Abstract: A wafer-level chip-size package includes a semiconductor structure. A bonding pad is formed over the semiconductor structure, including a plurality of conductive segments. A conductive component is formed over the semiconductor structure, being adjacent to the bonding pad. A passivation layer is formed, exposing a portions of the conductive segments of the first bonding pad. A conductive redistribution layer is formed over the portions of the conductive segments of the first bonding pad exposed by the passivation layer. A planarization layer is formed over the passivation layer and the conductive redistribution layer, exposing a portion of the conductive redistribution layer. A UBM layer is formed over the planarization layer and the portion of the conductive redistribution layer exposed by the planarization layer. A conductive bump is formed over the UBM layer.
    Type: Grant
    Filed: October 6, 2016
    Date of Patent: May 4, 2021
    Assignee: MediaTek Inc.
    Inventors: Yan-Liang Ji, Ming-Jen Hsiung
  • Patent number: 10991647
    Abstract: A printed circuit board including: an insulating material having a bump pad embedded in a first surface thereof; a first insulating layer stacked on the first surface of the insulating material and including an opening portion exposing the bump pad; a second insulating layer stacked on the first insulating layer and including a first cavity exposing the opening portion; and a bump disposed on the bump pad in the opening portion.
    Type: Grant
    Filed: October 21, 2019
    Date of Patent: April 27, 2021
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Yoong Oh, Sang-Hoon Kim, Hea-Sung Kim, Gyu-Mook Kim, Young-Kuk Ko
  • Patent number: 10991677
    Abstract: A semiconductor package includes: a first semiconductor chip in which a through-electrode is provided; a second semiconductor chip connected to a top surface of the first semiconductor chip; a first connection bump attached to a bottom surface of the first semiconductor chip and including a first pillar structure and a first solder layer, and a second connection hump located between the first semiconductor chip and the second semiconductor chip, configured to electrically connect the first semiconductor chip and the second semiconductor chip, and including a second pillar structure and a second solder layer.
    Type: Grant
    Filed: April 14, 2020
    Date of Patent: April 27, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sun-kyoung Seo, Cha-jea Jo, Soo-hyun Ha
  • Patent number: 10985031
    Abstract: Provided are a semiconductor device including an interposer having a relatively thin thickness without a through silicon via and a method of manufacturing the same. The method of manufacturing a semiconductor device includes forming an interposer including a redistribution layer and a dielectric layer on a dummy substrate, connecting a semiconductor die to the redistribution layer facing an upper portion of the interposer, encapsulating the semiconductor die by using an encapsulation, removing the dummy substrate from the interposer, and connecting a bump to the redistribution layer facing a lower portion of the interposer.
    Type: Grant
    Filed: May 21, 2019
    Date of Patent: April 20, 2021
    Assignee: Amkor Technology Singapore Holding Pte. Ltd.
    Inventors: Won Chul Do, Doo Hyun Park, Jong Sik Paek, Ji Hun Lee, Seong Min Seo
  • Patent number: 10985154
    Abstract: A multichip package comprising: a first chip package comprising a first semiconductor IC chip, a first polymer layer in a space beyond and extending from a sidewall of the first semiconductor IC chip, a first through package via in the first polymer layer, and a first interconnection scheme under the first semiconductor IC chip, first polymer layer and first through package via, wherein the first semiconductor IC chip comprises a plurality of volatile memory cells configured to store first data associated with a plurality of resulting values for a look-up table (LUT) and a selection circuit configured to select, in accordance with a first input data set thereof, a data from a second input data set thereof as an output data for the logic operation; a first metal bump under the first chip package; and a non-volatile memory IC chip over the first chip package, wherein the non-volatile memory IC chip comprises a plurality of first non-volatile memory cells configured to store second data associated with the plura
    Type: Grant
    Filed: July 1, 2020
    Date of Patent: April 20, 2021
    Assignee: iCometrue Company Ltd.
    Inventors: Jin-Yuan Lee, Mou-Shiung Lin
  • Patent number: 10978655
    Abstract: A semiconductor device includes a first conductive pattern at an upper portion of a first insulating interlayer on a first substrate, a first plurality of conductive nanotubes (CNTs) extending vertically, a second conductive pattern at a lower portion of a second insulating interlayer beneath a second substrate, and a second plurality of CNTs extending vertically. A lower surface of the second insulating interlayer contacts an upper surface of the first insulating interlayer. At least a portion of a sidewall of each of the first plurality of CNTs is covered by the first conductive pattern, and at least a portion of a sidewall of each of the second plurality of CNTs is covered by the second conductive pattern. The first and second conductive patterns vertically face each other, and at least one of the first plurality of CNTs and at least one of the second plurality of CNTs contact each other.
    Type: Grant
    Filed: September 5, 2019
    Date of Patent: April 13, 2021
    Inventors: Yi-Koan Hong, Kwang-Jin Moon, Nae-In Lee, Ho-Jin Lee
  • Patent number: 10971442
    Abstract: Embodiments include forming a die, the die including a pad and a passivation layer over the pad. A via is formed to the pad through the passivation layer. A solder cap is formed on the via, where a first material of the solder cap flows to the sidewall of the via. In some embodiments, the via is encapsulated in a first encapsulant, where the first encapsulant is a polymer or molding compound selected to have a low co-efficient of thermal expansion and/or low curing temperature. In some embodiments, the first material of the solder cap is removed from the sidewall of the via by an etching process and the via is encapsulated in a first encapsulant.
    Type: Grant
    Filed: February 1, 2019
    Date of Patent: April 6, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Yun Chen Hsieh, Hui-Jung Tsai, Hung-Jui Kuo
  • Patent number: 10971208
    Abstract: A semiconductor device includes a first die connected to a first channel, the first die comprising a first memory chip; and a second die connected to a second channel, the second die comprising a second memory chip, the first and second channels being independent of each other and a storage capacity and a physical size of the second die being the same as those of the first die. The first and second dies are disposed in one package, and the package includes an interconnection circuit disposed between the first die and the second die to transfer signals between the first memory chip and the second memory chip.
    Type: Grant
    Filed: January 6, 2020
    Date of Patent: April 6, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jaehyung Lee, JungSik Kim, Youngdae Lee, Duyeul Kim, Sungmin Yim, Kwangil Park, Chulsung Park
  • Patent number: 10964667
    Abstract: A semiconductor device, and a method of forming the device, are provided. The semiconductor device includes a first die having a first plurality of contact pads and a second die having a second plurality of contact pads. A substrate is bonded to a first contact pad of the first plurality of contact pads and a first contact pad of the second plurality of contact pads in a face-to-face orientation with the first die and the second die. A first through via extends through the substrate. Molding material is interposed between the first die, the second die and the substrate, the molding material extending along sidewalls of the first die, the second die, and the substrate. A second through via is positioned over a second contact pad of the first plurality of contact pads, the second through via extending through the molding material.
    Type: Grant
    Filed: September 12, 2019
    Date of Patent: March 30, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Ming Chen, Hsien-Pin Hu, Shang-Yun Hou, Wen-Hsin Wei
  • Patent number: 10964553
    Abstract: A manufacturing method of a semiconductor device includes mounting a semiconductor element on a first electrode disposed on a first surface of a substrate; preparing a metal plate including a main body part and a projection part; mounting the metal plate on the first surface side of the substrate, by joining the projection part to a second electrode that is disposed on the first surface of the substrate; sealing the semiconductor element and the projection part with a sealing resin; and forming an electrode terminal made of a base end part that is connected to the second electrode and has a side surface that is covered by the sealing resin, and a tip end part that is integrally formed with the base end part and that projects from a front surface of the sealing resin, by etching the main body part excluding a portion overlapping with the projection part.
    Type: Grant
    Filed: October 7, 2019
    Date of Patent: March 30, 2021
    Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventor: Tetsuichiro Kasahara
  • Patent number: 10957610
    Abstract: An integrated circuit component includes a semiconductor substrate, conductive pads, a passivation layer and conductive vias. The semiconductor substrate has an active surface. The conductive pads are located on the active surface of the semiconductor substrate and electrically connected to the semiconductor substrate, and the conductive pads each have a contact region and a testing region, where in each of the conductive pads, an edge of the contact region is in contact with an edge of the testing region. The passivation layer is located on the semiconductor substrate, where the conductive pads are located between the semiconductor substrate and the passivation layer, and the testing regions and the contact regions of the conductive pads are exposed by the passivation layer. The conductive vias are respectively located on the contact regions of the conductive pads.
    Type: Grant
    Filed: October 9, 2019
    Date of Patent: March 23, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tzuan-Horng Liu, Chao-Hsiang Yang, Hsien-Wei Chen, Ming-Fa Chen
  • Patent number: 10947150
    Abstract: A system includes a stress-engineered substrate comprising at least one tensile stress layer having a residual tensile stress and at least one compressive stress layer having a residual compressive stress. The at least one tensile layer and the at least one compressive layer are coupled such that the at least one tensile stress layer and the at least one compressive stress layer are self-equilibrating. At least one functional device is disposed on the stress-engineered substrate. The stress-engineered substrate is configured to fracture in response to energy applied to the substrate. Fracturing the stress-engineered substrate also fractures the functional device. The system includes at least one decoy device. Fragments of the decoy device are configured to obscure one or more physical characteristics of the functional device and/or one or more functional characteristics of the functional device after the functional device is fractured.
    Type: Grant
    Filed: December 3, 2018
    Date of Patent: March 16, 2021
    Assignee: Palo Alto Research Center Incorporated
    Inventors: Scott J. Limb, Patrick Murphy
  • Patent number: 10943886
    Abstract: Implementations of a method of forming semiconductor packages may include: providing a wafer having a plurality of devices, etching one or more trenches on a first side of the wafer between each of the plurality of devices, applying a molding compound to the first side of the wafer to fill the one or more trenches; grinding a second side of the wafer to a desired thickness, and exposing the molding compound included in the one or more trenches. The method may include etching the second side of the wafer to expose a height of the molding compound forming one or more steps extending from the wafer, applying a back metallization to a second side of the wafer, and singulating the wafer at the one or more steps to form a plurality of semiconductor packages. The one or more steps may extend from a base of the back metallization.
    Type: Grant
    Filed: April 27, 2018
    Date of Patent: March 9, 2021
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Eiji Kurose
  • Patent number: 10943884
    Abstract: Various aspects of this disclosure provide a method of manufacturing an electronic device and an electronic device manufactured thereby. As a non-limiting example, various aspects of this disclosure provide a method of manufacturing an electronic device, and an electronic device manufactured thereby, that utilizes ink to form an intermetallic bond between respective conductive interconnection structures of a semiconductor die and a substrate.
    Type: Grant
    Filed: March 23, 2020
    Date of Patent: March 9, 2021
    Assignee: Amkor Technology Singapore Holding Pte. Ltd.
    Inventors: Hwan Kyu Kim, Dae Gon Kim, Tae Kyeong Hwang, Ji Young Chung, Kwangmo Chris Lim
  • Patent number: 10937733
    Abstract: An insulating film (2) is provided on a base material (1). The insulating film (2) is a compressive film in which a stress is applied in a direction of peeling away from the base material at a central portion. A recess (3) is formed in the central portion of the insulating film (2) so that a thickness is partially reduced.
    Type: Grant
    Filed: April 25, 2017
    Date of Patent: March 2, 2021
    Assignee: Mitsubishi Electric Corporation
    Inventor: Takeshi Miura
  • Patent number: 10930609
    Abstract: A method of the present invention includes preparing a substrate having a surface on which a electrode pad is formed, forming a resist layer on the substrate, the resist layer having an opening on the electrode pad, filling conductive paste in the opening of the resist layer; sintering the conductive paste in the opening to form a conductive layer which covers a side wall of the resist layer and a surface of the electrode pad in the opening, a space on the conductive layer leading to the upper end of the opening being formed, filling solder in the space on the conductive layer and removing the resist layer.
    Type: Grant
    Filed: January 16, 2020
    Date of Patent: February 23, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Toyohiro Aoki, Takashi Hisada, Eiji Nakamura
  • Patent number: 10930610
    Abstract: A semiconductor chip includes a substrate having a low-k material layer. An electrode pad is disposed the substrate. A first protection layer at least partially surrounds the electrode pad. The first protection layer includes a first opening at an upper portion thereof. A buffer pad is electrically connected to the electrode pad. A second protection layer at least partially surrounds the buffer pad. The second protection layer includes a second opening at an upper portion thereof. A pillar layer and a solder layer are sequentially stacked on the buffer pad. A thickness of the buffer pad is greater than a thickness of the electrode pad. A width of the first opening in a first direction parallel to an upper surface of the semiconductor substrate is equal to or greater than a width of the second opening in the first direction.
    Type: Grant
    Filed: February 25, 2019
    Date of Patent: February 23, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD
    Inventors: Jin-Kuk Bae, Hyun-Soo Chung, Han-Sung Ryu, In-Young Lee, Chan-Ho Lee
  • Patent number: 10930633
    Abstract: A method of forming a package includes bonding a device die to an interposer wafer, with the interposer wafer including metal lines and vias, forming a dielectric region to encircle the device die, and forming a through-via to penetrate through the dielectric region. The through-via is electrically connected to the device die through the metal lines and the vias in the interposer wafer. The method further includes forming a polymer layer over the dielectric region, and forming an electrical connector. The electrical connector is electrically coupled to the through-via through a conductive feature in the polymer layer. The interposer wafer is sawed to separate the package from other packages.
    Type: Grant
    Filed: September 4, 2018
    Date of Patent: February 23, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jie Chen, Hsien-Wei Chen, Ming-Fa Chen, Chen-Hua Yu
  • Patent number: 10930611
    Abstract: An integrated circuit assembly having an improved solder connection, and methods for fabricating the same are provided that utilize platelets within the solder connections to inhibit solder connection failure, thus providing a more robust solder interface. In one example, an integrated circuit assembly is provided that includes a package substrate having a first plurality of contact pads exposed on a first surface of the package substrate and a second plurality of contact pads exposed on a second surface of the package substrate. The second plurality of contact pads have a pitch that is greater than a pitch of the first plurality of contact pads. Interconnect circuitry is disposed in the package substrate and couples the first and second pluralities of contact pads. At least a first contact pad of the second plurality of contact pads includes a solder ball disposed directly in contact with a palladium layer.
    Type: Grant
    Filed: July 26, 2019
    Date of Patent: February 23, 2021
    Assignee: XILINX, INC.
    Inventors: Jaspreet Singh Gandhi, Tien-Yu Lee
  • Patent number: 10923429
    Abstract: A multi-chip package includes a substrate (110) having a first side (111), an opposing second side (112), and a third side (213) that extends from the first side to the second side, a first die (120) attached to the first side of the substrate and a second die (130) attached to the first side of the substrate, and a bridge (140) adjacent to the third side of the substrate and attached to the first die and to the second die. No portion of the substrate is underneath the bridge. The bridge creates a connection between the first die and the second die. Alternatively, the bridge may be disposed in a cavity (615, 915) in the substrate or between the substrate and a die layer (750). The bridge may constitute an active die and may be attached to the substrate using wirebonds (241, 841, 1141, 1541).
    Type: Grant
    Filed: July 27, 2020
    Date of Patent: February 16, 2021
    Assignee: Intel Corporation
    Inventors: Henning Braunisch, Chia-Pin Chiu, Aleksandar Aleksov, Hinmeng Au, Stefanie M. Lotz, Johanna M. Swan, Sujit Sharan
  • Patent number: 10916519
    Abstract: A method includes placing a package component over a carrier, encapsulating the package component in an encapsulant, and forming a connection structure over and electrically coupling to the package component. The formation of the connection structure includes forming a first via group over and electrically coupling to the package component, forming a first conductive trace over and contacting the first via group, forming a second via group overlying and contacting the first conductive trace, wherein each of the first via group and the second via group comprises a plurality of vias, forming a second conductive trace over and contacting the second via group, forming a top via overlying and contacting the second conductive trace, and forming an Under-Bump-Metallurgy (UBM) over and contacting the top via.
    Type: Grant
    Filed: October 11, 2018
    Date of Patent: February 9, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien-Hsun Chen, Jiun Yi Wu, Chien-Hsun Lee, Chung-Shi Liu
  • Patent number: 10917965
    Abstract: A display panel includes: a substrate including a display area and a peripheral area outside the display area; and a first conductive layer in the peripheral area, an entire upper surface of which is exposed to an outside of the display device. The first conductive layer includes a main part and a plurality of protrusions protruding from the main part in a direction parallel to an upper surface of the substrate.
    Type: Grant
    Filed: September 26, 2019
    Date of Patent: February 9, 2021
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Hyunae Park, Wonkyu Kwak, Dongsoo Kim, Jieun Lee, Soyoung Lee, Wonmi Hwang
  • Patent number: 10910344
    Abstract: An integrated circuit and a method for designing an IC wherein the base or host chip is bonded to smaller chiplets via DBI technology. The bonding of chip to chiplet creates an uneven or multi-level surface of the overall chip requiring a releveling for future bonding. The uneven surface is built up with plating of bumps and subsequently releveled with various methods including planarization.
    Type: Grant
    Filed: June 22, 2018
    Date of Patent: February 2, 2021
    Assignee: Xcelsis Corporation
    Inventors: Javier A. Delacruz, Belgacem Haba, Cyprian Emeka Uzoh, Rajesh Katkar, Ilyas Mohammed
  • Patent number: 10903343
    Abstract: A semiconductor device includes an HBT; emitter wiring which is connected to an emitter electrode of the HBT and covers the HBT; a passivation film having an opening on the HBT in plan view; a UBM layer which is connected to the emitter wiring through the opening and made of a refractory metal with a thickness of 300 nm or more; and a pillar bump which is arranged on the UBM layer and includes a metal post and a solder layer. The UBM layer serves as a stress relaxation layer, thereby relaxing stress on the HBT due to a difference in thermal expansion coefficient between a GaAs-based material of each layer constituting the HBT and the pillar bump.
    Type: Grant
    Filed: January 28, 2020
    Date of Patent: January 26, 2021
    Assignee: Murata Manufacturing Co., Ltd.
    Inventor: Atsushi Kurokawa
  • Patent number: 10894935
    Abstract: Compositions for removing silicone resins and methods of thinning a substrate by using the same, as well as related methods, apparatus and systems for facilitating the removal of silicone resins are provided. The compositions for removing silicone resins, may include a heterocyclic solvent and an alkyl ammonium fluoride salt represented by a formula, (R)4N+F?, wherein R is a C1 to C4 linear alkyl group. Silicone resins may be effectively removed by using the compositions since the compositions exhibit an excellent decomposition rate with respect to the silicone resins that remain on a semiconductor substrate in a process of backside grinding of the semiconductor substrate, backside electrode formation, or the like.
    Type: Grant
    Filed: May 18, 2018
    Date of Patent: January 19, 2021
    Assignees: SAMSUNG ELECTRONICS CO., LTD., DONGWOO FINE-CHEM CO., LTD.
    Inventors: In-goo Kang, Sung-bae Kim, Baik-soon Choi, Sue-ryeon Kim, Young-taek Hong, Sang-tae Kim, Kyong-ho Lee, Hyung-pyo Hong, Seong-min Kim
  • Patent number: 10892291
    Abstract: A semiconductor substrate has a back side surface and a front side surface. Metallization levels are provide at the front side surface. Capacitive deep trench isolation structures extend completely through the semiconductor substrate from the front side surface to the back side surface. Each capacitive deep trench isolation structure includes a conductive region insulated from the semiconductor substrate by an insulating liner. The conductive regions at first ends of the plurality of capacitive deep trench isolation structures are electrically connected to a first metallization level by electrical contacts. A bonding pad structure is located at the back side surface of the semiconductor substrate in direct physical and electrical connection to the conductive regions at second ends of the capacitive deep trench isolation structures.
    Type: Grant
    Filed: February 26, 2019
    Date of Patent: January 12, 2021
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Sonarith Chhun, Gregory Imbert
  • Patent number: 10892241
    Abstract: To provide a substrate device, an electronic apparatus, and a method for manufacturing a substrate device that can make large the gap between a semiconductor substrate and a wiring substrate by making the height of a solder ball high. A substrate device includes a substrate; an electrical connection unit provided on the substrate; a metal post provided on the electrical connection unit; and a metal film that is provided in one body from a tip surface to at least part of a side surface of the metal post and of which wettability to a solder material is lower than wettability to the solder material of the metal post.
    Type: Grant
    Filed: May 15, 2017
    Date of Patent: January 12, 2021
    Assignee: SONY CORPORATION
    Inventor: Shigekazu Ishii
  • Patent number: 10892239
    Abstract: The disclosed subject matter relates to a structure and method to improve bond pad reliability of semiconductor devices. According to an aspect of the present disclosure, a bond pad structure is provided that includes a dielectric layer and at least one bond pad in the dielectric layer, wherein the bond pad has a top surface. A passivation layer has an opening over the bond pad, wherein the opening has sidewalls. A low-k barrier layer is covering the sidewalls of the opening and the top surface of the bond pad. Protective structures are formed over the sidewalls of the opening.
    Type: Grant
    Filed: July 10, 2019
    Date of Patent: January 12, 2021
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Ramasamy Chockalingam, Juan Boon Tan, Ian Melville
  • Patent number: 10886218
    Abstract: The presently disclosed programmable fabric die includes a direct fabric die-to-fabric die interconnect interface column disposed in a sector of programmable logic fabric. Each row of the interconnect interface column includes at least one interconnect interface that is electrically coupled to a microbump. The microbump is configured to be electrically coupled to another microbump of another interconnect interface of another fabric die through an interposer. The fabric die may include multiple interconnect interface columns that each extend deep into the sector, enabling low latency connections between the fabric dies and reducing routing congestion. In some embodiments, the fabric die may include interconnect interfaces that are instead distributed throughout logic blocks of the sector.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: January 5, 2021
    Assignee: Intel Corporation
    Inventors: Chee Hak Teh, Chee Seng Leong, Lai Guan Tang, Han Wooi Lim, Hee Kong Phoon
  • Patent number: 10879194
    Abstract: A semiconductor device package includes a substrate, a semiconductor chip, a first ring structure and a second ring structure. The substrate includes a surface. The semiconductor chip is over the surface of the substrate. The first ring structure is over the surface of the substrate. The second ring structure is over the surface of the substrate, wherein the first ring structure is between the semiconductor chip and the second ring structure.
    Type: Grant
    Filed: May 25, 2017
    Date of Patent: December 29, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Jing-Cheng Lin, Li-Hui Cheng, Po-Hao Tsai, Jeh-Yin Chang, Li-Chung Kuo, Hsien-Ju Tsou, Yi Chou, Ying-Ching Shih, Szu-Wei Lu
  • Patent number: 10879224
    Abstract: A package structure, a die and method of forming the same are provided. The package structure includes a die, an encapsulant, a RDL structure, and a conductive terminal. The die has a connector. The connector includes a seed layer and a conductive on the seed layer. The seed layer extends beyond a sidewall of the conductive pillar. The encapsulant is aside the die and encapsulates sidewalls of the die. The RDL structure is electrically connected to the die. The conductive terminal is electrically connected to the die through the RDL structure.
    Type: Grant
    Filed: January 29, 2019
    Date of Patent: December 29, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Yu Chen, An-Jhih Su, Der-Chyang Yeh, Hua-Wei Tseng, Li-Hsien Huang, Ming-Shih Yeh
  • Patent number: 10879208
    Abstract: A chip-on-film includes an insulating film including a bonding region for bonding to an external device, a plurality of interconnections disposed on the insulating film and partially extending into the bonding region, and an integrated circuit (IC) chip disposed on the insulating film so as to be electrically connected to the plurality of interconnections. The chip-on-film further includes a solder resist disposed so as to cover the insulating film excluding the bonding region and so as to cover the plurality of interconnections excluding portions extending into the bonding region, and a stepped portion located between the bonding region and the solder resist. The stepped portion forms a boundary against a flow of the solder resist into the bonding region.
    Type: Grant
    Filed: August 6, 2019
    Date of Patent: December 29, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Jae Min Jung
  • Patent number: 10872834
    Abstract: Integrated circuit (IC) structures with extended conductive pathways, as well as related structures, devices, and methods, are disclosed herein. For example, in some embodiments, an IC structure may include a die having a device side and an opposing back side; a mold compound disposed at the back side; and a conductive pathway extending into the die from the back side and extending into the mold compound from the back side.
    Type: Grant
    Filed: December 26, 2019
    Date of Patent: December 22, 2020
    Assignee: Intel Corporation
    Inventor: Yen Hsiang Chew
  • Patent number: 10872863
    Abstract: A semiconductor package includes a connection member having a first surface and a second surface opposing each other and including a first redistribution layer on the second surface and at least one second redistribution layer on a level different from a level of the first redistribution layer; a semiconductor chip on the first surface of the connection member; a passivation layer on the second surface of the connection member, and including openings; UBM layers connected to the first redistribution layer through the openings; and electrical connection structures on UBM layers. An interface between the passivation layer and the UBM layers has a first unevenness surface, an interface between the passivation layer and the first redistribution layer has a second unevenness surface, connected to the first unevenness surface, and the second unevenness surface has a surface roughness greater than a surface roughness of the second redistribution layer.
    Type: Grant
    Filed: December 11, 2018
    Date of Patent: December 22, 2020
    Assignee: SAMSUNG ELECTRONICS CO.. LTD.
    Inventors: Joo Young Choi, Doo Hwan Lee, Da Hee Kim, Jae Hoon Choi, Byung Ho Kim