Bump Leads Patents (Class 257/737)
  • Patent number: 10692791
    Abstract: An electronic component package includes a core member including an insulating layer, and having a first through-hole passing through the insulating layer, a semiconductor chip disposed in the first through-hole, and having an active surface on which a connection pad is disposed, and an inactive surface opposing the active surface, an encapsulant encapsulating the core member and the semiconductor chip, and filling at least a portion of the first through-hole, a connection member disposed on the core member and the semiconductor chip, and including a redistribution layer electrically connected to the connection pad, a backside metal layer disposed on the encapsulant, and covering at least the inactive surface of the semiconductor chip, and a backside metal via passing through the encapsulant, and connecting the backside metal layer to one side of the insulating layer. The backside metal via is in contact with the one side of the insulating layer.
    Type: Grant
    Filed: November 1, 2018
    Date of Patent: June 23, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Akihisa Kuroyanagi, Jun Woo Myung, Jae Kul Lee
  • Patent number: 10685948
    Abstract: Double side mounted package structures and memory modules incorporating such double side mounted package structures are described in which memory packages are mounted on both sides of a module substrate. A routing substrate is mounted to a bottom side of the module substrate to provide general purpose in/out routing and power routing, while signal routing from the logic die to double side mounted memory packages is provided in the module routing. In an embodiment, module substrate is a coreless module substrate and may be thinner than the routing substrate.
    Type: Grant
    Filed: November 29, 2018
    Date of Patent: June 16, 2020
    Assignee: Apple Inc.
    Inventors: Chonghua Zhong, Jun Zhai, Kunzhong Hu
  • Patent number: 10685933
    Abstract: A thermal bonding sheet includes a layer, in which an average area of a pore portion in a cross section of the layer after being heated at a heating rate of 1.5° C./sec from 80° C. to 300° C. under pressure of 10 MPa, and then held at 300° C. for 2.5 minutes is in a range of 0.005 ?m2 to 0.5 ?m2.
    Type: Grant
    Filed: September 28, 2016
    Date of Patent: June 16, 2020
    Assignee: NITTO DENKO CORPORATION
    Inventors: Yuki Sugo, Nao Kamakura
  • Patent number: 10672752
    Abstract: A semiconductor package and a manufacturing method for the semiconductor package are provided. The semiconductor package has a redistribution layer, at least one die over the redistribution layer, through interlayer vias on the redistribution layer and aside the die and a molding compound encapsulating the die and the through interlayer vias disposed on the redistribution layer. The semiconductor package has connectors connected to the through interlayer vias and a protection film covering the molding compound and the die. The protection film is formed by a printing process.
    Type: Grant
    Filed: October 11, 2018
    Date of Patent: June 2, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Li-Hui Cheng, Jing-Cheng Lin, Po-Hao Tsai
  • Patent number: 10672723
    Abstract: Some embodiments relate to a semiconductor package. The package includes a redistribution layer (RDL), and a first semiconductor die disposed over the RDL. The first semiconductor die includes a plurality of contact pads electrically coupled to the RDL. The RDL enables fan-out connection of the first semiconductor die. A die package is disposed over the first semiconductor die and over the RDL. The die package is coupled to a first surface of the RDL by a plurality of conductive bump structures. The plurality of conductive bump structures laterally surround the plurality of contact pads and have uppermost surfaces that are level with an uppermost surface of the first semiconductor die.
    Type: Grant
    Filed: April 24, 2019
    Date of Patent: June 2, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jing-Cheng Lin, Chin-Chuan Chang, Jui-Pin Hung
  • Patent number: 10665565
    Abstract: The present disclosure, in some embodiments, relates to an integrated chip structure. The integrated chip structure includes a bump structure disposed on a first substrate and a molding compound in physical contact with the bump structure. The bump structure protrudes from the molding compound. A conductive region is on a second substrate and contacts the bump structure. A no-flow underfill (NUF) material is vertically between the molding compound and the second substrate and laterally surrounds the bump structure. The NUF material is separated from the molding compound.
    Type: Grant
    Filed: December 17, 2018
    Date of Patent: May 26, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hung-Jen Lin, Tsung-Ding Wang, Chien-Hsiun Lee, Wen-Hsiung Lu, Ming-Da Cheng, Chung-Shi Liu
  • Patent number: 10658318
    Abstract: A bump structure with a barrier layer, and a method for manufacturing the bump structure, are provided. In some embodiments, the bump structure comprises a conductive pad, a conductive bump, and a barrier layer. The conductive pad comprises a pad material. The conductive bump overlies the conductive pad, and comprises a lower bump layer and an upper bump layer covering the lower bump layer. The barrier layer is configured to block movement of the pad material from the conductive pad to the upper bump layer along sidewalls of the lower bump layer. In some embodiments, the barrier layer is a spacer lining the sidewalls of the lower bump layer. In other embodiments, the barrier layer is between the barrier layer and the conductive pad, and spaces the sidewalls of the lower bump layer from the conductive pad.
    Type: Grant
    Filed: September 21, 2017
    Date of Patent: May 19, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yao-Wen Chang, Chern-Yow Hsu, Cheng-Yuan Tsai, Kong-Beng Thei
  • Patent number: 10658341
    Abstract: A semiconductor package includes: a first semiconductor chip in which a through-electrode is provided; a second semiconductor chip connected to a top surface of the first semiconductor chip; a first connection bump attached to a bottom surface of the first semiconductor chip and including a first pillar structure and a first solder layer, and a second connection hump located between the first semiconductor chip and the second semiconductor chip, configured to electrically connect the first semiconductor chip and the second semiconductor chip, and including a second pillar structure and a second solder layer.
    Type: Grant
    Filed: June 21, 2019
    Date of Patent: May 19, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sun-kyoung Seo, Cha-jea Jo, Soo-hyun Ha
  • Patent number: 10651142
    Abstract: A micro-connection structure is provided. The micro-connection structure includes an under bump metallurgy (UBM) pad, a bump and an insulating ring. The UBM pad is electrically connected to at least one metallic contact of a substrate. The bump is disposed on the UBM pad and electrically connected with the UBM pad. The insulating ring surrounds the bump and the UBM pad. The bump is separate from the insulating ring with a distance and the bump is isolated by a gap between the insulating ring and the bump.
    Type: Grant
    Filed: May 6, 2019
    Date of Patent: May 12, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wen-Hsiung Lu, Chen-Shien Chen, Chen-En Yen, Cheng-Jen Lin, Chin-Wei Kang, Kai-Jun Zhan
  • Patent number: 10651116
    Abstract: Generally discussed herein are systems, methods, and apparatuses that include conductive pillars that are about co-planar. According to an example, a technique can include growing conductive pillars on respective exposed landing pads of a substrate, situating molding material around and on the grown conductive pillars, removing, simultaneously, a portion of the grown conductive pillars and the molding material to make the grown conductive pillars and the molding material about planar, and electrically coupling a die to the conductive pillars.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: May 12, 2020
    Assignee: Intel Corporation
    Inventors: Robert L. Sankman, Sanka Ganesan
  • Patent number: 10651143
    Abstract: Provided is an electrode like a protruding electrode that is self-standing on a substrate. A conductive paste (202) contains a conductive powder, an alcoholic liquid component, and no adhesives. The conductive powder contains conductive particles having a thickness of 0.05 ?m or more and 0.1 ?m or less and a representative length of 5 ?m or more and 10 ?m or less, the representative length being a maximum diameter in a plane perpendicular to the direction of the thickness. The weight percentage of the alcoholic liquid component relative to the conductive paste is 8% or more and 20% or less.
    Type: Grant
    Filed: April 28, 2017
    Date of Patent: May 12, 2020
    Assignees: SHARP KABUSHIKI KAISHA, OSAKA UNIVERSITY
    Inventors: Tomotoshi Satoh, Hiroya Sato, Katsuaki Suganuma, Aiji Suetake, Shijo Nagao, Jinting Jiu, Seiichiro Kihara
  • Patent number: 10643984
    Abstract: A computing chip can include one or more voltage regulators to decrease a standard voltage, such as twelve volts, to a relatively low operating voltage of its processing cores, typically around one volt. Because the power consumed by the cores can be substantial, such as three hundred watts or more, it is desirable to locate the voltage regulators as close as possible to the cores, to reduce the distances that relatively large currents have to travel in the chip circuitry. The voltage regulators can be embedded within the package, such as in a layered structure, in a layer that electrically connects to the cores. While the cores are typically manufactured using the smallest possible lithographic features, the voltage regulators are less demanding and can instead use relatively large lithographic features, which can be formed using relatively old technology, and can therefore be relatively inexpensive.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: May 5, 2020
    Assignee: Intel Corporation
    Inventor: Edward A. Burton
  • Patent number: 10643954
    Abstract: An integrated circuit package may comprise a multilayer frame package including: a bottom layer; and a magnetic shield layer, including a sub-frame and a magnetic shield disposed within a periphery of the sub-frame; and an integrated circuit die provided on or above the magnetic shield layer of the multilayer frame package.
    Type: Grant
    Filed: August 6, 2018
    Date of Patent: May 5, 2020
    Assignee: Everspin Technologies, Inc.
    Inventor: Angelo V. Ugge
  • Patent number: 10643935
    Abstract: A semiconductor device includes a semiconductor chip including a gate structure, the semiconductor chip having a first region and a second region that surrounds sides of the first region, first solder balls on the first region of the semiconductor chip and containing a first weight percent of silver, second solder balls on the first region of the semiconductor chip and containing a second weight percent of silver greater than the first weight percent, and third solder balls on the second region of the semiconductor chip and containing a third weight percent of silver less than the first weight percent.
    Type: Grant
    Filed: September 10, 2018
    Date of Patent: May 5, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sung Young Yoon, Yong Sang Cho, Sang Su Ha
  • Patent number: 10636715
    Abstract: A semiconductor package including a circuit substrate, an interposer structure, a plurality of dies, and an insulating encapsulant is provided. The interposer structure is disposed on the circuit substrate. The plurality of dies is disposed on the interposer structure, wherein the plurality of dies is electrically connected to the circuit substrate through the interposer structure. The insulating encapsulant is disposed on the circuit substrate, wherein the insulating encapsulant surrounds the plurality of dies and the interposer structure and encapsulates at least the interposer structure, the insulating encapsulant has a groove that surrounds the interposer structure and the plurality of dies, and the interposer structure and the plurality of dies are confined to be located within the groove.
    Type: Grant
    Filed: January 19, 2018
    Date of Patent: April 28, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chun-Cheng Lin, Ching-Hua Hsieh, Chen-Hua Yu, Chung-Shi Liu, Chih-Wei Lin
  • Patent number: 10636760
    Abstract: A semiconductor package may include a base layer, and a redistribution layer on the base layer. The semiconductor package may include a first pattern, a second pattern, and a passivation layer covering the first and second patterns. The semiconductor package may include a semiconductor chip on the base layer, a first connection terminal between the base layer and the semiconductor chip and coupled to one of chip pads of the semiconductor chip, and a mold layer between the base layer and the semiconductor chip. The first connection terminal may extend into the passivation layer and may be coupled to the first pattern. The second pattern may be electrically insulated from the semiconductor chip.
    Type: Grant
    Filed: July 25, 2018
    Date of Patent: April 28, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seunghoon Yeon, Hyoeun Kim, Jongbo Shim, Yonghoe Cho
  • Patent number: 10636729
    Abstract: An integrated circuit (IC) package includes an encapsulation package that contains an integrated circuit die attached to a lead frame. A set of contacts is formed on the package that each have an exposed contact sidewall surface and an exposed contact lower surface. A protective layer of solder wettable material covers each contact sidewall surface.
    Type: Grant
    Filed: June 19, 2017
    Date of Patent: April 28, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Daiki Komatsu, Makoto Shibuya
  • Patent number: 10636745
    Abstract: A semiconductor package device comprises an electronic component, a conductive bump and a first conductive layer. The electronic component has a top surface. The conductive bump is disposed on the top surface of the electronic component. The conductive bump includes a main body and a protruding portion. The first conductive layer covers a portion of the protruding portion. The first conductive layer has a first upper surface and a second upper surface. The first upper surface and the second upper surface are not coplanar.
    Type: Grant
    Filed: September 27, 2017
    Date of Patent: April 28, 2020
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Jen-Kuang Fang, Wen-Long Lu
  • Patent number: 10638604
    Abstract: A printed circuit board (PCB) includes a first aluminum layer, having a first thickness, electrically insulated with a coating of alumina applied to a surface of the first aluminum layer; a second aluminum layer, having a second thickness that is different than the first thickness, insulated with a coating of alumina applied to a surface of the second aluminum layer; and a conductive layer bonded to the coating of alumina on the first aluminum layer, the coating of alumina on the second aluminum layer, or both.
    Type: Grant
    Filed: June 19, 2019
    Date of Patent: April 28, 2020
    Assignee: BORGWARNER, INC.
    Inventors: Jeffrey Carter, Lathom Alexander Louco
  • Patent number: 10636761
    Abstract: Provided is a method of fabricating a semiconductor package. The method includes preparing a package substrate having a substrate pad, and mounting a semiconductor chip on the substrate pad. Mounting the semiconductor chip includes forming a resin layer containing a solder and reducing agent granules having a first capsule layer, between a chip pad of the semiconductor chip and the substrate pad, and bonding the chip pad to the substrate pad using laser irradiated to the semiconductor chip.
    Type: Grant
    Filed: August 28, 2018
    Date of Patent: April 28, 2020
    Assignee: Electronics and Telecommunications Reearch Institute
    Inventors: Kwang-Seong Choi, Yong-Sung Eom, Keon-Soo Jang, Seok Hwan Moon, Hyun-Cheol Bae, Ieeseul Jeong, Wagno Alves Braganca Junior
  • Patent number: 10638614
    Abstract: A semiconductor package module is provided. The semiconductor package module may prevent dropout of a large-scale device from a module substrate by improving bonding strength between the module substrate and a part, and perform assembling parts on a top surface and a bottom surface of the module substrate, simultaneously. The semiconductor package module includes: a module substrate; at least one first electric/electronic device mounted on the module substrate by using surface mount technology (SMT); a plurality of passive devices mounted on the module substrate; and at least one second electric/electronic device mounted on the module substrate by using SMT and a resin film adhesive, the at least one second electric/electronic device having a size or a weight greater than a size or a weight of the at least one first electric/electronic device.
    Type: Grant
    Filed: August 26, 2018
    Date of Patent: April 28, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyuk-jin Lee, Kyu-deuk Kim, Jae-young Hong
  • Patent number: 10636747
    Abstract: A semiconductor package structure includes a first redistribution layer, a second redistribution layer and an interconnecting structure. The first redistribution layer has a first surface and a second surface opposite to each other. The second redistribution layer is disposed over the first surface of the first redistribution layer, wherein the second redistribution layer has a third surface and a fourth surface opposite to each other, and the third surface facing the first surface. The interconnecting structure is disposed between and electrically connected to the first redistribution layer and the second redistribution layer, wherein the interconnecting structure comprises a conductive post and a conductive bump stacked to each other.
    Type: Grant
    Filed: June 11, 2018
    Date of Patent: April 28, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Jui-Pin Hung, Feng-Cheng Hsu, Shuo-Mao Chen, Shin-Puu Jeng, De-Dui Marvin Liao
  • Patent number: 10629556
    Abstract: A composite bump includes a plurality of first bumps that is metal-bonded to an electrode pad of a semiconductor chip, and a second bump that is metal-bonded to the plurality of first bumps. A method for forming a composite bump, includes forming a plurality of first bumps to be metal-bonded to an electrode pad of a semiconductor chip, and forming a second bump to be metal-bonded to the plurality of first bumps.
    Type: Grant
    Filed: May 10, 2018
    Date of Patent: April 21, 2020
    Assignee: FUJITSU LIMITED
    Inventors: Takashi Kubota, Takayoshi Matsumura, Naoaki Nakamura
  • Patent number: 10629797
    Abstract: A structure has a first substrate bonded to a first under-bump metallization (UBM) structure, the first UBM structure comprising a first bonding region laterally surrounded by a first superconducting region. A second substrate is bonded to a second under-bump metallization (UBM) structure, the second UBM structure comprising a second bonding region laterally surrounded by a second superconducting region; and a superconducting solder material joins the first UBM structure to the second UBM structure.
    Type: Grant
    Filed: December 27, 2018
    Date of Patent: April 21, 2020
    Assignee: International Business Machines Corporation
    Inventors: David W. Abraham, John M. Cotte, Eric P. Lewandowski
  • Patent number: 10629522
    Abstract: A semiconductor package including at least one semiconductor device, a first redistribution layer, a first molding compound, a second molding compound, conductive vias and a second redistribution layer. The first redistribution layer is disposed beneath the semiconductor device and electrically connected to the semiconductor device. The first molding compound is disposed over the first redistribution layer and surrounds the semiconductor device. The second molding compound surrounds the first redistribution layer and at least a part of the first molding compound. The conductive vias extend through the second molding compound. The second redistribution layer is disposed on a surface of the second molding compound away from the first redistribution layer. The second redistribution layer is electrically connected to the first redistribution layer through the conductive vias.
    Type: Grant
    Filed: June 6, 2019
    Date of Patent: April 21, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Shing-Yih Shih
  • Patent number: 10622333
    Abstract: A microelectronic package may include stacked microelectronic dice, wherein a first microelectronic die is attached to a microelectronic substrate, and a second microelectronic die is stacked over at least a portion of the first microelectronic die, wherein the microelectronic substrate includes a plurality of pillars extending therefrom, wherein the second microelectronic die includes a plurality of pillars extending therefrom in a mirror-image configuration to the plurality of microelectronic substrate pillars, and wherein the second microelectronic die pillars are attached to microelectronic substrate pillars with an attachment material.
    Type: Grant
    Filed: August 28, 2015
    Date of Patent: April 14, 2020
    Assignee: Intel IP Corporation
    Inventor: Richard Patten
  • Patent number: 10622223
    Abstract: A semiconductor device includes a substrate including traces, wherein the traces protrude above a top surface of the substrate; a prefill material over the substrate and between the traces, wherein the prefill material directly contacts peripheral surfaces of the traces; a die attached over the substrate; and a wafer-level underfill between the prefill material and the die.
    Type: Grant
    Filed: June 14, 2018
    Date of Patent: April 14, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Shijian Luo, Jonathan S. Hacker
  • Patent number: 10607928
    Abstract: An integrated circuit (IC) device carrier, such as a chip carrier, die carrier, or the like, includes a contact that locally reduces laminate strain within the IC device carrier. One type of contact pad described includes tapered sidewall(s). For example, a positively tapered contact pad includes one or more sidewalls obtusely angled relative to the contact surface of the IC carrier and a negatively tapered contact pad includes one or more sidewalls acutely angled relative to the contact surface of the IC carrier. Another type of contact pad described includes a contact pad connected to one or more pillars. The pillar(s) are also connected to a ring formed within an internal wiring level of the IC device carrier.
    Type: Grant
    Filed: August 1, 2019
    Date of Patent: March 31, 2020
    Assignee: International Business Machines Corporation
    Inventors: Anson J. Call, Sushumna Iruvanti, Shidong Li, Brian W. Quinlan, Kamal K. Sikka, Rui Wang
  • Patent number: 10607905
    Abstract: A semiconductor package includes a package substrate including at least one through-hole in a chip mounting region, a plurality of wiring patterns at a top surface of the package substrate. The wiring patterns include respective extension portions and respective landing pads. At least some of the landing pads obliquely extend toward the through-hole. Conductive bumps are formed on corresponding landing pads to connect to a semiconductor chip mounted on the chip mounting region of the package substrate. A molding material extends between the top surface of the package substrate and the semiconductor chip and fills the through-hole.
    Type: Grant
    Filed: June 14, 2019
    Date of Patent: March 31, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Baek Ki, Tark-Hyun Ko, Kun-Dae Yeom, Yong-Kwan Lee, Keun-Ho Jang
  • Patent number: 10601396
    Abstract: A bulk acoustic wave (BAW) device includes a substrate, a reflector on the substrate, a piezoelectric layer on the reflector and including a first opening through which a portion of the reflector is exposed, an electrode layer on the portion of the reflector exposed through the first opening, a passivation layer on the piezoelectric layer and a portion of the electrode layer and including a second opening through which a portion of the electrode layer is exposed, an under-bump metallization layer on the portion of the electrode layer exposed through the second opening and extending over the second opening and the first opening on the passivation layer, and a copper pillar structure on the under-bump metallization layer such that the entirety of the under-bump metallization layer is covered by the copper pillar structure.
    Type: Grant
    Filed: February 24, 2017
    Date of Patent: March 24, 2020
    Assignee: Qorvo US, Inc.
    Inventors: Paul Stokes, Vishwavasu Potdar
  • Patent number: 10593638
    Abstract: Methods and apparatus are described for enabling copper-to-copper (Cu—Cu) bonding at reduced temperatures (e.g., at most 200° C.) by significantly reducing Cu oxide formation. These techniques provide for faster cycle time and entail no extraordinary measures (e.g., forming gas). Such techniques may also enable longer queue (Q) or staging times. One example semiconductor structure generally includes a semiconductor layer, an adhesion layer disposed above the semiconductor layer, an anodic metal layer disposed above the adhesion layer, and a cathodic metal layer disposed above the anodic metal layer. An oxidation potential of the anodic metal layer may be greater than an oxidation potential of the cathodic metal layer. Such a semiconductor structure may be utilized in fabricating IC packages implementing 2.5D or 3D integration.
    Type: Grant
    Filed: March 29, 2017
    Date of Patent: March 17, 2020
    Assignee: XILINX, INC.
    Inventors: Jaspreet Singh Gandhi, Suresh Ramalingam, Henley Liu
  • Patent number: 10583285
    Abstract: In certain embodiments an electrode array for epidural stimulation of the spinal cord is provided where the array comprises a plurality of electrodes disposed on a flexible polymer substrate; said electrodes being electrically connected to one or more lead wires and/or connection points on an electrical connector; where the electrodes of said array are bonded to said polymer so that the electrodes can carry an electrical stimulation signal having a voltage, frequency, and current sufficient to provide epidural stimulation of a spinal cord and/or brain in vivo or in a physiological saline solution, without separation of all or a part of an electrode from the polymer substrate.
    Type: Grant
    Filed: August 27, 2015
    Date of Patent: March 10, 2020
    Assignee: The Regents of the University of California
    Inventors: Wentai Liu, Chih-Wei Chang
  • Patent number: 10586778
    Abstract: An elastic wave element includes a vibrator, an electrode pad, a UBM portion including a first end surface joined to the electrode pad, and a bump joined to a second end surface of the UBM portion. Joint terminals are defined by joining the electrode pad, the UBM portion, and the bump. A shortest distance between a specified joint terminal and remaining joint terminals is an inter-bump distance of the specified joint terminal. Second end surfaces of first and second joint terminal have areas greater than areas of second end surfaces of remaining joint terminals. The inter-bump distance of the first joint terminal is longer than the shortest inter-bump distance of the joint terminals and is the longest of the inter-bump distances. The second joint terminal is spaced the longest inter-bump distance from the first joint terminal.
    Type: Grant
    Filed: October 3, 2018
    Date of Patent: March 10, 2020
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Kenichi Uesaka
  • Patent number: 10580755
    Abstract: A fan-out wafer level multilayer wiring package structure, wherein the package structure comprises a plurality of semiconductor chips, a multilayer interposer, a vertical interconnection interposer, molding materials and a redistribution layer; the back surface of the semiconductor chip is bonded to the back surface of the multilayer wiring interposer with the bonding material, and is placed on the same horizontal plane as the vertical interconnection interposer and packaged as a whole with the molding material, the redistribution layer is provided on the surface of the structure; the semiconductor chip, the multilayer interposer, the conductive material of the vertical interconnection interproser and the solder ball are connected by the conductive metal layer of the redistribution layer to achieve the signal interconnection between the semiconductor chip and the multilayer interposer and the I/O signal transfer of the semiconductor chip.
    Type: Grant
    Filed: July 24, 2018
    Date of Patent: March 3, 2020
    Assignee: The 58th Research Institute of China Electronics Technology Group Corporation
    Inventors: Yong Ji, Rongzhen Zhang, Chongchong Mao
  • Patent number: 10580749
    Abstract: A semiconductor device has a semiconductor die with a plurality of bumps formed over contact pads on a surface of the semiconductor die. The bumps can have a fusible portion and non-fusible portion. A plurality of conductive traces is formed over a substrate with interconnect sites having a width greater than 20% and less than 80% of a width of a contact interface between the bumps and contact pads. The bumps are bonded to the interconnect sites so that the bumps cover a top surface and side surface of the interconnect sites. An encapsulant is deposited around the bumps between the semiconductor die and substrate. The conductive traces have a pitch as determined by minimum spacing between adjacent conductive traces that can be placed on the substrate and the width of the interconnect site provides a routing density equal to the pitch of the conductive traces.
    Type: Grant
    Filed: July 11, 2014
    Date of Patent: March 3, 2020
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventor: Rajendra D. Pendse
  • Patent number: 10573571
    Abstract: A wafer-level chip-scale package includes: a power semiconductor comprising a first semiconductor device formed on a semiconductor substrate, and a second semiconductor device formed on the semiconductor substrate; a common drain electrode connected to the first semiconductor device and the second semiconductor device; a first source metal bump formed on a surface of the first semiconductor device; and a second source metal bump formed on the surface of the second semiconductor device; wherein the first source metal bump, the common drain electrode, and the second source metal bump form a current path in an order of the first source metal bump, the common drain electrode, and the second source metal bump.
    Type: Grant
    Filed: January 4, 2017
    Date of Patent: February 25, 2020
    Assignee: MagnaChip Semiconductor, Ltd.
    Inventors: Myung Ho Park, Beom Su Kim, Sun Hwan Kim
  • Patent number: 10559551
    Abstract: Semiconductor device assemblies with heat transfer structures formed from semiconductor materials are disclosed herein. In one embodiment, a semiconductor device assembly can include a thermal transfer structure formed from a semiconductor substrate. The thermal transfer structure includes an inner region, an outer region projecting from the inner region, and a cavity defined in the outer region by the inner and outer regions. The semiconductor device assembly further includes a stack of first semiconductor dies in the cavity, and a second semiconductor die attached to the outer region of the thermal transfer structure and enclosing the stack of first semiconductor dies within the cavity.
    Type: Grant
    Filed: April 5, 2019
    Date of Patent: February 11, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Sameer S. Vadhavkar, Jaspreet S. Gandhi, James M. Derderian
  • Patent number: 10559540
    Abstract: A fan-out semiconductor package includes a first connection member having a through-hole first and second semiconductor chips disposed in the through-hole, an encapsulant encapsulating the first and second semiconductor chips, a second connection member disposed on at least one side of the first and second semiconductor chips and including a redistribution layer electrically connected to the first and second semiconductor chips, and an insulating via in which at least a portion of the first connection member is removed in a thickness direction and is filled with an insulating material.
    Type: Grant
    Filed: June 8, 2018
    Date of Patent: February 11, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Chang Bo Lee, Joon Seok Oh, Hyun Chul Jung, Jeong Ho Yeo
  • Patent number: 10559464
    Abstract: A method for manufacturing a photoelectric conversion device comprising the steps of fixing a first substrate including a semiconductor layer provided with a photoelectric conversion element, to a second substrate, thinning the first substrate fixed to the second substrate, from the opposite side of the first substrate from the second substrate, fixing the first substrate to a third substrate provided with a semiconductor element such that the third substrate is located on the opposite side of the first substrate from the second substrate, and removing the second substrate after the step of fixing the first substrate to the third substrate.
    Type: Grant
    Filed: May 2, 2017
    Date of Patent: February 11, 2020
    Assignee: Canon Kabushiki Kaisha
    Inventors: Hideshi Kuwabara, Nobutaka Ukigaya
  • Patent number: 10553542
    Abstract: A semiconductor device with EMI shield and a fabricating method thereof are provided. In one embodiment, the semiconductor device includes EMI shield on all six surfaces of the semiconductor device without the use of a discrete EMI lid.
    Type: Grant
    Filed: January 12, 2017
    Date of Patent: February 4, 2020
    Assignee: AMKOR TECHNOLOGY, INC.
    Inventors: Doo Soub Shin, Tae Yong Lee, Kyoung Yeon Lee, Sung Gyu Kim
  • Patent number: 10553561
    Abstract: A method of forming a semiconductor device includes preparing a first semiconductor die package with conductive elements embedded in a molding compound, wherein the conductive elements are exposed on a surface of the molding compound. A top surface of the conductive elements is above or co-planar with a top-most surface of the molding compound. The method further includes providing a second semiconductor die package; and bonding the conductive elements of the first semiconductor die package to contacts on the semiconductor die package.
    Type: Grant
    Filed: August 8, 2016
    Date of Patent: February 4, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Feng Chen, Chun-Hung Lin, Han-Ping Pu, Ming-Da Cheng, Kai-Chiang Wu
  • Patent number: 10553451
    Abstract: A method for manufacturing a semiconductor device and a semiconductor device produced thereby. For example and without limitation, various aspects of this disclosure provide a method for manufacturing a semiconductor device, and a semiconductor device produced thereby, that comprises an interposer without through silicon vias.
    Type: Grant
    Filed: June 25, 2018
    Date of Patent: February 4, 2020
    Assignee: Amkor Technology, Inc.
    Inventors: Dong Jin Kim, Jin Han Kim, Won Chul Do, Jae Hun Bae, Won Myoung Ki, Dong Hoon Han, Do Hyung Kim, Ji Hun Lee, Jun Hwan Park, Seung Nam Son, Hyun Cho, Curtis Zwenger
  • Patent number: 10546829
    Abstract: A method of fabricating a semiconductor package including forming a preliminary first insulating layer including a first opening, curing the preliminary first insulating layer to form a first insulating layer, forming a preliminary second insulating layer on the first insulating layer at least partially filling the first opening. The method includes forming a second opening in the preliminary second insulating layer at least partially overlapping the first opening. A sidewall of the first opening is at least partially exposed during forming the second opening. The preliminary second insulating layer is cured to form a second insulating layer. A barrier metal layer is formed along the sidewall of the first opening and along a sidewall of the second opening. A redistribution conductive pattern is formed on the barrier metal layer. A planarization process is performed to at least partially expose the second insulating layer.
    Type: Grant
    Filed: January 10, 2018
    Date of Patent: January 28, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Youn Ji Min, Seokhyun Lee, Jongyoun Kim, Kyoung Lim Suk, SeokWon Lee
  • Patent number: 10546801
    Abstract: A semiconductor device includes at least one wafer and at least one TSV (through silicon via) structure. The at least one wafer each includes a substrate, an isolation structure, and a conductive pad. The isolation structure is formed in the substrate and extends from a first side of the substrate toward a second side opposite to the first side of the substrate. The conductive pad is formed at a dielectric layer disposed on the first side of the substrate, wherein the conductive pad is electrically connected to an active area in the substrate. The at least one TSV structure penetrates the at least one wafer. The conductive pad contacts a sidewall of the at least one TSV structure, and electrically connects the at least one TSV structure and the active area in the substrate. The isolation structure separates from and surrounds the at least one TSV structure.
    Type: Grant
    Filed: August 16, 2017
    Date of Patent: January 28, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Zhao-Bing Li, Ju-Bao Zhang, Chi Ren
  • Patent number: 10540473
    Abstract: A stacked chip layout includes a central processing chip; and a first active circuit block over the central processing chip. The stacked chip layout further includes a second active circuit block over the first active circuit. A center of the second active circuit block is offset from a center of the first active circuit block, the second active circuit block overlaps the first active circuit block in a partial overlap area, and the second active circuit block exposes a portion of the first active circuit block. The stacked chip layout further includes a local conductive element electrically connecting the first active circuit block to the second active circuit block. The local conductive element is within the partial overlap area.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: January 21, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: Ying-Yu Hsu
  • Patent number: 10542349
    Abstract: The invention relates to the field of micro-electromechanical technology, and more particularly, to a microphone structure with an enhanced back cavity and an electronic device, comprising: a first layer plate, an groove is configured on the first layer plate, wherein an acoustic sensor is installed above the groove by means of a support, and the acoustic sensor is provided with a back cavity facing towards the support, and a through-hole for penetrating through the back cavity and the groove is provided on the support; a second layer plate, covering the first layer plate, wherein an acoustic through-hole is configured on the second layer plate; wherein, the first layer plate and second layer plate form a microphone acoustic cavity.
    Type: Grant
    Filed: May 30, 2018
    Date of Patent: January 21, 2020
    Assignees: Zilltek Technology (Shanghai) Corp., Zilltek Technology Corp.
    Inventor: Jinghua Ye
  • Patent number: 10535626
    Abstract: A method of making an assembly can include juxtaposing a top surface of a first electrically conductive element at a first surface of a first substrate with a top surface of a second electrically conductive element at a major surface of a second substrate. One of: the top surface of the first conductive element can be recessed below the first surface, or the top surface of the second conductive element can be recessed below the major surface. Electrically conductive nanoparticles can be disposed between the top surfaces of the first and second conductive elements. The conductive nanoparticles can have long dimensions smaller than 100 nanometers. The method can also include elevating a temperature at least at interfaces of the juxtaposed first and second conductive elements to a joining temperature at which the conductive nanoparticles can cause metallurgical joints to form between the juxtaposed first and second conductive elements.
    Type: Grant
    Filed: March 27, 2018
    Date of Patent: January 14, 2020
    Assignee: Invensas Corporation
    Inventor: Cyprian Emeka Uzoh
  • Patent number: 10529924
    Abstract: This application discloses a flexible substrate device that includes a flexible substrate and a plurality of electronic devices. The flexible substrate includes a top surface and a bottom surface opposite to the top surface, and the plurality of electronic devices formed on the top surface of the flexible substrate. The bottom surface further includes one or more strong adhesion regions and one or more normal adhesion regions that are distinct from the one or more strong adhesion regions. Each of the one or more strong adhesion regions and the one or more normal adhesion regions are configured to attach to a rigid carrier with first adhesion strength and second adhesion strength, respectively. The first adhesion strength is substantially larger than the second adhesion strength. In some embodiments, the flexible substrate device is a thin film transistor (TFT) device, and the plurality of electronic devices includes a TFT array.
    Type: Grant
    Filed: April 13, 2016
    Date of Patent: January 7, 2020
    Assignee: SHENZHEN ROYOLE TECHNOLOGIES CO. LTD.
    Inventors: Xiaojun Yu, Peng Wei, Ze Yuan, Zihong Liu
  • Patent number: 10529690
    Abstract: An embodiment is a method including bonding a first die to a first side of an interposer using first electrical connectors, bonding a second die to first side of the interposer using second electrical connectors, attaching a first dummy die to the first side of the interposer adjacent the second die, encapsulating the first die, the second die, and the first dummy die with an encapsulant, and singulating the interposer and the first dummy die to form a package structure.
    Type: Grant
    Filed: August 11, 2017
    Date of Patent: January 7, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ying-Ching Shih, Chi-Hsi Wu, Chen-Hua Yu, Chih-Wei Wu, Jing-Cheng Lin, Pu Wang, Szu-Wei Lu
  • Patent number: 10522473
    Abstract: A package includes a device die, a molding material molding the device die therein, a through-via penetrating through the molding material, and an alignment mark penetrating through the molding material. A redistribution line is on a side of the molding material. The redistribution line is electrically coupled to the through-via.
    Type: Grant
    Filed: May 16, 2017
    Date of Patent: December 31, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Li-Hsien Huang, Hsien-Wei Chen, Ching-Wen Hsiao, Der-Chyang Yeh, Shin-Puu Jeng, Chen-Hua Yu