With Textured Surface Patents (Class 257/739)
  • Patent number: 10378105
    Abstract: Embodiments of the invention provide methods for selective deposition on different materials using a surface treatment. According to one embodiment, the method includes providing a substrate containing a first material layer having a first surface and a second material layer having a second surface, and performing a chemical oxide removal process that terminates that second surface with hydroxyl groups. The method further includes modifying the second surface by exposure to a process gas containing a hydrophobic functional group, the modifying substituting the hydroxyl groups on the second surface with the hydrophobic functional group, and selectively depositing a metal-containing layer on the first surface but not on the modified second surface by exposing the substrate to a deposition gas.
    Type: Grant
    Filed: May 31, 2017
    Date of Patent: August 13, 2019
    Assignee: Tokyo Electron Limited
    Inventors: Kai-Hung Yu, Kandabara N. Tapily, Takahiro Hakamata, Subhadeep Kal, Gerrit J. Leusink
  • Patent number: 10269739
    Abstract: Methods of forming connector pad structures, interconnect structures, and structures thereof are disclosed. In some embodiments, a method of forming a connector pad structure includes forming an underball metallization (UBM) pad, and increasing a surface roughness of the UBM pad by exposing the UBM pad to a plasma treatment. A polymer material is formed over a first portion of the UBM pad, leaving a second portion of the UBM pad exposed.
    Type: Grant
    Filed: March 27, 2018
    Date of Patent: April 23, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Lun Chang, Chung-Shi Liu, Hsiu-Jen Lin, Hsien-Wei Chen, Ming-Da Cheng, Wei-Yu Chen
  • Patent number: 10163829
    Abstract: A compound semiconductor substrate has a first main surface parallel to a first direction and a second direction perpendicular to the first direction, a second main surface located on a side opposite to the first main surface, and a recess. The recess has an opening, a bottom surface facing the opening, and a plurality of side surfaces located between the opening and the bottom surface. The side surfaces include at least one first side surface forming an angle of about ? degrees with the bottom surface in the recess and at least one second side surface forming an angle of about ? degrees with the bottom surface in the recess. The total length of edge lines between the first main surface and the at least one first side surface is larger than that of edge lines between the first main surface and the at least one second side surface.
    Type: Grant
    Filed: December 6, 2017
    Date of Patent: December 25, 2018
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Isao Obu, Yasunari Umemoto, Masahiro Shibata
  • Patent number: 10147616
    Abstract: A package frame includes a plurality of unit regions disposed on one surface of the package frame, a peripheral region surrounding the unit regions on the one surface, and a wrinkled structure disposed on the one surface in the peripheral region. A first surface of the wrinkled structure extends from the one surface and is disposed at a different level than the one surface. Each of the unit regions includes a plurality of conductive pads.
    Type: Grant
    Filed: October 26, 2015
    Date of Patent: December 4, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Soojae Park, Geunwoo Kim, Keunho Jang, Younjo Mun
  • Patent number: 10103305
    Abstract: A high-efficiency light-emitting device of the present invention includes: a nitride-based semiconductor laminate layer comprising a first conductive-type semiconductor layer, an active layer, and a second conductive-type semiconductor layer; a substrate comprising a first electrode and a second electrode each connected to the first conductive-type semiconductor layer and the second conductive-type semiconductor layer, a first pad electrode and a second pad electrode each connected with the first electrode and the second electrode, and a first connection pad and a second connection pad each connected with the first pad electrode and the second pad electrode; and a solder positioned between the pad electrodes and the connection pads.
    Type: Grant
    Filed: October 16, 2015
    Date of Patent: October 16, 2018
    Assignee: Seoul Viosys Co., Ltd.
    Inventors: Yeo Jin Yoon, Chung Hoon Lee
  • Patent number: 10083926
    Abstract: A wafer level chip scale package is described. At least one redistribution layer is connected to a wafer through an opening through a first polymer layer to a metal pad on a top surface of the wafer wherein the redistribution layer has a roughened top surface and wherein holes are formed through the at least one redistribution layer in an area where the redistribution layer has an area exceeding 0.2 mm2. At least one UBM layer contacts the at least one redistribution layer through an opening in a second polymer layer wherein the second polymer layer contacts the first polymer layer within the holes promoting cohesion between the first and second polymer layers and wherein the roughened top surface promotes adhesion between the at least one redistribution layer and the second polymer layer.
    Type: Grant
    Filed: December 13, 2017
    Date of Patent: September 25, 2018
    Assignee: Dialog Semiconductor (UK) Limited
    Inventors: Ian Kent, Rajesh Subraya Aiyandra, Jesus Mennen Belonio, Jr., Habeeb Mohiuddin Mohammed, Domingo Jr. Maggay, Robert Lamoon, Ernesto Gutierrez, III
  • Patent number: 9922924
    Abstract: An interposer and a semiconductor package including the interposer are provided. The interposer includes a first dielectric layer, a conductive pillar, a conductive ring, a solder bump, and a redistribution layer. The first dielectric layer has an upper surface and a lower surface. The conductive pillar and the conductive ring are partially embedded in the first dielectric layer. A portion of the conductive pillar protrudes from the lower surface of the first dielectric layer. The conductive ring surrounds the conductive pillar, and a portion of the conductive ring protrudes from the lower surface of the first dielectric layer. The solder bump is disposed on the lower surface of the first dielectric layer, wherein the portion of the conductive pillar and the portion of the conductive ring are embedded in the solder bump. The redistribution layer is disposed on the upper surface of the first dielectric layer.
    Type: Grant
    Filed: December 5, 2016
    Date of Patent: March 20, 2018
    Assignee: Micron Technology, Inc.
    Inventor: Shing-Yih Shih
  • Patent number: 9754894
    Abstract: Provided is a thermosetting sheet for sealing which is used to seal an electronic device. One surface of the sheet has a surface roughness (Ra) of 3 ?m or less before the sheet is cured.
    Type: Grant
    Filed: June 30, 2014
    Date of Patent: September 5, 2017
    Assignee: NITTO DENKO CORPORATION
    Inventors: Chie Iino, Takeshi Matsumura, Goji Shiga, Kosuke Morita
  • Patent number: 9679841
    Abstract: Methods and apparatus for formation of a semiconductor substrate with photoactive dielectric material, embedded traces, a padless skip via extending through two dielectric layers, and a coreless package are provided. In one embodiment, a method for forming a core having a copper layer; laminating the copper layer a photoactive dielectric layer; forming a plurality of trace patterns in the photoactive dielectric layer; plating the plurality of trace patterns to form a plurality of traces; forming an insulating dielectric layer on the photoactive dielectric layer; forming a via through the insulating dielectric layer and the photoactive dielectric layer; forming additional routing patterns on the insulating dielectric layer; removing the core; and applying a solder mask.
    Type: Grant
    Filed: May 13, 2014
    Date of Patent: June 13, 2017
    Assignee: QUALCOMM Incorporated
    Inventors: Houssam Wafic Jomaa, Omar James Bchir, Kuiwon Kang, Chin-Kwan Kim
  • Patent number: 9548282
    Abstract: A semiconductor device and a manufacturing method thereof. The semiconductor device includes a semiconductor substrate (300) provided with a plurality of pads (301), columnar electrodes on the pads (301) and a solder ball (321) provided on the columnar electrode. The columnar electrode comprises a main body (307) and a groove in the main body (307), and an opening of the groove is overlapped with the top surface of the columnar electrode. The solder ball (321) comprises a metal bump (320) arranged on the top of the columnar electrode and a filling part (319) filled in the groove. The solder ball and the columnar electrode form a structure similar to a bolt; thus the binding force between the solder ball and the columnar electrode is improved.
    Type: Grant
    Filed: October 30, 2013
    Date of Patent: January 17, 2017
    Assignee: NANTONG FUJITSU MICROELECTRONICS CO., LTD.
    Inventors: Chang-Ming Lin, Lei Shi, Yujuan Tao
  • Patent number: 9379077
    Abstract: A semiconductor device package and packaging method, the semiconductor device packaging method comprising: providing a chip with a bonding pad formed on the chip surface; forming a passivation layer and a bump on the chip surface, wherein the passivation layer has an opening exposing part of the pad, the bump is located in the opening and the size of the bump is less than the size of the opening; forming a solder ball covering the top surface and the side wall of the bump, and the bottom surface of the opening. The formed semiconductor device package is not easy to form a short circuit. The bonding strength between the solder ball and the bump is high and the performance of the semiconductor device is stable.
    Type: Grant
    Filed: October 30, 2013
    Date of Patent: June 28, 2016
    Assignee: NANTONG FUJITSU MICROELECTRONICS CO., LTD.
    Inventors: Chang-Ming Lin, Lei Shi, Honghui Wang
  • Patent number: 9000566
    Abstract: A compliant monopolar micro device transfer head array and method of forming a compliant monopolar micro device transfer array from an SOI substrate are described. In an embodiment, the micro device transfer head array including a base substrate and a patterned silicon layer over the base substrate. The patterned silicon layer may include a silicon interconnect and an array of silicon electrodes electrically connected with the silicon interconnect. Each silicon electrode includes a mesa structure protruding above the silicon interconnect, and each silicon electrode is deflectable into a cavity between the base substrate and the silicon electrode. A dielectric layer covers a top surface of each mesa structure.
    Type: Grant
    Filed: February 5, 2014
    Date of Patent: April 7, 2015
    Assignee: LuxVue Technology Corporation
    Inventors: Dariusz Golda, Andreas Bibl
  • Publication number: 20150048505
    Abstract: A wiring substrate includes: a substrate layer made of glass or silicon and including: a first surface formed with a first hole; and a second surface formed with a second hole and being opposite to the first surface, wherein the first hole is communicated with the second hole; a connection pad formed in the second hole; a first wiring layer formed in the first hole and electrically connected to the connection pad; a first insulation layer formed on the first surface of the substrate layer to cover the first wiring layer; and a second wiring layer formed on the first insulation layer and electrically connected to the first wiring layer. A diameter of the first hole is gradually decreased from the first surface toward the second surface, and a diameter of the second hole is gradually decreased from the second surface toward the first surface.
    Type: Application
    Filed: October 29, 2014
    Publication date: February 19, 2015
    Inventors: Yuji KUNIMOTO, Naoyuki KOIZUMI
  • Patent number: 8957450
    Abstract: According to one embodiment, a semiconductor light emitting device includes a semiconductor layer, a first electrode, a second electrode, an insulating layer, a first interconnect layer, a second interconnect layer, a first metal pillar, a second metal pillar, a film covering a side face of the first metal pillar and a side face of the second metal pillar, and a resin layer. The semiconductor layer includes a light emitting layer, a first major surface, and a second major surface formed on a side opposite to the first major surface. The film has a solder wettability poorer than a solder wettability of the first metal pillar and a solder wettability of the second metal pillar. The resin layer covers at least part of the film.
    Type: Grant
    Filed: June 24, 2013
    Date of Patent: February 17, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Yoshiaki Sugizaki
  • Patent number: 8946906
    Abstract: To provide a multilayer wiring substrate in which the connection reliability of via conductors is enhanced, via holes are formed in a resin interlayer insulation layer which isolates a lower conductor layer from an upper conductor layer, and via conductors are formed in the via holes for connecting the lower conductor layer and the upper conductor layer. The surface of the resin interlayer insulation layer is a rough surface, and the via holes open at the rough surface of the resin interlayer insulation layer. Stepped portions are formed in opening verge regions around the via holes such that the stepped portions are recessed from peripheral regions around the opening verge regions. The stepped portions are higher in surface roughness than the peripheral regions.
    Type: Grant
    Filed: December 13, 2011
    Date of Patent: February 3, 2015
    Assignee: NGK Spark Plug Co., Ltd.
    Inventor: Shinnosuke Maeda
  • Publication number: 20140374903
    Abstract: The present invention provides a stabilized fine textured metal microstructure that constitutes a durable activated surface usable for bonding a 3D stacked chip. A fine-grain layer that resists self anneal enables metal to metal bonding at moderate time and temperature and wider process flexibility.
    Type: Application
    Filed: September 13, 2014
    Publication date: December 25, 2014
    Inventors: Tien-Jen Cheng, Mukta G. Farooq, John A. Fitzsimmons
  • Patent number: 8912653
    Abstract: A semiconductor wafer has integrated circuits formed thereon and a top passivation layer applied. The passivation layer is patterned and selectively etched to expose contact pads on each semiconductor die. The wafer is exposed to ionized gas causing the upper surface of passivation layer to roughen and to slightly roughen the upper surface of the contact pads. The wafer is cut to form a plurality of semiconductor dies each with a roughened passivation layer. The plurality of semiconductor dies are placed on an adhesive layer and a reconstituted wafer formed. Redistribution layers are formed to complete the semiconductor package having electrical contacts for establishing electrical connections external to the semiconductor package, after which the wafer is singulated to separate the dice.
    Type: Grant
    Filed: December 15, 2011
    Date of Patent: December 16, 2014
    Assignee: STMicroelectronics Pte Ltd.
    Inventors: Kah Wee Gan, Yonggang Jin, Anandan Ramasamy, Yun Liu
  • Patent number: 8890317
    Abstract: An organic light emitting display device includes a first electrode on a substrate, an auxiliary electrode on the substrate, the auxiliary electrode being spaced apart from the first electrode, a protrusion on the auxiliary electrode, a pixel defining layer overlapping end portions of the first electrode and of the auxiliary electrode, the pixel defining layer separating the first electrode from the auxiliary electrode, an organic layer on the first electrode, and a second electrode on the organic layer, the protrusion electrically connecting the second electrode to the auxiliary electrode.
    Type: Grant
    Filed: September 26, 2013
    Date of Patent: November 18, 2014
    Assignee: Samsung Display Co., Ltd.
    Inventors: Young-Mo Koo, Ok-Keun Song, Min-Woo Lee, Jae-Goo Lee
  • Patent number: 8866296
    Abstract: A semiconductor device includes: a semiconductor chip with a plurality of electrode pads disposed at a top surface thereof; a plurality of thin film terminals set apart from one another via respective separator portions, which are located below a bottom surface of the semiconductor chip; an insulating layer disposed between the semiconductor chip and the thin-film terminals; connecting members that connect the electrode pads at the semiconductor chip with the thin-film terminals respectively and a resin layer disposed so as to cover the semiconductor chip, the plurality of thin-film terminals exposed at the semiconductor chip, the separator portions and the connecting members.
    Type: Grant
    Filed: June 24, 2009
    Date of Patent: October 21, 2014
    Assignee: AOI Electronics Co., Ltd.
    Inventors: Takashi Yamaji, Takaaki Kato
  • Patent number: 8860226
    Abstract: A semiconductor device includes a storage node contact plug, a bit line in communication with to the storage node contact plug, and an expansion unit formed on a sidewall of the bit line. Thermal expansion of the expansion unit serves to increase capacitance by ensuring a distance between the bit line and the storage node contact plug, thereby improving a sensing margin. A cell characteristic such as a record recovery time (tWR) may be enhanced.
    Type: Grant
    Filed: January 10, 2012
    Date of Patent: October 14, 2014
    Assignee: Hynix Semiconductor Inc.
    Inventor: Yong Won Seo
  • Patent number: 8796563
    Abstract: In ultrasonic bonding of a metal terminal to a substrate pad, a thin buffer metal layer which is formed of a soft metal or a highly slidable metal is interposed between a terminal edge and a pad so as to prevent direct contact between an end of the terminal and the pad upon bonding. This makes it possible to prevent abrasion and a crack in the pad at the end of the terminal caused by pressure and an ultrasonic wave upon the ultrasonic bonding. This makes it possible to realize a compact bonded structure with high reliability.
    Type: Grant
    Filed: January 29, 2010
    Date of Patent: August 5, 2014
    Assignee: Hitachi Automotive Systems, Ltd.
    Inventors: Ukyo Ikeda, Masato Nakamura, Shiro Yamashita
  • Publication number: 20140191398
    Abstract: A device including a first semiconductor layer and a contact to the first semiconductor layer is disclosed. An interface between the first semiconductor layer and the contact includes a first roughness profile having a characteristic height and a characteristic width. The characteristic height can correspond to an average vertical distance between crests and adjacent valleys in the first roughness profile. The characteristic width can correspond to an average lateral distance between the crests and adjacent valleys in the first roughness profile.
    Type: Application
    Filed: January 9, 2014
    Publication date: July 10, 2014
    Applicant: SENSOR ELECTRONIC TECHNOLOGY, INC.
    Inventors: Remigijus Gaska, Maxim S. Shatalov, Alexander Lunev, Alexander Dobrinsky, Jinwei Yang, Michael Shur
  • Patent number: 8766441
    Abstract: Solder on slot connections in package on package structures. An apparatus includes a substrate having a front side surface and a back side surface; a first passivation layer disposed over at least one of the front side and back side surfaces; at least one via opening formed in the first passivation layer; a conductor layer disposed over the first passivation layer, coupled to the at least one via and forming a conductive trace on the surface of the first passivation layer; a second passivation layer formed over the conductor layer; and at least one slot opening formed in the second passivation layer and exposing a portion of the conductive trace for receiving a solder connector. In additional embodiments the substrate may be a semiconductor wafer. Methods for forming the structures are disclosed.
    Type: Grant
    Filed: March 14, 2012
    Date of Patent: July 1, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei Sen Chang, Ching-Wen Hsiao, Chen-Shien Chen
  • Publication number: 20140151882
    Abstract: The three-dimensional integrated circuit has a first semiconductor chip and a second semiconductor chip stacked on the first semiconductor chip, wherein each of the first semiconductor chip and the second semiconductor chip is provided with a power supply wiring layer which has a wiring pattern structure for stably supplying a power supply voltage to an internal circuit of the semiconductor chip, and a ground wiring layer in succession, and one of the first semiconductor chip and the second semiconductor chip further includes a second ground wiring layer or a second power supply wiring layer on a surface facing to the other semiconductor chip.
    Type: Application
    Filed: April 10, 2013
    Publication date: June 5, 2014
    Inventor: Takashi Morimoto
  • Patent number: 8742554
    Abstract: A circuit member includes a frame substrate formed, by patterning a rolled copper plate or a rolled copper alloy plate, with a die pad portion for a semiconductor chip to be mounted thereon, and a lead portion for an electrical connection to the semiconductor chip, having rough surfaces formed as roughed surfaces on upsides and lateral wall sides of the die pad portion and the lead portion, and smooth surfaces formed on downsides of the die pad portion and the lead portion, and the die pad portion and the lead portion are buried in a sealing resin, having a downside of the lead portion exposed.
    Type: Grant
    Filed: April 26, 2006
    Date of Patent: June 3, 2014
    Assignee: Dai Nippon Printing Co., Ltd.
    Inventors: Yo Shimazaki, Hiroyuki Saito, Masachika Masuda, Kenji Matsumura, Masaru Fukuchi, Takao Ikezawa
  • Patent number: 8723328
    Abstract: To provide a multilayer wiring substrate in which the connection reliability of via conductors is enhanced, via holes are formed in a resin interlayer insulation layer which isolates a lower conductor layer from an upper conductor layer, and via conductors are formed in the via holes for connecting the lower conductor layer and the upper conductor layer. The surface of the resin interlayer insulation layer is a rough surface, and the via holes open at the rough surface of the resin interlayer insulation layer. Stepped portions are formed in opening verge regions around the via holes such that the stepped portions are recessed from peripheral regions around the opening verge regions. The stepped portions are higher in surface roughness than the peripheral regions.
    Type: Grant
    Filed: December 13, 2011
    Date of Patent: May 13, 2014
    Assignee: NGK Spark Plug Co., Ltd.
    Inventor: Shinnosuke Maeda
  • Patent number: 8709935
    Abstract: A semiconductor device has a substrate and first conductive pads formed over the substrate. An interconnect surface area of the first conductive pads is expanded by forming a plurality of recesses into the first conductive pads. The recesses can be an arrangement of concentric rings, arrangement of circular recesses, or arrangement of parallel linear trenches. Alternatively, the interconnect surface area of the first conductive pads is expanded by forming a second conductive pad over the first conductive pad. A semiconductor die has a plurality of interconnect structures formed over a surface of the semiconductor die. The semiconductor die is mounted to the substrate with the interconnect structures contacting the expanded interconnect surface area of the first conductive pads to increase bonding strength of the interconnect structure to the first conductive pads. A mold underfill material is deposited between the semiconductor die and substrate.
    Type: Grant
    Filed: February 15, 2013
    Date of Patent: April 29, 2014
    Assignee: STATS ChipPAC, Ltd.
    Inventors: DaeSik Choi, OhHan Kim, SungWon Cho
  • Publication number: 20140110843
    Abstract: A semiconductor unit includes a submount and a chip coupled to the submount. The submount is configured with a base and a plurality of layers between the base and the chip. One of the layers, a heat-spreading electro-conducting sliver (“Ag”) layer, is deposited atop the base. The thickness of the Ag layer is selected so that a cumulative coefficient of thermal expansion of the submount substantially matches that one of the chip. Coupled to the active zone of the chip is a stress-dumping layer made from elastic malleable materials.
    Type: Application
    Filed: December 30, 2013
    Publication date: April 24, 2014
    Applicant: IIPG Photonics Corporation
    Inventors: Alexander Ovtchinnikov, Alexey Komissarov, Igor Berishev, Svetlan Todorov
  • Patent number: 8686542
    Abstract: A compliant monopolar micro device transfer head array and method of forming a compliant monopolar micro device transfer array from an SOI substrate are described. In an embodiment, the micro device transfer head array including a base substrate and a patterned silicon layer over the base substrate. The patterned silicon layer may include a silicon interconnect and an array of silicon electrodes electrically connected with the silicon interconnect. Each silicon electrode includes a mesa structure protruding above the silicon interconnect, and each silicon electrode is deflectable into a cavity between the base substrate and the silicon electrode. A dielectric layer covers a top surface of each mesa structure.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: April 1, 2014
    Assignee: LuxVue Technology Corporation
    Inventors: Dariusz Golda, Andreas Bibl
  • Patent number: 8673773
    Abstract: A method for producing a nanoporous layer comprises applying a plating base with adhesion strengthening onto a substrate, depositing a layer made of gold and silver onto the substrate, the composition being in the range of 20% to 40% gold and 80% to 60% silver, and selectively removing the silver in order to produce a nanoporous gold layer.
    Type: Grant
    Filed: November 14, 2008
    Date of Patent: March 18, 2014
    Assignee: Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V.
    Inventors: Hermann Oppermann, Lothar Dietrich, Gunter Engelmann, Wolf Jürgen
  • Patent number: 8674367
    Abstract: Provided is an organic light-emitting display device. The organic light-emitting display device includes: a substrate; a buffer layer formed on the substrate; a gate insulating layer formed on the buffer layer; a conductive layer formed on the gate insulating layer; and a pixel defined layer exposing a portion of the conductive layer to form a pad portion connected to bumps of a drive integrated circuit (IC) chip, wherein protrusions and recesses are formed on a surface of the conductive layer.
    Type: Grant
    Filed: May 16, 2011
    Date of Patent: March 18, 2014
    Assignee: Samsung Display Co., Ltd.
    Inventors: Sun Park, Chun-gi You, Jong-Hyun Park, Yul-Kyu Lee
  • Patent number: 8669657
    Abstract: Stacked semiconductor devices and assemblies including attached lead frames are disclosed herein. One embodiment of a method of manufacturing a semiconductor assembly includes forming a plurality of first side trenches to a first intermediate depth in a molded portion of a molded wafer having a plurality of dies arranged in rows and columns. The method also includes forming a plurality of lateral contacts at sidewall portions of the trenches and electrically connecting first side bond-sites of the dies with corresponding lateral contacts of the trenches. The method further includes forming a plurality of second side channels to a second intermediate depth in the molded portion such that the channels intersect the trenches. The method also includes singulating and stacking the first and second dies with the channels associated with the first die aligned with channels associated with the second die.
    Type: Grant
    Filed: August 27, 2013
    Date of Patent: March 11, 2014
    Assignee: Micron Technology, Inc.
    Inventor: Swee Kwang Chua
  • Patent number: 8648463
    Abstract: A multi-chip module (MCM) that includes at least two substrates, having facing surfaces, which are mechanically coupled by a set of coupling elements having a reflow characteristic, is described. One of the two substrates includes another set of coupling elements having another reflow characteristic, which is different than the reflow characteristic. These different reflow characteristics of the sets of coupling elements allow different temperature profiles to be used when bonding the two substrates to each other than when bonding the one of the two substrates to a carrier. For example, the temperature profiles may have different peak temperatures and/or different durations from one another. These reflow characteristics may facilitate low-cost, high-yield assembly and alignment of the substrates in the MCM, and may allow temperature-sensitive components to be included in the MCM.
    Type: Grant
    Filed: May 17, 2010
    Date of Patent: February 11, 2014
    Assignee: Oracle International Corporation
    Inventors: Hiren D. Thacker, Jing Shi, John E. Cunningham, Ashok V. Krishnamoorthy
  • Patent number: 8637986
    Abstract: A semiconductor device which includes a first semiconductor chip 10, a first electrode 12 formed on the first semiconductor chip 10, a second semiconductor chip 20 to which the first semiconductor chip 10 is mounted, a second electrode 22 with a protrusion 24, which is formed on the second semiconductor chip 20, and a solder bump 14 which bonds the first electrode 12 and the second electrode 22 to cover at least a part of a side surface of the protrusion 24, and a method for manufacturing thereof are provided.
    Type: Grant
    Filed: October 22, 2008
    Date of Patent: January 28, 2014
    Assignee: Spansion LLC
    Inventors: Naomi Masuda, Masataka Hoshino, Ryota Fukuyama
  • Publication number: 20140021609
    Abstract: A wiring substrate includes: a substrate; an insulator formed in the substrate and having a through hole; an electrode formed in the substrate and provided within the through hole; and a conductor bonded to the electrode and provided within the through hole, wherein the through hole has a shape that is widened toward a direction away from the substrate, and the conductor is configured to cover the entire top surface of the electrode and has a shape that is widened toward the direction away from the substrate.
    Type: Application
    Filed: June 18, 2013
    Publication date: January 23, 2014
    Inventors: Taiga Fukumori, Daisuke Mizutani, Mamoru Kurashina
  • Patent number: 8624393
    Abstract: Methods for localized thinning of wafers used in semiconductor devices and the structures formed from such methods are described. The methods thin localized areas of the backside of the semiconductor wafer to form recesses with a bi-directional channel design that is repeated within the wafer (or die) so that no straight channel line crosses the wafer (or die). The bi-directional pattern design keeps the channels from being aligned with the crystal orientation of the wafer. The recesses are then filled by a solder ball drop process by dropping proper size solder balls into the recesses and then annealing the wafer to reflow the solder balls and flatten them out. The reflow process begins to fill in the recesses from the bottom up, thereby avoiding void formation and the resulting air traps in the reflowed solder material. Other embodiments are also described.
    Type: Grant
    Filed: February 24, 2012
    Date of Patent: January 7, 2014
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Suku Kim, James Murphy, Matthew Reynolds, Romel Manatad, Jan Mancelita, Michael Gruenhagen
  • Patent number: 8610274
    Abstract: A die structure includes a die and a metallization layer disposed over the front side of the die. The metallization layer includes copper. At least a part of the metallization layer has a rough surface profile. The part with the rough surface profile includes a wire bonding region, to which a wire bonding structure is to be bonded.
    Type: Grant
    Filed: September 14, 2010
    Date of Patent: December 17, 2013
    Assignee: Infineon Technologies AG
    Inventors: Khalil Hosseini, Frank Kahlmann, Josef Hoeglauer, Ralf Otremba, Georg Meyer-Berg
  • Patent number: 8593817
    Abstract: A power semiconductor module is provided in which power semiconductor chips with an aluminum-based chip metallization and power semiconductor chips with a copper-based chip metallization are included in the same module, and operated at different barrier-layer temperatures during use.
    Type: Grant
    Filed: September 30, 2010
    Date of Patent: November 26, 2013
    Assignee: Infineon Technologies AG
    Inventors: Reinhold Bayerer, Thilo Stolze
  • Patent number: 8581398
    Abstract: An integrated circuit chip is formed with a circuit layer, a trap rich layer and through-semiconductor-vias. The trap rich layer is formed above the circuit layer. The through-semiconductor-vias are also formed above the circuit layer. In some embodiments, the circuit layer is included in a wafer, and the trap rich layer and through-semiconductor-vias are included in another wafer. The two wafers are bonded together after formation of the trap rich layer and through-semiconductor-vias. Additionally, in some embodiments, yet another wafer may also be bonded to the wafer that includes the trap rich layer and through-semiconductor-vias. Furthermore, in some embodiments, another circuit layer may be formed in the wafer that includes the trap rich layer and through-semiconductor-vias.
    Type: Grant
    Filed: February 7, 2013
    Date of Patent: November 12, 2013
    Assignee: IO Semiconductor, Inc.
    Inventors: Anton Arriagada, Chris Brindle, Michael A. Stuber
  • Patent number: 8574949
    Abstract: Embodiments of the current invention describe methods of forming different types of crystalline silicon based solar cells that can be combinatorially varied and evaluated. Examples of these different types of solar cells include front and back contact silicon based solar cells, all-back contact solar cells and selective emitter solar cells. These methodologies all incorporate the formation of site-isolated regions using a combinatorial processing tool and the use of these site-isolated regions to form the solar cell area. Therefore, multiple solar cells may be rapidly formed on a single crystalline silicon substrate for use in combinatorial methodologies. Any of the individual processes of the methods described may be varied combinatorially to test varied process conditions or materials.
    Type: Grant
    Filed: September 20, 2010
    Date of Patent: November 5, 2013
    Assignee: Intermolecular, Inc.
    Inventors: Jian Li, Minh Anh Nguyen, Nikhil Kalyankar, Nitin Kumar, Craig Hunter
  • Patent number: 8513823
    Abstract: In a semiconductor package, a stamp is provided on at least one of at least a pair of opposed sides on an outer peripheral portion in contact with an edge of the package, which is a blank space up to now. With this configuration, the amount of stamp can be increased even in a narrow stamp area.
    Type: Grant
    Filed: June 29, 2011
    Date of Patent: August 20, 2013
    Assignee: Renesas Electronics Corporation
    Inventor: Hiroyuki Shoji
  • Patent number: 8501021
    Abstract: A process for laser forming a blind via in at least one layer of a circuit substrate having a plurality of capture pads of varying geometry can include, for at least one blind via to be formed in at least one layer of a circuit substrate, evaluating a capture pad geometry value (such as area and/or volume) within a predetermined distance from a drilling location with respect to a blind via geometry value (such as area and/or volume) to be formed at the drilling location. The process can include setting at least one laser operating parameter based on the evaluation in order to obtain a desired capture pad appearance after blind via formation. The process can include imaging a capture pad area defined as an area within a predetermined distance from a blind via drilling location in at least one layer of a circuit substrate, quantifying at least one appearance value for the imaged capture pad area, and determining an acceptability of the imaged capture pad areas based on the quantified appearance value.
    Type: Grant
    Filed: March 27, 2009
    Date of Patent: August 6, 2013
    Assignee: Electro Scientific Industries, Inc.
    Inventors: Hisashi Matsumoto, Mark Singer, Leo Baldwin, Jeffrey E. Howerton, David V. Childers
  • Patent number: 8492263
    Abstract: Protection of a solder ball joint is disclosed in which the solder ball joint is located below the surface level of the encapsulating buffer layer. The buffering layer is etched to expose one or more electrode posts, each of which may be made up of a single column or multiple columns. A top layer resulting either from a top conductive cap or a plating layer around the electrode posts also lies below the buffer layer. When the solder ball is placed onto the posts, the solder/ball joint is protected in a position below the surface of the buffer layer, while still maintaining an electrical connection between the various solder balls and their associated or capping/plating material, electrode posts, wiring layers, and circuit layers. Therefore, the entire ball joint is protected from direct stress.
    Type: Grant
    Filed: November 16, 2007
    Date of Patent: July 23, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung Yu Wang, Chien-Hsiun Lee, Pei-Haw Tsao, Kuo-Chin Chang, Chung-Yi Lin, Bill Kiang
  • Patent number: 8456011
    Abstract: A method of forming a metal semiconductor alloy that includes forming an intermixed metal semiconductor region to a first depth of a semiconductor substrate without thermal diffusion. The intermixed metal semiconductor region is annealed to form a textured metal semiconductor alloy. A second metal layer is formed on the textured metal semiconductor alloy. The second metal layer on the textured metal semiconductor alloy is then annealed to form a metal semiconductor alloy contact, in which metal elements from the second metal layer are diffused through the textured metal semiconductor alloy to provide a templated metal semiconductor alloy. The templated metal semiconductor alloy includes a grain size that is greater than 2× for the metal semiconductor alloy, which has a thickness ranging from 15 nm to 50 nm.
    Type: Grant
    Filed: January 14, 2011
    Date of Patent: June 4, 2013
    Assignees: International Business Machines Corporation, Globalfoundries Inc.
    Inventors: Christian Lavoie, Ahmet S. Ozcan, Zhen Zhang, Bin Yang
  • Patent number: 8450796
    Abstract: A gate electrode is provided for controlling a current flowing through a semiconductor layer. A gate insulating film electrically insulates the semiconductor layer and the gate electrode from each other. A conductor portion is provided on the semiconductor layer, and electrically connected with the semiconductor layer. An interlayer insulating film is provided on the gate electrode such that the conductor portion is electrically insulated from the gate electrode. A buffer insulating film covers a partial region on the conductor portion and the interlayer insulating film, and is made of an insulator. An electrode layer has a wiring portion located on a region from which the conductor portion is exposed, and a pad portion located on the buffer insulating film. Thereby, damage to an IGBT caused when a wire is connected to the pad portion can be suppressed. Further, larger electric power can be handled, while preventing occurrence of breakage due to current concentration.
    Type: Grant
    Filed: April 28, 2009
    Date of Patent: May 28, 2013
    Assignee: Mitsubishi Electric Corporation
    Inventor: Kazunari Nakata
  • Patent number: 8445907
    Abstract: The semiconductor device includes a process monitoring pattern and an input/output (I/O) pad array area, the process monitoring pattern including a lower layer having a peripheral area surrounding a first internal area, the first internal area exposed by an internal open area, an external structure on the peripheral area of the lower layer, and a first dam disposed in the peripheral area spaced apart from the external structure by an external open area, the first dam defining the first internal area. The peripheral area overlaps the input/output (I/O) pad array area of the semiconductor device.
    Type: Grant
    Filed: December 8, 2010
    Date of Patent: May 21, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Dong-Hyun Han
  • Patent number: 8436461
    Abstract: Disclosed is a semiconductor device wherein the adhesion of resin to a substrate is improved at a low cost. A semiconductor element and one or two substrates opposing one or both of the surfaces of the semiconductor element are sealed by a resin, a resin bonding coat which is formed by spraying a metal powder by a cold spray method is formed on one or both of the substrates, and recess portions which are widened from a film surface in a depth direction are formed on the resin bonding coat.
    Type: Grant
    Filed: May 21, 2010
    Date of Patent: May 7, 2013
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventor: Hirotaka Ohno
  • Publication number: 20130105974
    Abstract: Embodiments in accordance with the present invention relate to flip-chip packages for semiconductor devices, which feature a die sandwiched between metal layers. One metal layer comprises portions of the lead frame configured to be in electrical and thermal communication with various pads on a first surface of the die (e.g. IC pads or MOSFET gate or source pads) through a solder ball contact. The other metal layer is configured to be in at least thermal communication with the opposite side of the die. Embodiments of packages in accordance with the present invention exhibit superior heat dissipation qualities, while avoiding the expense of wire bonding. Embodiments of the present invention are particularly suited for packaging of power devices.
    Type: Application
    Filed: December 17, 2012
    Publication date: May 2, 2013
    Applicant: GEM SERVICES, INC.
    Inventor: GEM SERVICES, INC.
  • Patent number: 8410605
    Abstract: An integrated circuit (IC) has an under-bump metal (UBM) pad disposed between a solder bump and a semiconductor portion of the IC. A UBM layer is disposed between the solder bump and the semiconductor portion and includes the UBM pad and a UBM field. The UBM pad has a contact perimeter formed with the solder bump. The UBM pad extends beyond the contact perimeter a sufficient distance to block alpha particles emitted from the surface of the solder bump from causing an upset event in the semiconductor portion. The UBM field is separated from each UBM pad by a gap extending from the UBM pad to the UBM field so as to electrically isolate the UBM field from the UBM pad.
    Type: Grant
    Filed: April 19, 2012
    Date of Patent: April 2, 2013
    Assignee: Xilinx, Inc.
    Inventor: Michael J. Hart
  • Patent number: 8410604
    Abstract: A semiconductor device includes a semiconductor die and a plurality of lead-free solder bumps disposed on a surface of the semiconductor die. A substrate includes a plurality of metal layers and a plurality of dielectric layers. One of the metal layers includes a plurality of contact pads corresponding to the plurality of lead-free solder bumps, and one of the dielectric layers is an exterior dielectric layer having a plurality of respective openings for the contact pad. A plurality of respective copper posts is disposed on the contact pads. The respective copper post for each contact pad extends from the contact pad through the respective opening for the contact pad. The semiconductor die is mounted on the substrate with connections between the plurality of lead-free solder bumps and the plurality of copper posts.
    Type: Grant
    Filed: October 26, 2010
    Date of Patent: April 2, 2013
    Assignee: Xilinx, Inc.
    Inventors: Laurene Yip, Leilei Zhang, Kumar Nagarajan