Of Specified Configuration Patents (Class 257/773)
  • Patent number: 10851454
    Abstract: A method of forming conformal amorphous metal films is disclosed. A method of forming crystalline metal films with a predetermined orientation is also disclosed. An amorphous nucleation layer is formed on a substrate surface. An amorphous metal layer is formed from the nucleation layer by atomic substitution. A crystalline metal layer is deposited on the amorphous metal layer by atomic layer deposition.
    Type: Grant
    Filed: October 9, 2019
    Date of Patent: December 1, 2020
    Assignee: Applied Materials, Inc.
    Inventors: Yong Wu, Srinivas Gandikota, Abhijit Basu Mallick
  • Patent number: 10854499
    Abstract: An integrated circuit structure includes a set of rails, a first and second set of conductive structures and a first set of vias. The set of rails extends in a first direction and is located at a first level. Each rail of the set of rails is separated from one another in a second direction. The first set of conductive structures extends in the second direction, overlaps the set of rails and is located at a second level. The first set of vias is between the set of rails and the first set of conductive structures. Each of the first set of vias is located where each of the first set of conductive structures overlaps each of the set of rails. The first set of vias couple the first set of conductive structures to the set of rails. The second set of conductive structures is between the set of rails.
    Type: Grant
    Filed: July 7, 2017
    Date of Patent: December 1, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jung-Chan Yang, Ting-Wei Chiang, Cheng-I Huang, Hui-Zhong Zhuang, Chi-Yu Lu, Stefan Rusu
  • Patent number: 10847442
    Abstract: A semiconductor device in accordance with some embodiments includes a substrate structure and a conductive interconnect extending through at least a portion of the substrate structure. The conductive interconnect can include a through-silicon via and a stress-relief feature that accommodates thermal expansion and/or thermal contraction of material to manage internal stresses in the semiconductor device. Methods of manufacturing the semiconductor device in accordance with some embodiments includes removing material of the conductive interconnect to form the stress-relief gap.
    Type: Grant
    Filed: February 24, 2014
    Date of Patent: November 24, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Hongqi Li, Anurag Jindal, Jin Lu, Gowrisankar Damarla, Shyam Ramalingam
  • Patent number: 10847418
    Abstract: A method for forming a semiconductor device is provided. The method includes forming a first dielectric layer over a semiconductor substrate and forming a first conductive feature extending into the first dielectric layer. The first conductive feature has a planar top surface. The method also includes forming a second dielectric layer over the first conductive feature. The method further includes forming a hole in the second dielectric layer to expose the planar top surface of the first conductive feature. In addition, the method includes partially removing the first conductive feature from the planar top surface of the first conductive feature to form a curved surface of the first conductive feature. The method further includes forming a second conductive feature to fill the hole after the curved surface of the first conductive feature is formed.
    Type: Grant
    Filed: September 27, 2019
    Date of Patent: November 24, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tai-Yen Peng, Chia-Tien Wu, Jye-Yen Cheng
  • Patent number: 10840133
    Abstract: The present disclosure provides one embodiment of a semiconductor structure. The semiconductor structure includes a semiconductor substrate; a first conductive feature and a second conductive feature disposed on the semiconductor substrate; and a staggered dielectric feature interposed between the first and second conductive feature. The staggered dielectric feature includes first dielectric layers and second dielectric layers being interdigitated. The first dielectric layers include a first dielectric material and the second dielectric layers include a second dielectric material being different from the first dielectric material.
    Type: Grant
    Filed: March 27, 2019
    Date of Patent: November 17, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Zhi-Chang Lin, Teng-Chun Tsai, Wei-Hao Wu
  • Patent number: 10840203
    Abstract: An assembly platform for arrangement as an interposer device between an integrated circuit and a substrate to interconnect the integrated circuit and the substrate through the assembly platform, the assembly platform comprising: an assembly substrate; a plurality of conducting vias extending through the assembly substrate; at least one nanostructure connection bump on a first side of the assembly substrate, the nanostructure connection bump being conductively connected to the vias and defining connection locations for connection with at least one of the integrated circuit and the substrate, wherein each of the nanostructure connection bumps comprises: a plurality of elongated conductive nanostructures vertically grown on the first side of the assembly substrate, wherein the plurality of elongated nanostructures are embedded in a metal for the connection with at least one of the integrated circuit and the substrate, at least one connection bump on a second side of the assembly substrate, the second side being
    Type: Grant
    Filed: May 3, 2017
    Date of Patent: November 17, 2020
    Assignee: SMOLTEK AB
    Inventors: M Shafiqul Kabir, Anders Johansson, Vincent Desmaris, Muhammad Amin Saleem
  • Patent number: 10840186
    Abstract: A first metallization layer comprises a set of first conductive lines that extend along a first direction on a first dielectric layer on a substrate. Pillars are formed on recessed first dielectric layers and a second dielectric layer covers the pillars. A dual damascene etch provides a contact hole through the second dielectric layer and an etch removes the pillars to form air gaps.
    Type: Grant
    Filed: July 25, 2019
    Date of Patent: November 17, 2020
    Assignee: Applied Materials, Inc.
    Inventors: Susmit Singha Roy, Ziqing Duan, Abhijit Basu Mallick, Praburam Gopalraja
  • Patent number: 10833042
    Abstract: Embodiments of bonded semiconductor structures and fabrication methods thereof are disclosed. In an example, a semiconductor device includes a first and a second semiconductor structures. The first semiconductor structure includes a first interconnect layer including first interconnects. The first semiconductor structure further includes a first bonding layer including first bonding contacts. Each first interconnect is in contact with a respective first bonding contact. The second semiconductor structure includes a second interconnect layer including second interconnects. The second semiconductor structure further includes a second bonding layer including second bonding contacts. At least one second bonding contact is in contact with a respective second interconnect. At least another second bonding contact is separated from the second interconnects. The semiconductor device further includes a bonding interface between the first and second bonding layers.
    Type: Grant
    Filed: March 4, 2019
    Date of Patent: November 10, 2020
    Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
    Inventors: Tao Wang, Si Ping Hu, Jia Wen Wang, Shi Qi Huang, Jifeng Zhu, Jun Chen, Zi Qun Hua
  • Patent number: 10833060
    Abstract: According to one embodiment a semiconductor storage device includes a housing, a first rigid board, a controller, a second rigid hoard, a first semiconductor memory component, and a first connection board. The first rigid board includes a plurality of first terminals on a surface of the first rigid board. The second rigid board includes a plurality of second terminals on a surface of the second rigid board. The first connection board is in a state in which at least a part of the first connection board is bent. The first connection board includes a first end portion and a second end portion. The first end portion includes a plurality of third terminals connected to the plurality of first terminals of the first rigid board. The second end portion includes a plurality of fourth terminals connected to the plurality of second terminals of the second rigid board.
    Type: Grant
    Filed: March 12, 2019
    Date of Patent: November 10, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Kazuya Nagasawa, Norihiro Ishii, Seiji Kawahara
  • Patent number: 10832948
    Abstract: A semiconductor device includes a first interlayer dielectric film on a substrate, first and second wires respectively extending in a first direction within the first interlayer dielectric film, the first and second wires being adjacent to each other in a second direction different from the first direction, a hard mask pattern on the first interlayer dielectric film, the hard mask pattern including an opening, and an air gap within the first interlayer dielectric film, the air gap including a first portion overlapping vertically with the opening and a second portion not overlapping with the opening in the first direction.
    Type: Grant
    Filed: April 22, 2020
    Date of Patent: November 10, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kyu Hee Han, Jong Min Baek, Viet Ha Nguyen, Woo Kyung You, Sang Shin Jang, Byung Hee Kim
  • Patent number: 10825819
    Abstract: A semiconductor device includes a substrate, a first impurity implantation region and a second impurity implantation region on the substrate and spaced apart from each other, a storage node contact in contact with the first impurity implantation region, the storage node contact including an upper contact having a first width, and a lower contact having a second width that is greater than the first width at a lower portion of the upper contact, a bit line electrically connected to the second impurity implantation region and configured to cross the substrate, a bit line node contact between the bit line and the second impurity implantation region, and a spacer between the storage node contact and the bit line and between the storage node contact and the bit line node contact.
    Type: Grant
    Filed: June 11, 2019
    Date of Patent: November 3, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyo Sub Kim, Hui Jung Kim, Myeong Dong Lee, Jin Hwan Chun
  • Patent number: 10818818
    Abstract: A semiconductor device includes: a first semiconductor region; and a first electrode on the first semiconductor region; wherein first semiconductor region includes a first layer and a second layer, the second layer includes a first portion and a second portion adjacent to the first portion, the first portion has a first thickness, the second portion has a second thickness less than the first thickness, the first layer includes a first material and a first dopant, the first material includes multiple elements, the first dopant has a first concentration, the second layer includes a second material and a second dopant, the second material includes multiple elements, the second dopant has a second concentration, one of the elements of the first material of the first layer is different from the elements of the second material of the second layer.
    Type: Grant
    Filed: November 20, 2018
    Date of Patent: October 27, 2020
    Assignee: EPISTAR CORPORATION
    Inventors: Tzu-Chieh Hu, Wei-Chieh Lien, Chen Ou, Chia-Ming Liu, Tzu-Yi Chi
  • Patent number: 10818616
    Abstract: A semiconductor package structure and a method for forming the same are disclosed. The semiconductor package structure includes a semiconductor die, a molding layer and an inductor. The semiconductor die includes an active surface, a back surface and a sidewall surface between the active surface and the back surface. The molding layer covers the back surface and the sidewall surface of the semiconductor die. The inductor is in the molding layer. The sidewall surface of the semiconductor die faces toward the inductor.
    Type: Grant
    Filed: March 22, 2019
    Date of Patent: October 27, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chun-Hung Chen, Chu-Fu Lin, Ming-Tse Lin
  • Patent number: 10811366
    Abstract: A microelectronic package may be fabricated with at least one compliant external bond pad having at least one integrated spring structure for mitigating the effects of warpage of the microelectronic package during attachment to an external substrate. An embodiment for the microelectronic package may include a microelectronic package substrate having a first surface and an opposing second surface, wherein the microelectronic package substrate includes a void defined therein that extends into the microelectronic package substrate from the second surface thereof, and a compliant bond pad suspended over the void, wherein the compliant bond pad includes a land portion and at least one spring portion, and wherein the at least one spring portion extends from the compliant bond pad land portion to an anchor structure on the microelectronic package substrate second surface.
    Type: Grant
    Filed: January 16, 2019
    Date of Patent: October 20, 2020
    Assignee: Intel Corporation
    Inventors: Feras Eid, Robert L. Sankman, Sandeep B. Sane
  • Patent number: 10809615
    Abstract: A pattern forming method comprises forming a line pattern in a first film. The line pattern includes a first pattern part including feature portions at a first dimension and a second pattern part adjacent to the first pattern part and including feature portions at a second dimension smaller than the first dimension. A second film is formed on the substrate conformally over the first film. The second film is etched to expose a top surface of the first pattern part and remove the second pattern part. The remaining first film is then removed, leaving portions of the second film that were formed on sidewalls of the first pattern part. The substrate is then processed by using those portions of the second film left after the removal of the first film as a mask.
    Type: Grant
    Filed: February 27, 2019
    Date of Patent: October 20, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Noriko Sakurai
  • Patent number: 10804219
    Abstract: A semiconductor device includes a plurality of lower electrodes repeatedly arranged at a first pitch in a first direction and a second direction crossing the first direction at an acute angle on a substrate, and a support pattern in contact with sidewalls of the plurality of lower electrodes and supporting the plurality of lower electrodes. The support pattern includes a first support region having a plurality of openings penetrating the support pattern and a second support region disposed at a periphery of the first support region. The plurality of openings may continuously extend in a zigzag manner, respectively, throughout an entirety of the first support region.
    Type: Grant
    Filed: June 20, 2019
    Date of Patent: October 13, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Wan Gi Sohn
  • Patent number: 10804182
    Abstract: The invention is concerned with a semiconductor power module comprising an electrically and thermally conductive base plate (14) and a semiconductor chip (12) and where a first layer of graphene (32) is placed between the semiconductor chip (12) and the base plate (14) in electrical and thermal contact with a first side the base plate (14). Thereby the cooling of the semiconductor power module is improved.
    Type: Grant
    Filed: December 13, 2017
    Date of Patent: October 13, 2020
    Assignee: ABB Power Grids Switzerland AG
    Inventor: Muhammad Nawaz
  • Patent number: 10796952
    Abstract: Provided is a memory device, including a stacked structure, a pillar, a first stop layer, and a contact plug. The stacked structure includes a plurality of conductive layers. The pillar penetrates the plurality of series-connected memory cells. The plurality of series-connected memory cells are located in a layout pattern of pillar locations at cross-points between the pillar and the conductive layers. The first stop layer covers the stacked structure and a portion of a top surface of the pillar. The contact plug passes through the first stop layer, extending into the pillar, and is electrically connected to the plurality of series-connected memory cells. The contact is landed on the contact plug, and is electrically connected to a portion of the pillar through the contact plug.
    Type: Grant
    Filed: August 21, 2019
    Date of Patent: October 6, 2020
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventor: Kuan-Yuan Shen
  • Patent number: 10797024
    Abstract: A semiconductor device includes a substrate with an opening formed through the substrate. A first electronic component is disposed over the substrate outside a footprint of the first opening. A second electronic component is disposed over the substrate opposite the first electrical component. A third electronic component is disposed over the substrate adjacent to the first electronic component. The substrate is disposed in a mold including a second opening of the mold over a first side of the substrate. The mold contacts the substrate between the first electronic component and the third electronic component. An encapsulant is deposited into the second opening. The encapsulant flows through the first opening to cover a second side of the substrate. In some embodiments, a mold film is disposed in the mold, and an interconnect structure on the substrate is embedded in the mold film.
    Type: Grant
    Filed: March 21, 2020
    Date of Patent: October 6, 2020
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: DeokKyung Yang, YongMin Kim, JaeHyuk Choi, YeoChan Ko, HeeSoo Lee
  • Patent number: 10790205
    Abstract: A method includes: forming overlay structures at scribe lines of a wafer, each side of a die region of the wafer is disposed with at least one of the overlay structures, each of the overlay structures comprises at least one feature and at least one recess disposed above the feature, the feature and the recess are respectively disposed at a first and second layers of the wafer, the recess exposes a portion of the feature vertically aligned with the recess; acquiring an image of the overlay structures; measuring a first dimension and a second dimension of a first portion and a second portion of the recess, respectively; determining an overlay between the first and second layers of an edge region of the wafer based on an average of differences between the first and second dimensions; and modifying a subsequent lithography step to compensate for the overlay.
    Type: Grant
    Filed: January 10, 2019
    Date of Patent: September 29, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Feng-Pin Chen, Te-Chia Ku, Chien-Kwen Chen, Chi-Chang Wu, Cheng-Ming Ho
  • Patent number: 10785872
    Abstract: A jumper may be adapted to transmit an electrical signal. The jumper may be included in a system on a chip. The system on a chip may include a substrate, and the substrate may include one or more routing layers. The jumper may be included in the one or more routing layers of the substrate. A first interconnect may be positioned on a first side of the system on a chip, and a second interconnect may be positioned on a second side of the system on a chip. The jumper may be in electrical communication with the first interconnect, and may be in electrical communication with the second interconnect. The jumper may be electrically isolated from other components of the system on a chip, such as one or more die coupled to the substrate.
    Type: Grant
    Filed: January 31, 2019
    Date of Patent: September 22, 2020
    Assignee: Intel Corporation
    Inventors: Eng Huat Goh, Hoay Tien Teoh
  • Patent number: 10777655
    Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a first plurality of conductive interconnect lines in and spaced apart by a first ILD layer, wherein individual ones of the first plurality of conductive interconnect lines comprise a first conductive barrier material along sidewalls and a bottom of a first conductive fill material. A second plurality of conductive interconnect lines is in and spaced apart by a second ILD layer above the first ILD layer, wherein individual ones of the second plurality of conductive interconnect lines comprise a second conductive barrier material along sidewalls and a bottom of a second conductive fill material, wherein the second conductive fill material is different in composition from the first conductive fill material.
    Type: Grant
    Filed: December 30, 2017
    Date of Patent: September 15, 2020
    Assignee: Intel Corporation
    Inventors: Andrew W. Yeoh, Joseph Steigerwald, Jinhong Shin, Vinay Chikarmane, Christopher P. Auth
  • Patent number: 10770390
    Abstract: An interposer device comprising a first conductor pattern on a first side defining a portion of the interposer device to be covered by a first electrical circuit element; and a second conductor pattern on a second side to be connected to a second electrical circuit element. The second conductor pattern is electrically coupled to the first conductor pattern. The interposer device further comprises a plurality of nanostructure energy storage devices arranged within the portion of the interposer device to be covered by the first electrical circuit element. Each of the nanostructure energy storage devices comprises at least a first plurality of conductive nanostructures; a conduction controlling material embedding the nanostructures; a first electrode connected to each nanostructure in the first plurality of nanostructures; and a second electrode separated from each nanostructure in the first plurality of nanostructures by the conduction controlling material.
    Type: Grant
    Filed: August 23, 2018
    Date of Patent: September 8, 2020
    Assignee: SMOLTEK AB
    Inventors: M Shafiqul Kabir, Anders Johansson, Muhammad Amin Saleem, Rickard Andersson, Vincent Desmaris
  • Patent number: 10770682
    Abstract: A display panel comprises: a planarization layer that lies on a substrate and compensates for irregularities; an electrode pattern that lies on the planarization layer in a non-display area of the substrate and exposes at least part of the planarization layer; and a moisture-impermeable layer that covers the planarization layer exposed by the electrode pattern.
    Type: Grant
    Filed: December 17, 2018
    Date of Patent: September 8, 2020
    Assignee: LG DISPLAY CO., LTD.
    Inventors: Dohyung Kim, Seungwon Yoo, Jonghyeok Im, Jaesung Lee
  • Patent number: 10763278
    Abstract: A semiconductor memory device includes a substrate having a cell array region and a contact region, a stack structure including a plurality of gate electrodes on the cell array region and the contact region, a plurality of cell vertical channel structures extending through the stack structure on the cell array region, and a contact structure disposed beside of the stack structure on a top surface of the substrate and disposed along a line extending from the cell array region toward the contact region. The height of the contact structure on the cell array region is different from the height of the contact structure on the contact region.
    Type: Grant
    Filed: January 9, 2019
    Date of Patent: September 1, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kyunghwa Yun, Pansuk Kwak, Chanho Kim, Junghwa Lee
  • Patent number: 10756142
    Abstract: Provided is a display panel and display device. The display panel includes a first non-display area, a first display area, a second display area and a third display area. The first display area at least partially surrounds the first non-display area, the first display area and the second display area are arranged in a first direction, the third display area is arranged with the first and second display areas in a second direction. The first display area includes first sub-pixels arranged in array, the second display area includes second sub-pixels arranged in array, and the third display area includes third sub-pixels arranged in array. Each first sub-pixel, each second sub-pixel and each third sub-pixel have a same size in the first direction; each first sub-pixel and each second sub-pixel have a same size in the second direction and each second sub-pixel has the size greater than each third sub-pixel in the second direction.
    Type: Grant
    Filed: July 1, 2019
    Date of Patent: August 25, 2020
    Assignee: Shanghai Tianma AM-OLED Co., Ltd.
    Inventors: Huiping Chai, Lijing Han
  • Patent number: 10756072
    Abstract: A microelectronic structure (200) and a fabrication method of microelectronic are described. A first package (10) has a first conductive pad (40, 41, 47, 48) formed on a first foundation layer (12). A loop of conductive wire (50-53) is wirebonded to the first conductive pad ((40, 41, 47, 48) of the first foundation layer (12). A mold cap (70) is formed on the first foundation layer (12). A via (90-93) is formed in the mold cap (70) to reach the conductive wire (50-53). A solder structure (80-83) is coupled to the conductive wire (50-53). A second package (100) is connected to the first package (10) by attaching a second solder structure (110-113) of a second package (100) to the first solder structure (80-83) of the first package (10).
    Type: Grant
    Filed: December 25, 2015
    Date of Patent: August 25, 2020
    Assignee: Intel Corporation
    Inventor: Mao Guo
  • Patent number: 10748865
    Abstract: Provided is a copper paste for joining including copper particles, second particles including a metal element other than copper, and a dispersion medium, in which the copper particles include submicro copper particles having a volume-average particle diameter of 0.12 ?m or more and 0.8 ?m or less and micro copper particles having a volume-average particle diameter of 2 ?m or more and 50 ?m or less, a sum of a content of the submicro copper particles and a content of the micro copper particles is 80% by mass or more of a sum of masses of the copper particles and the second particles, the content of the submicro copper particles is 30% by mass or more and 90% by mass or less of a sum of a mass of the submicro copper particles and a mass of the micro copper particles, and a content of the second particles is 0.01% by mass or more and 10% by mass or less of the sum of the masses of the copper particles and the second particles.
    Type: Grant
    Filed: April 20, 2017
    Date of Patent: August 18, 2020
    Assignee: HITACHI CHEMICAL COMPANY, LTD.
    Inventors: Yuki Kawana, Hideo Nakako, Dai Ishikawa, Chie Sugama, Kazuhiko Kurafuchi, Yoshinori Ejiri
  • Patent number: 10743415
    Abstract: A camera module has a reduced light leakage. The camera module includes a printed circuit board and a mounting bracket mounted on the printed circuit board. The printed circuit board includes a first surface and at least one side surface perpendicularly connected to the first surface. Gaps are formed on the printed circuit board. The gaps extend from the first surface to a thickness direction of the first surface. Bumps are formed on the mounting bracket and correspondingly placed according to the gaps. Each of the bumps is received and fixed in a corresponding one of the gaps.
    Type: Grant
    Filed: February 28, 2019
    Date of Patent: August 11, 2020
    Assignee: TRIPLE WIN TECHNOLOGY(SHENZHEN) CO. LTD.
    Inventors: Jing-Wei Li, Shin-Wen Chen, Yu-Shuai Li, Sheng-Jie Ding
  • Patent number: 10741707
    Abstract: Photodetectors and methods of forming the same include a first electrode. A carbon nanotube film is formed on the first electrode. A first graphene sheet is formed on the carbon nanotube film. A second graphene sheet is configured to exert an electrical field on the first graphene sheet that changes an electrical property of the first graphene sheet.
    Type: Grant
    Filed: March 23, 2018
    Date of Patent: August 11, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Abram L. Falk, Kuan-Chang Chiu, Damon B. Farmer, Shu-Jen Han
  • Patent number: 10741523
    Abstract: A semiconductor package device includes a transparent carrier, a first patterned conductive layer, a second patterned conductive layer, and a first insulation layer. The transparent carrier has a first surface, a second surface opposite to the first surface and a third surface extended between the first surface and the second surface. The first patterned conductive layer is disposed on the first surface of the transparent carrier. The first patterned conductive layer has a first surface coplanar with the third surface of the transparent carrier. The second patterned conductive layer is disposed on the first surface of the transparent carrier and electrically isolated from the first patterned conductive layer. The first insulation layer is disposed on the transparent carrier and covers the first patterned conductive layer.
    Type: Grant
    Filed: October 11, 2018
    Date of Patent: August 11, 2020
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Yung-Shun Chang, Teck-Chong Lee
  • Patent number: 10734371
    Abstract: A semiconductor device includes a first substrate structure having a first substrate, circuit elements disposed on the first substrate, and first bonding pads disposed on the circuit elements. A second substrate structure is connected to the first substrate structure. The second substrate structure includes a second substrate having first and second surfaces, first and second conductive layers spaced apart from each other, a pad insulating layer having an opening exposing a portion of the second conductive layer and gate electrodes stacked to be spaced apart from each other in a first direction and electrically connected to the circuit elements. First contact plugs extend on the second surface in the first direction and connect to the gate electrodes. A second contact plug extends on the second surface in the first direction and electrically connects to the second conductive layer. Second bonding pads electrically connect to the first and second contact plugs.
    Type: Grant
    Filed: July 18, 2019
    Date of Patent: August 4, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Hyun Mog Park
  • Patent number: 10727398
    Abstract: A magnetic tunnel junction (MTJ) containing device is provided in which a bottom electrode having a small CD is formed and is located laterally adjacent to diamond like carbon (DLC). DLC replaces a material stack of, from bottom to top, a silicon nitride layer and an organic planarization layer (OPL) which is typically used in providing a conductive structure having a reduced CD. DLC provides a higher etch resistance to IBE than silicon nitride, but DLC can be patterned using conventional etchants. The use of DLC thus reduces the number of processing steps for providing a reduced CD bottom electrode, and also provides a more robust solution to the issue of punch through to an underlying conductive material layer.
    Type: Grant
    Filed: January 30, 2019
    Date of Patent: July 28, 2020
    Assignee: International Business Machines Corporation
    Inventors: Nathan P. Marchack, Bruce B. Doris, Chandrasekharan Kothandaraman
  • Patent number: 10727164
    Abstract: Present disclosure provides a semiconductor structure, including a semiconductor substrate having an active side, an interconnect layer in proximity to the active side of the semiconductor substrate, and a through substrate via extending from the semiconductor substrate to a first metal layer of the interconnect layer. The TSV being wider than the continuous metal feature. Present disclosure also provides a method for manufacturing the semiconductor structure described herein.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: July 28, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Min-Feng Kao, Dun-Nian Yaung, Jen-Cheng Liu, Ching-Chun Wang, Kuan-Chieh Huang, Hsing-Chih Lin, Yi-Shin Chu
  • Patent number: 10719687
    Abstract: A display panel capable of fingerprint identification includes a base substrate, a TFT layer, a pixel unit, and a dummy pixel. The base substrate includes a display area and a non-display area. The dummy pixel is formed on the TFT layer where the pixel unit is arranged as well, and distributed in the non-display area. The non-display area comprises a fingerprint identification cue area configured to transmit fingerprint information to a fingerprint identification module. The fingerprint identification module is arranged on one side of the TFT layer facing away from the dummy pixel. When a finger touches the fingerprint identification cue area, a light is emitted from the fingerprint identification cue area to the finger. The fingerprint identification module is configured to implement fingerprint identification based on the light that is reflected from a surface of the finger and passes through a gap between the dummy pixels.
    Type: Grant
    Filed: September 5, 2018
    Date of Patent: July 21, 2020
    Assignee: Wuhan China Star Optoelectronics Semiconductor Display Technology Co., Ltd.
    Inventors: Shaojing Wu, Shuang Li
  • Patent number: 10714435
    Abstract: The present application provides a fan-out antenna packaging structure and a method making the same. The method comprises: providing a carrier and forming a release layer on an upper surface of the carrier; forming a chip structure on an upper surface of the release layer, the chip structure comprises an unpacked chip and a contact pad disposed on and electrically connected to the unpacked chip; forming a plastic packaging layer packaging the chip structure on the upper surface of the release layer; removing the carrier and the release layer to expose the contact pad; forming a single-layer antenna structure and forming a redistribution layer on the surface where the contact pad is disposed; forming an under-bump metal layer on an upper surface of the redistribution layer; and forming a solder ball bump on an upper surface of the under-bump metal layer.
    Type: Grant
    Filed: December 4, 2018
    Date of Patent: July 14, 2020
    Assignee: SJ Semiconductor (Jiangyin) Corporation
    Inventors: Yenheng Chen, Chengchung Lin, Chengtar Wu, Jangshen Lin
  • Patent number: 10714508
    Abstract: Disclosed is a display device including: a substrate including a display area for displaying an image and a peripheral area neighboring the display area; a plurality of signal lines formed in the display area; a pad formed in the peripheral area; and a plurality of connection wires for connecting the signal lines and the pad, wherein a first connection wire and a second connection wire neighboring the first connection wire from among the plurality of connection wires are disposed on different layers, and the first connection wire and the second connection wire, which are formed to extend from the pad and are bent at least twice to have at least one being bent toward backward direction, are disposed in the peripheral area.
    Type: Grant
    Filed: July 31, 2019
    Date of Patent: July 14, 2020
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Seung-Kyu Lee, Tae Hoon Kwon, Ji-Hyun Ka
  • Patent number: 10714492
    Abstract: Embodiments of methods for forming a staircase structure of a three-dimensional (3D) memory device are disclosed. In an example, a first plurality of stairs of the staircase structure are formed based on a first photoresist mask. Each of the first plurality of stairs includes a number of divisions at different depths. After forming the first plurality of stairs, a second plurality of stairs of the staircase structure are formed based on a second photoresist mask. Each of the second plurality of stairs includes the number of divisions. The staircase structure tilts downward and away from a memory array structure of the 3D memory device from the first plurality of stairs to the second plurality of stairs.
    Type: Grant
    Filed: November 20, 2018
    Date of Patent: July 14, 2020
    Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
    Inventors: Wenyu Hua, Zhong Zhang, Zhiliang Xia
  • Patent number: 10700041
    Abstract: An assembly of circuit dies is stacked through oxide-oxide bonding. The assembly includes a silicon substrate, in which a plurality of through-silicon-vias are formed. The silicon substrate is attached onto a die through dielectric-dielectric bonding with at least part of the through-silicon-vias electrically connected to the die. The silicon substrate and die are attached onto another die through oxide-oxide bonding. Then the through-silicon-vias are revealed. The silicon substrate functions as a carrier substrate before the revealing. The silicon substrate and two dies can be attached to a printed circuit board, which is electrically connected to the two dies. One or more electrical components can be attached onto the silicon substrate and electrically connected to the die through the through-silicon-vias. The silicon substrate may include a metal element for diffusing heat generated from operation of the one or more electrical components.
    Type: Grant
    Filed: December 17, 2018
    Date of Patent: June 30, 2020
    Assignee: Facebook Technologies, LLC
    Inventor: Rajendra D. Pendse
  • Patent number: 10698512
    Abstract: An electrode substrate includes a sensing electrode formed on a glass substrate, a concave/convex pattern formed on the glass substrate, and a protective film formed so as to cover the sensing electrode. The concave/convex pattern is disposed closer to an outer periphery of the glass substrate than the sensing electrode is when seen in a plan view. The protective film is formed so as to cover a part of the glass substrate positioned between the sensing electrode and the concave/convex pattern when seen in a plan view.
    Type: Grant
    Filed: March 3, 2015
    Date of Patent: June 30, 2020
    Assignee: Japan Display Inc.
    Inventors: Koji Ishizaki, Toshimasa Ishigaki, Daisuke Sonoda
  • Patent number: 10692801
    Abstract: A semiconductor device package includes a die pad having a die attach surface, a first lead that is spaced apart and extends away from a first side of the die pad, and a semiconductor die mounted on the die attach surface. The semiconductor die includes a first bond pad disposed on an upper side of the semiconductor die that is opposite the die attach surface. A first clip electrically connects the first lead to the first bond pad. The first bond pad is elongated with first and second longer edge sides that are opposite one another and extend along a length of the first bond pad. The semiconductor die is oriented such that the first and second longer edge sides of the first bond pad are non-parallel to a first current flow direction of the first clip that extends between the first bond pad and the first lead.
    Type: Grant
    Filed: May 31, 2018
    Date of Patent: June 23, 2020
    Assignee: Infineon Technologies Austria AG
    Inventors: Eung San Cho, Chuan Cheah, Jobelito Anjao Guanzon
  • Patent number: 10685890
    Abstract: A semiconductor package including a redistribution substrate, and a semiconductor chip mounted on the redistribution substrate, the semiconductor chip having a conductive pad on one surface thereof may be provided. The redistribution substrate may include a first passivation pattern on the conductive pad, the first passivation pattern exposing a portion of the conductive pad, and a redistribution pattern covering the portion of the conductive pad exposed by the first passivation pattern and surrounding the first passivation pattern.
    Type: Grant
    Filed: February 19, 2019
    Date of Patent: June 16, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jongyoun Kim, Seokhyun Lee
  • Patent number: 10684519
    Abstract: A color-filter on array (COA) type array substrate is provided. Sub-pixels connected to an identical data line include red sub-pixels R, green sub-pixels G, and blue sub-pixels B, all of which are the same in number. The sub-pixels connected to an identical scan line include the red sub-pixels R, the green sub-pixels G, and the blue sub-pixels B, all of which are the same in number.
    Type: Grant
    Filed: May 3, 2017
    Date of Patent: June 16, 2020
    Assignee: SHENZHEN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Qiming Gan, Meng Wang
  • Patent number: 10679896
    Abstract: A method of forming a semiconductor device includes forming a source/drain region on a substrate and forming a first interlayer dielectric (ILD) layer over the source/drain region. The method further includes forming a first conductive region within the first ILD layer, selectively removing a portion of the first conductive region to form a concave top surface of the first conductive region. The method also includes forming a second ILD layer over the first ILD layer and forming a second conductive region within the second ILD layer and on the concave top surface. The concave top surface provides a large contact area, and hence reduced contact resistance between the first and second conductive regions.
    Type: Grant
    Filed: September 24, 2018
    Date of Patent: June 9, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yun-Yu Hsieh, Jeng Chang Her, Cha-Hsin Chao, Yi-Wei Chiu, Li-Te Hsu, Ying Ting Hsia
  • Patent number: 10679881
    Abstract: An apparatus for detecting a mark having first and second stripe groups on a substrate includes a detection module moveable over a surface of the substrate. The detection module includes a detection unit and a positioning unit configured to align the detection unit with the mark. The detection unit is configured to obtain data of the mark and operative to perform repeated acquisition operations on the first and second stripe groups of the mark. Each of the acquisition operations acquires data associated with the first stripe group or the second stripe group. The apparatus also includes a processing module configured to determine a positional deviation between the first stripe group and the second stripe group in response to the obtained data of the mark and data associated with a motion of the detection module.
    Type: Grant
    Filed: October 30, 2017
    Date of Patent: June 9, 2020
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION
    Inventors: Qiang Wu, Xuan Liu, Shifeng He, Jianyao Liu
  • Patent number: 10672710
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to interconnect structures with reduced capacitance and methods of manufacture. The method includes: forming one or more lower metal lines in a dielectric material; forming an airgap structure in an upper dielectric material above the one or more lower metal lines, by subjecting material to a curing process; and forming an upper metal structure above the airgap structure.
    Type: Grant
    Filed: June 5, 2018
    Date of Patent: June 2, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Sunil Kumar Singh, Shesh Mani Pandey
  • Patent number: 10672715
    Abstract: A semiconductor package includes a cavity substrate, a semiconductor die, and an encapsulant. The cavity substrate includes a redistribution structure and a cavity layer on an upper surface of the redistribution structure. The redistribution structure includes pads on the upper surface, a lower surface, and sidewalls adjacent the upper surface and the lower surface. The cavity layer includes an upper surface, a lower surface, sidewalls adjacent the upper surface and the lower surface, and a cavity that exposes pads of the redistribution structure. The semiconductor die is positioned in the cavity. The semiconductor die includes a first surface, a second surface, sidewalls adjacent the first surface and the second surface, and attachment structures that are operatively coupled to the exposed pads. The encapsulant encapsulates the semiconductor die in the cavity and covers sidewalls of the redistribution structure.
    Type: Grant
    Filed: April 16, 2018
    Date of Patent: June 2, 2020
    Assignee: AMKOR TECHNOLOGY, INC.
    Inventors: Young Do Kweon, JeongByung Chae, DongJoo Park, ByoungWoo Cho, SeHwan Hong
  • Patent number: 10672780
    Abstract: Memory openings and support openings are formed in a memory array region and a staircase region, respectively, through an alternating stack of insulating layers and spacer material layers. Pedestal channel portions and pedestal semiconductor portions are formed at the bottom of the memory openings and the support openings, respectively. Semiconductor oxide plates are provided only in a distal subset of the support openings that are spaced from the memory array region by more than a threshold separation distance. Memory openings are filled with memory opening fill structures, and support openings are filled with support pillar structures. Proximal support pillar structures located adjacent to the memory array region provide internal electrically conductive paths for discharging accumulated electrical charges.
    Type: Grant
    Filed: February 25, 2019
    Date of Patent: June 2, 2020
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Takeshi Kawamura, Akihisa Sai, Naoki Ihata
  • Patent number: 10672736
    Abstract: A method of liquid assisted micro cold binding is provided. The method includes: forming a conductive pad on the substrate in which the conductive pad consists essentially of indium; forming a liquid layer on the conductive pad; placing a micro device having an electrode facing the conductive pad over the conductive pad such that the micro device is in contact with the liquid layer and is gripped by a capillary force produced by the liquid layer between the micro device and the conductive pad in which the electrode consists essentially of indium; and evaporating the liquid layer such that the electrode is bound to the conductive pad and is in electrical contact with the conductive pad.
    Type: Grant
    Filed: April 1, 2019
    Date of Patent: June 2, 2020
    Assignee: MIKRO MESA TECHNOLOGY CO., LTD.
    Inventor: Li-Yi Chen
  • Patent number: 10665709
    Abstract: A semiconductor device includes a substrate, a power device, a protection circuit, a dielectric layer, a drain pad, a source pad, and a gate pad. The power device and the protection circuit are disposed on the substrate. The power device includes a drain electrode, a source electrode, and a gate electrode. The protection circuit has a first terminal electrically connected with the source pad and a second terminal electrically connected with the gate pad. The dielectric layer is disposed on the power device and the protection circuit. The drain pad, the source pad, and the gate pad are disposed on the dielectric layer and respectively electrically connected with the drain electrode, the source electrode, and the gate electrode. At least part of the protection circuit is disposed under the source pad, the gate pad, or the drain pad.
    Type: Grant
    Filed: March 24, 2017
    Date of Patent: May 26, 2020
    Assignee: DELTA ELECTRONICS, INC.
    Inventors: Li-Fan Lin, Po-Chin Peng