Of Specified Configuration Patents (Class 257/773)
  • Patent number: 11515143
    Abstract: There is provided a technique that includes (a) forming a first film having a first thickness on an underlayer by supplying a first process gas not including oxidizing gas to a substrate, wherein the first film contains silicon, carbon, and nitrogen and does not contain oxygen, and the underlayer is exposed on a surface of the substrate and is at least one selected from the group of a conductive metal-element-containing film and a nitride film; and (b) forming a second film having a second thickness larger than the first thickness on the first film by supplying a second process gas including oxidizing gas to the substrate, wherein the second film contains silicon, oxygen, and nitrogen, and wherein in (b), oxygen atoms derived from the oxidizing gas and diffuse from a surface of the first film toward the underlayer are absorbed by the first film and the first film is modified.
    Type: Grant
    Filed: June 18, 2020
    Date of Patent: November 29, 2022
    Assignee: KOKUSAI ELECTRIC CORPORATION
    Inventors: Yoshitomo Hashimoto, Tatsuru Matsuoka
  • Patent number: 11508614
    Abstract: A semiconductor device and method of forming the same, the semiconductor device includes plural bit lines, plural conductive patterns, plural conductive pads and a spacer. The bit lines are disposed on a substrate, along a first direction. The conductive patterns are disposed on the substrate, along the first direction, wherein the conductive patterns and the bit lines are alternately arranged in a second direction perpendicular to the first direction. The conductive pads are arranged in an array and disposed over the conductive patterns and the bit lines. The spacer is disposed between the bit lines and the conductive patterns, under the conductive pads, wherein the spacers includes a tri-layered structure having a first layer, a second layer and a third layer, and the second layer includes a plurality of air gaps separated arranged along the first direction.
    Type: Grant
    Filed: October 28, 2020
    Date of Patent: November 22, 2022
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Li-Wei Feng, Ying-Chiao Wang, Tzu-Tsen Liu, Tsung-Ying Tsai, Chien-Ting Ho
  • Patent number: 11506361
    Abstract: A light emitting device includes at least one light emitting element, a resin member including, a front surface provided with a recess in which the at least one light emitting element is mounted, a back surface, a bottom surface, an upper surface, a first lateral surface, and a second lateral surface; a first lead including a first inner lead portion and a first outer lead portion; and a second lead including a second inner lead portion and a second outer lead portion. Each of the outer lead portions includes a first-outer-lead base portion along the bottom surface, and first and second bent portions which are extended toward the upper surface side. The resin member is not arranged in at least a portion of a region between the second bent portion of the first outer lead portion and the first bent portion of the second outer lead portion.
    Type: Grant
    Filed: August 12, 2021
    Date of Patent: November 22, 2022
    Assignee: NICHIA CORPORATION
    Inventor: Hideki Hayashi
  • Patent number: 11482499
    Abstract: A structure includes a first die and a second die. The first die includes a first bonding layer having a first plurality of bond pads disposed therein and a first seal ring disposed in the first bonding layer. The first bonding layer extends over the first seal ring. The second die includes a second bonding layer having a second plurality of bond pads disposed therein. The first plurality of bond pads is bonded to the second plurality of bond pads. The first bonding layer is bonded to the second bonding layer. An area interposed between the first seal ring and the second bonding layer is free of bond pads.
    Type: Grant
    Filed: August 10, 2020
    Date of Patent: October 25, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih-Chia Hu, Chun-Chiang Kuo, Sen-Bor Jan, Ming-Fa Chen, Hsien-Wei Chen
  • Patent number: 11482776
    Abstract: An antenna device is disclosed. The disclosed antenna device comprises: a printed circuit board; and a waveguide antenna formed on the printed circuit board, wherein the waveguide antenna comprises; a first conductive area formed under the printed circuit board; a second conductive area formed above the printed circuit board and disposed to face the first conductive area; and a plurality of vias, formed at predetermined intervals along edges of the first conductive area, for electrically connecting the first conductive area and the second conductive area.
    Type: Grant
    Filed: June 25, 2019
    Date of Patent: October 25, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Yonghee Cho
  • Patent number: 11476210
    Abstract: A semiconductor device includes: a first semiconductor chip having a first pad and a second pad, a depression being formed in the second pad; an organic insulating film provided on the first semiconductor chip, the organic insulating film covering the depression and not covering at least a portion of the first pad; and a redistribution layer having a lower portion connected to the first pad and an upper portion disposed on the organic insulating film.
    Type: Grant
    Filed: September 3, 2020
    Date of Patent: October 18, 2022
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventor: Keiichiro Ohsawa
  • Patent number: 11462503
    Abstract: Embodiments of bonded semiconductor structures and fabrication methods thereof are disclosed. In an example, a method for forming a semiconductor device is disclosed. A first interconnect layer including first interconnects is formed above a first substrate. A first bonding layer including first bonding contacts is formed above the first interconnect layer, such that each first interconnect is in contact with a respective first bonding contact. A second interconnect layer including second interconnects is formed above a second substrate. A second bonding layer including second bonding contacts is formed above the second interconnect layer, such that at least one second bonding contact is in contact with a respective second interconnect, and at least another second bonding contact is separated from the second interconnects. The first and second substrates are bonded in a face-to-face manner, such that each first bonding contact is in contact with one second bonding contact at a bonding interface.
    Type: Grant
    Filed: October 6, 2020
    Date of Patent: October 4, 2022
    Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
    Inventors: Tao Wang, Si Ping Hu, Jia Wen Wang, Shi Qi Huang, Jifeng Zhu, Jun Chen, Zi Qun Hua
  • Patent number: 11450615
    Abstract: A structure including a first semiconductor die, an interposer and a first insulating encapsulation is provided. The first semiconductor die includes a semiconductor substrate, an interconnect structure disposed on the semiconductor substrate and conductive vias disposed on the interconnect structure. The interposer includes a dielectric layer and through vias penetrating through the dielectric layer. The first insulating encapsulation laterally encapsulates the first semiconductor die and the interposer, wherein a thickness of the dielectric layer of the interposer substantially equals to a thickness of the first semiconductor die and a thickness of the first insulating encapsulation.
    Type: Grant
    Filed: June 12, 2020
    Date of Patent: September 20, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsung-Fu Tsai, Szu-Wei Lu
  • Patent number: 11450596
    Abstract: A lead frame includes a die paddle, a plurality of leads, at least one connector and a bonding layer. The leads surround the die paddle. Each of the leads includes an inner lead portion adjacent to and spaced apart from the die paddle and an outer lead portion opposite to the inner lead portion. The connector is connected to the die paddle and the inner lead portions of the leads. The bonding layer is disposed on a lower surface of the die paddle and a lower surface of each of the outer lead portions.
    Type: Grant
    Filed: November 22, 2019
    Date of Patent: September 20, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Yi-Cheng Hsu, Chih-Hung Hsu, Mei-Lin Hsieh, Yuan-Chun Chen, Yu-Shun Hsieh, Ko-Pu Wu, Chin Li Huang
  • Patent number: 11450721
    Abstract: The present disclosure provides a pixel unit, a method of manufacturing the same, and an array substrate. The pixel unit includes: a driving transistor, a switching transistor, and a light emitting element on a substrate; wherein the driving transistor has an input electrode electrically connected to a first power supply terminal and an output electrode electrically connected to a first terminal of the light emitting element; the switching transistor has an input electrode electrically connected to a data line, a control electrode electrically connected to a scan line, and an output electrode electrically connected to a gate electrode of the driving transistor; wherein the switching transistor and the driving transistor have different threshold voltages.
    Type: Grant
    Filed: September 21, 2018
    Date of Patent: September 20, 2022
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Dongfang Wang, Bin Zhou, Ce Zhao, Tongshang Su, Yuankui Ding, Ming Wang
  • Patent number: 11444023
    Abstract: A package structure includes a semiconductor die, an insulating encapsulant, a first redistribution layer, a second redistribution layer, a heat dissipation element and conductive balls. The insulating encapsulant is encapsulating the semiconductor die, and has a first surface and a second surface opposite to the first surface. The first redistribution layer is located on the first surface of the insulating encapsulant and includes at least one feed line and one ground plate. The second redistribution layer is located on the second surface of the insulating encapsulant and electrically connected to the semiconductor die and the first redistribution layer. The heat dissipation element is disposed on the first redistribution layer and includes a conductive base and antenna patterns, wherein the antenna patterns is electrically connected to the feed line and is electrically coupled to the ground plate of the first redistribution layer.
    Type: Grant
    Filed: October 26, 2020
    Date of Patent: September 13, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sen-Kuei Hsu, Hsin-Yu Pan, Yi-Che Chiang
  • Patent number: 11444031
    Abstract: A semiconductor device is provided for implementing at least one logic element. The semiconductor device includes a semiconductor substrate. The first transistor and a second transistor are formed on the semiconductor substrate. Each transistor comprises a source, a drain, and a gate. The gate of the first transistor extends longitudinally as part of a first linear strip and the gate of the second transistor extends longitudinally as part of the second linear strip parallel to and spaced apart from the first linear strip. A first CB layer forms a local interconnect layer electrically connected to the gate of the first transistor. A second CB layer forms a local interconnect layer electrically connected to the gate of the second transistor. A CA layer forms a local interconnect layer extending longitudinally between a first end and a second end of the CA layer. The CA layer is electrically connected to the first and second CB layers.
    Type: Grant
    Filed: September 30, 2020
    Date of Patent: September 13, 2022
    Assignee: GLOBALFOUNDRIES U.S. INC.
    Inventors: Mahbub Rashed, Irene Y. Lin, Steven Soss, Jeff Kim, Chinh Nguyen, Marc Tarabbia, Scott Johnson, Subramani Kengeri, Suresh Venkatesan
  • Patent number: 11437283
    Abstract: Backside contact structures include etch selective materials to facilitate backside contact formation. An integrated circuit structure includes a frontside contact region, a device region below the frontside contact region, and a backside contact region below the device region. The device region includes a transistor. The backside contact region includes a first dielectric material under a source or drain region of the transistor, a second dielectric material laterally adjacent to the first dielectric material and under a gate structure of the transistor. A non-conductive spacer is between the first and second dielectric materials. The first and second dielectric materials are selectively etchable with respect to one another and the spacer. The backside contact region may include an interconnect feature that, for instance, passes through the first dielectric material and contacts a bottom side of the source/drain region, and/or passes through the second dielectric material and contacts the gate structure.
    Type: Grant
    Filed: March 15, 2019
    Date of Patent: September 6, 2022
    Assignee: Intel Corporation
    Inventors: Aaron D. Lilak, Ehren Mannebach, Anh Phan, Richard E. Schenker, Stephanie A. Bojarski, Willy Rachmady, Patrick R. Morrow, Jeffery D. Bielefeld, Gilbert Dewey, Hui Jae Yoo
  • Patent number: 11430731
    Abstract: A semiconductor arrangement includes a lower semiconductor chip, an upper semiconductor chip arranged over an upper main side of the lower semiconductor chip, a metallization layer arranged on the upper main side of the lower semiconductor chip, and a bonding material which fastens the upper semiconductor chip on the lower semiconductor chip. The metallization layer includes a structure with increased roughness in comparison with the rest of the metallization layer, the structure being arranged along a contour of the upper semiconductor chip.
    Type: Grant
    Filed: February 19, 2020
    Date of Patent: August 30, 2022
    Assignee: Infineon Technologies AG
    Inventor: Michael Stadler
  • Patent number: 11430514
    Abstract: An electronic circuit includes a plurality of word lines; a plurality of bit lines intersecting the plurality of word lines at a plurality of grid points; and a plurality of resistive random-access memory cells located at the plurality of grid points. Each of the resistive random-access memory cells includes a top metal coupled to one of: a corresponding one of the word lines and a corresponding one of the bit lines; a bottom metal coupled to another one of: the corresponding one of the word lines and the corresponding one of the bit lines; a dielectric sandwiched between the top metal and the bottom metal; and a high-resistance semiconductive spacer electrically connecting the top metal and the bottom metal in parallel with the dielectric.
    Type: Grant
    Filed: January 12, 2021
    Date of Patent: August 30, 2022
    Assignee: International Business Machines Corporation
    Inventors: Youngseok Kim, Soon-Cheon Seo, Choonghyun Lee, Injo Ok, Alexander Reznicek
  • Patent number: 11417623
    Abstract: A semiconductor device includes a semiconductor layer having a first surface, an insulating layer formed at the first surface of the semiconductor layer, a Cu conductive layer formed on the insulating layer, the Cu conductive layer made of a metal mainly containing Cu, a second insulating layer formed on the insulating layer, the second insulating layer covering the Cu conductive layer, a Cu pillar extending in a thickness direction in the second insulating layer, the Cu pillar made of a metal mainly containing Cu and electrically connected to the Cu conductive layer, and an intermediate layer formed between the Cu conductive layer and the Cu pillar, the intermediate layer made of a material having a linear expansion coefficient smaller than a linear expansion coefficient of the Cu conductive layer and smaller than a linear expansion coefficient of the Cu pillar.
    Type: Grant
    Filed: March 27, 2020
    Date of Patent: August 16, 2022
    Assignee: ROHM CO., LTD.
    Inventors: Shoji Takei, Yuji Koga
  • Patent number: 11417726
    Abstract: The present disclosure provides a semiconductor structure having an air gap dielectric and a method for preparing the semiconductor structure. The semiconductor structure includes a substrate; a plurality of conductive pillars disposed over the substrate; a plurality of dielectric pillars, disposed over the substrate, separated from the conductive pillars; a plurality of dielectric caps disposed over the conductive pillars, separated from the dielectric pillars; and a sealing layer disposed over the dielectric pillars and the dielectric caps.
    Type: Grant
    Filed: December 14, 2020
    Date of Patent: August 16, 2022
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Chin-Te Kuo
  • Patent number: 11417673
    Abstract: A microelectronic device comprises a stack structure comprising alternating conductive structures and insulative structures arranged in tiers, the tiers individually comprising one of the conductive structures and one of the insulative structures, first support pillar structures extending through the stack structure within a first region of the microelectronic device, the first support pillar structures electrically isolated from a source structure underlying the stack structure, second support pillar structures extending through the stack structure within a second region of the microelectronic device, the second support pillar structures comprising an electrically conductive material in electrical communication with the source structure, and bridge structures extending between at least some neighboring first support pillar structures of the first support pillar structures. Related memory devices, electronic systems, and methods are also described.
    Type: Grant
    Filed: June 22, 2020
    Date of Patent: August 16, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Shuangqiang Luo, Indra V. Chary, Justin B. Dorhout
  • Patent number: 11410903
    Abstract: An object is to provide a technique capable of suppressing insulation defects caused by the arrival of bubbles contained in an adhesive at a circuit pattern in a semiconductor device. A semiconductor device includes the resin-insulated copper base plate having the copper base plate, the insulating layer provided on the upper surface of the copper base plate, and the circuit pattern provided on the upper surface of the insulating layer, the semiconductor element mounted on the upper surface of the resin-insulated copper base plate, the case joined to the outer peripheral portion of the resin-insulated copper base plate via the adhesive, the sealing material sealing, in the case, the upper surface of the resin-insulated copper base plate and the semiconductor element, and the roughening patterns formed on the upper surface of the insulating layer such that the circuit pattern is enclosed therewith in a plan view.
    Type: Grant
    Filed: January 21, 2021
    Date of Patent: August 9, 2022
    Assignee: Mitsubishi Electric Corporation
    Inventor: Shotaro Sakumoto
  • Patent number: 11410914
    Abstract: A power module includes: a base plate having a first surface; electrode plate provided at the first surface; a wire connected to a semiconductor chip and the electrode plate; a metal member connected to the electrode plate; a terminal plate; a first resin layer, a connection portion of the wire and the semiconductor chip being disposed inside the first resin layer; and a second resin layer provided on the first resin layer and having a lower elastic modulus than the first resin layer. The terminal plate includes a bonding portion contacting an upper surface of the metal member, a curved portion curved upward from the bonding portion. The curved portion is disposed inside the second resin layer, and a length from the first surface of a lower surface of the bonding portion is greater than a length from the first surface of the connection portion.
    Type: Grant
    Filed: July 10, 2020
    Date of Patent: August 9, 2022
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Keiichiro Matsuo, Jun Karasawa, Haruka Yamamoto, Shinya Hayashiyama
  • Patent number: 11404277
    Abstract: Various implementations of a method of forming a semiconductor package may include forming a plurality of notches into the first side of a semiconductor substrate; applying a permanent coating material into the plurality of notches; forming a first organic material over the first side of the semiconductor substrate and the plurality of notches; thinning a second side of the semiconductor substrate opposite the first side one of to or into the plurality of notches; and singulating the semiconductor substrate through the permanent coating material into a plurality of semiconductor packages.
    Type: Grant
    Filed: May 20, 2020
    Date of Patent: August 2, 2022
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Francis J. Carney, Yusheng Lin, Michael J. Seddon, Chee Hiong Chew, Soon Wei Wang, Eiji Kurose
  • Patent number: 11404351
    Abstract: Methods, systems, and apparatuses for a power card for use in a vehicle. The power card includes an N lead frame, a P lead frame, and an O lead frame each having a body portion and a terminal portion, with the O lead frame located between the N lead frame and the P lead frame. The power card includes a first power device being located on a first side of the O lead frame and a second power device being located on a second side of the O lead frame, the body portion of the O lead frame having one or more channels configured to receive a cooling liquid for cooling the first power device and the second power device.
    Type: Grant
    Filed: April 21, 2020
    Date of Patent: August 2, 2022
    Assignee: TOYOTA MOTOR ENGINEERING & MANUFACTURING NORTH AMERICA, INC.
    Inventor: Feng Zhou
  • Patent number: 11398412
    Abstract: A semiconductor package includes a semiconductor chip with a normal connection electrode and a measurement connection electrode, formed on a first surface, and a substrate with a normal substrate pad, connected to the normal connection electrode, and a measurement substrate pad, connected to the measurement connection electrode. The normal substrate pad and the measurement substrate pad are formed on a surface that faces the first surface. The measurement connection electrode includes first and second edge measurement connection electrodes and first and second center measurement connection electrodes. The measurement substrate pad includes a center measurement substrate pad, a first edge measurement substrate pad, and a second edge measurement substrate pad.
    Type: Grant
    Filed: November 12, 2020
    Date of Patent: July 26, 2022
    Assignee: SK hynix Inc.
    Inventor: Hyun Chul Seo
  • Patent number: 11398342
    Abstract: An electronic component includes an element body and outer electrodes on the element body. The element body includes top and bottom opposed surfaces, and side surfaces connecting the top and bottom surfaces. An outer electrode includes a lower layer electrode on the top surface and the bottom surface, and an upper layer electrode overlying the lower layer electrode and extending from an upper side of the lower electrode onto the side surface. When viewed from a direction orthogonal to the top and bottom surfaces, an edge of the lower layer electrode is disposed at a position farther from the side surface at which the upper layer electrode is provided than a position of an edge of the upper layer electrode, and a radius of curvature of the edge of the lower electrode is larger than a radius of curvature of the edge of the upper layer electrode.
    Type: Grant
    Filed: April 15, 2019
    Date of Patent: July 26, 2022
    Assignee: MURATA MANUFACTURING CO., LTD
    Inventors: Jun Adachi, Naganori Hirakawa, Hiroyuki Asano, Sumiyo Nakamura
  • Patent number: 11393797
    Abstract: A chip package is provided. The chip package includes a semiconductor substrate having an edge and a protective layer surrounding the semiconductor substrate. The chip package also includes a conductive line over the protective layer and the semiconductor substrate. The conductive line has a first portion and a second portion in direct contact with the first portion, and the second section at least partially covers the edge. In a top view of the conductive layer, line widths of the first portion and the second portion are different from each other.
    Type: Grant
    Filed: December 14, 2020
    Date of Patent: July 19, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jie Chen, Hsien-Wei Chen
  • Patent number: 11393778
    Abstract: A semiconductor device according to the present invention includes: a semiconductor element; a first metal body having a die pad to which the semiconductor element is mounted, the semiconductor element being mounted on a die bond surface of the die pad; a second metal body which has a wire bond pad connected to a signal electrode of the semiconductor element via a wire, and is provided on the same side as the die bond surface such that the second metal body is separated from the first metal body and covered by the first metal body, the second metal body forming a transmission line together with the first metal body; and a molding resin holding the first metal body and the second metal body such that a surface of the first metal body opposite to the die bond surface is exposed.
    Type: Grant
    Filed: December 5, 2018
    Date of Patent: July 19, 2022
    Assignee: Mitsubishi Electric Corporation
    Inventors: Hiroaki Ichinohe, Akihiro Matsusue
  • Patent number: 11387167
    Abstract: Present disclosure provides a semiconductor structure, including a semiconductor substrate, a first metal layer, and a through substrate via (TSV). The semiconductor substrate has an active side. The first metal layer is closest to the active side of the semiconductor substrate, and the first metal layer has a first continuous metal feature. The TSV is extending from the semiconductor substrate to the first continuous metal feature. A width of the TSV at the first metal layer is wider than a width of the first continuous metal feature. Present disclosure also provides a method for manufacturing the semiconductor structure described herein.
    Type: Grant
    Filed: July 3, 2020
    Date of Patent: July 12, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Min-Feng Kao, Dun-Nian Yaung, Jen-Cheng Liu, Ching-Chun Wang, Kuan-Chieh Huang, Hsing-Chih Lin, Yi-Shin Chu
  • Patent number: 11387285
    Abstract: The present disclosure relates to a display substrate and a manufacturing method thereof, and a display device. The display substrate includes a plurality of pixel units each including a first sub-pixel and a second sub-pixel. The method includes: forming a first material layer and a patterned second material layer, the first material layer including a portion corresponding to an area between the first and second sub-pixels, and the second material layer has a first opening exposing the portion of the first material layer, corresponding to the area between the first and second sub-pixels; and forming a first quantum dot solution in a first area corresponding to the first sub-pixel, on the second material layer to form a first color filter sublayer, wherein wettability of the second material layer to the first quantum dot solution is greater than wettability of the first material layer to the first quantum dot solution.
    Type: Grant
    Filed: November 29, 2019
    Date of Patent: July 12, 2022
    Assignee: BOE Technology Group Co., Ltd.
    Inventor: Youngsuk Song
  • Patent number: 11387214
    Abstract: Apparatuses and methods are described. This apparatus includes a bridge die having first contacts on a die surface being in a molding layer of a reconstituted wafer. The reconstituted wafer has a wafer surface including a layer surface of the molding layer and the die surface. A redistribution layer on the wafer surface includes electrically conductive and dielectric layers to provide conductive routing and conductors. The conductors extend away from the die surface and are respectively coupled to the first contacts at bottom ends thereof. At least second and third IC dies respectively having second contacts on corresponding die surfaces thereof are interconnected to the bridge die and the redistribution layer. A first portion of the second contacts are interconnected to top ends of the conductors opposite the bottom ends thereof in part for alignment of the at least second and third IC dies to the bridge die.
    Type: Grant
    Filed: December 12, 2019
    Date of Patent: July 12, 2022
    Assignee: INVENSAS LLC
    Inventors: Liang Wang, Rajesh Katkar
  • Patent number: 11380674
    Abstract: Disclosed are an array substrate, display panel and display device. The array substrate includes: a substrate, where the substrate includes a display area and a peripheral circuit area surrounding the display area; the peripheral circuit area is provided with a gate drive circuit; the gate drive circuit includes a group of shift registers connected in cascade; a first metal layer; a second metal layer; scan lines and connection structures corresponding to the scan lines one-to-one; where the first metal layer includes the scan lines; the second metal layer includes the connection structures; the shift registers include scan signal output ends; the scan signal output ends are electrically connected to the scan lines one-to-one through the connection structures; at least one end of at least one scan line is provided with an electrostatic dispersion structure; the electrostatic dispersion structure includes an electrostatic dispersion line or an first electrostatic dispersion ring.
    Type: Grant
    Filed: June 30, 2020
    Date of Patent: July 5, 2022
    Assignee: Xiamen Tianma Micro-Electronics Co., Ltd.
    Inventors: Jianrong Chen, Manyu Lin, Xiu Liang, Xiaoli Xue
  • Patent number: 11380618
    Abstract: Various implementations described herein are directed to an integrated circuit having a power gate cell and a first power distribution grid. The integrated circuit may include a second power distribution grid aligned with and disposed above the power gate cell. The second power distribution grid may be disposed between the power gate cell and the first power distribution grid.
    Type: Grant
    Filed: February 2, 2018
    Date of Patent: July 5, 2022
    Assignee: Arm Limited
    Inventors: Marlin Wayne Frederick, Jr., Karen Lee Delk
  • Patent number: 11380644
    Abstract: Provided are a semiconductor package and a method for fabricating the semiconductor package. The method includes followings steps: a first workpiece is provided, where the first workpiece includes a first substrate and multiple first rewiring structures arranged on the first substrate at intervals, and each first rewiring structure includes at least two first rewiring layers; an encapsulation layer is formed on the first rewiring structures, where the encapsulation layer is provided with multiple first through holes, and the first through holes exposes one first rewiring layer; at least two second rewiring layers are disposed on a side of the encapsulation layer facing away from the first rewiring layer; multiple semiconductor elements are provided, where the semiconductor elements are arranged on a side of the first rewiring structures facing away from the encapsulation layer, where the first rewiring layers are electrically connected to pins of the semiconductor elements.
    Type: Grant
    Filed: June 30, 2020
    Date of Patent: July 5, 2022
    Assignees: Shanghai Tianma Micro-Electronics Co., Ltd., Shanghai AVIC OPTO Electronics Co., Ltd.
    Inventors: Feng Qin, Kerui Xi, Tingting Cui, Jie Zhang, Xuhui Peng
  • Patent number: 11371891
    Abstract: A semiconductor device that can detect temperature appropriately is provided. A semiconductor device provided with a semiconductor substrate in which one or more transistor portions and one or more diode portions are provided is provided, including: a temperature detecting portion provided above the top surface of the semiconductor substrate and having a longitudinal side in a predetermined longitudinal direction; a top surface electrode provided above the top surface of the semiconductor substrate; and one or more external lines that have a connecting part connected with the top surface electrode and electrically connect the top surface electrode to a circuit outside the semiconductor device. The temperature detecting portion extends across the one or more transistor portions and the one or more diode portions in the longitudinal direction, and the connecting part of at least one of the external lines is arranged around the temperature detecting portion when seen from above.
    Type: Grant
    Filed: September 29, 2020
    Date of Patent: June 28, 2022
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Kenichiro Sato
  • Patent number: 11367695
    Abstract: An interposer includes one or more capacitors to store charge to provide signals to an integrated circuit electrically connected to the interposer. First connectors to each capacitor are interspersed with second connectors to the capacitors and are spaced apart from adjacent second connectors. The one or more capacitors and the resistances associated with the conductive paths between each capacitor and a connector or another capacitor can be modeled.
    Type: Grant
    Filed: June 12, 2019
    Date of Patent: June 21, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Fong-yuan Chang, Cheng-Hung Yeh, Hsiang-Ho Chang, Po-Hsiang Huang, Chin-Her Chien, Sheng-Hsiung Chen, Aftab Alam Khan, Keh-Jeng Chang, Chin-Chou Liu, Yi-Kan Cheng
  • Patent number: 11362093
    Abstract: A method of performing co-integrated fabrication of a non-volatile memory (NVM) and a gate-all-around (GAA) nanosheet field effect transistor (FET) includes recessing fins in a channel region of the NVM and the FET to form source and drain regions adjacent to recessed fins, and removing alternating portions of the recessed fins of the NVM and the FET to form gaps in the recessed fins. A stack of layers that make up an NVM structure are conformally deposited within the gaps of the recessed fins leaving second gaps, smaller than the gaps, and above the recessed fins of the NVM while protecting the FET with the organic planarization layer (OPL) and a block mask. The OPL and block mask are removed from the FET, and another OPL and another block mask protect the NVM while a gate of the FET is formed above the recessed fins and within the gaps.
    Type: Grant
    Filed: September 30, 2020
    Date of Patent: June 14, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Zhenxing Bi, Zheng Xu, Dexin Kong, Kangguo Cheng
  • Patent number: 11348807
    Abstract: A semiconductor package includes an interposer having a separation layer on a rear surface of which a plurality of first recesses is arranged. A plurality of wiring structures is stacked on the separation layer alternately with a plurality of insulation interlayers. A plurality of semiconductor devices is arranged, side by side, on the interposer side and connected to a plurality of the wiring structures. A plurality of contact terminals on the rear surface of the separation layer is connected to the plurality of the wiring structures through the separation layer. A flatness deterioration of the interposer is minimized and the contact surface between the interposer and under fill resin is enlarged.
    Type: Grant
    Filed: July 10, 2020
    Date of Patent: May 31, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Junghoon Kang
  • Patent number: 11342296
    Abstract: A semiconductor structure includes an insulating encapsulant, a semiconductor element, a redistribution layer and an insulating layer. The semiconductor element is embedded in the insulating encapsulant. The redistribution layer is disposed over the insulating encapsulant and electrically connected to the semiconductor element. The insulating layer is disposed in between the insulating encapsulant and the redistribution layer, wherein an uneven interface exists between the insulating layer and the insulating encapsulant, and a planar interface exists between the insulating layer and the redistribution layer.
    Type: Grant
    Filed: November 23, 2020
    Date of Patent: May 24, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Chih Chen, Hung-Jui Kuo, Yu-Hsiang Hu, Sih-Hao Liao, Po-Han Wang
  • Patent number: 11333707
    Abstract: Methods for testing an application specific integrated circuit (ASIC). A set of representations is created that overlays power density information and clock gate physical locations of a set of clock gates in a critical sub-chip of the ASIC for test mode power analysis. The set of representations are further grouped in the sub-chip into various groups based on overlapping of the set of representations. Then, a set of test control signals is generated corresponding to each of the set of clock gates during at-speed test mode of operation such that each clock gate with overlapping representations receive different test control signals. Further, patterns are generated using a virtual constraint function to selectively enable the set of test control signals such that the set of test control signals are not activated simultaneously.
    Type: Grant
    Filed: December 5, 2019
    Date of Patent: May 17, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Khushboo Agarwal, Sanjay Krishna Hulical Vijayaraghavachar, Raashid Moin Shaikh, Srivaths Ravi, Wilson Pradeep, Rajesh Kumar Tiwari
  • Patent number: 11325388
    Abstract: A liquid ejecting unit includes: a liquid ejecting head configured to eject a liquid; a holding portion holding the liquid ejecting head; a coupling member; and a first fixing member fixing the liquid ejecting head to the holding portion, in which the coupling member is provided with a first coupling portion and a first through-hole, the liquid ejecting head is provided with a second coupling portion that is configured to be coupled to the first coupling portion, and the first fixing member passes through the first through-hole in a state in which the first coupling portion and the second coupling portion are coupled to each other.
    Type: Grant
    Filed: March 17, 2020
    Date of Patent: May 10, 2022
    Assignee: Seiko Epson Corporation
    Inventors: Daiki Tatsuta, Osamu Murayama, Yoji Takahashi
  • Patent number: 11322395
    Abstract: Some embodiments relate to a semiconductor structure including a first inter-level dielectric (ILD) structure overlying a substrate. A conductive contact directly overlies the substrate and is disposed within the first ILD structure. A conductive wire directly overlies the conductive contact. A conductive capping layer overlies the conductive wire such that the conductive capping layer continuously extends along an upper surface of the conductive wire. A second ILD structure overlies the conductive capping layer. The second ILD structure is disposed along opposing sides of the conductive wire. A pair of air-gaps are disposed within the second ILD structure. The conductive wire is spaced laterally between the pair of air-gaps. A dielectric capping layer is disposed along an upper surface of the conductive capping layer. The dielectric capping layer is spaced laterally between the pair of air-gaps and is laterally offset from an upper surface of the first ILD structure.
    Type: Grant
    Filed: May 18, 2020
    Date of Patent: May 3, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsin-Yen Huang, Chi-Lin Teng, Hai-Ching Chen, Shau-Lin Shue, Shao-Kuan Lee, Cheng-Chin Lee, Ting-Ya Lo
  • Patent number: 11322538
    Abstract: The present technology relates to an imaging device, an electronic apparatus, and a method of manufacturing an imaging device capable of thinning a semiconductor on a terminal extraction surface while maintaining a strength of a semiconductor chip. There is provided an imaging device including: a first substrate having a pixel region in which pixels are two-dimensionally arranged, the pixels performing photoelectric conversion of light; and a second substrate in which a through silicon via is formed, in which a dug portion is formed in a back surface of the second substrate opposite to an incident side of light of the second substrate, and a redistribution layer (RDL) connected to a back surface of the first substrate is formed in the dug portion. The present technology can be applied to, for example, a semiconductor package including a semiconductor chip.
    Type: Grant
    Filed: February 8, 2018
    Date of Patent: May 3, 2022
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Suguru Saito, Nobutoshi Fujii
  • Patent number: 11315860
    Abstract: A package manufacturing process and semiconductor packages are provided. An interposer having a crystal structure is provided. A first die and a second die are bonded on the interposer. The second die is positioned to be spaced apart from the first die with a gap extending direction that is perpendicular to a shortest distance of the gap, and the gap extending direction is not parallel with a crystallographic orientation of the crystal structure of the interposer. A molding compound is formed over the interposer covering the first and second dies. The molding compound and the interposer are cut into packages.
    Type: Grant
    Filed: October 17, 2019
    Date of Patent: April 26, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Li-Huan Chu, Hsu-Hsien Chen, Liang-Chen Lin, Tsung-Yang Hsieh, Hsin-Hsien Lee, Kuen-Hong Tsai
  • Patent number: 11302577
    Abstract: A method includes using a second hard mask layer over a gate stack to protect the gate electrode during etching a self-aligned contact. The second hard mask is formed over a first hard mask layer, where the first hard mask layer has a lower etch selectivity than the second hard mask layer.
    Type: Grant
    Filed: January 17, 2020
    Date of Patent: April 12, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Yu-Lien Huang
  • Patent number: 11296108
    Abstract: According to one embodiment, a semiconductor memory device includes conductive layers stacked at intervals and extending from a memory cell array region to a contact region. The contact region includes a staircase contact region and a staircase connection region. The staircase contact region includes a descending step contact region with steps descending in a first direction away from the memory cell array region and an ascending step contact region with steps ascending in the first direction, and the descending step contact region and the ascending step contact region include terrace faces provided with respective contacts connected thereto. The staircase connection region includes conductive layers formed of layers same as conductive layers connected to the contacts of the ascending step contact region.
    Type: Grant
    Filed: August 2, 2019
    Date of Patent: April 5, 2022
    Assignee: Kioxia Corporation
    Inventor: Ayumu Ozawa
  • Patent number: 11289680
    Abstract: A flexible display and manufacturing method thereof are disclosed. In one aspect, the flexible display includes a flexible substrate including a bending area, an insulating layer disposed on the flexible substrate, and at least one groove in the insulating layer within the bending area. The flexible display also includes a stress relaxation layer disposed on the at least one groove and a plurality of wires formed over the insulating layer and the stress relaxation layer.
    Type: Grant
    Filed: February 10, 2020
    Date of Patent: March 29, 2022
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventor: Nam Jin Kim
  • Patent number: 11289420
    Abstract: A semiconductor device includes a first conductive pattern having a first line portion extending in a first direction and a first bending portion that extends from the first line portion. A closed area, surrounded by the first line portion and the first bending portion, is defined at one side of the first line portion. The semiconductor device further includes a second conductive pattern disposed in the closed area, the second conductive pattern being spaced apart from the first conductive pattern.
    Type: Grant
    Filed: June 12, 2019
    Date of Patent: March 29, 2022
    Assignee: SK hynix Inc.
    Inventor: Dae Sung Eom
  • Patent number: 11289424
    Abstract: Provided are a package and a method of manufacturing the same. The package includes a first die, a second die, a bridge structure, an encapsulant, and a redistribution layer (RDL) structure. The first die and the second die are disposed side by side. The bridge structure is disposed over the first die and the second die to electrically connect the first die and the second die. The encapsulant laterally encapsulates the first die, the second die, and the bridge structure. The RDL structure is disposed over a backside of the bridge structure and the encapsulant. The RDL structure includes an insulating structure and a conductive pattern, the conductive pattern is disposed over the insulating structure and extending through the insulating structure and a substrate of the bridge structure, so as to form at least one through via in the substrate of the bridge structure.
    Type: Grant
    Filed: October 17, 2019
    Date of Patent: March 29, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Wei Wu, Chen-Hua Yu, Kuo-Chung Yee, Szu-Wei Lu, Ying-Ching Shih
  • Patent number: 11282779
    Abstract: A package structure including a first circuit board structure, a redistribution layer structure, bonding elements, and a semiconductor package is provided. The redistribution layer structure is disposed over and electrically connected to the first circuit board structure. The bonding elements are disposed between and electrically connected to the redistribution layer structure and the first circuit board structure. Each of the bonding elements has a core portion and a shell portion surrounding the core portion. A stiffness of the core portion is higher than a stiffness of the shell portion. A semiconductor package is disposed over and electrically connected to the redistribution layer structure.
    Type: Grant
    Filed: February 20, 2020
    Date of Patent: March 22, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kai-Chiang Wu, Jiun-Yi Wu, Yu-Min Liang
  • Patent number: 11282782
    Abstract: According to one embodiment, a semiconductor memory device includes first and second conductor layers, a first pillar, a first contact, and a source line drive circuit. The first pillar is passing through the second conductor layers. The first pillar includes a first semiconductor layer and a second insulator layer. The first semiconductor layer includes a side surface partially in contact with the first conductor layer. The first contact is passing through the second conductor layers. The first contact includes a third conductor layer and a third insulator layer. The third conductor layer includes a side surface partially in contact with the first conductor layer. The source line drive circuit is electrically coupled to the first conductor layer via the first contact.
    Type: Grant
    Filed: September 11, 2019
    Date of Patent: March 22, 2022
    Assignee: KIOXIA CORPORATION
    Inventor: Hisashi Kato
  • Patent number: 11276741
    Abstract: The present disclosure discloses a display substrate and a display device. The package structure of the display component includes: a base substrate, a display component arranged on a surface of the base substrate, and a package layer covering the display component, in which the display component includes a display area and a peripheral area surrounding the display area, and the peripheral area is provided with a signal line pattern having an inclined side along a direction perpendicular to an extending direction of the signal line pattern with a slope angle of less than 90 degrees.
    Type: Grant
    Filed: May 29, 2019
    Date of Patent: March 15, 2022
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventor: Chunping Long