Of Specified Configuration Patents (Class 257/773)
  • Patent number: 10381322
    Abstract: A first substrate has a first mesa structure that protrudes from a first bonding-side planar surface. A first metal pad structure is embedded within the first mesa structure. A second substrate has a first recess cavity that is recessed from a second bonding-side planar surface. A second metal pad structure is located at a recessed region of the first recess cavity. The first bonding-side planar surface and the second bonding-side planar surface are brought into physical contact with each other, while the first mesa structure is disposed within a volume of the first recess cavity by self-alignment. A gap is provided between the first metal pad structure and the second metal pad structure within a volume of the first recess cavity. A metal connection pad is formed by selectively growing a third metallic material from the first metal pad structure and the second metal pad structure.
    Type: Grant
    Filed: April 23, 2018
    Date of Patent: August 13, 2019
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Yasunobu Azuma, Michiaki Sano
  • Patent number: 10374085
    Abstract: A semiconductor device includes a first active region that extends on a substrate in a first direction, a second active region that extends in parallel with the first active region, an element isolation region between the first and second active regions, a gate structure that extends in a second direction different from the first direction, and intersects the first and second active regions, a lower contact spaced apart from the gate structure in the first direction, the lower contact being on the first active region, the element isolation region, and the second active region, and an upper contact on the lower contact between the first active region and the second active region. A width of the lower contact in the first direction that is on the first active region m narrower than a width of the lower contact in the first direction that is on the element isolation region.
    Type: Grant
    Filed: June 5, 2018
    Date of Patent: August 6, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang Young Kim, Deok Han Bae, Byung Chan Ryu, Da Un Jeon
  • Patent number: 10373864
    Abstract: Methods of wetting a semiconductor substrate may include forming a controlled atmosphere in a processing chamber housing the semiconductor substrate. The semiconductor substrate may define a plurality of features, which may include vias. The methods may include flowing a wetting agent into the processing chamber. A chamber pressure may be maintained below about 100 kPa. The methods may also include wetting the plurality of features defined in the substrate.
    Type: Grant
    Filed: December 22, 2017
    Date of Patent: August 6, 2019
    Assignee: Applied Materials, Inc.
    Inventors: Paul McHugh, Bridger Hoerner, Marvin Bernt, Thomas H. Oberlitner, Brian Aegerter, Richard W. Plavidal, Andrew Anten, Adam McClure, Randy Harris
  • Patent number: 10361219
    Abstract: A silicon-on-insulator substrate which includes a semiconductor substrate, a buried oxide layer, and a semiconductor layer is provided. A hard mask layer is formed over a first region of the silicon-on-insulator substrate. A first silicon-germanium layer is epitaxially grown on the semiconductor layer within a second region of the silicon-on-insulator substrate. The second region is at least a portion of the semiconductor layer not covered by the hard mask layer. A thermal annealing process is performed, such that germanium atoms from the first silicon-germanium layer are migrated to the portion of the semiconductor layer to form a second silicon-germanium layer. The hard mask layer is removed. A layer of semiconductor material is epitaxially grown on top of the semiconductor layer and the second silicon-germanium layer, where the layer of semiconductor material composed of the same material as semiconductor layer.
    Type: Grant
    Filed: June 30, 2015
    Date of Patent: July 23, 2019
    Assignee: International Business Machines Corporation
    Inventors: Josephine B. Chang, Leland Chang, Isaac Lauer, Jeffrey W. Sleight
  • Patent number: 10361350
    Abstract: An optoelectronic component and a method for producing an optoelectronic component are disclosed. In an embodiment the component includes a semiconductor chip, a molded body and an electrical through-contact constituting an electrically conductive connection through the molded body. The through-contact and the semiconductor chip are embedded alongside one another and are spaced apart in the molded body. A first contact pad of the through-contact is arranged at an underside of the molded body. A second contact pad of the through-contact is arranged at a top side of the molded body. The second contact pad is electrically conductively connected to the electrical contact of the semiconductor chip. The through-contact is arranged such that a molded body is arranged at least in a section between the first and second contact pads on a straight line between the first and second contact pads.
    Type: Grant
    Filed: June 9, 2016
    Date of Patent: July 23, 2019
    Assignee: OSRAM Opto Semiconductors GmbH
    Inventor: Andreas Ploessl
  • Patent number: 10360314
    Abstract: A method of forming conductive lines in a circuit is disclosed. The method includes arranging a plurality of signal traces in a first set of signal traces and a second set of signal traces, fabricating, using a first mask, a first conductive line for a first signal trace of the first set of signal traces and fabricating, using a second mask, a second conductive line for a second signal trace of the second set of signal traces. Each signal trace of the first set of signal traces has a first width. Each signal trace of the second set of signal traces has a second width different from the first width. The arranging is based on at least a length of a signal trace of the plurality of signal traces.
    Type: Grant
    Filed: September 25, 2017
    Date of Patent: July 23, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: Chung-Hui Chen
  • Patent number: 10354885
    Abstract: Embodiments are directed to a method of forming a semiconductor device and resulting structures having a hard masks for sidewall image transfer (SIT) block patterning. The method includes forming a first hard mask on a substrate. Spacers are formed on the first hard mask, and a second hard mask is formed over the spacers. The second hard mask and a portion of the first hard mask are concurrently removed by the same hard mask removal process to expose a surface of the substrate. After concurrently removing the second hard mask and portions of the first hard mask, the heights of the spacers are substantially equal.
    Type: Grant
    Filed: February 15, 2018
    Date of Patent: July 16, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ekmini A. De Silva, Isabel C. Estrada-Raygoza, Yann A. M. Mignot, Indira P. V. Seshadri, Yongan Xu
  • Patent number: 10354932
    Abstract: It is an object to particularly improve compositions of interlayer insulation films so as to provide semiconductor devices which exert high elongation percentage, are excellent in adherence and are hard to generate a crack, and methods of manufacturing the devices, and a semiconductor device (1) of the present invention is a semiconductor device provided with a semiconductor element (2) and a redistribution layer (4) electrically connected to the semiconductor element, and is characterized in that a solvent with specific gravity of 0.96 g/cm3 or more at a temperature of 25° C. remains in an amount of 5 ppm or more relative to the entire weight of an interlayer insulation film (6) inside the interlayer insulation film of the redistribution layer. According to the semiconductor device of the present invention, it is possible to exert high elongation percentage, provide excellent adherence, and suppress generation of a crack.
    Type: Grant
    Filed: March 14, 2018
    Date of Patent: July 16, 2019
    Assignee: ASAHI KASEI KABUSHIKI KAISHA
    Inventor: Tomoshige Yunokuchi
  • Patent number: 10355161
    Abstract: To achieve a high-reliability germanium photoreceiver. A photoreceiver portion of a germanium photoreceiver comprised of a p type silicon core layer, an i type germanium layer, and an n type silicon layer is covered with a second insulating film and from a coupling hole formed in the second insulating film, a portion of the upper surface of the photoreceiver portion is exposed. The coupling hole has, on the inner wall thereof, a barrier metal film and the barrier metal film has thereon a first-layer wiring made of a tungsten film. Tungsten hardly diffuses from the tungsten film into the i type germanium layer even when a thermal stress is applied, making it possible to prevent the resulting germanium photoreceiver from having diode characteristics deteriorated by the thermal stress.
    Type: Grant
    Filed: September 13, 2017
    Date of Patent: July 16, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Teruhiro Kuwajima, Shinichi Watanuki, Futoshi Komatsu, Tomoo Nakayama
  • Patent number: 10347524
    Abstract: A trench isolation structure is provided. The trench isolation structure includes a substrate. A polygonal trench is disposed in the substrate. An insulating material is disposed in the polygonal trench, and a polygon top-side contact structure is disposed in the polygonal trench and surrounded by the insulating material. The polygon top-side contact structure has the same shape as the polygonal trench from a top view. A method for forming the trench isolation structure is also provided.
    Type: Grant
    Filed: September 12, 2016
    Date of Patent: July 9, 2019
    Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Hsiung-Shih Chang, Jui-Chun Chang, Li-Che Chen
  • Patent number: 10347643
    Abstract: Some embodiments include a method of forming an integrated assembly. A construction is formed to include a conductive structure having a top surface, and a pair of sidewall surfaces extending downwardly from the top surface. Insulative material is over the top surface, and rails are along the sidewall surfaces. The rails include sacrificial material. The sacrificial material is removed to leave openings. Sealant material is formed to extend within the openings. The sealant material has a lower dielectric constant than the insulative material. Some embodiments include an integrated assembly having a conductive structure with a top surface and a pair of opposing sidewall surfaces extending downwardly from the top surface. Insulative material is over the top surface. Voids are along the sidewall surfaces and are capped by sealant material. The sealant material has a lower dielectric constant than the insulative material.
    Type: Grant
    Filed: June 7, 2018
    Date of Patent: July 9, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Guangjun Yang, Mohd Kamran Akhtar, Silvia Borsari, Alex J. Schrinsky
  • Patent number: 10340244
    Abstract: A semiconductor device includes a low-density substrate, a high-density patch positioned inside a cavity in the low-density substrate, a first semiconductor die, and a second semiconductor die. The first semiconductor dies includes high-density bumps and low-density bumps. The second semiconductor die includes high-density bumps and low-density bumps. The high-density bumps of the first semiconductor die and the high-density bumps of the second semiconductor die are electrically connected to the high-density patch. The low-density bumps of the first semiconductor die and the low-density bumps of the second semiconductor die are electrically connected to the low-density substrate.
    Type: Grant
    Filed: December 19, 2017
    Date of Patent: July 2, 2019
    Assignee: AMKOR TECHNOLOGY, INC.
    Inventors: Jae Hun Bae, Won Chul Do, Min Yoo, Young Rae Kim, Min Hwa Chang, Dong Hyun Kim, Ah Ra Jo, Seok Geun Ahn
  • Patent number: 10325786
    Abstract: The application provides a double-sided plastic fan-out package structure having an antenna structure. It includes a redistribution layer (RDL); a semiconductor chip, invertedly mounted on a first surface of the redistribution layer with a front surface facing downward; a first plastic encapsulation material layer, located on the first surface of the redistribution layer, encapsulating the semiconductor chip; a second plastic encapsulation material layer, located on a second surface of the redistribution layer; an antenna structure, located on a surface of the second plastic packaging material layer distant from the redistribution layer; an electrical connection structure, located inside the second plastic encapsulation material layer, and electrically connected to the antenna structure on the lower side of the redistribution layer. This structure can shield an interference signal of the antenna structure, thereby preventing the antenna structure from interfering the semiconductor chip.
    Type: Grant
    Filed: March 16, 2018
    Date of Patent: June 18, 2019
    Assignee: SJ SEMICONDUCTOR (JIANGYIN) CORPORATION
    Inventors: Yenheng Chen, Chengchung Lin, Chengtar Wu, Jangshen Lin
  • Patent number: 10319650
    Abstract: A semiconductor package including a redistribution substrate, and a semiconductor chip mounted on the redistribution substrate, the semiconductor chip having a conductive pad on one surface thereof may be provided. The redistribution substrate may include a first passivation pattern on the conductive pad, the first passivation pattern exposing a portion of the conductive pad, and a redistribution pattern covering the portion of the conductive pad exposed by the first passivation pattern and surrounding the first passivation pattern.
    Type: Grant
    Filed: May 24, 2017
    Date of Patent: June 11, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jongyoun Kim, Seokhyun Lee
  • Patent number: 10308480
    Abstract: An embedded power module includes a substrate, first and second semiconducting dies, first and second gates, and first and second vias. The first semiconducting die is embedded in the substrate and spaced between opposite first and second surfaces of the substrate. The second semiconducting die is embedded in the substrate, is spaced between the first and second surfaces, and is spaced from the first semiconducting die. The first gate is located on the first surface. The second gate is located on the second surface. The first via is electrically engaged to the first gate and the second semiconducting die, and the second via is electrically engaged to the second gate and the first semiconducting die.
    Type: Grant
    Filed: July 8, 2016
    Date of Patent: June 4, 2019
    Assignee: OTIS ELEVATOR COMPANY
    Inventor: Shashank Krishnamurthy
  • Patent number: 10304816
    Abstract: A semiconductor device and a fabricating method of semiconductor device are disclosed. The semiconductor device includes: a substrate having a bonding pad on a surface of the substrate; at least two semiconductor components each having a first surface and a second surface opposite the first surface, the semiconductor components stacked on top of each other on the surface of the substrate via a layer of component attach material attached on the second surface of the respective semiconductor component; an integral through via hole extending completely through the semiconductor components and the layers of component attach material and having a substantially uniform diameter along an extending direction of the integral through via hole aligned with the bonding pad on the surface of the substrate, and a continuous conductive material filled in the integral through via hole and in physical and electrical contact with the bonding pad of the substrate.
    Type: Grant
    Filed: December 30, 2016
    Date of Patent: May 28, 2019
    Assignee: Western Digital Technologies, Inc.
    Inventors: Shiv Kumar, Chin Tien Chiu, Honny Chen
  • Patent number: 10290536
    Abstract: Various self-aligned interconnect structures are disclosed herein. An exemplary interconnect structure includes a first dielectric layer disposed over a substrate; a first conductive feature disposed in the first dielectric layer; an etch stop layer disposed over a top surface of the first dielectric layer and a top surface of the first conductive feature; a second dielectric layer disposed over the first dielectric layer; and a second conductive feature disposed in the second dielectric layer. The top surface of the first conductive feature is lower than the top surface of the first dielectric layer. The etch stop layer includes a portion that extends between the top surface of the first conductive feature and the top surface of the first dielectric layer, on which the second conductive feature may or may not be disposed. In some implementations, the second conductive feature may be a via feature.
    Type: Grant
    Filed: June 27, 2017
    Date of Patent: May 14, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih Wei Lu, Chung-Ju Lee, Tien-I Bao
  • Patent number: 10289141
    Abstract: A method for generating a power distribution network (PDN) is provided. A heterogeneous circuit data is input. A plurality of horizontal power lines and a plurality of vertical power lines are determined according to the heterogeneous circuit data. A PDN model of the heterogeneous circuit is determined according to the horizontal power lines and the vertical power lines. Power consumption value is assigned to a plurality of internal nodes of the PDN model of the heterogeneous circuit. The PDN model of the heterogeneous circuit is adjusted to meet a target voltage drop limitation of the heterogeneous circuit data.
    Type: Grant
    Filed: November 18, 2015
    Date of Patent: May 14, 2019
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Chang-Tzu Lin, Ding-Ming Kwai, Tzu-Min Lin
  • Patent number: 10283550
    Abstract: A semiconductor structure includes: a semiconductor substrate arranged over a back end of line (BEOL) metallization stack, and including a scribe line opening; a conductive pad having an upper surface that is substantially flush with an upper surface of the semiconductor substrate, the conductive pad including an upper conductive region and a lower conductive region, the upper conductive region being confined to the scribe line opening substantially from the upper surface of the semiconductor substrate to a bottom of the scribe line opening, and the lower conductive region protruding downward from the upper conductive region, through the BEOL metallization stack; a passivation layer arranged over the semiconductor substrate; and an array of pixel sensors arranged in the semiconductor substrate adjacent to the conductive pad.
    Type: Grant
    Filed: March 28, 2017
    Date of Patent: May 7, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Sheng-Chau Chen, Cheng-Hsien Chou, Min-Feng Kao
  • Patent number: 10283444
    Abstract: Even when a stiffener is omitted, the semiconductor device which can prevent the generation of twist and distortion of a wiring substrate is obtained. As for a semiconductor device which has a wiring substrate, a semiconductor chip by which the flip chip bond was made to the wiring substrate, and a heat spreader adhered to the back surface of the semiconductor chip, and which omitted the stiffener for reinforcing a wiring substrate and maintaining the surface smoothness of a heat spreader, a wiring substrate has a plurality of insulating substrates in which a through hole whose diameter differs, respectively was formed, and each insulating substrate contains a glass cloth.
    Type: Grant
    Filed: October 27, 2017
    Date of Patent: May 7, 2019
    Assignee: Renesas Electronics Corporation
    Inventors: Eiji Hayashi, Kyo Go, Kozo Harada, Shinji Baba
  • Patent number: 10247971
    Abstract: There is provided a flexible display having a new wire structure and a new insulating layer structure. A flexible display includes a flexible substrate having a first area and a second area. The second area is curved in a non-zero angle relative to the plane of the first area. The flexible display further includes a plurality of wires that extend over from the first area to the second area of the flexible substrate. Each of the wires is covered by an upper insulating pattern, which is separated from other upper insulating pattern. Each upper insulating pattern covering the wire has substantially the same trace pattern shape of the corresponding wire thereunder. Accordingly, by adopting the above-described wire structure and upper insulating layer structure, crack generation and propagation in the wires and the insulating layers from bending of the flexible display can be minimized.
    Type: Grant
    Filed: July 18, 2017
    Date of Patent: April 2, 2019
    Assignee: LG Display Co., Ltd.
    Inventors: Seyeoul Kwon, Sang Hyeon Kwak, Sangcheon Youn
  • Patent number: 10236282
    Abstract: An embodiment includes an apparatus comprising: a first layer, including a first semiconductor switching element, coupled to a first portion of a first bonding material; and a second layer, including a second semiconductor switching element, coupled to a second portion of a second bonding material; wherein (a) the first layer is over the second layer, (b) the first portion is directly connected to the second portion, and (c) first sidewalls of the first portion are unevenly serrated. Other embodiments are described herein.
    Type: Grant
    Filed: December 18, 2013
    Date of Patent: March 19, 2019
    Assignee: Intel Corporation
    Inventors: Patrick Morrow, Kimin Jun, Il-Seok Son, Rajashree Baskaran, Paul B. Fischer
  • Patent number: 10224312
    Abstract: A modification to the standard layout of vias used for vertically-stacked wafer bonding is proposed which has been found to improve the interconnect overlay while avoiding the dishing problems associated with the planarization processes used in the creation of conductive posts within the vias. In particular, the pitch, i.e. the spacing between adjacent posts, is intentionally chosen to be different for each wafer. By using different pitches, there is an increase in the probability of overlap of posts on each wafer, even when one wafer is slightly offset with respect to the other (which is possible when aligning one wafer with another in a standard bonding tool). Advantageously, the use of different pitches allows for the use of relatively small diameter (one micron or less) posts while still creating sufficient overlap for the necessary connections.
    Type: Grant
    Filed: May 23, 2017
    Date of Patent: March 5, 2019
    Assignee: National Technology & Engineering Solutions of Sandia, LLC
    Inventor: Adam Jones
  • Patent number: 10224287
    Abstract: An RDL structure on a passivation layer includes a first landing pad disposed directly above a first on-chip metal pad; a first via in a passivation layer to electrically connect the first landing pad with the first on-chip metal pad; a second landing pad disposed directly above the second on-chip metal pad; a second via in the passivation layer to electrically connect the second landing pad with the second on-chip metal pad; and at least five traces being disposed on the passivation layer and passing through a space between the first landing pad and the second landing pad.
    Type: Grant
    Filed: June 3, 2017
    Date of Patent: March 5, 2019
    Assignee: MediaTek Inc.
    Inventors: Shih-Yi Syu, Tung-Hsien Hsieh, Che-Ya Chou
  • Patent number: 10211171
    Abstract: A semiconductor device has a semiconductor die and an encapsulant deposited over the semiconductor die. A first conductive layer is formed with an antenna over a first surface of the encapsulant. A second conductive layer is formed with a ground plane over a second surface of the encapsulant with the antenna located within a footprint of the ground plane. A conductive bump is formed on the ground plane. A third conductive layer is formed over the first surface of the encapsulant. A fourth conductive layer is formed over the second surface of the encapsulant. A conductive via is disposed adjacent to the semiconductor die prior to depositing the encapsulant. The antenna is coupled to the semiconductor die through the conductive via. The antenna is formed with the conductive via between the antenna and semiconductor die. A PCB unit is disposed in the encapsulant.
    Type: Grant
    Filed: September 14, 2017
    Date of Patent: February 19, 2019
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: Kai Liu, Yaojian Lin
  • Patent number: 10211129
    Abstract: A process for manufacturing surface-mount semiconductor devices, in particular of the Quad-Flat No-Leads Multi-Row type, comprising providing a metal leadframe, in particular a copper leadframe, which includes a plurality of pads, each of which is designed to receive the body of the device, the pads being separated from adjacent pads by one or more rows of wire-bonding contacting areas, outermost rows from among the one or more rows of wire-bonding contacting areas identifying, together with outermost rows corresponding to the adjacent pads, separation regions.
    Type: Grant
    Filed: October 30, 2017
    Date of Patent: February 19, 2019
    Assignee: STMicroelectronics S.R.L.
    Inventor: Fulvio Vittorio Fontana
  • Patent number: 10204872
    Abstract: An object of the present invention is to provide a power module that secures a heat dissipation route and has increased reliability. A power module of the present invention includes a first circuit body having a first semiconductor element and a first conductor portion, a second circuit body having a second semiconductor element and a second conductor portion, a resin sealing material for sealing the first circuit body and the second circuit body, and a warpage suppression portion that is formed along an array direction of the first circuit body and the second circuit body and is formed to have greater rigidity than a sealing portion of the resin sealing material, wherein the warpage suppression portion is formed of the same material as a resin member of the resin sealing material and is formed to be thicker than the sealing portion of the resin sealing material.
    Type: Grant
    Filed: October 6, 2015
    Date of Patent: February 12, 2019
    Assignee: Hitachi Automotive Systems, Ltd.
    Inventors: Toshiyuki Kobayashi, Takuro Kanazawa
  • Patent number: 10204853
    Abstract: A bonding pad of a semiconductor chip in a QFP includes, in its exposed portion, a via disposition area comprising: a first segment that connects a corner and a first point; a second segment that connects the corner and a second point; and an arc that connects the first point and the second point and forms a convex shape toward the corner. Further, in a plan view of the bonding pad, at least a part of a via is disposed so as to overlap with the via disposition area.
    Type: Grant
    Filed: June 13, 2017
    Date of Patent: February 12, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Masahiro Matsumoto, Akira Yajima, Kazuyoshi Maekawa
  • Patent number: 10204801
    Abstract: A process of forming, on a surface of the substrate a plurality of resist layers made of two kinds of dry film resist that differ in main peak wavelength in spectral photosensitivity. An exposure process of selectively exposing and affecting a particular resist layer in accordance with a first pattern upon using a first exposure mask overlaid on the plurality of resist layers. A second exposure process of exposing another resist layer in accordance with a second pattern upon using a second exposure mask overlaid on the plurality of resist layers. Partially uncovering the surface of the substrate by removing unexposed portions of the plurality of resist layers, to form a resist mask having an aperture. Finally, forming a coat layer by plating a portion of the substrate where the surface thereof is uncovered; and a process of removing the resist mask.
    Type: Grant
    Filed: March 11, 2014
    Date of Patent: February 12, 2019
    Assignee: OHKUCHI MATERIALS CO., LTD.
    Inventor: Shigeru Hosomomi
  • Patent number: 10199310
    Abstract: A thin stacked semiconductor device has a plurality of circuits that are laminated and formed sequentially in a specified pattern to form a multilayer wiring part. At the stage for forming the multilayer wiring part, a filling electrode is formed on the semiconductor substrate such that the surface is covered with an insulating film, a post electrode is formed on specified wiring at the multilayer wiring part, a first insulating layer is formed on one surface of the semiconductor substrate, the surface of the first insulating layer is removed by a specified thickness to expose the post electrode, and the other surface of the semiconductor substrate is ground to expose the filling electrode and to form a through-type electrode. A second insulating layer is formed on one surface of the semiconductor substrate while exposing the forward end of the through-type electrode, and bump electrodes are formed on both electrodes.
    Type: Grant
    Filed: December 22, 2017
    Date of Patent: February 5, 2019
    Assignee: LAPIS SEMICONDUCTOR CO., LTD.
    Inventor: Masamichi Ishihara
  • Patent number: 10192929
    Abstract: A three-dimensional memory device includes conductive structures located over a substrate, an alternating stack of insulating layers and electrically conductive layers formed over the conductive structures, and an array of memory structures formed through the alternating stack. Each of the memory structures includes memory elements located at levels of the electrically conductive layers. A contact region can be formed on the alternating stack. Two-stage contact via cavities having a greater width above a top surface of a respective electrically conductive layer and having a narrower width through the alternating stack can be formed in the contact region. Upper insulating spacers and lower insulating spacers are formed such that annular surfaces of the respective electrically conductive layer are physically exposed. Two-stage contact via structures can provide electrical contact between the electrically conductive layers and the conductive structures.
    Type: Grant
    Filed: March 24, 2017
    Date of Patent: January 29, 2019
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventor: Yoshio Mori
  • Patent number: 10186491
    Abstract: An integrated circuit chip includes an interconnection stack with a cavity formed therein. The cavity extends through one or more interconnection levels of the stack. A material at least partially fills the cavity. The fill material has a selectivity to polishing and/or to etching different by more than 10% from a selectivity to polishing and/or to etching of a material forming an insulator of the interconnection stack.
    Type: Grant
    Filed: May 26, 2017
    Date of Patent: January 22, 2019
    Assignees: STMicroelectronics (Crolles 2) SAS, STMicroelectronics (Rousset) SAS
    Inventors: Sébastien Petitdidier, Mathieu Lisart
  • Patent number: 10186978
    Abstract: Converter output terminals of a converter are located adjacent to each other on a first side and an external terminal for external connection of a composite module is located adjacent to the converter output terminal. AC input terminals of the converter are located on a second side. Each of the distances between the converter output terminals and between the converter output terminal and the external terminal is set to a first formation pitch. Each of the distances between the AC input terminals is set to a second formation pitch. The first formation pitch is set to be equal to the second formation pitch.
    Type: Grant
    Filed: April 20, 2015
    Date of Patent: January 22, 2019
    Assignee: Mitsubishi Electric Corporation
    Inventors: Kosuke Yamaguchi, Tomofumi Tanaka, Shinya Nakagawa, Toru Iwagami
  • Patent number: 10186467
    Abstract: A semiconductor package device includes a first die, an adhesive layer, and an encapsulant layer. The first die comprises a first electrode at a first surface of the first die and a second electrode at a second surface of the first die opposite to the first surface of the first die. The adhesive layer is disposed on the first surface of the first die. The encapsulant layer encapsulates the first die and the adhesive layer, wherein substantially an entire surface of the second electrode is exposed from the encapsulant layer.
    Type: Grant
    Filed: July 13, 2017
    Date of Patent: January 22, 2019
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Bernd Karl Appelt, Kay Stefan Essig, Chi-Tsung Chiu
  • Patent number: 10185911
    Abstract: A radio frequency identifier (RFID) tag is provided for receiving and reflecting electromagnetic energy at select frequency bands of visible and infrared wavelengths. The RFID tag includes an electrically conductive backplane; a dielectric substrate disposed on the backplane; a light guide film (LGF) disposed on the substrate, and metamaterial elements. The LGF has an exposed surface segregated into domains. The metamaterial devices are disposed on a domain. Each device is tuned to respond to a corresponding frequency among the select frequency bands.
    Type: Grant
    Filed: January 10, 2018
    Date of Patent: January 22, 2019
    Assignee: The United States of America as represented by the Secretary of the Navy
    Inventors: Simin Feng, Kevin A. Boulais, Robert B. Nichols, Victor H. Gehman, Jr.
  • Patent number: 10177293
    Abstract: An optoelectronic component includes a first lead frame section and a second lead frame section spaced apart from one another, and having an optoelectronic semiconductor chip arranged on the first lead frame section and the second lead frame section, wherein the first lead frame section and the second lead frame section respectively have an upper side, a lower side and a first side flank extending between the upper side and the lower side, a first lateral solder contact surface of the optoelectronic component is formed on the first side flank of the first lead frame section, and the first lateral solder contact surface is formed by a recess arranged on the first side flank of the first lead frame section and extends from the upper side to the lower side of the first lead frame section.
    Type: Grant
    Filed: November 5, 2015
    Date of Patent: January 8, 2019
    Assignee: OSRAM Opto Semiconductors GmbH
    Inventors: Michael Wittmann, Tobias Gebuhr, David Racz
  • Patent number: 10177032
    Abstract: Devices, packaging devices, and methods of packaging semiconductor devices are disclosed. In some embodiments, a packaged semiconductor device includes a molding material and a plurality of through-vias disposed within the molding material. A dummy through-via and an integrated circuit die are also disposed within the molding material. An interconnect structure is disposed over the molding material, the plurality of through-vias, the dummy through-via, and the integrated circuit die.
    Type: Grant
    Filed: March 31, 2015
    Date of Patent: January 8, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsien-Wei Chen, An-Jhih Su, Jo-Mei Wang
  • Patent number: 10170399
    Abstract: The present disclosure relates to a chip including a wafer, a back-end-of-line (BEOL) layer deposited on the wafer, a chip TSV in the wafer containing a conductive material, and a chip cap layer disposed between the chip TSV and the BEOL layer, and configured to reduce via extrusion of conductive material in the chip TSV during operation of the chip. The present disclosure further includes a 3D integrated circuit including a plurality of electrically connected chips, at least one of which is a chip as described above. The disclosure further relates to a 3D integrated circuit with an interposer, a TSV in the interposer containing a conductive material, and an interposer cap layer configured to reduce via extrusion of the conductive material located in the interposer TSV during operation of the circuit. The present disclosure further includes methods of forming such chips and 3D integrated circuits.
    Type: Grant
    Filed: September 21, 2017
    Date of Patent: January 1, 2019
    Assignee: Board of Regents, The University of Texas System
    Inventors: Paul S. Ho, Tengfei Jiang
  • Patent number: 10163927
    Abstract: A semiconductor memory device includes a cell array region formed on a substrate, a word line contact region, and a page buffer region coupled to the cell array region through bit lines, wherein at least one of the bit lines has a curved structure toward the word line contact region. According to an embodiment, a misalignment between a cell plug and a contact plug caused by a natural cell plug bending phenomenon may be reduced to improve operational reliability of a semiconductor memory device.
    Type: Grant
    Filed: June 28, 2017
    Date of Patent: December 25, 2018
    Assignee: SK Hynix Inc.
    Inventors: Yung Jun Kim, Suk Goo Kim
  • Patent number: 10157810
    Abstract: Some embodiments relate to a semiconductor device. The semiconductor device includes a layer disposed over a substrate. A conductive body extends through the layer. A plurality of bar or pillar structures are spaced apart from one another and laterally surround the conductive body. The plurality of bar or pillar structures are generally concentric around the conductive body.
    Type: Grant
    Filed: September 25, 2017
    Date of Patent: December 18, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ying-Chieh Liao, Han-Wei Yang, Chen-Chung Lai, Kang-Min Kuo, Bor-Zen Tien
  • Patent number: 10141372
    Abstract: A three-dimensional semiconductor device is provided as follows. A substrate includes a contact region, a dummy region, and a cell array region. A stack structure includes electrodes vertically stacked on the substrate. The electrodes are stacked to have a first stepwise structure on the contact region and a second stepwise structure in the dummy region. Ends of at least two adjacent electrodes in the second stepwise structure have first sidewalls vertically aligned so that horizontal positions of the first sidewalls are substantially the same.
    Type: Grant
    Filed: March 11, 2016
    Date of Patent: November 27, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Joyoung Park, Seok-Won Lee, Seongjun Seo
  • Patent number: 10134747
    Abstract: A semiconductor device may include a first cell structure, a second cell structure, a pad structure, a circuit, and an opening. The pad structure may include a first stepped structure and a second stepped structure located between the first cell structure and the second cell structure. The first stepped structure may include first pads electrically connected to the first and second cell structures and stacked on top of each other, and the second stepped structure may include second pads electrically connected to the first and second cell structures and stacked on top of each other. The circuit may be located under the pad structure. The opening may pass through the pad structure to expose the circuit, and may be located between the first stepped structure and the second stepped structure to insulate the first pads and the second pads from each other.
    Type: Grant
    Filed: September 19, 2016
    Date of Patent: November 20, 2018
    Assignee: SK hynix Inc.
    Inventor: Nam Jae Lee
  • Patent number: 10134669
    Abstract: A semiconductor device structure includes a first metal layer formed over a substrate and an interconnect structure formed over the first metal layer. The interconnect structure includes an upper portion, a middle portion and a lower portion, the middle portion is connected between the upper portion and the lower portion. The upper portion and the lower portion each have a constant width, and the middle portion has a tapered width which is gradually tapered from the upper portion to the lower portion.
    Type: Grant
    Filed: March 5, 2018
    Date of Patent: November 20, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Che-Cheng Chang, Chih-Han Lin
  • Patent number: 10128225
    Abstract: Embodiments of the present disclosure are directed towards techniques and configurations of interconnect structures having a polymer core in integrated circuit (IC) package assemblies. In one embodiment, an apparatus includes a first die having a plurality of transistor devices disposed on an active side of the first die and a plurality of interconnect structures electrically coupled with the first die, wherein individual interconnect structures of the plurality of interconnect structures have a polymer core, and an electrically conductive material disposed on the polymer core, the electrically conductive material being configured to route electrical signals between the transistor devices of the first die and a second die. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: February 17, 2017
    Date of Patent: November 13, 2018
    Assignee: INTEL CORPORATION
    Inventors: Sandeep Razdan, Edward R. Prack, Sairam Agraharam, Robert L. Sankman, Shan Zhong, Robert M. Nickerson
  • Patent number: 10128205
    Abstract: Embodiments of the present disclosure describe integrated circuit (IC) package assemblies and methods of fabricating IC package assemblies. These embodiments include dies embedded in embedding substrates to provide larger pitch interconnects to facilitate coupling to substrates or circuit boards through flip chip techniques. The embedding substrates may contain conductive pathways for coupling die contacts to larger pitch contacts located on the embedding substrate. By embedding the dies in the embedding substrates, dies having smaller pitch contacts can be used in package assemblies with larger pitch components without the need for silicon interposers and without having to utilize more stringent pick and place operations. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: March 6, 2014
    Date of Patent: November 13, 2018
    Assignee: Intel Corporation
    Inventors: Thorsten Meyer, Sven Albers
  • Patent number: 10128130
    Abstract: A compact and high-reliability semiconductor device is implemented. The bonding wires situated in the vicinity of a gate, and the bonding wires situated in the vicinity of a vent facing to the gate across the center of a semiconductor chip in a molding step have a loop shape falling inwardly of the semiconductor chip, have a weaker pulling force (tension) than those of other bonding wires, and are loosely stretched with a margin. The bonding wires situated in the vicinity of the gate in the molding step are, for example, a first wire and a fifth wire to be connected with a first electrode pad and a fifth electrode pad, respectively. Whereas, the bonding wires situated in the vicinity of the vent in the molding step are, for example, a third wire and a seventh wire to be connected with a third electrode pad and a seventh electrode pad, respectively.
    Type: Grant
    Filed: December 1, 2017
    Date of Patent: November 13, 2018
    Assignee: Renesas Electronics Corporation
    Inventor: Yuki Yagyu
  • Patent number: 10128268
    Abstract: Provided herein is a semiconductor device including N stacked groups (where N is a natural number greater than or equal to two) sequentially stacked over a substrate, each stacked group including interlayer insulating films and conductive patterns alternately stacked, and N concave portions each having stepped sidewalls formed in the interlayer insulating films and the conductive patterns of the stacked groups, the N concave portions each having stepped sidewalls being aligned in a first direction.
    Type: Grant
    Filed: August 11, 2017
    Date of Patent: November 13, 2018
    Assignee: SK hynix Inc.
    Inventor: Nam Jae Lee
  • Patent number: 10118712
    Abstract: The disclosure provides in one embodiment an electrical conductor pathway system for diverting an electric charge. The electrical conductor pathway system includes a substrate having a first surface to be printed on and having one or more grounding points. The electrical conductor pathway system further includes a direct write conductive material pattern printed directly onto the first surface via a direct write printing process. The direct write conductive material pattern forms one or more electrical pathways interconnected with the one or more grounding points. The one or more electrical pathways interconnected with the one or more grounding points divert the electric charge from the first surface to the one or more grounding points.
    Type: Grant
    Filed: March 31, 2016
    Date of Patent: November 6, 2018
    Assignee: The Boeing Company
    Inventors: Victoria L. Garcia, Mark J. Gardner, Otis F. Layton, Jeffrey Lynn Duce, Joseph A. Marshall, IV
  • Patent number: 10121763
    Abstract: Implementations of a clip for a semiconductor package may include: an electrically conductive clip having a first end and a second end and a middle section between the first end and the second end. The first end may be configured to couple to a first die through a bonding material. The second end may be configured to couple to a second die through a bonding material. The middle section may be configured to couple to an emitter structure through a bonding material. The clip may include an integrally formed electrically conductive material and include an M-shape. A middle of the M-shape may be coupled to the emitter structure.
    Type: Grant
    Filed: March 5, 2018
    Date of Patent: November 6, 2018
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Chee Hiong Chew, Atapol Prajuckamol, Yushuang Yao
  • Patent number: 10112237
    Abstract: A device for drying and sintering metal-containing ink on a substrate enables homogeneous irradiation of the substrate, has compact construction, and is simple and economical to produce. Optical infrared radiators have a cylindrical radiator tube and a longitudinal axis, and emit radiation having an IR-B radiation component of at least 30% and an IR-C radiation component of at least 5% of total radiator output power. The radiators are arranged in a module with their longitudinal axes running parallel to each other and transverse to the transport direction. They thereby irradiate on the surface of the substrate an irradiation field, which is divided into a drying zone and a sintering zone arranged downstream of the drying zone in the transport direction. The drying zone is exposed to at least 15% less average irradiation density than the sintering zone along a center axis running in the transport direction.
    Type: Grant
    Filed: April 10, 2014
    Date of Patent: October 30, 2018
    Assignee: Heraeus Noblelight GmbH
    Inventors: Holger Zissing, Jürgen Weber, Sven Linow, Oliver Weiss