Of Specified Configuration Patents (Class 257/773)
  • Patent number: 11189562
    Abstract: The present disclosure provides a semiconductor device and a method of manufacturing the same. The semiconductor device includes a substrate, a diffusion barrier layer, a passivation layer, and a plurality of conductive features. The diffusion barrier layer is disposed on the substrate, and the passivation layer is disposed on the diffusion barrier layer. The conductive features penetrate through the passivation layer and contact the diffusion barrier layer.
    Type: Grant
    Filed: May 28, 2020
    Date of Patent: November 30, 2021
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Chen Chu, Hsih-Yang Chiu
  • Patent number: 11189558
    Abstract: An integrated circuit includes a first conductive layer and a first insulation layer formed on the first conductive layer. The integrated circuit also includes a second insulation layer formed on the first insulation layer and a second conductive layer formed on the second insulation layer. The first insulation layer may include a first defect, and the second insulation layer may include a second defect. The integrated circuit may also include a third insulation layer formed on the second conductive layer, a fourth insulation layer formed on the third insulation layer, and a third conductive layer formed on the fourth insulation layer. The third insulation layer may include a third defect, and the fourth insulation layer may include a fourth defect.
    Type: Grant
    Filed: February 12, 2020
    Date of Patent: November 30, 2021
    Assignee: Raytheon Company
    Inventor: David Madajian
  • Patent number: 11183421
    Abstract: An interconnection structure for metal lines, a method of fabricating the same, and a semiconductor device are provided. A plurality of interconnection structure layers are stacked one above another on a substrate with the support of at least one supporting and covering layer. In each of the interconnection structure layers, spaces between a plurality of conductive components are filled with air which has a low dielectric constant, rather than with dielectric material. Thus, parasitic capacitances in the interconnection structure can be significantly reduced and RC delay can be mitigated.
    Type: Grant
    Filed: April 30, 2020
    Date of Patent: November 23, 2021
    Assignee: Changxin Memory Technologies, Inc.
    Inventor: Ming-Teng Hsieh
  • Patent number: 11177381
    Abstract: A semiconductor device includes a semiconductor part, a first electrode, a plurality of control electrodes and a second electrode. The semiconductor part has a plurality of first trenches and a second trench. The plurality of first trenches are spaced from each other and arranged around the second trench. The first electrode is provided above the semiconductor part. The first electrode is provided over the plurality of first trenches and the second trench. The control electrodes are provided in the first trenches, respectively. The control electrodes each are electrically isolated from the semiconductor part by a first insulating film. The second electrode is provided in the second trench. The second electrode is electrically isolated from the semiconductor part by a second insulating film and electrically connected to the first electrode.
    Type: Grant
    Filed: March 9, 2020
    Date of Patent: November 16, 2021
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Hiroaki Katou, Kenya Kobayashi, Tatsuya Nishiwaki
  • Patent number: 11177154
    Abstract: A carrier structure suitable for transferring or supporting a plurality of micro devices including a carrier and a plurality of transfer units is provided. The transfer units are disposed on the carrier. Each of the transfer units includes a plurality of transfer parts. Each of the transfer parts has a transfer surface. Each of the micro devices has a device surface. The transfer surfaces of the transfer parts of each of the transfer units are connected to the device surface of corresponding micro device. The area of each of the transfer surfaces is smaller than the area of the device surface of the corresponding micro device. A micro device structure using the carrier structure is also provided.
    Type: Grant
    Filed: December 19, 2018
    Date of Patent: November 16, 2021
    Assignee: PixeLED Display CO., LTD.
    Inventors: Pei-Hsin Chen, Yi-Chun Shih, Yi-Ching Chen, Ying-Tsang Liu, Yu-Chu Li, Huan-Pu Chang, Chih-Ling Wu, Yu-Yun Lo, Tzu-Yang Lin, Yu-Hung Lai
  • Patent number: 11177218
    Abstract: A package has a first semiconductor die, a second semiconductor die, a redistribution structure and a metallic bolstering pattern. The second semiconductor die is disposed beside the first semiconductor die and spaced apart from the first semiconductor die with a distance. The redistribution structure is disposed over the first semiconductor die and the second semiconductor die and is electrically connected with the first and second semiconductor dies. The metallic bolstering pattern is disposed between the redistribution structure and the first and second semiconductor dies. The metallic bolstering pattern is disposed on the redistribution structure and located over the first and second semiconductor dies, and the metallic bolstering pattern extends across the distance between the first and second semiconductor dies and extends beyond borders of the first and second semiconductor dies.
    Type: Grant
    Filed: March 20, 2020
    Date of Patent: November 16, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jiun-Yi Wu, Chien-Hsun Lee, Shou-Yi Wang, Chien-Hsun Chen
  • Patent number: 11171116
    Abstract: A semiconductor device includes a first substrate structure and a second substrate structure. The first substrate structure includes a base substrate, circuit elements disposed on the base substrate, a first substrate disposed on the circuit elements, first memory cells disposed on the first substrate and electrically connected to the circuit elements, first bit lines disposed on the first memory cells and connected to the first memory cells, and first bonding pads disposed on the first bit lines to be connected to the first bit lines, respectively. The second substrate structure is connected to the first substrate structure on the first substrate structure, and includes a second substrate, second memory cells disposed on the second substrate, second bit lines disposed on the second memory cells and connected to the second memory cells, and second bonding pads disposed on the second bit lines to be connected to the second bit lines, respectively.
    Type: Grant
    Filed: April 29, 2019
    Date of Patent: November 9, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Hyun Mog Park
  • Patent number: 11171131
    Abstract: A diode and method of design the layout of the same having reduced parasitic capacitance is disclosed. In particular, the diode for providing fast response protection of an RF circuit from a high power noise event, such as an ESD, voltage spike, power surge or other noise is disclose. The parasitic capacitance in disclosed circuit is a greatly reduced compared to the prior art, thus significantly increasing the speed of the response to dissipate all high power noise events.
    Type: Grant
    Filed: August 19, 2019
    Date of Patent: November 9, 2021
    Assignee: STMICROELECTRONICS INTERNATIONAL N.V.
    Inventor: Vishal Kumar Sharma
  • Patent number: 11171107
    Abstract: A semiconductor package includes: a semiconductor chip including a body having a first surface and a second surface, opposing the first surface, a connection pad disposed on the first surface of the body, and an extension pad disposed on the connection pad; and a connection structure including an insulating layer disposed on the first surface of the body of the semiconductor chip, a redistribution via penetrating through the insulating layer and having one side thereof in contact with the extension pad, and a redistribution layer disposed on the insulating layer and having a via pad in contact with the other side of the redistribution via, wherein a horizontal cross-sectional area of extension pad of the semiconductor chip is greater than a horizontal cross-sectional area of the connection pad of the semiconductor chip.
    Type: Grant
    Filed: December 13, 2019
    Date of Patent: November 9, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Gyu Jin Choi, Sung Hoan Kim, Chang Eun Joo, Chil Woo Kwon, Young Kyu Lim, Sung Uk Lee
  • Patent number: 11164811
    Abstract: A 3D semiconductor device, the device including: a first level including single crystal first transistors, and a first metal layer, where the first level is overlaid by a first isolation layer; a second level including second transistors, where the first isolation layer is overlaid by the second level, and where the second level is overlaid by a second isolation layer; a third level including single crystal third transistors, where the second isolation layer is overlaid by the third level, where the third level is overlaid by a third isolation layer, where the third level is bonded to the second isolation layer, and where the bonded includes at least one oxide to oxide bond.
    Type: Grant
    Filed: May 6, 2021
    Date of Patent: November 2, 2021
    Assignee: MONOLITHIC 3D INC.
    Inventors: Zvi Or-Bach, Deepak C. Sekar, Brian Cronquist
  • Patent number: 11164837
    Abstract: Semiconductor devices having mechanical pillar structures, such as angled pillars, that are rectangular and orientated with respect to a semiconductor die to reduce bending stress and in-plane shear stress at a semiconductor die to which the angled pillars are attached, and associated systems and methods, are disclosed herein. The semiconductor device can include angled pillars connected to the semiconductor die and to a package substrate. The angled pillars can be configured such that they are orientated relative to a direction of local stress to increase section modulus.
    Type: Grant
    Filed: May 20, 2020
    Date of Patent: November 2, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Shams U. Arifeen
  • Patent number: 11158737
    Abstract: Provided in the present invention are an LDMOS component, a manufacturing method therefor, and an electronic device, comprising: a semiconductor substrate (100); a drift area (101) provided in the semiconductor substrate; a gate electrode structure (103) provided on a part of the surface of the semiconductor substrate and covers a part of the surface of the drift area; a source electrode (1052) and a drain electrode (1051) respectively provided in the semiconductor substrate on either side of the gate electrode structure, where the drain electrode is provided in the drift area and is separated from the gate electrode structure; a metal silicide barrier layer (106) covering the surface of at least a part of the semiconductor substrate between the gate electrode structure and the drain electrode; and a first contact hole (1081) provided on the surface of at least a part of the metal silicide barrier layer.
    Type: Grant
    Filed: August 3, 2018
    Date of Patent: October 26, 2021
    Assignee: CSMC TECHNOLOGIES FAB2 CO., LTD.
    Inventors: Huajun Jin, Guipeng Sun, Hongfeng Jin
  • Patent number: 11158825
    Abstract: A display device may include a substrate, pixels, and a crack mitigation structure. The substrate may include a main region, a sub-region, and a bending region. The bending region may be connected between the main region and the sub-region and may include a curved outline section. The pixels may be disposed on the main region. The crack mitigation structure may be disposed on the bending region. A section of the crack mitigation structure may be substantially parallel to the curved outline section.
    Type: Grant
    Filed: March 9, 2020
    Date of Patent: October 26, 2021
    Inventors: Min Hee Choi, Chung Yi, Yun Kyeong In
  • Patent number: 11152301
    Abstract: A method of designing a memory circuit is provided that includes generating a layout of a first memory cell using an integrated circuit design system. The layout of the first memory cell is generated by routing a first word line in a first layer on a first level, and routing a second word line in the first layer. Also, the method includes generating a layout of a second memory cell using the integrated circuit design system. The layout of the second memory cell is generated by routing a third word line in the first layer, the second word line being between the first word line and the third word line, and routing a fourth word line in the first layer, the third word line being between the second word line and the fourth word line. Moreover, the method includes assigning a first color scheme to the first word line and to the third word line, and assigning a second color scheme to the second word line and to the fourth word line.
    Type: Grant
    Filed: July 15, 2019
    Date of Patent: October 19, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hidehiro Fujiwara, Li-Wen Wang, Yen-Huei Chen, Hung-Jen Liao
  • Patent number: 11139264
    Abstract: Examples relate to a die interconnect substrate comprising a bridge die comprising at least one bridge interconnect connecting a first bridge die pad of the bridge die to a second bridge die pad of the bridge die. The die interconnect substrate further comprises a substrate structure comprising a substrate interconnect electrically insulated from the bridge die, wherein the bridge die is embedded in the substrate structure. The die interconnect substrate further comprises a first interface structure for attaching a semiconductor die to the substrate structure, wherein the first interface structure is connected to the first bridge die pad. The die interconnect substrate further comprises a second interface structure for attaching a semiconductor die to the substrate structure, wherein the second interface structure is connected to the substrate interconnect. A surface of the first interface structure and a surface of the second interface structure are at the same height.
    Type: Grant
    Filed: September 27, 2019
    Date of Patent: October 5, 2021
    Assignee: Intel Corporation
    Inventors: Rahul Jain, Ji Yong Park, Kyu Oh Lee
  • Patent number: 11127791
    Abstract: According to the embodiment, a semiconductor memory device includes a first conductive layer, a second conductive layer, a first memory cell, a second memory cell, a third conductive layer, a first contact, a intermediate memory cell, a fourth conductive layer, a third memory cell, a fifth conductive layer, and a second contact. The third conductive layer is separated from the first conductive layer and the second conductive layer in a third direction crossing a first direction and crossing a second direction and extends in the second direction. The fifth conductive layer is separated from the second conductive layer in the third direction and extends in the second direction. A first length of the second conductive layer along the second direction is shorter than a second length of the fifth conductive layer along the second direction.
    Type: Grant
    Filed: April 10, 2020
    Date of Patent: September 21, 2021
    Assignee: Toshiba Memory Corporation
    Inventors: Yusuke Kobayashi, Yoshihisa Iwata, Takeshi Sugimoto
  • Patent number: 11127807
    Abstract: An manufacturing method of a display device may include the following steps: forming a transistor on a substrate; forming an insulating layer on the transistor; forming a conductive layer including silver on the insulating layer; forming a photosensitive member on the conductive layer; forming an electrode of a light-emitting element by etching the conductive layer; performing plasma treatment on a structure that comprises the electrode, the plasma treatment using a gas including a halogen; and removing a product that is resulted from the plasma treatment.
    Type: Grant
    Filed: July 24, 2019
    Date of Patent: September 21, 2021
    Inventors: Sang Gab Kim, Hyun Min Cho, Tae Sung Kim, Yu-Gwang Jeong, Su Bin Bae, Jin Seock Kim, Sang Gyun Kim, Hyo Min Ko, Kil Won Cho, Hansol Lee
  • Patent number: 11127628
    Abstract: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a first semiconductor structure, a first connecting structure, and a second semiconductor structure positioned on the first connecting structure. The first connecting structure includes a first connecting insulating layer positioned on the first semiconductor structure, two first conductive layers positioned in the first connecting insulating layer, and a first porous layer positioned between the two first conductive layers. The second semiconductor structure is positioned on the first connecting structure and includes two second conductive features positioned on the two first conductive layers. The first conductive layer has a first width, the second conductive feature has a second width greater than the first width, and the different width forms a step-shaped cross-sectional profile near an interface of the first conductive layer and the second conductive feature.
    Type: Grant
    Filed: March 16, 2020
    Date of Patent: September 21, 2021
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Shing-Yih Shih
  • Patent number: 11107765
    Abstract: A three-dimensional (3D) semiconductor device includes a stack structure including first and second stacks stacked on a substrate. Each of the first and second stacks includes a first electrode and a second electrode on the first electrode. A sidewall of the second electrode of the first stack is horizontally spaced apart from a sidewall of the second electrode of the second stack by a first distance. A sidewall of the first electrode is horizontally spaced apart from the sidewall of the second electrode by a second distance in each of the first and second stacks. The second distance is smaller than a half of the first distance.
    Type: Grant
    Filed: April 21, 2020
    Date of Patent: August 31, 2021
    Inventors: Sung-Hun Lee, Seokjung Yun, Chang-Sup Lee, Seong Soon Cho, Jeehoon Han
  • Patent number: 11101169
    Abstract: Structures that include interconnects and methods for forming a structure that includes interconnects. A metallization level has a first interconnect, a second interconnect, and a cavity with an entrance between the first interconnect and the second interconnect. A first dielectric layer includes a first section arranged on the first interconnect adjacent to the entrance of the cavity and a second section arranged on the second interconnect adjacent to the entrance of the cavity. A second dielectric layer is formed on the first section of the first dielectric layer and the second section of the first dielectric layer. The second dielectric layer extends from the first section of the first dielectric layer to the second section of the first dielectric layer and across the entrance to the cavity to close an airgap between the first interconnect and the second interconnect.
    Type: Grant
    Filed: January 10, 2019
    Date of Patent: August 24, 2021
    Assignee: GLOBALFOUNDRIES U.S. INC.
    Inventor: Nicholas V. LiCausi
  • Patent number: 11094718
    Abstract: The TFT array substrate has a third conductive layer connected to a first conductive layer and a second conductive layer through a first via and a second via, respectively. The third conductive layer further has separated first and second openings. The first opening has a vertical projection to a side of the second via and has an end extending beyond an edge of the second via adjacent to the first via. The second opening has a vertical projection to a side of the first via and has an end extending beyond an edge of the first via adjacent to the second via. As such, when the third conductive layer is stricken by static electricity, the first and second openings prevent a crack from breaking the first and second conductive layers apart, thereby enhancing the reliability of the connection between the first and second conductive layers.
    Type: Grant
    Filed: September 27, 2018
    Date of Patent: August 17, 2021
    Assignee: WUHAN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Zuomin Liao, Yanyang Li
  • Patent number: 11094632
    Abstract: The present disclosure provides a semiconductor device and a method for preparing the semiconductor device. The semiconductor device includes a plurality of spacer bit lines disposed over a substrate; a plurality of dielectric pillars disposed over the substrate, between the plurality of spacer bit lines; and a sealing dielectric layer disposed over the plurality of spacer bit lines and the plurality of dielectric pillars such that air gaps are formed between the sealing dielectric layer and the substrate.
    Type: Grant
    Filed: September 27, 2019
    Date of Patent: August 17, 2021
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Chih-Tsung Wu
  • Patent number: 11092620
    Abstract: Provided is a conduction inspection device member, wherein cracks and voids are less likely to form in conductive parts, conduction performance is less likely to be impaired even when a conduction test is repeated, and contact marks are less likely to remain in the portion of the member in contact with a member to be tested. Also provided is a conduction inspection device comprising the conduction inspection device member. The conduction inspection device member comprises a substrate 13, through holes 11, and conductive parts 12. The multiple through holes 11 are arranged in the substrate 13, the conductive parts 12 are housed inside the through holes 11, and the conductive parts 12 contain conductive particles 2. The conductive particles 2 each comprise a substrate particle 21 and a conductive layer 22 on the surface of the substrate particle 21. The conductive layer 22 has multiple protrusions 23 on the outer surface thereof.
    Type: Grant
    Filed: August 8, 2017
    Date of Patent: August 17, 2021
    Assignee: SEKISUI CHEMICAL CO., LTD.
    Inventors: Masao Sasadaira, Xiaoge Wang
  • Patent number: 11088092
    Abstract: The present disclosure relates to a method of forming an integrated chip. The method may be performed by forming first and second source regions within a substrate. The first and second source regions are separated by a drain region along a first direction. First and second middle-end-of-the-line (MEOL) structures are formed over the substrate. The first and second MEOL structures have bottom surfaces that continually extend past edges of the first and second source regions, respectively, along a second direction perpendicular to the first direction. A power rail is formed that is electrically coupled to the first and second MEOL structures. The power rail has a first interconnect wire, a via rail on and in contact with the first interconnect wire, and a second interconnect wire on and in contact with the via rail. The via rail continuously extends along the first direction past the first and second MEOL structures.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: August 10, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kam-Tou Sio, Chih-Ming Lai, Chun-Kuang Chen, Chih-Liang Chen, Charles Chew-Yuen Young, Chi-Yeh Yu, Jiann-Tyng Tzeng, Ru-Gun Liu, Wen-Hao Chen
  • Patent number: 11081467
    Abstract: A semiconductor device may include a bond pad/probe pad pair that includes a bond pad and a probe pad positioned to be adjacent to each other to form an L shape. The device may also include a through-silicon via (TSV) pad positioned to be at least partially or entirely inside the recess area of the L shape. The bond pad and the probe pad may each have an opening, and at least a portion of the opening of the bond pad may extend into a portion of the opening of the probe pad. The arrangement of the bond pad, the probe pad and the TSV may be implemented in a wafer-on-wafer (WOW) that includes multiple stacked wafers. A method of fabricating the TSV may include etching the stacked wafers to form a TSV opening that extends through the multiple wafers, and filling the TSV opening with conductive material.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: August 3, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Tomohiro Kitano
  • Patent number: 11075166
    Abstract: A microelectronic structure includes a microelectronic substrate having a first surface and a cavity extending into the substrate from the microelectronic substrate first surface, a first microelectronic device and a second microelectronic device attached to the microelectronic substrate first surface, and a microelectronic bridge disposed within the microelectronic substrate cavity and attached to the first microelectronic device and to the second microelectronic device. In one embodiment, the microelectronic structure may include a reconstituted wafer formed from the first microelectronic device and the second microelectronic device. In another embodiment, a flux material may extend between the first microelectronic device and the microelectronic bridge and between the second microelectronic device and the microelectronic bridge.
    Type: Grant
    Filed: August 27, 2020
    Date of Patent: July 27, 2021
    Assignee: Intel Corporation
    Inventors: Eric J. Li, Timothy A. Gosselin, Yoshihiro Tomita, Shawna M. Liff, Amram Eitan, Mark Saltas
  • Patent number: 11075188
    Abstract: A package structure includes a plurality of lower elements, a reinforcement structure and an encapsulant. The lower elements are disposed side by side. The reinforcement structure surrounds the lower elements. The encapsulant covers the lower elements and the reinforcement structure. The electrical connectors of the lower elements are exposed from the encapsulant.
    Type: Grant
    Filed: July 31, 2019
    Date of Patent: July 27, 2021
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Wen Hung Huang
  • Patent number: 11069597
    Abstract: Semiconductor chips and methods of manufacturing the same are provided. The semiconductor chip includes a substrate, an interlayer insulation layer including a bottom interlayer insulation layer on an upper surface of the substrate and a top interlayer insulation layer on the bottom interlayer insulation layer, an etch stop layer between the bottom interlayer insulation layer and the top interlayer insulation layer, a landing pad on the interlayer insulation layer, and a through via connected to the landing pad through the substrate, the interlayer insulation layer, and the etch stop layer. The etch stop layer is isolated from direct contact with the landing pad.
    Type: Grant
    Filed: March 27, 2019
    Date of Patent: July 20, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dae-suk Lee, Hak-seung Lee, Dong-chan Lim, Tae-seong Kim, Kwang-jin Moon
  • Patent number: 11062074
    Abstract: Boundary cells may be provided. A boundary of a first functional cell of a circuit is determined. A first plurality of a first type of dummy cells are placed along a first portion of the determined boundary. The first portion extends in a first direction. Each of the first type of dummy cells comprises first pre-defined dimensions. A second plurality of a second type of dummy cells are placed along a second portion of the determined boundary. The second portion extends in a second direction. Each of the second type of dummy cells comprises second pre-defined dimensions. The second pre-defined dimensions is different than the first pre-defined dimensions.
    Type: Grant
    Filed: September 20, 2019
    Date of Patent: July 13, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Jung Chang, Min-Yuan Tsai, Wen-Ju Yang
  • Patent number: 11055467
    Abstract: A method for performing power mesh optimization with the aid of additional wires and an associated apparatus are provided. The method includes: reading a clock cell definition file to obtain respective basic information of a plurality of clock cells in a circuit design; and according to the respective basic information of the plurality of clock cells, executing a power mesh optimization procedure, including: regarding any type of clock cells in multiple types of clock cells within the plurality of clock cells, classifying the clock cells into a plurality of sub-types according to respective sizes of the type of clock cells; and performing power mesh enhancement on respective clock cells of a set of sub-types within the plurality of sub-types, to add a set of additional wires crossing a set of original wires in an original power mesh at each clock cell of any sub-type of the set of sub-types.
    Type: Grant
    Filed: May 18, 2020
    Date of Patent: July 6, 2021
    Assignee: Realtek Semiconductor Corp.
    Inventors: Chien-Cheng Liu, Yun-Chih Chang
  • Patent number: 11049834
    Abstract: Embodiments of bonded semiconductor structures and fabrication methods thereof are disclosed. In an example, a semiconductor device includes a first and a second semiconductor structures. The first semiconductor structure includes a first interconnect layer including first interconnects. The first semiconductor structure further includes a first bonding layer including first bonding contacts. Each first interconnect is in contact with a respective first bonding contact. The second semiconductor structure includes a second interconnect layer including second interconnects. The second semiconductor structure further includes a second bonding layer including second bonding contacts. At least one second bonding contact is in contact with a respective second interconnect. At least another second bonding contact is separated from the second interconnects. The semiconductor device further includes a bonding interface between the first and second bonding layers.
    Type: Grant
    Filed: March 4, 2019
    Date of Patent: June 29, 2021
    Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
    Inventors: Tao Wang, Si Ping Hu, Jia Wen Wang, Shi Qi Huang, Jifeng Zhu, Jun Chen, Zi Qun Hua
  • Patent number: 11049821
    Abstract: Breakage of a board due to local concentration of stress at the time when a circuit module deforms is reduced. A circuit module includes a base, a lower layer, and a surface layer. The base has a mounting region in which an electronic component is mounted. The lower layer is made of a resin material. The lower layer is formed over from the mounting region to a region other than the mounting region on the base. The surface layer is made of a resin material different in hardness from the resin material of the lower layer. A periphery of the surface layer is located outside the mounting region and inside a region in which the lower layer is formed.
    Type: Grant
    Filed: February 14, 2019
    Date of Patent: June 29, 2021
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Takayoshi Obata
  • Patent number: 11036911
    Abstract: A method of the present disclosure includes receiving a design layout; performing routing to the design layout to obtain a routed layout including an interconnect structure including a first metal layer, a second metal layer over the first metal layer, a third metal layer over the second metal layer, and a plurality of functional vias; performing optical proximity correction (OPC) operations to the routed layout to obtain an OPC'ed layout; and modifying the OPC'ed layout to obtain a modified layout. The modifying of the routed layout includes inserting a first plurality of dummy vias between the first metal layer and the second metal layer to avoid horizontal bridging between two adjacent metal lines in the first metal layer, and inserting a second plurality of dummy vias between the second metal layer and the third metal layer to avoid vertical coupling to the first plurality of dummy vias.
    Type: Grant
    Filed: December 30, 2019
    Date of Patent: June 15, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Han-Chung Lin, Chung-Yi Lin, Yen-Sen Wang
  • Patent number: 11037878
    Abstract: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a plurality of semiconductor memory dies vertically stacked through a plurality of microbumps; a plurality of through silicon vias positioned in the plurality of semiconductor dies and electrically coupled through the plurality of microbumps; and a plurality of protection liners positioned on sides of the plurality of through silicon vias; wherein the plurality of protection liners are formed of manganese-zinc ferrite, nickel-zinc ferrite, cobalt ferrite, strontium ferrite, barium ferrite, lithium ferrite, lithium-zinc ferrite, single crystal yttrium iron garnet, or gallium substituted single crystal yttrium iron garnet.
    Type: Grant
    Filed: April 16, 2020
    Date of Patent: June 15, 2021
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Huan-Yung Yeh
  • Patent number: 11024601
    Abstract: Hyperchip structures and methods of fabricating hyperchips are described. In an example, an integrated circuit assembly includes a first integrated circuit chip having a device side opposite a backside. The device side includes a plurality of transistor devices and a plurality of device side contact points. The backside includes a plurality of backside contacts. A second integrated circuit chip includes a device side having a plurality of device contact points thereon. The second integrated circuit chip is on the first integrated circuit chip in a device side to device side configuration. Ones of the plurality of device contact points of the second integrated circuit chip are coupled to ones of the plurality of device contact points of the first integrated circuit chip. The second integrated circuit chip is smaller than the first integrated circuit chip from a plan view perspective.
    Type: Grant
    Filed: December 21, 2017
    Date of Patent: June 1, 2021
    Assignee: Intel Corporation
    Inventors: Mark T. Bohr, Wilfred Gomes, Rajesh Kumar, Pooya Tadayon, Doug Ingerly
  • Patent number: 11018134
    Abstract: A semiconductor device is provided. The semiconductor device includes a first transistor, a first interconnect structure, and a second transistor. The first transistor has a first gate length. The first interconnect structure is over the first transistor. The second transistor is over the first interconnect structure. The second transistor is electrically coupled to the first transistor through the first interconnect structure. The second transistor has a second gate length, and the first gate length is shorter than the second gate length.
    Type: Grant
    Filed: September 26, 2017
    Date of Patent: May 25, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chung-Te Lin, Wei-Yuan Lu, Feng-Cheng Yang
  • Patent number: 11018007
    Abstract: A method of forming a structure for etch masking that includes forming first dielectric spacers on sidewalls of a plurality of mandrel structures and forming non-mandrel structures in space between adjacent first dielectric spacers. Second dielectric spacers are formed on sidewalls of an etch mask having a window that exposes a connecting portion of a centralized first dielectric spacer. The connecting portion of the centralized first dielectric spacer is removed. The mandrel structures and non-mandrel structures are removed selectively to the first dielectric spacers to provide an etch mask. The connecting portion removed from the centralized first dielectric spacer provides an opening connecting a first trench corresponding to the mandrel structures and a second trench corresponding to the non-mandrel structures.
    Type: Grant
    Filed: November 6, 2019
    Date of Patent: May 25, 2021
    Assignee: Tessera, Inc.
    Inventors: Sean D. Burns, Lawrence A. Clevenger, Matthew E. Colburn, Nelson M. Felix, Sivananda K. Kanakasabapathy, Christopher J. Penny, Roger A. Quon, Nicole A. Saulnier
  • Patent number: 11018079
    Abstract: A semiconductor package structure includes a substrate comprising a land structure. The land structure includes a first land section having a first height in a cross-sectional view and a second land section having a second height in the cross-sectional view that is different than the first height. A mold encapsulant is disposed adjacent a lateral portion of the first land section and is disposed below a bottom portion of the second land section. A semiconductor die is attached to the substrate, and includes a first major surface, a second major surface opposing the first major surface, and an outer perimeter. The semiconductor die further includes a bonding structure disposed adjacent the first major surface, which is coupled to the second land section such that the first land section is disposed outside the perimeter of the semiconductor die A mold member encapsulates at least portions of the semiconductor die.
    Type: Grant
    Filed: November 28, 2017
    Date of Patent: May 25, 2021
    Assignee: Amkor Technology Singapore Holding Pte. Ltd.
    Inventors: Kyoung Yeon Lee, Byong Jin Kim, Jae Min Bae, Hyung Il Jeon, Gi Jeong Kim, Ji Young Chung
  • Patent number: 11018081
    Abstract: A semiconductor device and method of manufacture are provided whereby an interposer and a first semiconductor device are placed onto a carrier substrate and encapsulated. The interposer comprises a first portion and conductive pillars extending away from the first portion. A redistribution layer located on a first side of the encapsulant electrically connects the conductive pillars to the first semiconductor device.
    Type: Grant
    Filed: October 4, 2019
    Date of Patent: May 25, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Po-Hao Tsai, Po-Yao Chuang, Shin-Puu Jeng, Techi Wong
  • Patent number: 11011568
    Abstract: A semiconductor structure includes: a semiconductor substrate arranged over a back end of line (BEOL) metallization stack, and including a scribe line opening; a conductive pad having an upper surface that is substantially flush with an upper surface of the semiconductor substrate, the conductive pad including an upper conductive region and a lower conductive region, the upper conductive region being confined to the scribe line opening substantially from the upper surface of the semiconductor substrate to a bottom of the scribe line opening, and the lower conductive region protruding downward from the upper conductive region, through the BEOL metallization stack; a passivation layer arranged over the semiconductor substrate; and an array of pixel sensors arranged in the semiconductor substrate adjacent to the conductive pad.
    Type: Grant
    Filed: April 13, 2020
    Date of Patent: May 18, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Sheng-Chau Chen, Cheng-Hsien Chou, Min-Feng Kao
  • Patent number: 11004779
    Abstract: A substrate includes a first dielectric layer having a first surface and a second surface opposite to the first surface, a first patterned conductive layer adjacent to the first surface of the first dielectric layer and comprising an interconnection structure, and an interconnection element. The interconnection element extends from the first surface of the first dielectric layer to the second surface of the first dielectric layer and is surrounded by the interconnection structure.
    Type: Grant
    Filed: February 9, 2018
    Date of Patent: May 11, 2021
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Po-Shu Peng, Cheng-Lin Ho, Chih-Cheng Lee
  • Patent number: 11004787
    Abstract: A semiconductor chip includes a memory cell array and a wiring layer. The memory cell array includes a plurality of blocks arranged in a first direction along a surface of the semiconductor chip. The wiring layer includes a plurality of first pattern regions at different positions along the first direction, each first pattern region including a different pattern corresponding to one or more of the blocks. The first pattern regions can be used to identify portions of the semiconductor chip during analysis or the like.
    Type: Grant
    Filed: September 3, 2019
    Date of Patent: May 11, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Masaya Ichikawa, Takashi Sugihara, Kaito Shirai, Satoshi Kotomari
  • Patent number: 10998269
    Abstract: A semiconductor structure with an improved metal structure is described. The semiconductor structure can include a substrate having an upper surface, an interconnect layer over the upper surface, and an additional structure deposited over the interconnect layer. The interconnect layer can include a patterned seed layer over the substrate, at least two metal lines over the seed layer, and a dielectric material between adjacent metal lines. A barrier layer can be deposited over the at least two metal lines. Methods of making the semiconductor structures are also described.
    Type: Grant
    Filed: June 22, 2020
    Date of Patent: May 4, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wen-Jiun Liu, Chen-Yuan Kao, Hung-Wen Su, Ming-Hsing Tsai, Syun-Ming Jang
  • Patent number: 10985166
    Abstract: A method for forming a memory device is disclosed, including providing a substrate, forming an isolation structure and plural active regions in the substrate, forming a plurality of island features on the substrate respectively covering two of the terminal portions of the active regions, using the island features as an etching mask to etch the substrate to perform a first etching process to define a first recessed region and plural island structures on the substrate. The island structures respectively comprise the two terminal portions of the active regions and the first recessed region comprises the central portions of the active regions.
    Type: Grant
    Filed: October 31, 2018
    Date of Patent: April 20, 2021
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Hsu-Yang Wang, Ping-Cheng Hsu, Shih-Fang Tzou, Chin-Lung Lin, Yi-Hsiu Lee, Koji Taniguchi, Harn-Jiunn Wang, Tsung-Ying Tsai
  • Patent number: 10985125
    Abstract: A chip package structure is provided. The chip package structure includes a substrate having a first surface and a second surface opposite to the first surface. The chip package structure includes a first chip structure and a second chip structure over the first surface. The chip package structure includes a protective layer over the first surface and surrounding the first chip structure and the second chip structure. A portion of the protective layer is between the first chip structure and the second chip structure. The chip package structure includes a first anti-warpage bump over the second surface and extending across the portion of the protective layer. The chip package structure includes a conductive bump over the second surface and electrically connected to the first chip structure or the second chip structure. The first anti-warpage bump is wider than the conductive bump.
    Type: Grant
    Filed: September 23, 2020
    Date of Patent: April 20, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kuan-Yu Huang, Sung-Hui Huang, Shu-Chia Hsu, Leu-Jen Chen, Yi-Wei Liu, Shang-Yun Hou, Jui-Hsieh Lai, Tsung-Yu Chen, Chien-Yuan Huang, Yu-Wei Chen
  • Patent number: 10978370
    Abstract: A semiconductor structure includes a die embedded in a molding material, the die having die connectors on a first side; a first redistribution structure at the first side of the die, the first redistribution structure being electrically coupled to the die through the die connectors; a second redistribution structure at a second side of the die opposing the first side; and a thermally conductive material in the second redistribution structure, the die being interposed between the thermally conductive material and the first redistribution structure, the thermally conductive material extending through the second redistribution structure, and the thermally conductive material being electrically isolated.
    Type: Grant
    Filed: September 13, 2019
    Date of Patent: April 13, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hao-Jan Pei, Wei-Yu Chen, Chia-Shen Cheng, Chih-Chiang Tsao, Cheng-Ting Chen, Chia-Lun Chang, Chih-Wei Lin, Hsiu-Jen Lin, Ching-Hua Hsieh, Chung-Shi Liu
  • Patent number: 10978295
    Abstract: Systems, apparatuses, and methods related to epitaxial growth on semiconductor structures are described. An apparatus may include a working surface of a substrate material and a storage node connected to an active area of an access device on the working surface. The apparatus may also include a material epitaxially grown over the storage node contact to enclose a non-solid space between the storage node contact and passing sense lines.
    Type: Grant
    Filed: June 19, 2019
    Date of Patent: April 13, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Guangjun Yang, Nicholas R. Tapias
  • Patent number: 10978434
    Abstract: A system-in-package includes a package substrate that at least partially surrounds an embedded radio-frequency integrated circuit chip and a processor chip mated to a redistribution layer. A wide-band phased-array antenna module is mated to the package substrate with direct interconnects from the radio-frequency integrated circuit chip to antenna patches within the antenna module. Additionally, fan-out antenna pads are also coupled to the radio-frequency integrated circuit chip.
    Type: Grant
    Filed: January 28, 2020
    Date of Patent: April 13, 2021
    Assignee: Intel Corporation
    Inventors: Bok Eng Cheah, Jackson Chung Peng Kong, Boon Ping Koh, Kooi Chi Ooi
  • Patent number: 10978336
    Abstract: A method of manufacturing a semiconductor device includes forming a first dielectric layer and a through hole passing through the first dielectric layer over a substrate; forming a plurality of dummy contacts in the through hole; forming a plurality of first dummy wires on the plurality of dummy contacts; filling a second dielectric layer between the plurality of first dummy wires, wherein the second dielectric layer has a first air gap; removing the dummy contacts and the first dummy wires to expose the through hole, thereby forming a first wiring trench over the through hole; and forming a contact and a first wire in the through hole and the first wiring trench.
    Type: Grant
    Filed: December 5, 2019
    Date of Patent: April 13, 2021
    Assignee: Winbond Electronics Corp.
    Inventors: Cheng-Hui Tu, Chi-Ching Liu, Ting-Ying Shen, Yen-De Lee, Ping-Kun Wang
  • Patent number: 10969998
    Abstract: A semiconductor apparatus includes a substrate, a first die, and a second die. The substrate includes first and second byte pads of a first channel and first and second byte pad of a second channel. First byte pads of the first die are respectively coupled to the first byte pads of the first channel, and second byte pads of the first die are respectively coupled to the second byte pads of the first channel. The second die, as disposed, is rotated by 180° with respect to the first die. First byte pads of the second die are respectively coupled to the second byte pads of the second channel, and second byte pads of the second die are respectively coupled to the first byte pads of the second channel.
    Type: Grant
    Filed: December 10, 2018
    Date of Patent: April 6, 2021
    Assignee: SK hynix Inc.
    Inventor: Soo Bin Lim