Abstract: According to one embodiment, the interconnect layer includes a fourth conductive member and a fifth conductive member. The fourth conductive member is provided between the first region of the first chip and the third region of the second chip. The fourth conductive member connects the first conductive member of the first chip and the second conductive member of the second chip. The fifth conductive member is provided between the second region of the first chip and the fifth region of the third chip. The fifth conductive member connects the first conductive member of the first chip and the third conductive member of the third chip. The first chip is provided between the first terminal and the second terminal.

Abstract: Method for packaging a semiconductor die assemblies. In one embodiment, a method is directed to packaging a semiconductor die assembly having a first die and a plurality of second dies arranged in a stack over the first die, wherein the first die has a peripheral region extending laterally outward from the stack of second dies. The method can comprise coupling a thermal transfer structure to the peripheral region of the first die and flowing an underfill material between the second dies. The underfill material is flowed after coupling the thermal transfer structure to the peripheral region of the first die such that the thermal transfer structure limits lateral flow of the underfill material.

Abstract: A method of manufacturing a package-on-package device includes a bonding step carried out by a bonding apparatus including a pressing member and a light source that produces a laser beam. A bottom package including a lower substrate, lower solder balls alongside an edge of the lower substrate, and a lower chip on a center of the lower substrate is provided, the bottom package is bonded to an interposer substrate having upper solder balls aligned with the lower solder balls, and a top package having an upper substrate and an upper chip on the upper substrate is bonded to the interposer substrate. While the interposer substrate is disposed on the bottom package, the pressing member presses the interposer substrate against the bottom package, and the laser beam adheres the lower solder balls to the upper solder balls.

Abstract: A method of forming a semiconductor structure includes providing a semiconductor wafer including a plurality of semiconductor dies, providing a polymerized material layer, attaching the polymerized material layer to the semiconductor wafer such that the polymerized material layer is polymerized prior to the step of attaching the polymerized material layer to the semiconductor wafer, applying and patterning an etch mask layer over the polymerized material layer, such that openings are formed through the etch mask layer, etching portions of the polymerized material layer that are proximal to the openings through the etch mask layer by applying an etchant into the openings through the etch mask layer in an etch process, and removing the etch mask layer selective to the polymerized material layer. Alternatively, a patterned polymerized material layer may be transferred from a transfer substrate to the semiconductor wafer.

Abstract: A semiconductor package and a method of forming the same are provided. The semiconductor package includes one or a plurality of chips on a substrate, bumps disposed below each of the one or plurality of chips, an underfill material layer on the substrate, on a side surface of each of the bumps, and extending to side surfaces of the one or plurality of chips, and a mold layer on the substrate and contacting the underfill material layer. The underfill material layer includes a first side portion, a second side portion on the first side portion and having a slope, steeper than a slope of the first side portion, and a third side portion on the second side portion and having a slope that is less steep than a slope of the second side portion.

Abstract: A semiconductor package includes a first semiconductor die, a semiconductor device comprising a second semiconductor die, and one or more wire bond structures. The wire bond structure includes a bond interface portion. The wire bond structure is arranged next to the first semiconductor die. The first semiconductor die and the bond interface portion of the wire bond structure are arranged at the same side of the semiconductor device. An interface contact structure of the semiconductor device is electrically connected to the wire bond structure.

Abstract: A semiconductor device includes a stack structure comprising decks. Each deck of the stack structure comprises a memory element level comprising memory elements and control logic level in electrical communication with the memory element level, the control logic level comprising a first subdeck structure comprising a first number of transistors comprising a P-type channel region or an N-type channel region and a second subdeck structure comprising a second number of transistors comprising the other of the P-type channel region or the N-type channel region overlying the first subdeck structure. Related semiconductor devices and methods of forming the semiconductor devices are disclosed.

Abstract: Electronic package structures and systems are described in which a 3D interconnect structure is integrated into a package redistribution layer and/or chiplet for power and signal delivery to a die. Such structures may significantly improve input output (IO) density and routing quality for signals, while keeping power delivery feasible.

Abstract: Techniques are employed to mitigate the anchoring effects of cavity sidewall adhesion on an embedded conductive interconnect structure, and to allow a lower annealing temperature to be used to join opposing conductive interconnect structures. A vertical gap may be disposed between the conductive material of an embedded interconnect structure and the sidewall of the cavity to laterally unpin the conductive structure and allow uniaxial expansion of the conductive material. Additionally or alternatively, one or more vertical gaps may be disposed within the bonding layer, near the embedded interconnect structure to laterally unpin the conductive structure and allow uniaxial expansion of the conductive material.

Abstract: Three-dimensional integrated circuit structures are disclosed. A three-dimensional integrated circuit structure includes a first die, a second die and a device-free die. The first die includes a first device. The second die includes a second device and is bonded to the first die. The device-free die is located aside the second die and is bonded to the first die. The device-free die includes a conductive feature electrically connected to the first die and the second die.

Abstract: Various semiconductor chip devices and methods of making the same are disclosed. In one aspect, an apparatus is provided that includes a first redistribution layer (RDL) structure having a first plurality of conductor traces, a first molding layer on the first RDL structure, plural conductive pillars in the first molding layer, each of the conductive pillars including a first end and a second end, a second RDL structure on the first molding layer, the second RDL structure having a second plurality of conductor traces, and wherein some of the conductive pillars are electrically connected between some of the first plurality of conductor traces and some of the second plurality of conductor traces to provide a first inductor coil.

Abstract: First signaling indicative of instructions to enter a self-refresh (SREF) mode can be received concurrently by a plurality of memory dies. Responsive to a memory die of the plurality of memory dies entering the SREF mode, self-refreshing of memory banks of the memory die can be delayed, at the memory die and based on fuse states of an array of fuses of the memory die, an amount of time relative to receipt of the signaling by the memory die. Delaying self-refreshing of memory banks of memory dies in a staggered, or asynchronous, manner can evenly distribute power consumption of the memory dies so that the likelihood of an associated power spike is reduced or eliminated.

Abstract: A semiconductor device assembly includes a first remote distribution layer (RDL), the first RDL comprising a lower outermost planar surface of the semiconductor device assembly; a first semiconductor die directly coupled to an upper surface of the first RDL by a first plurality of interconnects; a second RDL, the second RDL comprising an upper outermost planar surface of the semiconductor device assembly opposite the lower outermost planar surface; a second semiconductor die directly coupled to a lower surface of the second RDL by a second plurality of interconnects; an encapsulant material disposed between the first RDL and the second RDL and at least partially encapsulating the first and second semiconductor dies; and a third plurality of interconnects extending fully between and directly coupling the upper surface of the first RDL and the lower surface of the second RDL.

Abstract: An interconnection structure of a system on wafer and a PCB based on a TSV process and a method for manufacturing the same. The structure comprises a bottom structural part and a top structural part, the upper surface of the bottom structural part is provided with a plurality of positioning holes; the lower surface of the top structural part is provided with positioning pins; the upper surface of the bottom structural part is provided with a bottom groove, and a system on wafer is arranged in the bottom groove; the lower surface of the system on wafer is connected with the bottom groove; the lower surface of the top structural part is provided with a top groove, and a PCB preformed die is connected in the top groove, and the other end of the PCB preformed die is connected with the system on wafer by an elastic connector.

Abstract: Disclosed are semiconductor packages and methods of manufacturing the same. The method of manufacturing a semiconductor package may include providing a carrier substrate having a trench formed on a first top surface of the carrier substrate, providing a first semiconductor chip on the carrier substrate, mounting at least one second semiconductor chip on a second top surface of the first semiconductor chip, coating a mold member to surround a first lateral surface of the first semiconductor chip and a second lateral surface of the at least one second semiconductor chip, and curing the mold member to form a mold layer. The trench may be provided along a first edge of the first semiconductor chip. The mold member may cover a second edge of a bottom surface the first semiconductor chip.

Abstract: A semiconductor device package and a method of manufacturing the same are provided. The semiconductor device package includes a first module, a second module, a first intermediate circuit layer, a first conductive transmission path and a second conductive transmission path. The second module is stacked on the first module. The first intermediate circuit layer is arranged between the first module and the second module. The first conductive transmission is configured to electrically connect the first semiconductor module with the first intermediate circuit layer. The second conductive transmission path is configured to electrically connect the first intermediate circuit layer with the second semiconductor module.

Abstract: Semiconductor packages including active package substrates are described. In an example, the active package substrate includes an active die between a top substrate layer and a bottom substrate layer. The top substrate layer may include a via and the active die may include a die pad. An anisotropic conductive layer may be disposed between the via and the die pad to conduct electrical current unidirectionally between the via and the die pad. In an embodiment, the active die is a flash memory controller and a memory die is mounted on the top substrate layer and placed in electrical communication with the flash memory controller through the anisotropic conductive layer.

Abstract: A semiconductor package is provided. The semiconductor package may include a first semiconductor die, a second semiconductor die stacked on the first semiconductor die, the second semiconductor die having a width smaller than a width of the first semiconductor die, a third semiconductor die stacked on the second semiconductor die, the third semiconductor die having a width smaller than the width of the first semiconductor die, and a mold layer covering side surfaces of the second and third semiconductor dies and a top surface of the first semiconductor die. The second semiconductor die may include a second through via, and the third semiconductor die may include a third conductive pad in contact with the second through via.

Abstract: A chip package including a first semiconductor die, a support structure and a second semiconductor die is provided. The first semiconductor die includes a first dielectric layer and a plurality of conductive vias, the first dielectric layer includes a first region and a second region, the conductive vias is embedded in the first region of the first dielectric layer; a plurality of conductive pillars is disposed on and electrically connected to the conductive vias. The second semiconductor die is stacked over the support structure and the second region of the first dielectric layer; and an insulating encapsulant encapsulates the first semiconductor die, the second semiconductor die, the support structure and the conductive pillars, wherein the second semiconductor die is electrically connected to the first semiconductor die through the conductive pillars.

Abstract: A semiconductor chip includes a chip body including a signal input/output circuit unit, a chip pad unit disposed on one surface of the chip body and including first and second chip pads having different surface areas from each other, and a chip pad selection circuit unit disposed in the chip body and electrically connected to the signal input/output circuit unit and the chip pad unit. The chip pad selection circuit unit is configured to select one chip pad of the first and second chip pads and electrically connect the selected one chip pad to the signal input/output circuit unit.

Abstract: Various embodiments described herein provide for execution of a memory function within a memory sub-system. For example, some embodiments provide for execution of certain memory-related functions internally within the memory sub-system, at the request of a host system, using one or more memory access operations (e.g., direct memory access operations) performed internally within the memory sub-system.

Abstract: The present disclosure provides a method for preparing a semiconductor device with a composite dielectric structure. The method includes forming a photoresist pattern structure over a first semiconductor die. The method also includes forming a second dielectric layer surrounding the photoresist pattern structure, and removing the photoresist pattern structure to form a first opening in the second dielectric layer. The method further includes forming dielectric spacers along sidewalls of the first opening, and forming an interconnect structure surrounded by the dielectric spacers. In addition, the method includes bonding a second semiconductor die to the second dielectric layer. The second semiconductor die includes a second conductive pad facing the interconnect structure, and the second conductive pad is electrically connected to the first conductive pad of the first semiconductor die through the interconnect structure.

Abstract: A chip includes a semiconductor substrate, an electrical connector over the semiconductor substrate, and a molding compound molding a lower part of the electrical connector therein. A top surface of the molding compound is lower than a top end of the electrical connector. A recess extends from the top surface of the molding compound into the molding compound.

Abstract: A die bonding structure includes a first die and a second die. The first die includes a first sealing ring and a plurality of first metal contacts, wherein sidewalls of the first metal contacts align a sidewall of the first sealing ring. The second die includes a second sealing ring and a plurality of second metal contacts, wherein sidewalls of the second metal contacts align a sidewall of the second sealing ring. The first metal contacts are directly bonded to the second metal contacts, respectively, and the first sealing ring is directly bonded to the second sealing ring.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first polymer layer formed between a first substrate and a second substrate, and a first conductive layer formed over the first polymer. The semiconductor device includes a first through substrate via (TSV) formed over the first conductive layer, and the conductive layer is in direct contact with the first TSV and the first polymer.

Abstract: Methods of forming microelectronic package structures, and structures formed thereby, are described. Those methods/structures may include attaching a first die on a board, attaching an interposer on a top surface of the first die, and attaching a second die on the top surface of the first die that is adjacent the interposer, wherein the second die is offset from a center region of the first die. A first wire conductive structure may be attached to the second die that extends from the second die to a top surface of the interposer. A second wire conductive structure is attached to the interposer and extends from the interposer to the board.

Abstract: A semiconductor package includes a package substrate including a first substrate channel pad and a second substrate channel pad, a chip stack including a plurality of semiconductor chips stacked on the package substrate to be offset in a first direction, wherein first semiconductor chips located on odd layers from among the plurality of semiconductor chips and second semiconductor chips located on even layers from among the plurality of semiconductor chips are offset in a second direction perpendicular to the first direction, each of the first semiconductor chips includes a first chip channel pad, and each of the second semiconductor chips includes a second chip channel pad, first inter-chip connection wires configured to electrically connect the first chip channel pads of the first semiconductor chips to one another, second inter-chip connection wires configured to electrically connect the second chip channel pads of the second semiconductor chips to one another.

Abstract: An integrated circuit assembly may be formed having a substrate, a first integrated circuit device electrically attached to the substrate, a second integrated circuit device electrically attached to the first integrated circuit device, and a heat dissipation device comprising at least one first thermally conductive structure proximate at least one of the first integrated circuit device, the second integrated circuit device, and the substrate; and a second thermally conductive structure disposed over the first thermally conductive structure(s), the first integrated circuit device, and the second integrated circuit device, wherein the first thermally conductive structure(s) have a lower electrical conductivity than an electrical conductivity of the second thermally conductive structure. The first thermally conductive structure(s) may be formed by an additive process or may be pre-formed and attached to at least one of the first integrated circuit device, the second integrated circuit device, and the substrate.

Abstract: The present disclosure provides a semiconductor package, including a substrate, a semiconductor die, and a conductive bump. The substrate has a first surface and a second surface opposite to the first surface. The substrate further includes a conductive line surrounded by a dielectric, and a conductive via connected to the conductive line and protruding from the dielectric at the second surface. The semiconductor die is connected to the first surface of the substrate. The conductive bump is connected to the conductive via at the second surface.

Abstract: Semiconductor devices with duplicated die bond pads and associated device packages and methods of manufacture are disclosed herein. In one embodiment, a semiconductor device package includes a plurality of package contacts and a semiconductor die having a plurality of first die bond pads, a plurality of second die bond pads, and a plurality of duplicate die bond pads having the same pin assignments as the first die bond pads. The semiconductor die further includes an integrated circuit operably coupled to the package contacts via the plurality of first die bond pads and either the second die bond pads or the duplicate die bond pads, but not both. The integrated circuit is configured to be programmed into one of (1) a first pad state in which the first and second die bond pads are enabled for use with the package contacts and (2) a second pad state in which the first and duplicate die bond pads are enabled for use with the package contacts.

Abstract: A method of manufacturing component carriers is disclosed. The method includes providing a stack with at least one electrically conductive layer structure and/or at least one electrically insulating layer structure, forming a first hole in a core of the stack and subsequently embedding a first component in the first hole, thereafter forming a second hole in the same core of the stack and subsequently embedding a second component in the second hole. A component carrier has a stack with at least one electrically conductive layer structure and/or at least one electrically insulating layer structure. A first hole is formed in a core of the stack. A first component is embedded in the first hole. A second hole is formed in the same core of the stack and subsequently a second component is embedded in the second hole.

Abstract: A semiconductor device, having a substrate including an insulating plate and a circuit board provided on a front surface of the insulating plate. The circuit board has a first disposition area and a second disposition area with a gap therebetween, and a groove portion, of which a longitudinal direction is parallel to the gap, formed in the gap. The semiconductor device further includes a first semiconductor chip and a second semiconductor chip located on the circuit board in the first disposition area and the second disposition area, respectively, and a blocking member located in the gap across the groove portion in parallel to the longitudinal direction in a plan view of the semiconductor device.

Abstract: A semiconductor device includes a first switching element; a second switching element; a first metal member; a second metal member; a first terminal that has a potential on a high potential side; a second terminal that has a potential on a low potential side; a third terminal that has a midpoint potential; and a resin part. A first potential part has potential equal to potential of the first terminal. A second potential part has potential equal to potential of the second terminal. A third potential part has potential equal to potential of the third terminal. A first creepage distance between the first potential part and the second potential part is longer than a minimum value of a second creepage distance between the first potential part and the third potential part and a third creepage distance between the second potential part and the third potential part.

Abstract: A method for forming a hybrid-bonding structure is provided. The method includes forming a first dielectric layer over a first semiconductor substrate. The first semiconductor substrate includes a conductive structure. The method also includes partially removing the first dielectric layer to form a first dielectric dummy pattern, a second dielectric dummy pattern and a third dielectric dummy pattern and an opening through the first dielectric layer. The first dielectric dummy pattern, the second dielectric dummy pattern and the third dielectric dummy pattern are surrounded by the opening. In addition, the method includes forming a first conductive line in the opening. The first conductive line is in contact with the conductive structure.

Abstract: According to one embodiment, a semiconductor device includes a substrate, first stacked components, second stacked components, and a coating resin. The first stacked components include first chips and are stacked on a surface of the substrate. The second stacked components include second chips and are stacked on the surface. The coating resin covers the surface, the first stacked components, and the second stacked components. A first top surface of a second farthest one of the first chips away from the surface differs in position in a first direction from a second top surface of second farthest one of the second chips away from the surface.

Abstract: A method comprises forming a plurality of interconnect structures including a dielectric layer, a metal line and a redistribution line over a carrier, attaching a semiconductor die on a first side of the plurality of interconnect structures, forming an underfill layer between the semiconductor die and the plurality of interconnect structures, mounting a top package on the first side the plurality of interconnect structures, wherein the top package comprises a plurality of conductive bumps, forming an encapsulation layer over the first side of the plurality of interconnect structures, wherein the top package is embedded in the encapsulation layer, detaching the carrier from the plurality of interconnect structures and mounting a plurality of bumps on a second side of the plurality of interconnect structures.

Abstract: Embodiments for a packaged semiconductor device and methods of making are provided herein, where a packaged semiconductor device includes a package body having a recess in which a pressure sensor is exposed; a polymeric gel within the recess that vertically and laterally surrounds the pressure sensor; and a protection layer including a plurality of beads embedded within a top region of the polymeric gel.

Abstract: A semiconductor device package includes a redistribution layer, a plurality of conductive pillars, a reinforcing layer and an encapsulant. The conductive pillars are in direct contact with the first redistribution layer. The reinforcing layer surrounds a lateral surface of the conductive pillars. The encapsulant encapsulates the first redistribution layer and the reinforcing layer. The conductive pillars are separated from each other by the reinforcing layer.

Abstract: Disclosed herein are integrated circuit (IC) package supports and related apparatuses and methods. For example, in some embodiments, an IC package support may include a layer of dielectric material; a conductive pad at least partially on a top surface of the layer of dielectric material; and a layer of material on side surfaces of the conductive pad, wherein the layer of material does not extend onto the top surface of the layer of dielectric material. Other embodiments are also disclosed.

Abstract: A package includes a device die, an encapsulant encapsulating the device die therein, a first plurality of through-vias penetrating through the encapsulant, a second plurality of through-vias penetrating through the encapsulant, and redistribution lines over and electrically coupling to the first plurality of through-vias. The first plurality of through-vias include an array. The second plurality of through-vias are outside of the first array, and the second plurality of through-vias are larger than the first plurality of through-vias.

Abstract: A method of monitoring microelectromechanical system (MEMS) pressure sensors arranged on a carrier includes: generating a first measurement value by a first MEMS pressure sensor arranged on the carrier; generating a second measurement value by a second MEMS pressure sensor arranged on the carrier; and determining, by an integrated circuit, whether the first measurement value of the first MEMS pressure sensor corresponds to the second measurement value of the second MEMS pressure sensor in accordance with a predefined criterion, wherein the integrated circuit is arranged on the carrier and is coupled to the first MEMS pressure sensor and the second MEMS pressure sensor.

Abstract: A method of three-dimensionally integrating elements such as singulated die or wafers and an integrated structure having connected elements such as singulated dies or wafers. Either or both of the die and wafer may have semiconductor devices formed therein. A first element having a first contact structure is bonded to a second element having a second contact structure. First and second contact structures can be exposed at bonding and electrically interconnected as a result of the bonding. A via may be etched and filled after bonding to expose and form an electrical interconnect to interconnected first and second contact structures and provide electrical access to this interconnect from a surface.

Abstract: The routing of conductors in the conductor layers in an integrated circuit are routed using mixed-Manhattan-diagonal routing. Various techniques are disclosed for selecting a conductor scheme for the integrated circuit prior to fabrication of the integrated circuit. Techniques are also disclosed for determining the supply and/or the demand for the edges in the mixed-Manhattan-diagonal routing.

Abstract: Various embodiments of a die carrier package and a method of forming such package are disclosed. The package includes one or more dies disposed within a cavity of a carrier substrate, where a first die contact of one or more of the dies is electrically connected to a first die pad disposed on a recessed surface of the cavity, and a second die contact of one or more of the dies is electrically connected to a second die pad also disposed on the recessed surface. The first and second die pads are electrically connected to first and second package contacts respectively. The first and second package contacts are disposed on a first major surface of the carrier substrate adjacent the cavity.

Abstract: A hybridized image sensor includes a first die and a second die. The first die includes a first surface, a first plurality of conductive bumps fabricated on the first surface, and a first alignment feature fabricated on the first surface. The second die includes a second surface, a second plurality of conductive bumps fabricated on the second surface, and second alignment features fabricated on the second surface, wherein the first alignment features interact with the second alignment features to align the first plurality of conductive bumps with the second plurality of conductive bumps.

Abstract: A system comprises an interposer including multiple conductive interconnects; multiple chiplets arranged on the interposer and interconnected by the interposer; each chiplet including a die-to-die physical layer interface including one or more pads to engage the interconnect of the interposer; and wherein at least one chiplet includes multiple input-output channels organized into at least one column and arranged in an order at a periphery of the chiplet forming a die-to-die physical layer interface to engage the interconnects of the interposer, wherein the order of the channels of the column is programmable.

Abstract: A semiconductor package includes a package substrate, a lower package structure on the package substrate that includes a mold substrate, a semiconductor chip in the mold substrate having chip pads exposed through the mold substrate, spacer chips in the mold substrate and spaced apart from the semiconductor chip, and a redistribution wiring layer on the mold substrate that has redistribution wirings electrically connected to the chip pads, first and second stack structures on the lower package structure spaced apart from each other, each of the first and second stack structures including stacked memory chips, and a molding member covering the lower package structure and the first and second stack structures, wherein the mold substrate includes a first covering portion covering side surfaces of the semiconductor chip and the spacer chips, and a second covering portion covering a lower surface of the semiconductor chip.

Abstract: Embodiments of mechanisms for testing a die package with multiple packaged dies on a package substrate use an interconnect substrate to provide electrical connections between dies and the package substrate and to provide probing structures (or pads). Testing structures, including daisy-chain structures, with metal lines to connect bonding structures connected to signals, power source, and/or grounding structures are connected to probing structures on the interconnect substrate. The testing structures enable determining the quality of bonding and/or functionalities of packaged dies bonded. After electrical testing is completed, the metal lines connecting the probing structures and the bonding structures are severed to allow proper function of devices in the die package. The mechanisms for forming test structures with probing pads on interconnect substrate and severing connecting metal lines after testing could reduce manufacturing cost.

Abstract: Systems and methods for a semiconductor device having an edge-notched substrate are provided. The device generally includes a substrate having a front side, a backside having substrate contacts, and an inward notch at an edge of the substrate. The device includes a die having an active side attached to the front side of the substrate and positioned such that bond pads of the die are accessible from the backside of the substrate through the inward notch. The device includes wire bonds routed through the inward notch and electrically coupling the bond pads of the die to the substrate contacts. The device may further include a second die having an active side attached to the backside of the first die and positioned laterally offset from the first die such that the second bond pads are accessible by wire bonds around the edge of the first die and through the inward notch.

Abstract: An integrated circuit structure includes a first transistor, an interconnect structure, a first dielectric layer, polycrystalline plugs, a semiconductor structure and a second transistor. The first transistor is formed on a substrate. The interconnect structure is over the first transistor. The first dielectric layer is over the interconnect structure. The polycrystalline plugs extend from a top surface of the dielectric layer into the dielectric layer. The semiconductor structure is disposed over the first dielectric layer. The second transistor is formed on the semiconductor structure.