Abstract: A cryptographic system includes a memory device and a processor. The memory device has at least two sections, including a first section and a second section. The processor is configured to determine a mode of operation, receive a signal, and selectively zeroize at least one section of the memory device based at least in part on the received signal and the determined mode of operation.

Abstract: A multi-die package has a plurality of leads and first and second semiconductor dies in superimposition and bonded together defining a die stack. The die stack has opposed first and second sides, with each of the first and second semiconductor dies having gate, drain and source regions, and gate, drain and source contacts. The first opposed side has the drain contact of the second semiconductor die, which is in electrical communication with a first set of the plurality of leads. The gate, drain and source contacts of the first semiconductor die and the gate and source contacts of the second semiconductor die are disposed on the second of said opposed sides and in electrical communication with a second set of the plurality of leads. The lead for the source of the first semiconductor die may be the same as the lead for the drain of the second semiconductor die.

Abstract: A semiconductor device has a chip mounting part, a first semiconductor chip, and a second semiconductor chip. The first semiconductor chip is mounted over the chip mounting part in a direction in which its first principal plane faces the chip mounting part. A part of the second semiconductor chip is mounted over the chip mounting part in a direction in which its third principal plane faces the first semiconductor chip. The element mounting part has a notch part. A part of the second semiconductor chip overlaps the notch part. In a region of the third principal plane of the second semiconductor chip that overlaps the notch part, a second electrode pad is provided.

Abstract: One or more embodiments are directed to a system-in-package (SiP) that includes a plurality of semiconductor chips and an interposer that that are molded in an encapsulation layer together. That is, a single processing step may be used to encapsulate the semiconductor chips and the interposer in the encapsulation layer. Furthermore, prior to setting or curing, the encapsulation layer is able to flow between the semiconductor chips and the interposer to provide further mechanical support for the semiconductor chips. Thus, the process for forming the SiP is reduced, resulting in a faster processing time and a lower cost. Additionally, one or more embodiments described herein reduce or eliminate warpage of the interposer.

Abstract: A semiconductor wafer has a contact pad. A first insulating layer is formed over the wafer. A second insulating layer is formed over the first insulating layer and contact pad. A portion of the second insulating layer is removed to expose the contact pad. A first UBM layer is formed over and follows a contour of the second insulating layer and contact pad to create a well over the contact pad. A first buffer layer is formed in the well over the first UBM layer and the contact pad. A second UBM layer is formed over the first UBM layer and first buffer layer. A third UBM layer is formed over the second UBM layer. A bump is formed over the third UBM layer. The first buffer layer reduces stress on the bump and contact pad. A second buffer layer can be formed between the second and third UBM layers.

Abstract: A circuit module including: a wiring substrate having a shape elongated in one direction; a semiconductor chip mounted on the wiring substrate; and a molding material that molds the semiconductor chip, wherein end faces of the molding material that extend along a lengthwise direction of the wiring substrate and intersect with a lateral direction of the wiring substrate are formed by dicing performed along end faces of a partial region of the wiring substrate.

Abstract: An apparatus for a stacked silicon interconnect technology (SSIT) product comprises an interposer die, a plurality of integrated circuit dies, a plurality of active components forming an active connection between the integrated circuit dies and the interposer die, and a plurality of dummy components at the interposer die, the dummy components not forming an active connection between the integrated circuit dies and the interposer die. At least a subset of the dummy components forms a pattern, and the pattern comprises an identifier for the interposer die.

Abstract: A semiconductor device includes a substrate (102) with a cavity (112) formed therein for receiving a semiconductor die. In examples, the semiconductor die is a controller die (114). The controller die (114) may be electrically connected to the substrate (102) with electrical traces (120) which may be formed for example by printing. After the controller die (114) is electrically connected to the substrate (102), one or more memory die (150) may be affixed to the substrate (102), over the cavity (112) and controller die (114).

Abstract: Redistribution layers for microfeature workpieces, and associated systems and methods are disclosed. One method for processing a microfeature workpiece system includes positioning a pre-formed redistribution layer as a unit proximate to and spaced apart from a microfeature workpiece having an operable microfeature device. The method can further include attaching the redistribution layer to the microfeature workpiece and electrically coupling the redistribution layer to the operable microfeature device.

Abstract: A semiconductor ESD protection device comprising a vertical arrangement of alternating conductivity type layers, wherein the layers are arranged as silicon controlled rectifier and wherein the silicon controlled rectifier is arranged as vertical device and having top and bottom opposing contacts.

Abstract: In one embodiment, a semiconductor device includes a first semiconductor chip and a second semiconductor chip stacked on the first semiconductor chip. The first and second semiconductor chips are electrically connected via first bump connection parts. Stopper projections and bonding projections are provided at least one of the first and second semiconductor chips. The stopper projections are in contact with the other of the first and second semiconductor chips in an unbonded state. The bonding projections are bonded to the first and second semiconductor chips.

Abstract: A new Power DFN and Power QFN package architecture that accommodates Bump-chip die and other components in cavities on the bottom-side of the matrix leadframe, and the technique is also applicable to laminated substrate packages like the BGA and LGA. The package is especially suited for high speed power compound semiconductor devices like GaN and SiC. The package enables single and multiple power switch configurations, and well controlled paralleling of high speed power die switches. It enables co-packaging of associated components like cascoded switchs, gate drivers, isolators and protection devices, which must be tightly coupled at high switching speeds. The architecture accommodates components on the top-side of the leadframe as well allowing for multi-chip functions with extremely low interconnect inductance and resistance, and higher circuit and power densities.

Abstract: Some embodiments include apparatus, systems, and methods comprising semiconductor dice arranged in a stack, a number of connections configured to provide communication among the dice, at least a portion of the connections going through at least one of the dice, and a module configured to check for defects in the connections and to repair defects the connections.

Abstract: A first substrate with a penetration electrode formed thereon is stacked on a second substrate with a protruding electrode formed thereon. The penetration electrode has a recessed portion. The substrates are stacked with the protruding electrode entered in the recessed portion. A distal width of the protruding electrode is smaller than an opening width of the recessed portion.

Abstract: A semiconductor package and a method of forming a semiconductor package with one or more dies over an interposer die are provided. By forming a first redistribution structure over the interposer die with TSVs, the die(s) bonded to the interposer die can have edge(s) beyond the boundary of the interposer die. In addition, a second redistribution structure may be formed on the opposite surface of the interposer die from the redistribution structure. The second redistribution structure enables reconfiguration and fan-out of bonding structures for external connectors of the interposer die.

Abstract: A semiconductor stacked package may include a substrate formed with a plurality of coupling pads, a plurality of semiconductor chips stacked on the substrate. The semiconductor stacked package may also include first circuit units disposed on each of the semiconductor chips, and electrically connected with the coupling pads by the medium of bonding pads. The semiconductor stacked package may include second circuit units disposed on each of the semiconductor chips and electrically disconnected with the coupling pads, connection pads disposed on each of the semiconductor chips and corresponding to the second circuit units, and blocking circuits coupled between the second circuit units and the connection pads. The semiconductor stacked package may also include bonding wires electrically connecting the bonding pads and the coupling pads.

Abstract: Embodiments of the present disclosure provide a package on package arrangement comprising a bottom package and a second package. The first package includes a substrate layer including (i) a top side and (ii) a bottom side that is opposite to the top side. Further, the top side defines a substantially flat surface. The first package also includes a die coupled to the bottom side of the substrate layer. The second package includes a plurality of rows of solder balls, and the second package is attached to the substantially flat surface of the substrate layer via the plurality of rows of solder balls.

Abstract: A method of manufacture of an enhanced capacity memory system includes: providing a dual in-line memory module carrier having a memory module and an integrated memory buffer coupled to the memory module; coupling a memory expansion board, having a supplementary memory module, to the dual in-line memory module carrier including attaching a bridge transposer; and providing a system interface connector coupled to the integrated memory buffer and the bridge transposer for controlling the memory module, the supplementary memory module, or a combination thereof.

Abstract: A Dual-Side Illumination (DSI) image sensor chip includes a first image sensor chip configured to sense light from a first direction, and a second image sensor chip aligned to, and bonded to, the first image sensor chip. The second image sensor chip is configured to sense light from a second direction opposite the first direction.

Abstract: An integrated electronic device, delimited by a first surface and by a second surface and including: a body made of semiconductor material, formed inside which is at least one optoelectronic component chosen between a detector and an emitter; and an optical path which is at least in part of a guided type and extends between the first surface and the second surface, the optical path traversing the body. The optoelectronic component is optically coupled, through the optical path, to a first portion of free space and a second portion of free space, which are arranged, respectively, above and underneath the first and second surfaces.

Abstract: Provided is a semiconductor chip that is flip-chip mounted where an inner chip pad array and an outer chip pad array, which are arranged on an inner side and an outer side of IO cells in a staggered manner, are arranged to be spaced away from each other by a predetermined gap or greater. The predetermined gap represents a gap where one via can be arranged between an inner substrate pad array and an outer substrate pad array on a substrate which faces and is connected to the inner chip pad array and the outer chip pad array. In addition, the predetermined gap represents a gap where a plated wire is interconnected and then a resist opening for etch-back can be formed. Even in a case where a space for forming an interconnection is not present between outer substrate pad arrays, interconnection characteristics of the substrate are improved.

Abstract: A multi-chip package is provided. The multi-chip package includes a plurality of chips including at least one bad chip and at least one good chip that are stacked and a plurality of through electrodes each penetrating the chips. A logic circuit included in the at least one bad chip is isolated from each of the plurality of through electrodes.

Abstract: A package includes a first molding material, a first device die molded in the molding material, a Through Via (TV) penetrating through the first molding material, and a redistribution line over the first molding material. The redistribution line is electrically connected to the TV. A second device die is over and bonded to the first device die through flip-chip bonding. A second molding material molds the second device die therein.

Abstract: The invention relates to a power semiconductor device and a preparation method, particularly relates to preparation of stacked dual-chip packaging structure of MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) using flip chip technology with two interconnecting plates. The first chip is flipped and attached on the base such that the first chip is overlapped with the third pin; the back metal layer of the first chip is connected to the bonding strip of the first pin through a first interconnecting plate; the second chip is flipped and attached on a main plate portion of the first interconnecting plate such that the second chip is overlapped with the fourth pin; and the back metal layer of the second chip is connected to the bonding strip of the second pin through the second interconnecting plate.

Abstract: A semiconductor chip 109 is mounted on a substrate 100, first wire group 120 and a second wire group 118 having a wire length shorter than the first wire group are provided so as to connect the substrate 100 and the semiconductor chip 109 to each other, and a sealing resin 307 is injected from the first wire group 120 toward the second wire group 118 so as to form a sealer 401 covering the semiconductor chip 109, the first wire group 120, and the second wire group 118.

Abstract: The invention provides a semiconductor package and a method for fabricating a base for a semiconductor package. The semiconductor package includes a conductive trace embedded in a base. A semiconductor device is mounted on the conductive trace via a conductive structure.

Abstract: A package structure includes a plurality of die carriers identical to each other. The respective features in each of the plurality of die carriers vertically overlap corresponding features in other ones of the plurality of die carriers. Each of the plurality of die carriers includes a plurality of through-substrate vias (TSVs) including a plurality of data buses. The plurality of die carriers is stacked and electrically connected to each other through the plurality of TSVs. The package structure further includes a plurality of device dies. Each of the plurality of device dies is bonded to one of the plurality of die carriers. Each of the plurality of data buses is configured to dedicate to data transmission of one of the plurality of device dies.

Abstract: A semiconductor device and a method of fabricating the same includes providing a first semiconductor chip which has first connection terminals, providing a second semiconductor chip which comprises top and bottom surfaces facing each other and has second connection terminals and a film-type first underfill material formed on the bottom surface thereof, bonding the first semiconductor chip to a mounting substrate by using the first connection terminals, bonding the first semiconductor chip and the second semiconductor chip by using the first underfill material, and forming a second underfill material which fills a space between the mounting substrate and the first semiconductor chip and covers side surfaces of the first semiconductor chip and at least part of side surfaces of the second semiconductor chip.

Abstract: A substrate for a semiconductor package includes a substrate body having a first surface and a second surface which faces away from the first surface, and formed with at least one bump land on the first surface, and a dam formed and projected over an edge of the first surface of the substrate body, and having an underfill member discharge unit.

Abstract: Embodiments of the present disclosure provide a method comprising forming an electrically conductive structure on a surface of a semiconductor die, attaching the semiconductor die to a substrate, forming a molding compound to encapsulate the semiconductor die, forming an opening in the molding compound, the opening to at least partially expose the electrically conductive structure, and electrically coupling a passive component to the electrically conductive structure through the opening in the molding compound. Other embodiments may be described and/or claimed.

Abstract: An embodiment of a circuit module includes module nodes, a first submodule, a second submodule, and a conductive structure. The first submodule has a first submodule node, and the second submodule is disposed over the first submodule and has a second submodule node. The conductive structure couples the first submodule node to one of the module nodes and couples the second submodule node to one of the module nodes. Another embodiment of a circuit module includes module nodes, a first submodule, a second submodule, and a conductive structure. The first submodule has first submodule nodes, and the second submodule is disposed over the first submodule and has second submodule nodes. The conductive structure couples one of the first and second submodule nodes to one of the module nodes and couples one of the first submodule nodes to one of the second submodule nodes.

Abstract: Provided is a semiconductor package that may prevent deformation of stacked semiconductor chips and minimize a semiconductor package size. The semiconductor package includes a package base substrate, a lower chip stacked on the package base substrate, an upper chip stacked on the lower chip, and a first die attach film (DAF) attached to a bottom surface of the upper chip to cover at least a portion of the lower chip. The first DAF may be a multi-layer film including a first attaching layer contacting the bottom surface of the upper chip and a second attaching layer attached to a bottom of the first attaching layer to cover at least a portion of a side surface of the lower chip.

Abstract: A semiconductor device comprises: a semiconductor package having a top surface, a bottom surface, and a through hole provided from the top surface to the bottom surface; and an electrode inserted into the through hole of the semiconductor package. The semiconductor package includes: an insulating substrate; a semiconductor chip on the insulating substrate; an electrode pattern on the insulating substrate and connected to the semiconductor chip; a resin sealing the insulating substrate, the semiconductor chip, and the electrode pattern; and an electrode section on an inner wall of the through hole and connected to the electrode pattern. The through hole penetrates the insulating substrate and the resin. The electrode inserted into the through hole is connected to the electrode section inside the semiconductor package.

Abstract: According to the embodiment, a semiconductor storage device includes an organic substrate, a semiconductor memory chip, a lead frame, and a resin mold section. The lead frame includes an adhering portion. The organic substrate is singulated to have a shape in which a portion in which the organic substrate does not overlap with the placing portion is larger than a portion in which the organic substrate overlaps with the placing portion, in plan view. The lead frame further includes a first extending portion in the adhering portion that extends to a surface different from a surface of the resin mold section on a side of an insertion direction.

Abstract: An electronic device is obtained in such a way that a MEMS substrate having a MEMS element mounted thereon and a CMOS substrate are bonded together at bonding surfaces and with a bonding material M having fluidity, wherein the MEMS substrate has a bonding projection part provided to project from a substrate main body and having the bonding surface and a gap formation part disposed between the bonding projection part and the MEMS element, and the gap formation part is supported by the bonding projection part via a plurality of support pieces extending from the bonding projection part and forms reception gaps, which are capable of receiving the bonding material M extruded from the bonding surface to the side of the MEMS element, between the wall surface thereof and the bonding projection part.

Abstract: Interconnect structures for stacked dies, including penetrating structures for through-silicon vias, and associated systems and methods are disclosed. A system in accordance with a particular embodiment includes a first semiconductor substrate having a first substrate material, and a penetrating structure carried by the first semiconductor substrate. The system further includes a second semiconductor substrate having a second substrate material with a preformed recess. The penetrating structure of the first semiconductor substrate is received in the recess of the second semiconductor substrate and is mechanically engaged with the recess and secured to the second semiconductor substrate.

Abstract: A semiconductor device comprises a substrate, pluralities of first and second external electrodes formed in two end portions of one surface of the substrate, a first semiconductor chip mounted on the other surface of the substrate, the first semiconductor chip having an electrode pad row formed in one end portion of one surface of the first semiconductor chip and electrically connected to the first external electrodes, the first semiconductor chip being disposed so that the one end portion of the first semiconductor chip is positioned on an end portion on which the first external electrodes of the substrate are formed, and a second semiconductor chip mounted on the first semiconductor chip, the second semiconductor chip having an electrode pad row formed in one end portion of one surface of the second semiconductor chip and electrically connected to the second external electrode, the second semiconductor chip being disposed so that the one end portion of the second semiconductor chip is positioned on an end p

Abstract: In the solid-state imaging device, first and second substrates are electrically connected to each other via connectors electrically connecting the first and second substrates. A photoelectric conversion element is disposed in the first substrate. A read circuit is disposed in the second substrate and reads a signal generated by the photoelectric conversion element and transmitted via the connector. In a signal processing circuit including elements or circuits performing signal processing on the read signal, some of the elements or circuits are disposed in the first substrate, the remaining elements or circuits are disposed in the second substrate, and the elements or circuits disposed in the first and second substrates are electrically connected to each other via the connector.

Abstract: A backside illuminated image sensor comprises a photodiode and a first transistor located in a first chip, wherein the first transistor is electrically coupled to the photodiode. The backside illuminated image sensor further comprises a second transistor formed in a second chip and a plurality of logic circuits formed in a third chip, wherein the second chip is stacked on the first chip and the third chip is stacked on the second chip. The logic circuit, the second transistor and the first transistor are coupled to each other through a plurality of boding pads and through vias.

Abstract: A method is provided for forming a die stack. The method includes forming a plurality of through-wafer vias and a first plurality of alignment features in a first die. A second plurality of alignment features is formed in a second die, and the first die is stacked on the second die such that the first plurality of alignment features engage the second plurality of alignment features. A method of manufacturing a die stack is also provided that includes forming a plurality of through-wafer vias on a first die, forming a plurality of recesses on a first die, and forming a plurality of protrusions on a second die. A die stack and a system are also provided.

Abstract: An embodiment of the disclosure is a structure comprising an interposer. The interposer has a test structure extending along a periphery of the interposer, and at least a portion of the test structure is in a first redistribution element. The first redistribution element is on a first surface of a substrate of the interposer. The test structure is intermediate and electrically coupled to at least two probe pads.

Abstract: A stacked die package includes a package substrate, a first die mounted on the package substrate and electrically connected to the package substrate, a second die electrically connected to the package substrate, and an interposer mounted on the package substrate and including a plurality of vertical electrical connection means electrically connecting the package substrate to the second die. At least part of the first die is disposed between the second die and the package substrate in a vertical direction.

Abstract: A semiconductor device of an embodiment is provided with a normally-off transistor having a first source connected to a source terminal, a first drain, and a first gate connected to a gate terminal and a normally-on transistor having a second source connected to the first drain, a second drain connected to a drain terminal, and a second gate connected to the source terminal. A withstand voltage between the first source and the first drain when the normally-off transistor is turned off is lower than a withstand voltage between the second source and the second gate of the normally-on transistor.

Abstract: A method for fabricating a flip-chip semiconductor package. The method comprises processing a semiconductor device, for example a semiconductor chip and processing a device carrier, for example a substrate. The semiconductor device comprises bump structures formed on a surface thereof. The substrate comprises bond pads formed on a surface thereof. Processing of the semiconductor chip results in heating of the semiconductor chip to a chip process temperature. The chip process temperature melts solder portions on the bump structures Processing of the substrate results in heating of the substrate to a substrate process temperature. The method comprises spatially aligning the semiconductor chip in relation to the substrate to correspondingly align the bump structures in relation to the bump pads. The semiconductor chip is then displaced towards the substrate for abutting the bump structures of the semiconductor chip with the bond pads of the substrate to thereby form bonds therebetween.

Abstract: A wiring member includes a first leg portion, a second leg portion, a third leg portion, a first connecting wall and a second connecting wall. The first leg portion is electrically connected to a first conductive portion. The second leg portion is electrically connected to a second conductive portion. The third leg portion is electrically connected to a third conductive portion. The first connecting wall connects the first leg portion and the second leg portion. The second connecting wall connects the second leg portion and the third leg portion. The first leg portion, the second leg portion, and the third leg portion are non-linearly arranged.

Abstract: In an embodiment, there is provided a packaging arrangement comprising a substrate; a multi-memory die coupled to the substrate, wherein the multi-memory die comprises multiple individual memory dies, and each of the multiple individual memory dies is defined as an individual memory die within a wafer of semiconductor material during production of memory dies, and the multi-memory die is created by singulating the wafer of semiconductor material into memory dies, where at least one of the memory dies is the multi-memory die that includes the multiple individual memory dies that are still physically connected together; and a semiconductor die coupled to the multi-memory die and the substrate, wherein the semiconductor die is configured as a system on a chip, wherein at least one of the multi-memory die and the semiconductor die is attached to the substrate.

Abstract: A conductive line of a semiconductor device includes a conductive layer disposed on a semiconductor substrate. A thickness of the conductive layer is substantially larger than 10000 angstrom (?), and at least a side of the conductive layer has at least two different values of curvature.

Abstract: A semiconductor device includes a first semiconductor package including a first mold part, a second semiconductor package including a second mold part, a connecting pattern configured to electrically connect the first and second semiconductor packages to each other, and a molding pattern between the first and second semiconductor packages. The molding pattern extends to cover at least a portion of a sidewall of only the second semiconductor package.

Abstract: Aspects of the disclosure provide a circuit that includes a printed circuit board (PCB) substrate formed with an opening portion that is dimensioned to accommodate an integrated circuit (IC) package. When the IC package is disposed in the opening portion and is electrically coupled to the PCB substrate for PCB assembling, a thickness of the assembled PCB is less than a thickness sum of the IC package and the PCB substrate.

Abstract: According to example embodiments, a semiconductor package includes: a lower molding element; a lower semiconductor chip in the lower molding element and having lower chip pads on an upper surface and at an areas close to first and second sides of the lower molding element; conductive pillars surrounding the lower semiconductor chip and passing through the lower molding element; an upper semiconductor chip on the upper surface of the lower molding element and lower semiconductor chip, the upper semiconductor chip having upper chip pads on a top surface and at areas close to third and the fourth sides of the upper semiconductor chip, and a connecting structure on the lower molding element and the upper semiconductor chip and electrically connecting each of the lower chip pads and upper chip pads to a corresponding conductive pillar. The upper semiconductor chip is substantially orthogonal to the lower semiconductor chip.