Ball Or Nail Head Type Contact, Lead, Or Bond Patents (Class 257/780)
  • Patent number: 10916510
    Abstract: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a semiconductor substrate, a stress-relieving structure including a conductive frame positioned above the semiconductor substrate and a plurality of insulating pillars positioned within the conductive frame, and a conductive structure including a supporting portion positioned above the stress-relieving structure, a conductive portion positioned adjacent to the supporting portion, and a plurality of spacers attached to two sides of the conductive portion. A width of the conductive frame is equal to a width of a bottom of the conductive portion.
    Type: Grant
    Filed: November 19, 2019
    Date of Patent: February 9, 2021
    Assignee: Nanya Technology Corporation
    Inventor: Tse-Yao Huang
  • Patent number: 10916497
    Abstract: A semiconductor device may include a multi-level wiring structure comprising a first-level wiring layer, a second-level wiring layer and an insulating layer between the first-level wiring layer and the second-level wiring layer. The device may also include a bond pad, a first wiring extending from the bond pad, and a second wiring overlapping at least in part with the first wiring through the insulating layer to be capacitively coupled to the first wiring. The first wiring and the second wiring may each be formed respectively as the first-level wiring layer and the second-level wiring layer. The device may also include a protection circuit configured to be DC coupled to the second wiring. The first-level wiring layer may include a redistribution layer (RDL).
    Type: Grant
    Filed: September 27, 2018
    Date of Patent: February 9, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Takashi Ishihara, Wataru Nobehara
  • Patent number: 10910305
    Abstract: Embodiments of the invention include a microelectronic device that includes a substrate having transistor layers and interconnect layers including conductive layers to form connections to transistor layers. A capacitive bump is disposed on the interconnect layers. The capacitive bump includes a first electrode, a dielectric layer, and a second electrode. In another example, an inductive bump is disposed on the interconnect layers. The inductive bump includes a conductor and a magnetic layer that surrounds the conductor.
    Type: Grant
    Filed: December 30, 2016
    Date of Patent: February 2, 2021
    Assignee: Intel Corporation
    Inventors: Telesphor Kamgaing, Georgios C. Dogiamis, Sasha N. Oster
  • Patent number: 10910331
    Abstract: A semiconductor device manufacturing method including preparing a semiconductor substrate including an electrode; forming a wire connected to the electrode; forming a first insulating film including a first opening that partially exposes the wire; forming a base portion that is connected to a portion of the wire exposed via the first opening, and that includes a conductor including a recess corresponding to the first opening; forming a solder film on a surface of the base portion; and fusing solder included in the solder film by a first heat treatment, and filling the recess with the fused solder.
    Type: Grant
    Filed: November 6, 2018
    Date of Patent: February 2, 2021
    Assignee: LAPIS SEMICONDUCTOR CO., LTD.
    Inventor: Masanori Shindo
  • Patent number: 10896869
    Abstract: A method for forming packaged electronic devices includes providing a substrate having pads connected by conductive pad linking portions and semiconductor devices attached to the pads in different orientations. A second substrate is provided having conductive connectors each with a plate portion, a conductive member extending from a side segment of the plate portion, and a connective portion extending from the conductive member distal to the plate portion. The second substrate further has conductive linking portions physically connecting adjoining plate portions together. Each plate portion is attached to one of the semiconductor devices to provide a subassembly. The conductive linking portions are configured to maintain the adjoining plate portions in substantial alignment with the semiconductor devices and to maintain the connective portions is a desired alignment during the plate portion attachment step.
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: January 19, 2021
    Assignee: Amkor Technology Singapore Holding Pte. Ltd.
    Inventors: Siang Miang Yeo, Mohd Hasrul Bin Zulkifli
  • Patent number: 10840179
    Abstract: An electronic device comprises: a molybdenum layer; a bond pad formed on the molybdenum layer, the bond pad comprising aluminum; and a wire bonded to the bond pad, the wire comprising gold.
    Type: Grant
    Filed: February 19, 2018
    Date of Patent: November 17, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Ricky Alan Jackson, Ting-Ta Yen, Brian E. Goodlin
  • Patent number: 10818610
    Abstract: There are provided an adhesive film for a semiconductor including: a conductive layer containing at least one metal selected from the group consisting of copper, nickel, cobalt, iron, stainless steel (SUS), and aluminum, and having a thickness of 0.05 ?m or more; and an adhesive layer formed on at least one surface of the conductive layer and including a (meth)acrylate-based resin, a curing agent, and an epoxy resin, and a semiconductor device including the above-mentioned adhesive film.
    Type: Grant
    Filed: November 15, 2017
    Date of Patent: October 27, 2020
    Assignee: LG CHEM, LTD.
    Inventors: Hee Jung Kim, Nu Ri Na, Young Kook Kim, Kwang Joo Lee
  • Patent number: 10809048
    Abstract: Probe systems and methods for calibrating capacitive height sensing measurements. A probe system includes a probe assembly with a probe support body that supports a capacitive displacement sensor that terminates in a sensing tip relative to a substrate and that is configured to generate an uncalibrated capacitive height measurement. A method of utilizing the probe system to generate a calibrated capacitive height measurement includes receiving a height calibration structure architecture; calculating a layer impedance magnitude of each substrate layer of the height calibration structure; and calculating a total layer impedance magnitude of the height calibration structure. The method further includes measuring a measured impedance magnitude and calculating the calibrated capacitive height measurement.
    Type: Grant
    Filed: December 30, 2019
    Date of Patent: October 20, 2020
    Assignee: FormFactor Beaverton, Inc.
    Inventors: Kazuki Negishi, Joseph George Frankel, Eric Robert Christenson
  • Patent number: 10811377
    Abstract: A package structure is provided. The package structure includes a first bump structure formed over a substrate, a solder joint formed over the first bump structure and a second bump structure formed over the solder joint. The first bump structure includes a first pillar layer formed over the substrate and a first barrier layer formed over the first pillar layer. The first barrier layer has a first protruding portion which extends away from a sidewall surface of the first pillar layer, and a distance between the sidewall surface of the first pillar layer and a sidewall surface of the first barrier layer is in a range from about 0.5 ?m to about 3 ?m. The second bump structure includes a second barrier layer formed over the solder joint and a second pillar layer formed over the second barrier layer, wherein the second barrier layer has a second protruding portion which extends away from a sidewall surface of the second pillar layer.
    Type: Grant
    Filed: November 19, 2018
    Date of Patent: October 20, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Cheng-Hung Chen, Yu-Nu Hsu, Chun-Chen Liu, Heng-Chi Huang, Chien-Chen Li, Shih-Yen Chen, Cheng-Nan Hsieh, Kuo-Chio Liu, Chen-Shien Chen, Chin-Yu Ku, Te-Hsun Pang, Yuan-Feng Wu, Sen-Chi Chiang
  • Patent number: 10667399
    Abstract: A printed circuit board (PCB) carrier including a multi-layer structure including a plurality of conductive layers and a plurality of insulating layers respectively spaced between the plurality of conductive layers, the multi-layer structure having a footprint corresponding to a large size component of the PCB, and a pocket formed in the multi-layer structure, the pocket configured to receive a discrete component of a size smaller than the large size component.
    Type: Grant
    Filed: November 27, 2018
    Date of Patent: May 26, 2020
    Assignee: NOKIA SOLUTIONS AND NETWORKS OY
    Inventors: Alex Chan, Paul Brown
  • Patent number: 10468352
    Abstract: Semiconductor packages with embedded bridge interconnects, and related assemblies and methods, are disclosed herein. In some embodiments, a semiconductor package may have a first side and a second side, and may include a bridge interconnect, embedded in a build-up material, having a first side with a plurality of conductive pads. The semiconductor package may also include a via having a first end that is narrower than a second end. The bridge interconnect and via may be arranged so that the first side of the semiconductor package is closer to the first side of the bridge interconnect than to the second side of the bridge interconnect, and so that the first side of the semiconductor package is closer to the first end of the via than to the second end of the via. Other embodiments may be disclosed and/or claimed.
    Type: Grant
    Filed: September 19, 2014
    Date of Patent: November 5, 2019
    Assignee: Intel Corporation
    Inventor: Kyu-Oh Lee
  • Patent number: 10373924
    Abstract: A method and device for input/output connections is provided. Devices and methods for connection structure are shown with improved mechanical properties such as hardness and abrasion resistance. Land grid array structures are provided that are less expensive to manufacture due to reductions in material cost such as gold. Ball grid array structures are provided with improved resistance to corrosion during fabrication. Ball grid array structures are also provided with improved mechanical properties resulting in improved shock testing results.
    Type: Grant
    Filed: May 1, 2018
    Date of Patent: August 6, 2019
    Assignee: INTEL CORPORATION
    Inventors: Munehiro Toyama, Siew Fong Tai, Kian Sin Sim, Charavanakumara Gurumurthy, Tamil Selvy Selvamuniandy
  • Patent number: 10340226
    Abstract: A system and method for preventing cracks is provided. An embodiment comprises placing crack stoppers into a connection between a semiconductor die and a substrate. The crack stoppers may be in the shape of hollow or solid cylinders and may be placed so as to prevent any cracks from propagating through the crack stoppers.
    Type: Grant
    Filed: January 4, 2016
    Date of Patent: July 2, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Da-Yuan Shih
  • Patent number: 10312204
    Abstract: Presented herein are an interconnect structure and method for forming the same. The interconnect structure includes a contact pad disposed over a substrate and a connector disposed over the substrate and spaced apart from the contact pad. A passivation layer is disposed over the contact pad and over connector, the passivation layer having a contact pad opening, a connector opening, and a mounting pad opening. A post passivation layer including a trace and a mounting pad is disposed over the passivation layer. The trace may be disposed in the contact pad opening and contacting the mounting pad, and further disposed in the connector opening and contacting the connector. The mounting pad may be disposed in the mounting pad opening and contacting the opening. The mounting pad may be separated from the trace by a trace gap, which may optionally be at least 10 ?m.
    Type: Grant
    Filed: August 6, 2018
    Date of Patent: June 4, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsien-Wei Chen, Hao-Yi Tsai, Mirng-Ji Lii, Chen-Hua Yu, Tsung-Yuan Yu
  • Patent number: 10304867
    Abstract: A semiconductor device manufacturing technique which allows reduction of semiconductor chip size. First, a pad and other wires are formed over an insulating film. A surface protective film is formed over the insulating film including the pad and wires, and an opening is made in the surface protective film. The opening lies over the pad and exposes a surface of the pad. A bump electrode is formed over the surface protective film including the opening. Here, the pad is smaller than the bump electrode. Consequently, the wires are arranged just beneath the bump electrode in the same layer as the pad 10. In other words, the wires are arranged in space which becomes available because the pad is small enough.
    Type: Grant
    Filed: February 19, 2018
    Date of Patent: May 28, 2019
    Assignee: Renesas Electronics Corporation
    Inventors: Akihiko Yoshioka, Shinya Suzuki
  • Patent number: 10297550
    Abstract: A device includes an interposer, which includes a substrate having a top surface. An interconnect structure is formed over the top surface of the substrate, wherein the interconnect structure includes at least one dielectric layer, and metal features in the at least one dielectric layer. A plurality of through-substrate vias (TSVs) is in the substrate and electrically coupled to the interconnect structure. A first die is over and bonded onto the interposer. A second die is bonded onto the interposer, wherein the second die is under the interconnect structure.
    Type: Grant
    Filed: May 5, 2010
    Date of Patent: May 21, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsien-Pin Hu, Chen-Hua Yu, Ming-Fa Chen, Jing-Cheng Lin, Jiun Ren Lai, Yung-Chi Lin
  • Patent number: 10269851
    Abstract: Methods and apparatus for integrating a CMOS image sensor and an image signal processor (ISP) together using an interposer to form a system in package device module are disclosed. The device module may comprise an interposer with a substrate. An interposer contact is formed within the substrate. A sensor device may be bonded to a surface of the interposer, wherein a sensor contact is bonded to a first end of the interposer contact. An ISP may be connected to the interposer, by bonding an ISP contact in the ISP to a second end of the interposer contact. An underfill layer may fill a gap between the interposer and the ISP. A printed circuit board (PCB) may further be connected to the interposer by way of a solder ball connected to another interposer contact. A thermal interface material may be in contact with the ISP and the PCB.
    Type: Grant
    Filed: September 14, 2015
    Date of Patent: April 23, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuo-Chung Yee, Chun Hui Yu
  • Patent number: 10236248
    Abstract: The manufacturing method of a semiconductor device can improve the mechanical strength of a pad more than before, and suppress the occurrence of a crack. The manufacturing method of a semiconductor device includes: forming a first pad constituted by a first metal layer; forming an insulating layer on the first pad; providing an opening portion in the insulating layer by removing the insulating layer on at least a partial region of the first pad; forming a second pad constituted by a second metal layer in the opening portion of the insulating layer so as to have a film thickness that is smaller than the film thickness of the insulating layer; and forming a third pad constituted by a third metal layer on the second pad.
    Type: Grant
    Filed: May 24, 2017
    Date of Patent: March 19, 2019
    Assignee: SEIKO EPSON CORPORATION
    Inventors: Takahiko Yoshizawa, Kunio Watanabe, Tatsuki Shirasawa, Takashi Sakuda
  • Patent number: 10224470
    Abstract: A light emitting device includes a semiconductor chip including a p-type semiconductor layer and an n-type semiconductor layer, the semiconductor chip being adapted to emit light between the p-type semiconductor layer and the n-type semiconductor layer; a p-side pad electrode disposed on an upper surface side of the semiconductor chip and over the p-type semiconductor layer; an n-side pad electrode disposed on an upper surface side of the semiconductor chip and over the n-type semiconductor layer; a resin layer disposed to cover the upper surface of the semiconductor chip; a p-side connection electrode and an n-side connection electrode disposed at an outer surface of the resin layer and positioned on the upper surface side of the semiconductor chip; and a metal wire disposed in the resin. The metal wire is adapted to make connection at least one of between the p-side pad electrode and the p-side connection electrode, and between the n-side pad electrode and the n-side connection electrode.
    Type: Grant
    Filed: August 25, 2016
    Date of Patent: March 5, 2019
    Assignee: NICHIA CORPORATION
    Inventors: Akinori Yoneda, Akiyoshi Kinouchi, Hisashi Kasai, Yoshiyuki Aihara, Hirokazu Sasa, Shinji Nakamura
  • Patent number: 10206275
    Abstract: A control unit has a substrate with an electrically conductive structure, an integrated circuit device, which is installed on the substrate in an electrically conductive manner, and a sacrificial structure on the substrate. The sacrificial structure is configured to be irreversibly destroyed if the integrated circuit device is removed from the substrate. The electrically conductive structure has at least one conducting track applied to the substrate. The sacrificial structure is formed by a segment of the conducting track. An electrically insulating connecting layer that connects the integrated circuit device, the substrate, and the segment of the conducting track is formed. The sacrificial structure can be destroyed by the connecting layer when the integrated circuit device is removed.
    Type: Grant
    Filed: December 11, 2012
    Date of Patent: February 12, 2019
    Assignee: Continental Automotive GmbH
    Inventors: Jan Keller, Thomas Riepl
  • Patent number: 10177104
    Abstract: Some embodiments relate to a semiconductor device package, which includes a substrate with a contact pad. A non-solder ball is coupled to the contact pad at a contact pad interface surface. A layer of solder is disposed over an outer surface of the non-solder ball, and has an inner surface and an outer surface which are generally concentric with the outer surface of the non-solder ball. An intermediate layer separates the non-solder ball and the layer of solder. The intermediate layer is distinct in composition from both the non-solder ball and the layer of solder. Sidewalls of the layer of solder are curved or sphere-like and terminate at a planar surface, which is disposed at a maximum height of the layer of solder as measured from the contact pad interface surface.
    Type: Grant
    Filed: June 23, 2017
    Date of Patent: January 8, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chen-Hua Yu, Chung-Shi Liu, Ming-Da Cheng, Mirng-Ji Lii, Meng-Tse Chen, Wei-Hung Lin
  • Patent number: 10163838
    Abstract: A semiconductor device includes a semiconductor chip, pads provided on the semiconductor chip, and insulating patterns provided on the semiconductor chip. The insulating patterns having openings exposing the pads, and conductive patterns are provided in the openings and coupled to the pads. When viewed in a plan view, two opposite ends of the pads are spaced apart from the conductive patterns and two opposite ends of the conductive patterns are spaced apart from the pads. Additionally, when viewed in a plan view, the conductive patterns include a first conductive pattern whose length is parallel to a first direction and a second conductive pattern whose length is parallel to a second direction. The first and second directions are oblique to each other.
    Type: Grant
    Filed: April 27, 2017
    Date of Patent: December 25, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Soojeoung Park, Bona Baek, Yongho Kim
  • Patent number: 10157847
    Abstract: Semiconductor packages with embedded bridge interconnects, and related assemblies and methods, are disclosed herein. In some embodiments, a semiconductor package may have a first side and a second side, and may include a bridge interconnect, embedded in a build-up material, having a first side with a plurality of conductive pads. The semiconductor package may also include a via having a first end that is narrower than a second end. The bridge interconnect and via may be arranged so that the first side of the semiconductor package is closer to the first side of the bridge interconnect than to the second side of the bridge interconnect, and so that the first side of the semiconductor package is closer to the first end of the via than to the second end of the via. Other embodiments may be disclosed and/or claimed.
    Type: Grant
    Filed: September 19, 2014
    Date of Patent: December 18, 2018
    Assignee: Intel Corporation
    Inventor: Kyu-Oh Lee
  • Patent number: 10147671
    Abstract: A semiconductor device includes: a semiconductor chip having an electrode on one surface; a first conductive member disposed on one surface side of the semiconductor chip; a metal member having a base member and a membrane and disposed between the semiconductor chip and the first conductive member; a first solder disposed between the electrode of the semiconductor chip and the metal member; and a second solder disposed between the metal member and the first conductive member. The membrane has a metal thin film arranged on the surface of the base member and an uneven oxide film. The uneven oxide film is arranged on the metal thin film in at least a part of a connection region of a surface of the metal member, the connection region connecting a first connection region to which the first solder is connected and a second connection region to which the second solder is connected.
    Type: Grant
    Filed: December 4, 2015
    Date of Patent: December 4, 2018
    Assignee: DENSO CORPORATION
    Inventors: Eiji Hayashi, Wataru Kobayashi, Eiji Nomura, Kazuki Kouda
  • Patent number: 10134697
    Abstract: Various embodiments provide a semiconductor chip, wherein the semiconductor chip comprises a first contact area and a second contact area both formed at a frontside of the semiconductor chip; a passivation layer arranged at the frontside between the first contact area and the second contact area; and a contact stack formed over the frontside of the semiconductor chip and comprising a plurality of layers, wherein at least one layer of the plurality of layers is removed from the passivation layer and boundary regions of the contact areas being adjacent to the passivation layer and wherein at least one another layer of the plurality of different layer is present in the boundary region of the contact areas adjoining the passivation layer.
    Type: Grant
    Filed: January 13, 2016
    Date of Patent: November 20, 2018
    Assignee: Infineon Technologies AG
    Inventors: Dietrich Bonart, Ludger Borucki, Martina Debie, Bernhard Weidgans
  • Patent number: 10134647
    Abstract: An interconnect assembly includes a bond pad and an interconnect structure configured to electrically couple an electronic structure to the bond pad. The interconnect structure physically contacts areas of the bond pad that are located outside of a probe contact area that may have been damaged during testing. Insulating material covers the probe contact area and defines openings spaced apart from the probe contact area. The interconnect structure extends through the openings to contact the bond pad.
    Type: Grant
    Filed: April 3, 2017
    Date of Patent: November 20, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Owen R. Fay, Kyle K. Kirby, Luke G. England, Jaspreet S. Gandhi
  • Patent number: 10103038
    Abstract: Semiconductor devices having a semiconductor die electrically coupled to a redistribution structure and a molded material over the redistribution structure are disclosed herein, along with associated systems and methods. In one embodiment, a semiconductor device includes a semiconductor die attached to a first side of a substrate-free redistribution structure, and a plurality of conductive columns extending through a molded material disposed on the first side of the redistribution structure. The semiconductor device can also include a second redistribution structure on the molded material and electrically coupled to the conductive columns. A semiconductor device can be manufactured using a single carrier and requiring processing on only a single side of the semiconductor device.
    Type: Grant
    Filed: August 24, 2017
    Date of Patent: October 16, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Chan H. Yoo, John F. Kaeding, Ashok Pachamuthu, Mark E. Tuttle
  • Patent number: 10074617
    Abstract: A semiconductor device structure and method for forming the same are provided. The semiconductor device structure includes a substrate and a conductive pad formed on the substrate. The semiconductor device structure includes a protection layer formed over the conductive pad and a post-passivation interconnect (PPI) structure formed at least in the protection layer. The PPI structure is electrically connected to the conductive pad. The semiconductor device structure also includes a first moisture-resistant layer formed over the protection layer, and the protection layer and the first moisture-resistant layer are made of different materials. The semiconductor device structure further includes an under bump metallurgy (UBM) layer formed over the first moisture-resistant layer and connected to the PPI structure.
    Type: Grant
    Filed: December 12, 2016
    Date of Patent: September 11, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shin-Puu Jeng, Hsien-Wen Liu
  • Patent number: 10068843
    Abstract: In a semiconductor device, a first semiconductor die is mounted with its active surface oriented to a temporary carrier. An encapsulant is deposited over the first semiconductor die and temporary carrier. The temporary carrier is removed to expose a first side of the encapsulant and active surface of the first semiconductor die. A masking layer is formed over the active surface of the first semiconductor die. A first interconnect structure is formed over the first side of the encapsulant. The masking layer blocks formation of the first interconnect structure over the active surface of the first semiconductor die. The masking layer is removed to form a cavity over the active surface of the first semiconductor die. A second semiconductor die is mounted in the cavity. The second semiconductor die is electrically connected to the active surface of the first semiconductor die with a short signal path.
    Type: Grant
    Filed: December 24, 2012
    Date of Patent: September 4, 2018
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventor: Reza A. Pagaila
  • Patent number: 10050355
    Abstract: A conductive material that includes a metal component consisting of a first metal and a second metal having a melting point higher than that of the first metal, wherein the first metal is Sn or an alloy containing 70% by weight or more of Sn, and the second metal is a metal or alloy which forms an intermetallic compound having a melting point of 310° C. or higher with the first metal and has a lattice constant difference of 50% or greater between itself and the intermetallic compound generated at the circumference of the second metal.
    Type: Grant
    Filed: April 23, 2013
    Date of Patent: August 14, 2018
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Kosuke Nakano, Hidekiyo Takaoka
  • Patent number: 9966351
    Abstract: A method and device for input/output connections is provided. Devices and methods for connection structure are shown with improved mechanical properties such as hardness and abrasion resistance. Land grid array structures are provided that are less expensive to manufacture due to reductions in material cost such as gold. Ball grid array structures are provided with improved resistance to corrosion during fabrication. Ball grid array structures are also provided with improved mechanical properties resulting in improved shock testing results.
    Type: Grant
    Filed: August 24, 2016
    Date of Patent: May 8, 2018
    Assignee: INTEL CORPORATION
    Inventors: Munehiro Toyama, Siew Fong Tai, Kian Sin Sim, Charan K. Gurumurthy, Tamil Selvy Selvamuniandy
  • Patent number: 9929185
    Abstract: A semiconductor device manufacturing technique which allows reduction of semiconductor chip size. First, a pad and other wires are formed over an insulating film. A surface protective film is formed over the insulating film including the pad and wires, and an opening is made in the surface protective film. The opening lies over the pad and exposes a surface of the pad. A bump electrode is formed over the surface protective film including the opening. Here, the pad is smaller than the bump electrode. Consequently, the wires are arranged just beneath the bump electrode in the same layer as the pad 10. In other words, the wires are arranged in space which becomes available because the pad is small enough.
    Type: Grant
    Filed: December 1, 2016
    Date of Patent: March 27, 2018
    Assignee: Renesas Electronics Corporation
    Inventors: Akihiko Yoshioka, Shinya Suzuki
  • Patent number: 9837385
    Abstract: A package includes a chip, a wire, a mold layer and a redistribution layer. The chip includes a conductive pad. The wire is bonded to the conductive pad of the chip. The mold layer surrounds the first chip and the wire. The redistribution layer is disposed on the mold layer and contacts an exposed portion of the wire.
    Type: Grant
    Filed: March 16, 2017
    Date of Patent: December 5, 2017
    Assignee: POWERTECH TECHNOLOGY INC.
    Inventor: Wen-Jeng Fan
  • Patent number: 9812413
    Abstract: A chip module is provided. The chip module includes a chip having an upper surface, a lower surface and a sidewall. The chip includes a signal pad region adjacent to the upper surface. A recess extends from the upper surface toward the lower surface along the sidewall of the chip. A redistribution layer is electrically connected to the signal pad region and extends into the recess. A circuit board is located between the upper surface and the lower surface and extends into the recess. A conducting structure is located in the recess and electrically connects the circuit board to the redistribution layer. A method for forming the chip module is also provided.
    Type: Grant
    Filed: January 13, 2016
    Date of Patent: November 7, 2017
    Assignee: XINTEC INC.
    Inventors: Ho-Yin Yiu, Ying-Nan Wen, Chien-Hung Liu
  • Patent number: 9773866
    Abstract: Semiconductor integrated circuits (ICs) employing localized low dielectric constant (low-K) material in inter-layer dielectric (ILD) material for improved speed performance are disclosed. To speed up performance of selected circuits in an IC that would otherwise lower overall speed performance of the IC, low-K dielectric material is employed during IC fabrication. The low-K dielectric material is provided in selected, localized areas of ILD material in which selected circuits are disposed. In this manner, the IC will experience an overall increased speed performance during operation, because circuit components and/or circuit element interconnects of selected circuit(s) that are disposed in the low-K ILD material will experience reduced signal delay.
    Type: Grant
    Filed: June 18, 2015
    Date of Patent: September 26, 2017
    Assignee: QUALCOMM Incorporated
    Inventors: Haining Yang, Xiangdong Chen
  • Patent number: 9768223
    Abstract: Embodiments provide a chip device package and a method for fabricating thereof. A semiconductor chip has a substrate. A supporting brick is separated from the substrate by a certain distance. A bonding pad having a surface is disposed across the substrate and the supporting brick. A bonding wire is electrically connected to the bonding pad.
    Type: Grant
    Filed: December 21, 2011
    Date of Patent: September 19, 2017
    Assignee: Xintec Inc.
    Inventors: Chia-Sheng Lin, Yu-Ting Huang
  • Patent number: 9750136
    Abstract: A wiring board includes an insulating substrate, a first conductor layer laminated on a first side of the insulating substrate, a second conductor layer laminated on a second side of the insulating substrate, first plating posts fitted in through holes in the insulating substrate respectively such that the first plating posts are projecting from the first conductor layer, and plating connecting parts connecting the second conductor layer and the first plating posts and having electronic component connecting portions such that the electronic component connecting portions form an electronic component mounting part positioned to mount an electronic component and are positioned on the through holes, respectively.
    Type: Grant
    Filed: December 12, 2016
    Date of Patent: August 29, 2017
    Assignee: IBIDEN CO., LTD.
    Inventors: Michimasa Takahashi, Katsutoshi Kitagawa
  • Patent number: 9691694
    Abstract: An integrated circuit device that includes a package substrate and a die coupled to the package substrate. The package substrate includes at least one dielectric layer, a first stack of first interconnects in the at least one dielectric layer, and a second interconnect formed on at least one side portion of the at least one dielectric layer. The first stack of first interconnects is configured to provide a first electrical path for a non-ground reference signal, where the first stack of first interconnects is located along at least one side of the package substrate. The second interconnect is configured to provide a second electrical path for a ground reference signal.
    Type: Grant
    Filed: May 4, 2015
    Date of Patent: June 27, 2017
    Assignee: QUALCOMM Incorporated
    Inventors: Uei-Ming Jow, Young Kyu Song, Jong-Hoon Lee, Xiaonan Zhang, Mario Francisco Velez
  • Patent number: 9686860
    Abstract: A printed circuit board includes an insulating layer, a circuit pattern on the insulating layer, and a surface treatment layer on the circuit pattern. The surface treatment layer includes a bottom surface having a width wider than a width of a top surface of the circuit pattern.
    Type: Grant
    Filed: August 20, 2015
    Date of Patent: June 20, 2017
    Assignee: LG INNOTEK CO., LTD
    Inventors: Yun Mi Bae, Soon Gyu Kwon, Sang Hwa Kim, Sang Young Lee, Jin Hak Lee, Han Su Lee, Dong Hun Jeong, In Ho Jeong, Dae Young Choi, Jung Ho Hwang
  • Patent number: 9646923
    Abstract: Semiconductor devices, methods of manufacture thereof, and packaged semiconductor devices are disclosed. In one embodiment, a semiconductor device includes a substrate and conductive traces disposed over the substrate. Each of the conductive traces has a bottom region proximate the substrate and a top region opposite the bottom region. The top region has a first width and the bottom region has a second width. The second width is greater than the first width.
    Type: Grant
    Filed: December 18, 2012
    Date of Patent: May 9, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Jen Tseng, Yen-Liang Lin, Tin-Hao Kuo, Chen-Shien Chen, Mirng-Ji Lii
  • Patent number: 9607963
    Abstract: A semiconductor device is disclosed, which includes: a substrate having a substrate body and a plurality of conductive pads formed on the substrate body, wherein each of the conductive pads has at least an opening formed in a first surface thereof; a semiconductor component having a plurality of bonding pads; a plurality of conductive elements formed between the bonding pads and the conductive pads and in the openings of the conductive pads; and an encapsulant formed between the substrate and the semiconductor component for encapsulating the conductive elements, thereby strengthening the bonding between the conductive elements and the conductive pads and consequently increasing the product yield.
    Type: Grant
    Filed: April 22, 2014
    Date of Patent: March 28, 2017
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Chang-Fu Lin, Chin-Tsai Yao, Ming-Chin Chuang, Fu-Tang Huang
  • Patent number: 9607956
    Abstract: A semiconductor device in which reliability of a bonding pad to which a conductive wire is bonded is achieved. A bonding pad having an OPM structure is formed of an Al—Cu alloy film having a Cu concentration of 2 wt % or more. By increasing the Cu concentration, the Al—Cu alloy film forming the bonding pad is hardened. Therefore, the bonding pad is difficult to be deformed by impact in bonding of a Cu wire, and deformation of an OPM film as following the deformation of the bonding pad can be reduced. In this manner, concentration of a stress on the OPM film caused by the impact from the Cu wire can be reduced, and therefore, the breakage of the OPM film can be prevented.
    Type: Grant
    Filed: May 26, 2016
    Date of Patent: March 28, 2017
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Masahiro Matsumoto, Kazuyoshi Maekawa, Masahiko Fujisawa
  • Patent number: 9589989
    Abstract: An array substrate for a liquid crystal display (LCD) device include: a substrate; a gate line formed in one direction on one surface of the substrate; a data line crossing the gate line to define a pixel area; a thin film transistor (TFT) configured at a crossing of the gate line and the data line; a pixel electrode formed at a pixel region of the substrate; an insulating film formed on the entire surface of the substrate including the pixel electrode and the TFT, including a first insulating film formed of a high temperature silicon nitride film and a second insulating film formed of a low temperature silicon nitride film, and having a contact hole having an undercut shape exposing the pixel electrode; a pixel electrode connection pattern formed within the contact hole having an undercut shape and connected with the pixel electrode and the TFT; and a plurality of common electrodes separately formed on the insulating film.
    Type: Grant
    Filed: November 12, 2014
    Date of Patent: March 7, 2017
    Assignee: LG Display Co., Ltd.
    Inventors: Jeong-Oh Kim, Yong-Il Kim
  • Patent number: 9564391
    Abstract: An integrated circuit (IC) device is provided. The IC device includes an IC die having opposing first and second surfaces, a carrier coupled to the first surface of the IC die, a laminate coupled to the carrier and the second surface of the IC die, and a trace located on a surface of the laminate and electrically coupled to a bond pad located on the second surface of the IC die. The trace is configured to couple the bond pad to a circuit board.
    Type: Grant
    Filed: February 18, 2011
    Date of Patent: February 7, 2017
    Assignee: Broadcom Corporation
    Inventors: Kevin (Kunzhong) Hu, Edward Law
  • Patent number: 9527728
    Abstract: A method of forming a packaged electronic device includes fabricating a MEMS structure, such as a BAW structure, on a first semiconductor wafer substrate; forming a cavity in a second semiconductor wafer substrate; and mounting the second substrate on the first substrate such that the MEMS structure is positioned inside the cavity in the second substrate. A wafer level assembly and an integrated circuit package are also described.
    Type: Grant
    Filed: July 22, 2013
    Date of Patent: December 27, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Matthew David Romig, Marie-Solange Anne Milleron, Benjamin Michael Sutton
  • Patent number: 9502456
    Abstract: An electronic component device includes a first electronic component on which a first electrode pad is disposed, a second electronic component on which a second electrode pad having a first pad portion and a second pad portion is disposed, a first bonding wire having one end connected to the first electrode pad and the other end connected to the first pad portion, and a second bonding wire having one end connected to a connection portion between the first pad portion and the first bonding wire and the other end connected to the second pad portion. The second electrode pad is disposed on the second electronic component so that the first pad portion and the second pad portion are laid along a direction intersecting with an extending direction of the first bonding wire. The extending direction of the first bonding wire intersects with an extending direction of the second bonding wire.
    Type: Grant
    Filed: September 24, 2013
    Date of Patent: November 22, 2016
    Assignee: HAMAMATSU PHOTONICS K.K.
    Inventors: Shin-ichiro Takagi, Shingo Ishihara, Masaharu Muramatsu
  • Patent number: 9398699
    Abstract: A microelectronic device mounting substrate includes a bond pad with a side wall and an upper surface. A dielectric first layer is disposed on the mounting substrate and a solder mask second layer is disposed on the dielectric first layer. A uniform recess is disposed through the solder mask second layer and the dielectric first layer that exposes the portion of the bond pad upper surface.
    Type: Grant
    Filed: August 27, 2012
    Date of Patent: July 19, 2016
    Assignee: Intel Corporation
    Inventors: Houssam Jomaa, Omar Bchir
  • Patent number: 9385076
    Abstract: A semiconductor device includes a post-passivation interconnect (PPI) structure having a landing pad region. A polymer layer is formed on the PPI structure and patterned with a first opening and a second opening to expose portions of the landing pad region. The second opening is a ring-shaped opening surrounding the first opening. A bump structure is formed on the polymer layer to electrically connect the landing pad region through the first opening and the second opening.
    Type: Grant
    Filed: December 7, 2011
    Date of Patent: July 5, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hsien-Wei Chen, Yi-Wen Wu, Wen-Hsiung Lu
  • Patent number: 9385101
    Abstract: A semiconductor device has a semiconductor die with a plurality of composite bumps formed over a surface of the semiconductor die. The composite bumps have a fusible portion and non-fusible portion, such as a conductive pillar and bump formed over the conductive pillar. The composite bumps can also be tapered. Conductive traces are formed over a substrate with interconnect sites having edges parallel to the conductive trace from a plan view for increasing escape routing density. The interconnect site can have a width less than 1.2 times a width of the conductive trace. The composite bumps are wider than the interconnect sites. The fusible portion of the composite bumps is bonded to the interconnect sites so that the fusible portion covers a top surface and side surface of the interconnect sites. An encapsulant is deposited around the composite bumps between the semiconductor die and substrate.
    Type: Grant
    Filed: June 19, 2015
    Date of Patent: July 5, 2016
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventor: Rajendra D. Pendse
  • Patent number: 9368466
    Abstract: A bump contact electrically connects a conductor on a substrate and a contact pad on a semiconductor device mounted to the substrate. The first end of an electrically conductive pillar effects electrical contact and mechanical attachment of the pillar to the contact pad with the pillar projecting outwardly from the semiconductor device. A solder crown reflowable at a predetermined temperature into effecting electrical contact and mechanical attachment with the conductor is positioned in axial alignment with the second end of the pillar. A diffusion barrier electrically and mechanically joins the solder bump to the second end of the pillar and resists electro-migration into the first end of the solder crown of copper from the pillar. One diffusion barrier takes the form of a 2-20 micron thick control layer of nickel, palladium, titanium-tungsten, nickel-vanadium, or tantalum nitride positioned between the pillar and the solder crown.
    Type: Grant
    Filed: September 17, 2012
    Date of Patent: June 14, 2016
    Assignee: Maxim Integrated Products, Inc.
    Inventor: Pradip D. Patel