Layered Contact, Lead Or Bond Patents (Class 257/781)
  • Patent number: 11404390
    Abstract: Sacrificial pillars for a semiconductor device assembly, and associated methods and systems are disclosed. In one embodiment, a region of a semiconductor die may be identified to include sacrificial pillars that are not connected to bond pads of the semiconductor die, in addition to live conductive pillars connected to the bond pads. The region with the sacrificial pillars, when disposed in proximity to the live conductive pillars, may prevent an areal density of the live conductive pillars from experiencing an abrupt change that may result in intolerable variations in heights of the live conductive pillars. As such, the sacrificial pillars may improve a coplanarity of the live conductive pillars by reducing variations in the heights of the live conductive pillars. Thereafter, the sacrificial pillars may be removed from the semiconductor die.
    Type: Grant
    Filed: June 30, 2020
    Date of Patent: August 2, 2022
    Assignee: Micron Technology, Inc.
    Inventor: Chao Wen Wang
  • Patent number: 11398440
    Abstract: An integrated circuit structure includes a metal pad, a passivation layer including a portion over the metal pad, a first polymer layer over the passivation layer, and a first Post-Passivation Interconnect (PPI) extending into to the first polymer layer. The first PPI is electrically connected to the metal pad. A dummy metal pad is located in the first polymer layer. A second polymer layer is overlying the first polymer layer, the dummy metal pad, and the first PPI. An Under-Bump-Metallurgy (UBM) extends into the second polymer layer to electrically couple to the dummy metal pad.
    Type: Grant
    Filed: October 22, 2018
    Date of Patent: July 26, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hao-Hsiang Chuang, Shih-Wei Liang, Ching-Feng Yang, Kai-Chiang Wu, Hao-Yi Tsai, Chuei-Tang Wang, Chen-Hua Yu
  • Patent number: 11398389
    Abstract: Provided is a method of producing an electronic device, including a step of preparing a structure which includes an electronic component having a circuit forming surface, and an adhesive laminated film which includes a base material layer and an adhesive resin layer and in which the adhesive resin layer is attached to the circuit forming surface of the electronic component; a step of back-grinding a surface of the electronic component opposite to the circuit forming surface in a state of being attached to the adhesive laminated film; a step of dicing the electronic component in a state of being attached to the adhesive laminated film; and a step of forming an electromagnetic wave-shielding layer on the separated electronic components in a state of being attached to the adhesive laminated film, in this order.
    Type: Grant
    Filed: July 9, 2018
    Date of Patent: July 26, 2022
    Assignee: MITSUI CHEMICALS TOHCELLO, INC.
    Inventors: Takashi Unezaki, Jun Kamada, Akimitsu Morimoto, Jin Kinoshita
  • Patent number: 11315862
    Abstract: A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes a redistribution structure, a circuit substrate, and an insulating encapsulation. The redistribution structure includes a first under-bump metallization (UBM) pattern covered by a first dielectric layer, and the first UBM pattern includes a surface substantially leveled with a surface of the first dielectric layer. The circuit substrate is electrically coupled to the redistribution structure through a conductive joint disposed on the surface of the first UBM pattern. The insulating encapsulation is disposed on the redistribution structure to cover the circuit substrate.
    Type: Grant
    Filed: June 29, 2020
    Date of Patent: April 26, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuan-Lin Ho, Chin-Liang Chen, Jiun-Yi Wu, Chi-Yang Yu, Yu-Min Liang, Wei-Yu Chen
  • Patent number: 11309268
    Abstract: A method of designing a layout includes determining a first layout pattern, wherein the first layout pattern corresponds to a plurality of contact pads. The method further includes generating a second layout pattern. The method further includes checking whether an edge of the second layout pattern overlaps the first layout pattern. The method further includes adjusting the second layout pattern so that the edge of the second layout pattern overlaps the first layout pattern in response to a determination that the edge of the second layout pattern is separated from the first layout pattern.
    Type: Grant
    Filed: June 17, 2020
    Date of Patent: April 19, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Gulbagh Singh, Chih-Ming Lee, Chi-Yen Lin, Wen-Chang Kuo, C. C. Liu
  • Patent number: 11295997
    Abstract: A method of manufacturing a semiconductor device prepares contact members, each of which has a cylindrical through-hole, and column-shaped connection terminals, each having a polygonal shape in a cross-sectional view along a length direction thereof, wherein a length of a diagonal of the polygonal shape is greater than an inner diameter of the through-holes. Chamfers with a curvature for fitting an inner surface of the through-holes are formed at corners of the connection terminal, and the connection terminals are press-fitted into the through-holes of the contacts. By doing so, the area of contact where the connection terminals press-fitted into the contacts contact the inner circumferential surfaces of the through-holes of the contacts is increased. This increases the tensile load of the connection terminals fitted into the contacts.
    Type: Grant
    Filed: May 26, 2020
    Date of Patent: April 5, 2022
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Rikihiro Maruyama, Masaoki Miyakoshi
  • Patent number: 11217558
    Abstract: A method and a device for establishing a wire connection between a first contact surface and at least one further contact surface. A contact end of a wire is positioned in a contact position relative to the first contact surface with a wire guiding tool. Subsequently, a mechanical, electrically conductive connection is established between the first contact surface and the contact end with a first solder material connection, and subsequently the wire guiding tool is moved to the further contact surface thus forming a wire section and establishing a further mechanical, electrically conductive connection between the wire section end and the further contact surface with a further solder material connection.
    Type: Grant
    Filed: March 15, 2018
    Date of Patent: January 4, 2022
    Assignee: PAC TECH—PACKAGING TECHNOLOGIES GMBH
    Inventors: Andrej Kolbasow, Jan Hoffmann, Matthias Fettke
  • Patent number: 11177233
    Abstract: An optoelectronic semiconductor chip includes a rear side with a center and with two contact points for electrical contacting of the semiconductor chip, the contact points being spaced apart from one another, and two solder pads arranged on the contact points, wherein the center is located in a region between the contact points, the solder pads protrude from the rear side and are exposed, and on average, the solder pads are thicker further away from the center than in the vicinity of the center or vice versa.
    Type: Grant
    Filed: November 10, 2017
    Date of Patent: November 16, 2021
    Assignee: OSRAM OLED GmbH
    Inventors: Christian Leirer, Martin Rudolf Behringer
  • Patent number: 11171104
    Abstract: An IC chip package includes a substrate having a plurality of interconnect metal pads, and a chip having a plurality of interconnect metal pads arranged thereon. An interconnect solder structure electrically connects each of the plurality of interconnect metal pads. The chip is devoid of the interconnect solder structures and interconnect metal pads at one or more corners of the chip. Rather, a dummy solder structure connects the IC chip to the substrate at each of the one or more corners of the IC chip, and the dummy solder structure is directly under at least one side of the IC chip at the one or more corners of the IC chip. The dummy solder structure has a larger volume than a volume of each of the plurality of interconnect solder structures. The dummy solder structure eliminates a chip-underfill interface at corner(s) of the chip where delamination would occur.
    Type: Grant
    Filed: October 24, 2019
    Date of Patent: November 9, 2021
    Assignee: MARVELL ASIA PTE, LTD.
    Inventors: Manish Nayini, Richard S. Graf, Janak G. Patel, Nazmul Habib
  • Patent number: 11121108
    Abstract: A flip chip package includes a substrate having a die attach surface, and a die mounted on the die attach surface with an active surface of the die facing the substrate. The die includes a base, a passivation layer overlying the base, a topmost metal layer overlying the passivation, and a stress buffering layer overlying the topmost metal layer, wherein at least two openings are disposed in the stress buffering layer to expose portions of the topmost metal layer. The die is interconnected to the substrate through a plurality of conductive pillar bumps on the active surface. At least one of the conductive pillar bumps is electrically connected to one of the exposed portions of the topmost metal layer through one of the at least two openings.
    Type: Grant
    Filed: May 31, 2020
    Date of Patent: September 14, 2021
    Assignee: MediaTek Inc.
    Inventors: Tzu-Hung Lin, Thomas Matthew Gregorich
  • Patent number: 11121050
    Abstract: In order to prevent cracks from occurring at the corners of semiconductor dies after the semiconductor dies have been bonded to other substrates, an opening is formed adjacent to the corners of the semiconductor dies, and the openings are filled and overfilled with a buffer material that has physical properties that are between the physical properties of the semiconductor die and an underfill material that is placed adjacent to the buffer material.
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: September 14, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuan-Yu Huang, Chih-Wei Wu, Li-Chung Kuo, Long Hua Lee, Sung-Hui Huang, Ying-Ching Shih, Pai Yuan Li
  • Patent number: 11049800
    Abstract: In a described example, a method for making a packaged semiconductor device includes laser ablating a first groove with a first width and a first depth into a mounting surface of a substrate between landing pads. A first pillar bump on an active surface of a semiconductor device is bonded to a first landing pad; and a second pillar bump on the semiconductor device is bonded to a second landing pad. A channel forms with the active surface of the semiconductor device forming a first wall of the channel, the first pillar bump forms a second wall of the channel, the second pillar bump forming a third wall of the channel, and a surface of the first groove forms a fourth wall of the channel. The channel is filled with mold compound and at least a portion of the substrate and the semiconductor device are covered with mold compound.
    Type: Grant
    Filed: February 25, 2020
    Date of Patent: June 29, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Dolores Babaran Milo, Cherry Lyn Marquez Aranas
  • Patent number: 10811365
    Abstract: Semiconductor devices having metallization structures including crack-inhibiting structures, and associated systems and methods, are disclosed herein. In one embodiment, a semiconductor device includes a metallization structure formed over a semiconductor substrate. The metallization structure can include a bond pad electrically coupled to the semiconductor substrate via one or more layers of conductive material, and an insulating material—such as a low-? dielectric material—at least partially around the conductive material. The metallization structure can further include a crack-inhibiting structure positioned beneath the bond pad between the bond pad and the semiconductor substrate. The crack-inhibiting structure can include (a) a metal lattice extending laterally between the bond pad and the semiconductor substrate and (b) barrier members extending vertically between the metal lattice and the bond pad.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: October 20, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Shams U. Arifeen, Hyunsuk Chun, Sheng Wei Yang, Keizo Kawakita
  • Patent number: 10727114
    Abstract: Integrated circuits including at least two electrically conductive interconnect lines and methods of manufacturing generally include a surface of the integrated circuit. At least two electrically conductive interconnect lines are separated by a space of less than 90 nm and are formed on the surface. Each of the at least two interconnect lines includes a metal cap, a copper conductor having an average grain size greater than a line width of the interconnect. A liner layer is provided, wherein the liner layer and the metal cap encapsulate the copper conductor. A dielectric layer overlaying the at least two electrically conductive interconnect lines and extending along sidewalls thereof is provided, wherein the dielectric layer is configured to provide an airgap between the at least two interconnect lines at the spacing.
    Type: Grant
    Filed: January 13, 2017
    Date of Patent: July 28, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Robert L. Bruce, Alfred Grill, Eric A. Joseph, Teddie P. Magbitang, Hiroyuki Miyazoe, Deborah A. Neumayer
  • Patent number: 10727191
    Abstract: A semiconductor structure includes a first contact pad over a passivation layer, wherein the first contact pad is in a circuit region. The semiconductor structure further includes a plurality of second contact pads over the passivation layer, wherein each second contact pad of the plurality of second contact pads is in a non-circuit region. The semiconductor structure further includes a first buffer layer over the first contact pad and over a first second contact pad of the plurality of second contact pads. The semiconductor structure further includes a second buffer layer over the first buffer layer, the first contact pad, the first second contact pad and a portion of a second second contact pad of the plurality of second contact pads, wherein the second buffer layer exposes a portion of the second second contact pad of the plurality of second contact pads.
    Type: Grant
    Filed: December 24, 2018
    Date of Patent: July 28, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Gulbagh Singh, Chih-Ming Lee, Chi-Yen Lin, Wen-Chang Kuo, C. C. Liu
  • Patent number: 10656738
    Abstract: A touch panel includes at least one touch sensing layer, a first metal layer, a second metal layer, a through hole, a metal film, and a conductive structure. The first and second metal layers are respectively located above and below the touch sensing layer. The through hole penetrates through the first metal layer, the touch sensing layer, and the second metal layer. The through hole has a first opening and a second opening. The metal film is on a bottom surface of the second metal layer and covers the second opening of the through hole. The conductive structure is located on the metal film and in the through hole. An end of the conductive structure adjacent to the first opening has a microstructure. The microstructure extends to a top surface of the first metal layer and surrounds the first opening of the through hole.
    Type: Grant
    Filed: January 7, 2019
    Date of Patent: May 19, 2020
    Assignees: INTERFACE TECHNOLOGY (CHENGDU) CO., LTD., INTERFACE OPTOELECTRONICS (SHENZHEN) CO., LTD., GENERAL INTERFACE SOLUTION LIMITED
    Inventor: Yi-Hung Ho
  • Patent number: 10381312
    Abstract: Disclosed herein are a semiconductor package and a method of manufacturing the same. The semiconductor package according to embodiments of the present disclosure includes a wiring including a plurality of layers including an insulating layer and a wiring layer, a semiconductor chip mounted on the wiring and electrically connected to the wiring layer through a bonding pad, a cover member configured to cover side surfaces of the semiconductor chip and the wiring and be in contact with at least one wiring layer, and an encapsulant configured to seal the cover member. Accordingly, the cover member covers the semiconductor chip and is in contact with the wiring formed under the semiconductor chip, thereby reducing electromagnetic interference, minimizing noise between operations of the semiconductor package, and improving a signal speed.
    Type: Grant
    Filed: May 11, 2017
    Date of Patent: August 13, 2019
    Assignee: NEPES CO., LTD.
    Inventors: Il-Hwan Kim, Jun-Kyu Lee, Min-A Yoon, Dong-Hoon Oh, Tae-Won Kim
  • Patent number: 10340295
    Abstract: A flexible display device includes a substrate and a border unit. The substrate has a display area and a border area that surrounds the display area. The border unit is located in the border area and includes a first metal layer on the substrate, an insulation layer covering the first metal layer and the substrate, a second metal layer on the insulation layer, a protection layer covering the second metal layer and the insulation layer, a semiconductor layer between the insulation layer and the protection layer, a planarization layer covering the protection layer, and a third metal layer on the planarization layer. The third metal layer has a first part, a second part, and a third part that is between and physically connected to the first and second parts. A notch is defined by the first, second, and third parts.
    Type: Grant
    Filed: August 7, 2018
    Date of Patent: July 2, 2019
    Assignee: E Ink Holdings Inc.
    Inventors: Yi-Lung Wen, Jia-Hung Chen, Kuang-Heng Liang, Chi-Ming Wu
  • Patent number: 10085627
    Abstract: An image pickup apparatus includes an image pickup device configured such that a plurality of electrode pads are disposed in a row on an inclined surface; a wiring board configured such that a plurality of first bonded electrodes that are bonded to the plurality of electrode pads via first solder bumps, respectively, are disposed in a row on a first end portion, and a plurality of second bonded electrodes are disposed in a row on a second end portion; and a signal cable configured to be bonded to the plurality of second bonded electrodes via second solder bumps, respectively. The wiring board includes a first protective film which covers the first end portion, and a second protective film which covers the second end portion, and is of a thickness that is greater than a thickness of the first protective film and less than a height of the second solder bumps.
    Type: Grant
    Filed: July 18, 2017
    Date of Patent: October 2, 2018
    Assignee: OLYMPUS CORPORATION
    Inventors: Kazuya Maeda, Shoichiro Kawayoke
  • Patent number: 9972505
    Abstract: The present invention makes it possible to improve the reliability of a semiconductor device. The semiconductor device has, over a semiconductor substrate, a pad electrode formed at the uppermost layer of a plurality of wiring layers, a surface protective film having an opening over the pad electrode, a redistribution line being formed over the surface protective film and having an upper surface and a side surface, a sidewall barrier film comprising an insulating film covering the side surface and exposing the upper surface of the redistribution line, and a cap metallic film covering the upper surface of the redistribution line. Then the upper surface and side surface of the redistribution line are covered with the cap metallic film or the sidewall barrier film and the cap metallic film and the sidewall barrier film have an overlapping section.
    Type: Grant
    Filed: November 17, 2015
    Date of Patent: May 15, 2018
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Masahiro Matsumoto, Kazuyoshi Maekawa, Yuichi Kawano
  • Patent number: 9905503
    Abstract: A package structure and a method of fabricating the same are provided. The method includes forming a first wiring layer on a carrier board, forming a plurality of first conductors on the first wiring layer, encapsulating the first wiring layer and the first conductors with a first insulating layer, forming a second wiring layer on the first insulating layer, forming a plurality of second conductors on the second wiring layer, encapsulating the second wiring layer and the second conductors with a second insulating layer, and forming at least one opening in the second insulating layer. The at least one opening extends to a second surface of the first insulating layer, such that at least one electronic component can be disposed in the at least one opening. With forming two insulating layers first followed by forming the at least one opening, there is no need to stack or laminate the substrate that already has an opening, and the electronic component is free of displacement due to any compression.
    Type: Grant
    Filed: December 9, 2015
    Date of Patent: February 27, 2018
    Assignee: PHOENIX PIONEER TECHNOLOGY CO., LTD.
    Inventors: Shih-Ping Hsu, Chao-Chung Tseng
  • Patent number: 9824974
    Abstract: Die (110) and/or undiced wafers and/or multichip modules (MCMs) are attached on top of an interposer (120) or some other structure (e.g. another integrated circuit) and are covered by an encapsulant (160). Then the interposer is thinned from below. Before encapsulation, a layer (410) more rigid than the encapsulant is formed on the interposer around the die to reduce or eliminate interposer dishing between the die when the interposer is thinned by a mechanical process (e.g. CMP). Other features are also provided.
    Type: Grant
    Filed: November 30, 2016
    Date of Patent: November 21, 2017
    Assignee: INVENSAS CORPORATION
    Inventors: Guilian Gao, Cyprian Emeka Uzoh, Charles G. Woychik, Hong Shen, Arkalgud R. Sitaram, Liang Wang, Akash Agrawal, Rajesh Katkar
  • Patent number: 9818700
    Abstract: A semiconductor package structure includes a substrate; and a die region having a plurality of dies disposed on the substrate. A first die of the plurality of dies is larger than a second die of the plurality of dies. The semiconductor package structure further includes a plurality of stress relief structures on the substrate. At least one stress relief structure of the plurality of stress relief structures is at a corner of the substrate. Each stress relief structure is spaced from a closest die of the plurality of dies by a first distance. Upper surfaces of each stress relief structure of the plurality of stress relief structures are unconnected.
    Type: Grant
    Filed: March 7, 2016
    Date of Patent: November 14, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: Hsien-Wei Chen
  • Patent number: 9755030
    Abstract: A structure and method for fabricating a semiconductor device is described. A device structure including a gate structure, a source region and a drain region is disposed on a first surface of a substrate. Contact holes are etched through the source and drain regions and through a first portion of the substrate. The contact holes are filled with a conductive material to produce contact studs coupled to the source and drain regions. A second portion of the substrate is removed. A surface of the contact studs is exposed through a second surface of the substrate opposite to the gate structure for connection to a wiring layer disposed over the second surface of the substrate.
    Type: Grant
    Filed: December 17, 2015
    Date of Patent: September 5, 2017
    Assignee: International Business Machines Corporation
    Inventors: Carl John Radens, Richard Quimby Williams
  • Patent number: 9735075
    Abstract: An electronic module is provided, including an electronic element and a strengthening layer formed on a side surface of the electronic element but not formed on an active surface of the electronic element so as to strengthen the structure of the electronic module. Therefore, the electronic element is prevented from being damaged when the electronic module is picked and placed.
    Type: Grant
    Filed: October 16, 2014
    Date of Patent: August 15, 2017
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Lu-Yi Chen, Chang-Lun Lu, Shih-Ching Chen
  • Patent number: 9651979
    Abstract: A circuit carrier includes a dielectric isolation carrier, an upper metallization layer applied to the dielectric isolation carrier, and a dielectric coating. The upper metallization layer has a metallization section which has an underside facing the isolation carrier, a top side facing away from the isolation carrier, and a side surface closed in a ring-shaped fashion. The side surface laterally delimits the metallization section and extends continuously between the top side and the underside. The dielectric coating is on the side surface and the top side, and extends continuously from the side surface onto the top side.
    Type: Grant
    Filed: October 28, 2015
    Date of Patent: May 16, 2017
    Assignee: Infineon Technologies AG
    Inventors: Thomas Hunger, Carsten Ehlers
  • Patent number: 9601570
    Abstract: A structure of a semiconductor device is described. A device structure including a gate structure, a source region and a drain region is disposed on a first surface of a substrate. Contact holes are etched through the source and drain regions and through a first portion of the substrate. The contact holes are filled with a conductive material to produce contact studs coupled to the source and drain regions. A second portion of the substrate is removed. A surface of the contact studs is exposed through a second surface of the substrate opposite to the gate structure for connection to a wiring layer disposed over the second surface of the substrate.
    Type: Grant
    Filed: July 31, 2016
    Date of Patent: March 21, 2017
    Assignee: International Business Machines Corporation
    Inventors: Carl J Radens, Richard Q Williams
  • Patent number: 9564364
    Abstract: A semiconductor device includes a semiconductor substrate, which includes a through hole that extends through the semiconductor substrate. An insulative layer includes a first surface, an opposite second surface covering the semiconductor substrate, and an opening aligned with the through hole. An insulative film covers an inner wall surface of the semiconductor substrate and the opening. A through electrode is formed in the through hole and the opening inward from the insulative film. The through electrode includes a first end surface that forms a pad exposed from the first surface of the insulative layer. The first end surface of the through electrode is flush with the first surface of the insulative layer.
    Type: Grant
    Filed: August 3, 2012
    Date of Patent: February 7, 2017
    Assignee: Shinko Electric Industries Co., LTD.
    Inventor: Takaharu Yamano
  • Patent number: 9530740
    Abstract: A 3D interconnect structure and method of manufacture are described in which a through-silicon vias (TSVs) and metal redistribution layers (RDLs) are formed using a dual damascene type process flow. A silicon nitride or silicon carbide passivation layer may be provided between the thinned device wafer back side and the RDLs to provide a hermetic barrier and etch stop layer during the process flow.
    Type: Grant
    Filed: August 26, 2015
    Date of Patent: December 27, 2016
    Assignee: Intel Corporation
    Inventors: Kevin J. Lee, Mark T. Bohr, Andrew W. Yeoh, Christopher M. Pelto, Hiten Kothari, Seshu V. Sattiraju, Hang-Shing Ma
  • Patent number: 9418872
    Abstract: A microelectronic component package includes a plurality of electrical leads which are coupled to a microelectronic component and which have exposed lengths extending outwardly beyond a peripheral edge of an encapsulant. A plurality of terminals may be positioned proximate a terminal face of the encapsulant and these terminals may be electrically coupled to the same leads. This can facilitate connection of the microelectronic component to a substrate using the leads as a conventional leaded package. The terminals, however, can facilitate stacking of the leaded package with one or more additional microelectronic components, e.g., a BGA package.
    Type: Grant
    Filed: January 28, 2014
    Date of Patent: August 16, 2016
    Assignee: Micron Technology, Inc.
    Inventors: Meow Koon Eng, Sui Waf Low, Min Yu Chan, Yong Poo Chia, Bok Leng Ser, Wei Zhou
  • Patent number: 9362246
    Abstract: A semiconductor device is provided with a plurality of protrusions which are made of a resin and which protrude higher than electrodes, and conductive layers which are electrically connected to the electrodes and which cover the top surfaces of the protrusions. A method for manufacturing the semiconductor device includes a step of applying a layer of the resin to the semiconductor device except for the electrodes, a step of patterning the conductive layers on the electrodes and the layer of the resin in accordance with the protrusions, and a step of removing the layer of the resin located between the conductive layers by the use of the patterned conductive layers as masks so as to form the protrusions.
    Type: Grant
    Filed: June 16, 2015
    Date of Patent: June 7, 2016
    Assignee: Seiko Epson Corporation
    Inventor: Haruki Ito
  • Patent number: 9324631
    Abstract: A bump structure or pillar structure formed above a metallization system of a complex semiconductor device may include a stress buffer layer, which may efficiently distribute the resulting mechanical stress which may typically occur during the chip package interaction due to a thermal mismatch of these components. The stress buffer layer comprises copper-based buffer regions that cover a significant portion of the overall surface, wherein a thickness of approximately 3-10 ?m may also be used. Moreover, the buffer regions may efficiently replace aluminum as a terminal metal active region.
    Type: Grant
    Filed: April 25, 2013
    Date of Patent: April 26, 2016
    Assignee: GLOBALFOUNDIRES Inc.
    Inventors: Axel Walter, Matthias Lehr
  • Patent number: 9324673
    Abstract: A method of manufacture of an integrated circuit packaging system includes: removing a portion of a leadframe to form a partially removed region and an upper portion of a peripheral lead on the leadframe first side; mounting a first integrated circuit over the partially removed region with a first adhesive; forming a first molding layer directly on the first integrated circuit and the peripheral lead; removing a portion of a leadframe second side exposing the first adhesive; mounting a second integrated circuit on the first adhesive of the first integrated circuit; forming a first interconnection layer directly on the first integrated circuit with the first integrated circuit and the peripheral lead electrically connected; and forming a second interconnection layer directly on the second integrated circuit with the second integrated circuit and the peripheral lead electrically connected.
    Type: Grant
    Filed: June 23, 2011
    Date of Patent: April 26, 2016
    Assignee: STATS ChipPAC Ltd.
    Inventor: Zigmund Ramirez Camacho
  • Patent number: 9316447
    Abstract: There is provided a thermal interface material, TIM, a thermal interface application comprising such a TIM, and corresponding methods for providing the material and the thermal interface. The TIM comprises a TIM layer in which an activable shrinkage material is distributed, such that upon activation of the shrinkage material the thickness of the TIM layer is increased. In the thermal interface application, where the TIM (400) is arranged between a heat generating component (20) and a heat conducting element (30), the increase in thickness of the TIM layer is utilized to increase the contact pressure on mating surfaces.
    Type: Grant
    Filed: March 11, 2013
    Date of Patent: April 19, 2016
    Assignee: KONINKLIJKE PHILIPS N.V.
    Inventors: Bas Fleskens, Reinier Imre Anton Den Boer
  • Patent number: 9253873
    Abstract: Disclosed herein are a printed circuit board and a method of manufacturing the same. The printed circuit board includes: a core layer having a first circuit wiring layer formed on one surface or both surfaces thereof; an insulating layer laminated, as at least one layer, on one surface or both surfaces of the core layer; and a second circuit wiring layer formed on one surface of the insulating layer, wherein a conductive core is included in upper and lower insulating layers contacting the second circuit wiring layer requiring an electromagnetic wave shielding, or the conductive core is included in the insulating layer or the core layer contacting the first circuit wiring layer requiring the electromagnetic wave shielding.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: February 2, 2016
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Seung Wook Park, Dong Hwan Lee, Jin Gu Kim, Chang Bae Lee, Christian Romero
  • Patent number: 9196581
    Abstract: A microelectronic assembly includes a first component with first conductive elements; a second component with second conductive elements; a bond metal; and an underfill layer. The posts have a height above the respective surface from which the posts project. A bond metal can be disposed between respective pairs of conductive elements, each pair including at least one of the posts and at least one of the first or second conductive elements confronting the at least one post. The bond metal can contact edges of the posts along at least one half the height of the posts. An underfill layer contacts and bonds the first and second surfaces of the first and second components. A residue of the underfill layer may be present at at least one interfacial surfaces between at least some of the posts and the bond metal or may be present within the bond metal.
    Type: Grant
    Filed: April 14, 2014
    Date of Patent: November 24, 2015
    Assignee: Tessera, Inc.
    Inventors: Belgacem Haba, Ilyas Mohammed, Ellis Chau, Sang Il Lee, Kishor Desai
  • Patent number: 9190364
    Abstract: A die according to an embodiment includes a contact pad configured to provide an electrical contact to a circuit element included in the die, a lateral edge closest to the contact pad and a cover layer including a protective structure, the protective structure including at least one elongated structure, wherein the cover layer includes an opening providing access to the contact pad to couple the contact pad electrically to an external contact, wherein the protective structure is arranged between the lateral edge and the contact pad. Using an embodiment may reduce a danger of contamination of a top side of a die during fabrication and packaging a chip.
    Type: Grant
    Filed: October 16, 2013
    Date of Patent: November 17, 2015
    Assignee: Infineon Technologies Austria AG
    Inventor: Bernhard Knuepfer
  • Patent number: 9177930
    Abstract: A flip chip semiconductor package has a substrate with a plurality of active devices. A contact pad is formed on the substrate in electrical contact with the plurality of active devices. A passivation layer, second barrier layer, and adhesion layer are formed between the substrate and an intermediate conductive layer. The intermediate conductive layer is in electrical contact with the contact pad. A copper inner core pillar is formed by plating over the intermediate conductive layer. The inner core pillar has a rectangular, cylindrical, toroidal, or hollow cylinder form factor. A solder bump is formed around the inner core pillar by plating solder material and reflowing the solder material to form the solder bump. A first barrier layer and wetting layer are formed between the inner core pillar and solder bump. The solder bump is in electrical contact with the intermediate conductive layer.
    Type: Grant
    Filed: September 17, 2012
    Date of Patent: November 3, 2015
    Assignee: STATS ChipPAC, Ltd.
    Inventor: Yaojian Lin
  • Patent number: 9177929
    Abstract: Techniques for fabricating fine-pitch micro-bumps are disclosed. According to one embodiment, a fabrication process may comprise the following steps: depositing a dielectric layer on a wafer; forming a pattern of through holes in the dielectric layer; depositing a seed metal layer on top of the dielectric layer and inside the through holes; depositing a layer of UBM metal on top of the seed metal layer (including inside the holes), and further filling the holes with a low melting point metal; performing chemical mechanical polishing (CMP) to remove conductive material(s) outside the holes and/or on the surface of the dielectric layer, such that the metal stacks of adjacent holes are insulated by the dielectric material between them; and etching the dielectric material surrounding the holes to cause the tip of the metal stacks to extend slightly higher than the surrounding dielectric surface, thereby forming fine-pitch micro-bumps.
    Type: Grant
    Filed: May 13, 2014
    Date of Patent: November 3, 2015
    Assignee: NATIONAL CENTER FOR ADVANCED PACKAGING CO., LTD.
    Inventor: Wenqi Zhang
  • Patent number: 9159687
    Abstract: A solder bump structure for a ball grid array (BGA) includes at least one under bump metal (UBM) layer and a solder bump formed over the at least one UBM layer. The solder bump has a bump width and a bump height and the ratio of the bump height over the bump width is less than 1.
    Type: Grant
    Filed: August 10, 2012
    Date of Patent: October 13, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jung-Hua Chang, Cheng-Lin Huang, Jing-Cheng Lin
  • Patent number: 9059158
    Abstract: A semiconductor device comprises a semiconductor substrate, an under-bump metallization (UBM) structure overlying the semiconductor substrate, and a solder bump overlying and electrically connected to the UBM structure. The UBM structure comprises a first metallization layer comprising a first metal, a second metallization layer comprising a second metal different from the first metal, and a first intermetallic compound (IMC) layer between the first metallization layer and the second metallization layer, the first IMC layer comprising the first metal and the second metal.
    Type: Grant
    Filed: July 18, 2014
    Date of Patent: June 16, 2015
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tsung-Fu Tsai, Yian-Liang Kuo, Chih-Horng Chang
  • Patent number: 9053973
    Abstract: A semiconductor device includes a semiconductor substrate, an interlayer insulation film, multiple wiring layers, a first hard film, and an electrical pad. The semiconductor substrate has a semiconductor element. The interlayer insulation film is disposed above the semiconductor substrate. The multiple wiring layers are disposed within the interlayer insulation film. The first hard film is disposed above the interlayer insulation film, and the first hard film is harder than the interlayer insulation film. The electrical pad is disposed above the first hard film, and the electrical pad is used for an external connection. The electrical pad includes a lower layer pad, the upper layer pad, and a second hard film.
    Type: Grant
    Filed: December 26, 2013
    Date of Patent: June 9, 2015
    Assignee: DENSO CORPORATION
    Inventors: Kouichi Sawada, Yasushi Tanaka
  • Patent number: 9041225
    Abstract: An embodiment is an integrated circuit structure including a first die attached to a second die by a first connector. The first connector includes a solder joint portion between a first nickel-containing layer and a second nickel-containing layer, a first copper-containing layer between the first nickel-containing layer and the solder joint portion, and a second copper-containing layer between the second nickel-containing layer and the solder joint portion.
    Type: Grant
    Filed: August 11, 2014
    Date of Patent: May 26, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jing-Cheng Lin, Cheng-Lin Huang
  • Patent number: 9040407
    Abstract: A method including depositing an alloying layer along a sidewall of an opening and in direct contact with a seed layer, the alloying layer includes a crystalline structure that cannot serve as a seed for plating a conductive material, exposing the opening to an electroplating solution including the conductive material, the conductive material is not present in the alloying layer, applying an electrical potential to a cathode causing the conductive material to deposit from the electroplating solution onto the cathode exposed at the bottom of the opening and causing the opening to fill with the conductive material, the cathode includes an exposed portion of the seed layer and excludes the alloying layer, and forming a first intermetallic compound along an intersection between the alloying layer and the conductive material, the first intermetallic compound is formed as a precipitate within a solid solution of the alloying layer and the conductive material.
    Type: Grant
    Filed: October 1, 2013
    Date of Patent: May 26, 2015
    Assignee: International Business Machines Corporation
    Inventors: Mukta G. Farooq, John A. Fitzsimmons, Troy L. Graves-Abe
  • Patent number: 9035471
    Abstract: A routing layer for a semiconductor die is disclosed. The routing layer includes traces interconnecting integrated circuit bond-pads to UBMs. The routing layer is formed on a layer of dielectric material. The routing layer includes conductive traces arranged underneath the UBMs as to absorb stress from solder bumps attached to the UMBs. Traces beneath the UBMs protect parts of the underlying dielectric material proximate the solder bumps, from the stress.
    Type: Grant
    Filed: February 25, 2014
    Date of Patent: May 19, 2015
    Assignee: ATI Technologies ULC
    Inventors: Roden Topacio, Gabriel Wong
  • Patent number: 9030019
    Abstract: A semiconductor device and a method of making a semiconductor device are disclosed. The semiconductor device comprises a redistribution layer arranged over a chip, the redistribution layer comprising a first redistribution line. The semiconductor further comprises an isolation layer disposed over the redistribution layer, the isolation layer having a first opening forming a first pad area and a first interconnect located in the first opening and in contact with the first redistribution line. The redistribution line in the first pad area is arranged orthogonal to a first direction to a neutral point of the semiconductor device.
    Type: Grant
    Filed: December 14, 2010
    Date of Patent: May 12, 2015
    Assignee: Infineon Technologies AG
    Inventors: Thorsten Meyer, Ludwig Heitzer
  • Patent number: 9018774
    Abstract: A Chip Scale Package (CSP) and a method of forming the same are disclosed. Single chips without the conventional ball mountings, are first attached to an adhesive-substrate (adsubstrate) composite having openings that correspond to the input/output (I/O) pads on the single chips to form a composite chip package. Ball mounting is then performed over the openings, thus connecting the I/O pads at the chip sites to the next level of packaging directly. In another embodiment, the adhesive layer is formed on the wafer side first to form an adwafer, which is then die sawed in CSPs. Then the CSPs with the adhesive already on them are bonded to a substrate. The composite chip package may optionally be encapsulated with a molding material. The CSPs provide integrated and shorter chip connections especially suited for high frequency circuit applications, and can leverage the currently existing test infrastructure.
    Type: Grant
    Filed: September 9, 2008
    Date of Patent: April 28, 2015
    Assignee: Qualcomm Incorporated
    Inventors: Jin-Yuan Lee, Ching-Cheng Huang, Mou-Shiung Lin
  • Patent number: 9018750
    Abstract: Disclosed is a package that includes a wafer substrate and a metal stack seed layer. The metal stack seed layer includes a titanium thin film outer layer. A resist layer is provided in contact with the titanium thin film outer layer of the metal stack seed layer, the resist layer forming circuitry. A method for manufacturing a package is further disclosed. A metal stack seed layer having a titanium thin film outer layer is formed. A resist layer is formed so as to be in contact with the titanium thin film outer layer of the metal stack seed layer, and circuitry is formed from the resist layer.
    Type: Grant
    Filed: August 10, 2012
    Date of Patent: April 28, 2015
    Assignee: Flipchip International, LLC
    Inventors: Robert Forcier, Douglas Scott
  • Patent number: 9006893
    Abstract: An electronic device which in one embodiment comprises a metallization stack is provided. The metallization stack comprises a barrier metal deposited electrolessly and a substantially gold-free wetting layer deposited electrolessly. Additionally, the barrier metal contacts the wetting layer, where the wetting layer is wettable by solder.
    Type: Grant
    Filed: August 22, 2013
    Date of Patent: April 14, 2015
    Assignee: Lam Research Corporation
    Inventors: Artur Kolics, William T. Lee, Fritz Redeker
  • Patent number: 9000594
    Abstract: A contiguous layer of graphene is formed on exposed sidewall surfaces and a topmost surface of a copper-containing structure that is present on a surface of a substrate. The presence of the contiguous layer of graphene on the copper-containing structure reduces copper oxidation and surface diffusion of copper ions and thus improves the electromigration resistance of the structure. These benefits can be obtained using graphene without increasing the resistance of copper-containing structure.
    Type: Grant
    Filed: December 16, 2013
    Date of Patent: April 7, 2015
    Assignee: International Business Machines Corporation
    Inventors: John A. Ott, Ageeth A. Bol