Layered Contact, Lead Or Bond Patents (Class 257/781)
  • Patent number: 11894329
    Abstract: Sacrificial pillars for a semiconductor device assembly, and associated methods and systems are disclosed. In one embodiment, a region of a semiconductor die may be identified to include sacrificial pillars that are not connected to bond pads of the semiconductor die, in addition to live conductive pillars connected to the bond pads. The region with the sacrificial pillars, when disposed in proximity to the live conductive pillars, may prevent an areal density of the live conductive pillars from experiencing an abrupt change that may result in intolerable variations in heights of the live conductive pillars. As such, the sacrificial pillars may improve a coplanarity of the live conductive pillars by reducing variations in the heights of the live conductive pillars. Thereafter, the sacrificial pillars may be removed from the semiconductor die.
    Type: Grant
    Filed: June 27, 2022
    Date of Patent: February 6, 2024
    Assignee: Micron Technology, Inc.
    Inventor: Chao Wen Wang
  • Patent number: 11894330
    Abstract: A method of manufacturing a semiconductor device includes providing a carrier, disposing a first pad on the carrier, forming a post on the first pad, and disposing a joint adjacent to the post and the first pad to form a first entire contact interface between the first pad and the joint and a second entire contact interface between the first pad and the post. The first entire contact interface and the second entire contact interface are flat surfaces.
    Type: Grant
    Filed: March 22, 2021
    Date of Patent: February 6, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chun-Lin Lu, Kai-Chiang Wu, Ming-Kai Liu, Yen-Ping Wang, Shih-Wei Liang, Ching-Feng Yang, Chia-Chun Miao, Hao-Yi Tsai
  • Patent number: 11876004
    Abstract: A printed circuit board according to an embodiment includes: an insulating layer; a first pad disposed on a first surface of the insulating layer; a first conductive layer disposed on the first pad and including gold (Au); a second pad disposed on a second surface of the insulating layer; and a second conductive layer disposed on the second pad and including gold (Au), wherein the first conductive layer is a conductive layer connected to a wire, the second conductive layer is a conductive layer connected to a solder, and the first conductive layer is thicker than the second conductive layer.
    Type: Grant
    Filed: April 21, 2022
    Date of Patent: January 16, 2024
    Assignee: LG INNOTEK CO., LTD.
    Inventors: Sung Oh Cho, Yoon Tai Kim
  • Patent number: 11869862
    Abstract: A microelectronic component comprises a substrate having at least one bond pad on a surface thereof and a metal pillar structure on the at least one bond pad, the metal pillar structure comprising a metal pillar on the at least one bond pad and a solder material having a portion within a reservoir within the metal pillar and another portion protruding from an end of the metal pillar opposite the at least one bond pad. Methods for forming the metal pillar structures, metal pillar structures, assemblies and systems incorporating the metal pillar structures are also disclosed.
    Type: Grant
    Filed: March 4, 2022
    Date of Patent: January 9, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Shams U. Arifeen, Christopher Glancey, Koustav Sinha
  • Patent number: 11862478
    Abstract: A semiconductor device has a semiconductor package including a substrate with a land grid array. A component is disposed over the substrate. An encapsulant is deposited over the component. The land grid array remains outside the encapsulant. A metal mask having a fiducial marker is disposed over the land grid array. A shielding layer is formed over the semiconductor package. The metal mask is removed after forming the shielding layer.
    Type: Grant
    Filed: June 14, 2022
    Date of Patent: January 2, 2024
    Inventors: ChangOh Kim, KyoungHee Park, JinHee Jung, OMin Kwon, JiWon Lee, YuJeong Jang
  • Patent number: 11848261
    Abstract: An apparatus includes a plurality of layers arranged on top of one another and including at least one ground layer and a signal layer; a first set of signal pads and a second set of signal pads on the signal layer; and a slot formed in the at least one ground layer between the first set of signal pads and the second set of signal pads. The apparatus can include an optical assembly housed by the plurality of layers and connected to the first set of signal pads and the second set of signal pads. The optical assembly can include a micro Intradyne Coherent Receiver (?ICR), a Coherent Driver Modulator (CDM), or a Coherent Optical Subassembly (COSA).
    Type: Grant
    Filed: October 5, 2021
    Date of Patent: December 19, 2023
    Assignee: Ciena Corporation
    Inventors: Ramin Deban, Jean-Frédéric Gagné
  • Patent number: 11848282
    Abstract: Semiconductor devices having metallization structures including crack-inhibiting structures, and associated systems and methods, are disclosed herein. In one embodiment, a semiconductor device includes a metallization structure formed over a semiconductor substrate. The metallization structure can include a bond pad electrically coupled to the semiconductor substrate via one or more layers of conductive material, and an insulating material—such as a low-? dielectric material—at least partially around the conductive material. The metallization structure can further include a crack-inhibiting structure positioned beneath the bond pad between the bond pad and the semiconductor substrate. The crack-inhibiting structure can include a barrier member extending vertically from the bond pad toward the semiconductor substrate and configured to inhibit crack propagation through the insulating material.
    Type: Grant
    Filed: August 16, 2022
    Date of Patent: December 19, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Hyunsuk Chun, Sheng Wei Yang, Shams U. Arifeen
  • Patent number: 11837528
    Abstract: A method of manufacturing a semiconductor device includes: forming a base portion of a bonding pad on a semiconductor portion, the base portion further comprising a base layer; forming a main surface of the bonding pad, the main surface comprising a bonding region; bonding a bond wire or clip to the bonding region; and forming a supplemental structure directly on the base portion. The supplemental structure laterally adjoins the bond wire or clip or is laterally spaced apart from the bond wire or clip. A volume-related specific heat capacity of the supplemental structure is higher than a volume-related specific heat capacity of the base layer.
    Type: Grant
    Filed: February 4, 2021
    Date of Patent: December 5, 2023
    Assignee: Infineon Technologies AG
    Inventors: Anton Mauder, Hans-Joachim Schulze
  • Patent number: 11805685
    Abstract: The present application relates to an electronic device. The electronic device includes a first electronic component and a second electronic component. The first electronic component includes a first pad area including first pads and second pads spaced apart from the first pads. A number of the first pads is greater than a number of the second pads. The second electronic component includes first bumps electrically connected to the first pads, and second bumps electrically connected to the second pads. Each of the second bumps has a bonding area greater than a bonding area of each of the first bumps. A conductive adhesive layer is disposed between the first electronic component and the second electronic component to electrically connect the first pads to the first bumps.
    Type: Grant
    Filed: March 18, 2021
    Date of Patent: October 31, 2023
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Youngmin Cho, Hongam Kim
  • Patent number: 11791313
    Abstract: A semiconductor package includes a semiconductor die and a redistribution structure. The semiconductor die is laterally surrounded by a molding compound, and the semiconductor die has a conductive pillar and a complex compound sheath sandwiched between the conductive pillar and the molding compound. The redistribution structure is electrically connected with the semiconductor die and comprises a first via portion at a first side of the redistribution structure and a second via portion at a second side of the redistribution structure, and a base angle of the second via portion is greater than a base angle of the first via portion.
    Type: Grant
    Filed: August 9, 2022
    Date of Patent: October 17, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Chih Chen, Hung-Jui Kuo, Yu-Hsiang Hu, Sih-Hao Liao, Hung-Chun Cho
  • Patent number: 11764156
    Abstract: Example embodiments relate to a layer structure having a diffusion barrier layer, and a method of manufacturing the same. The layer structure includes first and second material layers and a diffusion barrier layer therebetween. The diffusion barrier layer includes a nanocrystalline graphene (nc-G) layer. In the layer structure, the diffusion barrier layer may further include a non-graphene metal compound layer or a graphene layer together with the nc-G layer. One of the first and second material layers is an insulating layer, a metal layer, or a semiconductor layer, and the remaining layer may be a metal layer.
    Type: Grant
    Filed: June 29, 2021
    Date of Patent: September 19, 2023
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyunjae Song, Seunggeol Nam, Yeonchoo Cho, Seongjun Park, Hyeonjin Shin, Jaeho Lee
  • Patent number: 11756882
    Abstract: A semiconductor package includes a metallic pad and leads, a semiconductor die including a semiconductor substrate attached to the metallic pad, and a conductor including a sacrificial fuse element above the semiconductor substrate, the sacrificial fuse element being electrically coupled between one of the leads and at least one terminal of the semiconductor die, and a multilayer dielectric between the sacrificial fuse element and the semiconductor substrate, the multilayer dielectric forming one or more planar gaps beneath a profile of the sacrificial fuse element.
    Type: Grant
    Filed: December 31, 2020
    Date of Patent: September 12, 2023
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Enis Tuncer, Alejandro Hernandez-Luna
  • Patent number: 11749652
    Abstract: A display panel including a circuit board having first pads, light emitting devices disposed on the circuit board and having second pads and including at least one first light emitting device to emit light having a first peak wavelength and second light emitting devices to emit light having a second peak wavelength, and a metal bonding layer electrically connecting the first pads and the second pads, in which the metal bonding layer of the first light emitting device has a thickness different from that of the metal bonding layer of the second light emitting devices while including a same material, and an upper surface of the second light devices are disposed at an elevation between an upper surface and a bottom surface of the first light emitting device.
    Type: Grant
    Filed: November 20, 2022
    Date of Patent: September 5, 2023
    Assignee: SEOUL VIOSYS CO., LTD.
    Inventors: Jong Hyeon Chae, Ik Kyu You, Seom Geun Lee, Seong Kyu Jang, Yong Woo Ryu
  • Patent number: 11713248
    Abstract: A method of selectively growing graphene includes forming an ion implantation region and an ion non-implantation region by implanting ions locally into a substrate; and selectively growing graphene in the ion implantation region or the ion non-implantation region.
    Type: Grant
    Filed: December 30, 2020
    Date of Patent: August 1, 2023
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Changseok Lee, Changhyun Kim, Kyung-Eun Byun, Keunwook Shin, Hyeonjin Shin, Eunkyu Lee
  • Patent number: 11699678
    Abstract: A semiconductor device has a semiconductor wafer including a plurality of semiconductor die and a plurality of contact pads formed over a first surface of the semiconductor wafer. A trench is formed partially through the first surface of the semiconductor wafer. An insulating material is disposed over the first surface of the semiconductor wafer and into the trench. A conductive layer is formed over the contact pads. The conductive layer can be printed to extend over the insulating material in the trench between adjacent contact pads. A portion of the semiconductor wafer opposite the first surface of the semiconductor wafer is removed to the insulating material in the trench. An insulating layer is formed over a second surface of the semiconductor wafer and side surfaces of the semiconductor wafer. The semiconductor wafer is singulated through the insulating material in the first trench to separate the semiconductor die.
    Type: Grant
    Filed: November 5, 2020
    Date of Patent: July 11, 2023
    Assignee: Semtech Corporation
    Inventors: Satyamoorthi Chinnusamy, Kevin Simpson, Mark C. Costello
  • Patent number: 11694982
    Abstract: Disclosed are examples of integrated circuit (IC) structures and techniques to fabricate IC structures. Each IC package may include a die (e.g., a flip-chip (FC) die) and one or more die interconnects to electrically couple the die to a substrate. The die interconnect may include a pillar, a wetting barrier on the pillar, and a solder cap on the wetting barrier. The wetting barrier may be wider than the pillar. The die interconnect may also include a low wetting layer formed on the wetting barrier.
    Type: Grant
    Filed: February 25, 2021
    Date of Patent: July 4, 2023
    Assignee: QUALCOMM INCORPORATED
    Inventors: Wei Hu, Dongming He, Wen Yin, Zhe Guan, Lily Zhao
  • Patent number: 11688668
    Abstract: A component carrier includes a stack having at least one electrically conductive layer structure and/or at least one electrically insulating layer structure. At least part of the at least one electrically insulating layer structure comprises or consists of a material having a curing shrinkage value of less than 2%.
    Type: Grant
    Filed: October 30, 2020
    Date of Patent: June 27, 2023
    Assignee: AT&S (China) Co. Ltd.
    Inventors: Mikael Tuominen, Seok Kim Tay
  • Patent number: 11682646
    Abstract: An integrated circuit (IC) chip package includes a substrate and a wafer comprising an IC chip arranged on the substrate. The substrate includes first mounting pads unconnected to electrical connections in the substrate. The wafer includes second mounting pads that are disposed around corners of the IC chip, that extend radially outward relative to circuitry in the IC chip, that are unconnected to circuitry in the IC chip, and that mate with the first mounting pads on the substrate, respectively.
    Type: Grant
    Filed: November 2, 2021
    Date of Patent: June 20, 2023
    Assignee: MARVELL ASIA PTE LTD.
    Inventors: Manish Nayini, Richard S. Graf, Janak G. Patel, Nazmul Habib
  • Patent number: 11670573
    Abstract: Semiconductor devices and methods of forming the same are provided. In one embodiment, a semiconductor device includes a redistribution layer including a first conductive feature and a second conductive feature, a first contact feature disposed over and electrically coupled to the first conductive feature, a second contact feature disposed over and electrically coupled to the second conductive feature, and a passivation feature extending from between the first conductive feature and the second conductive feature between the first contact feature and the second contact feature. The passivation feature includes a dielectric feature and a dielectric layer. The dielectric layer is disposed on a planar top surface of the dielectric feature and a composition of the dielectric feature is different from a composition of the dielectric layer.
    Type: Grant
    Filed: June 3, 2021
    Date of Patent: June 6, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsiang-Ku Shen, Chun-Li Lin, Dian-Hau Chen
  • Patent number: 11646279
    Abstract: A semiconductor structure may be provided, including a conductive pad, a slot arranged through the conductive pad, a passivation layer arranged over the conductive pad and a plurality of electrical interconnects arranged under the conductive pad. The conductive pad may include an electrically conductive material and the slot may include an electrically insulating material. The passivation layer may include an opening that may expose a portion of the conductive pad and the slot may be arranged laterally between the exposed portion of the conductive pad and the plurality of electrical interconnects.
    Type: Grant
    Filed: February 25, 2021
    Date of Patent: May 9, 2023
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Xiaodong Li, Ramasamy Chockalingam, Juan Boon Tan
  • Patent number: 11640193
    Abstract: A system-on-a-chip (“SoC”) in a computing device may be provided with a power delivery network (“PDN”) self-test to detect marginal PDN performance. In the self-test, a current surge may be generated on power supply connections of logic circuit blocks. Voltage monitors may measure voltage droop on the power supply connections responsive to the current surge. Voltage droop measurements may be compared with thresholds. An action, such as generation of an alert, may be performed if a voltage droop measurement exceeds a threshold.
    Type: Grant
    Filed: September 24, 2021
    Date of Patent: May 2, 2023
    Assignee: QUALCOMM Incorporated
    Inventors: Kunal Desai, Ankit Shambhu, Srinivas Maddali, Sanjeev Shukla
  • Patent number: 11615963
    Abstract: An electronic device, an electronic module comprising the electronic device and methods for fabricating the same are disclosed. In one example, the electronic device includes a semiconductor substrate and a metal stack disposed on the semiconductor substrate, wherein the metal stack comprises a first layer, wherein the first layer comprises NiSi.
    Type: Grant
    Filed: July 10, 2020
    Date of Patent: March 28, 2023
    Assignee: Infineon Technologies AG
    Inventors: Paul Frank, Gretchen Adema, Thomas Bertaud, Michael Ehmann, Eric Graetz, Kamil Karlovsky, Evelyn Napetschnig, Werner Robl, Tobias Schmidt, Joachim Seifert, Frank Wagner, Stefan Woehlert
  • Patent number: 11574882
    Abstract: A method of manufacturing a semiconductor device includes: forming a conductive pad region over a substrate; depositing a dielectric layer over the conductive pad region; forming a first passivation layer over the dielectric layer; etching the first passivation layer through the dielectric layer, thereby exposing a first area of the conductive pad region; forming a second passivation layer over the first area of the conductive pad region; and removing portions of the second passivation layer to expose a second area of the conductive pad region.
    Type: Grant
    Filed: November 3, 2020
    Date of Patent: February 7, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company Ltd.
    Inventors: Hung-Shu Huang, Ming-Chyi Liu
  • Patent number: 11552066
    Abstract: A bonded assembly of a first wafer including a first semiconductor substrate and a second wafer including a second semiconductor substrate may be formed. The second semiconductor substrate may be thinned to a first thickness, and an inter-wafer moat trench may be formed at a periphery of the bonded assembly. A protective material layer may be formed in the inter-wafer moat trench and over the backside surface of the second semiconductor substrate. A peripheral portion of the second semiconductor substrate located outside the inter-wafer moat trench may be removed, and a cylindrical portion of the protective material layer laterally surrounds a remaining portion of the bonded assembly. The second semiconductor substrate may be thinned to a second thickness by performing at least one thinning process while the cylindrical portion of the protective material layer protects the remaining portion of the bonded assembly.
    Type: Grant
    Filed: February 22, 2021
    Date of Patent: January 10, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Kuo-Ming Wu, Ming-Che Lee, Hau-Yi Hsiao, Cheng-Hsien Chou, Sheng-Chau Chen, Cheng-Yuan Tsai
  • Patent number: 11538726
    Abstract: A method for forming a packaged electronic die includes forming a plurality of bonding pads on a device wafer. A photoresist layer is deposited over the device wafer and is patterned so as to form a photoresist frame that completely surrounds a device formed on the device wafer. Conductive balls are deposited over the bonding pads. The wafer is cut to form the electronic die and the electronic die is placed over the substrate. The conductive balls are heated and compressed, moving the electronic die closer to the substrate such that the photoresist frame is in direct contact with the substrate or with a landing pad formed on the substrate. Encapsulant material is deposited such that the encapsulant material covers the electronic die and the substrate. The encapsulant material is cured so as to encapsulate the electronic die. The substrate is cut to separate the packaged electronic die.
    Type: Grant
    Filed: December 20, 2021
    Date of Patent: December 27, 2022
    Assignee: Microchip Technology Inc.
    Inventors: Matthias Klein, Andreas Zakrzewski, Richard Gruenwald
  • Patent number: 11538778
    Abstract: A semiconductor package and a method for manufacturing a semiconductor package are provided. The semiconductor package includes a first semiconductor device, a second semiconductor device, and an alignment material. The first semiconductor device has a first bonding layer, and the first bonding layer includes a first bond pad contacting an organic dielectric material. The second semiconductor device has a second bonding layer, and the second bonding layer includes a second bond pad contacting the organic dielectric material. The alignment material is between the first bonding layer and the second bonding layer.
    Type: Grant
    Filed: December 18, 2020
    Date of Patent: December 27, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Hsu-Nan Fang
  • Patent number: 11532582
    Abstract: Semiconductor devices and methods of manufacture are described herein. The methods include forming a local organic interconnect (LOI) by forming a stack of conductive traces embedded in a passivation material, forming first and second local contacts over the passivation material, the second local contact being electrically coupled to the first local contact by a first conductive trace of the stack. The methods further include forming a backside redistribution layer (RDL) and a front side RDL on opposite sides of the LOI with TMVs electrically coupling the backside and front side RDLs to one another. First and second external contacts are formed over the backside RDL for mounting of semiconductor devices, the first and second external contacts being electrically connected to one another by the LOI. An interconnect structure is attached to the front side RDL for further routing. External connectors electrically coupled to the external contacts at the backside RDL.
    Type: Grant
    Filed: August 25, 2020
    Date of Patent: December 20, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jiun Yi Wu, Chen-Hua Yu
  • Patent number: 11495729
    Abstract: Highly deformable heterostructures utilizing liquid metals and nanostructures that are suitable for various applications, including but not limited to stretchable electronic devices that can be worn, for example, by a human being. Such a deformable heterostructure includes a stretchable substrate, a conductive liquid metal on the substrate, and nanostructures forming a solid-liquid heterojunction with the conductive liquid metal.
    Type: Grant
    Filed: November 6, 2018
    Date of Patent: November 8, 2022
    Assignee: Purdue Research Foundation
    Inventors: Wenzhuo Wu, Ruoxing Wang
  • Patent number: 11482502
    Abstract: A semiconductor device includes a substrate that includes a first insulating layer, a conductive layer on the first insulating layer, a second insulating layer on the conductive layer, and an opening that passes through the conductive layer and the second insulating layer and in which part of the conductive layer is exposed, a conductive material that contacts at least the first insulating layer and the part of the conductive layer in the opening, and a semiconductor chip that has an electrode extending towards the first insulating layer within the opening and contacting the conductive material.
    Type: Grant
    Filed: August 31, 2020
    Date of Patent: October 25, 2022
    Assignee: KIOXIA CORPORATION
    Inventor: Keiichi Niwa
  • Patent number: 11456280
    Abstract: A semiconductor package includes a first die, a second die, a molding compound and a redistribution structure. The first die has a first conductive pillar and a first complex compound sheath surrounding and covering a sidewall of the first conductive pillar. The second die has a second conductive pillar and a protection layer laterally surrounding the second conductive pillar. The molding compound laterally surrounds and wraps around the first and second dies, and is in contact with the first complex compound sheath of the first die. The redistribution structure is disposed on the first and second dies and the molding compound.
    Type: Grant
    Filed: November 9, 2020
    Date of Patent: September 27, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Chih Chen, Hung-Jui Kuo, Yu-Hsiang Hu, Sih-Hao Liao, Hung-Chun Cho
  • Patent number: 11444037
    Abstract: Semiconductor devices having metallization structures including crack-inhibiting structures, and associated systems and methods, are disclosed herein. In one embodiment, a semiconductor device includes a metallization structure formed over a semiconductor substrate. The metallization structure can include a bond pad electrically coupled to the semiconductor substrate via one or more layers of conductive material, and an insulating material—such as a low-? dielectric material—at least partially around the conductive material. The metallization structure can further include a crack-inhibiting structure positioned beneath the bond pad between the bond pad and the semiconductor substrate. The crack-inhibiting structure can include a barrier member extending vertically from the bond pad toward the semiconductor substrate and configured to inhibit crack propagation through the insulating material.
    Type: Grant
    Filed: September 3, 2020
    Date of Patent: September 13, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Hyunsuk Chun, Sheng Wei Yang, Shams U. Arifeen
  • Patent number: 11430776
    Abstract: Packaged devices and methods of manufacturing the devices are described herein. The packaged devices may be fabricated using heterogeneous devices and asymmetric dual-side molding on a multi-layered redistribution layer (RDL) structure. The packaged devices may be formed with a heterogeneous three-dimensional (3D) Fan-Out System-in-Package (SiP) structure having small profiles and can be formed using a single carrier substrate.
    Type: Grant
    Filed: June 15, 2020
    Date of Patent: August 30, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yi-Wen Wu, Po-Yao Chuang, Meng-Liang Lin, Techi Wong, Shih-Ting Hung, Po-Hao Tsai, Shin-Puu Jeng
  • Patent number: 11404390
    Abstract: Sacrificial pillars for a semiconductor device assembly, and associated methods and systems are disclosed. In one embodiment, a region of a semiconductor die may be identified to include sacrificial pillars that are not connected to bond pads of the semiconductor die, in addition to live conductive pillars connected to the bond pads. The region with the sacrificial pillars, when disposed in proximity to the live conductive pillars, may prevent an areal density of the live conductive pillars from experiencing an abrupt change that may result in intolerable variations in heights of the live conductive pillars. As such, the sacrificial pillars may improve a coplanarity of the live conductive pillars by reducing variations in the heights of the live conductive pillars. Thereafter, the sacrificial pillars may be removed from the semiconductor die.
    Type: Grant
    Filed: June 30, 2020
    Date of Patent: August 2, 2022
    Assignee: Micron Technology, Inc.
    Inventor: Chao Wen Wang
  • Patent number: 11398389
    Abstract: Provided is a method of producing an electronic device, including a step of preparing a structure which includes an electronic component having a circuit forming surface, and an adhesive laminated film which includes a base material layer and an adhesive resin layer and in which the adhesive resin layer is attached to the circuit forming surface of the electronic component; a step of back-grinding a surface of the electronic component opposite to the circuit forming surface in a state of being attached to the adhesive laminated film; a step of dicing the electronic component in a state of being attached to the adhesive laminated film; and a step of forming an electromagnetic wave-shielding layer on the separated electronic components in a state of being attached to the adhesive laminated film, in this order.
    Type: Grant
    Filed: July 9, 2018
    Date of Patent: July 26, 2022
    Assignee: MITSUI CHEMICALS TOHCELLO, INC.
    Inventors: Takashi Unezaki, Jun Kamada, Akimitsu Morimoto, Jin Kinoshita
  • Patent number: 11398440
    Abstract: An integrated circuit structure includes a metal pad, a passivation layer including a portion over the metal pad, a first polymer layer over the passivation layer, and a first Post-Passivation Interconnect (PPI) extending into to the first polymer layer. The first PPI is electrically connected to the metal pad. A dummy metal pad is located in the first polymer layer. A second polymer layer is overlying the first polymer layer, the dummy metal pad, and the first PPI. An Under-Bump-Metallurgy (UBM) extends into the second polymer layer to electrically couple to the dummy metal pad.
    Type: Grant
    Filed: October 22, 2018
    Date of Patent: July 26, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hao-Hsiang Chuang, Shih-Wei Liang, Ching-Feng Yang, Kai-Chiang Wu, Hao-Yi Tsai, Chuei-Tang Wang, Chen-Hua Yu
  • Patent number: 11315862
    Abstract: A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes a redistribution structure, a circuit substrate, and an insulating encapsulation. The redistribution structure includes a first under-bump metallization (UBM) pattern covered by a first dielectric layer, and the first UBM pattern includes a surface substantially leveled with a surface of the first dielectric layer. The circuit substrate is electrically coupled to the redistribution structure through a conductive joint disposed on the surface of the first UBM pattern. The insulating encapsulation is disposed on the redistribution structure to cover the circuit substrate.
    Type: Grant
    Filed: June 29, 2020
    Date of Patent: April 26, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuan-Lin Ho, Chin-Liang Chen, Jiun-Yi Wu, Chi-Yang Yu, Yu-Min Liang, Wei-Yu Chen
  • Patent number: 11309268
    Abstract: A method of designing a layout includes determining a first layout pattern, wherein the first layout pattern corresponds to a plurality of contact pads. The method further includes generating a second layout pattern. The method further includes checking whether an edge of the second layout pattern overlaps the first layout pattern. The method further includes adjusting the second layout pattern so that the edge of the second layout pattern overlaps the first layout pattern in response to a determination that the edge of the second layout pattern is separated from the first layout pattern.
    Type: Grant
    Filed: June 17, 2020
    Date of Patent: April 19, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Gulbagh Singh, Chih-Ming Lee, Chi-Yen Lin, Wen-Chang Kuo, C. C. Liu
  • Patent number: 11295997
    Abstract: A method of manufacturing a semiconductor device prepares contact members, each of which has a cylindrical through-hole, and column-shaped connection terminals, each having a polygonal shape in a cross-sectional view along a length direction thereof, wherein a length of a diagonal of the polygonal shape is greater than an inner diameter of the through-holes. Chamfers with a curvature for fitting an inner surface of the through-holes are formed at corners of the connection terminal, and the connection terminals are press-fitted into the through-holes of the contacts. By doing so, the area of contact where the connection terminals press-fitted into the contacts contact the inner circumferential surfaces of the through-holes of the contacts is increased. This increases the tensile load of the connection terminals fitted into the contacts.
    Type: Grant
    Filed: May 26, 2020
    Date of Patent: April 5, 2022
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Rikihiro Maruyama, Masaoki Miyakoshi
  • Patent number: 11217558
    Abstract: A method and a device for establishing a wire connection between a first contact surface and at least one further contact surface. A contact end of a wire is positioned in a contact position relative to the first contact surface with a wire guiding tool. Subsequently, a mechanical, electrically conductive connection is established between the first contact surface and the contact end with a first solder material connection, and subsequently the wire guiding tool is moved to the further contact surface thus forming a wire section and establishing a further mechanical, electrically conductive connection between the wire section end and the further contact surface with a further solder material connection.
    Type: Grant
    Filed: March 15, 2018
    Date of Patent: January 4, 2022
    Assignee: PAC TECH—PACKAGING TECHNOLOGIES GMBH
    Inventors: Andrej Kolbasow, Jan Hoffmann, Matthias Fettke
  • Patent number: 11177233
    Abstract: An optoelectronic semiconductor chip includes a rear side with a center and with two contact points for electrical contacting of the semiconductor chip, the contact points being spaced apart from one another, and two solder pads arranged on the contact points, wherein the center is located in a region between the contact points, the solder pads protrude from the rear side and are exposed, and on average, the solder pads are thicker further away from the center than in the vicinity of the center or vice versa.
    Type: Grant
    Filed: November 10, 2017
    Date of Patent: November 16, 2021
    Assignee: OSRAM OLED GmbH
    Inventors: Christian Leirer, Martin Rudolf Behringer
  • Patent number: 11171104
    Abstract: An IC chip package includes a substrate having a plurality of interconnect metal pads, and a chip having a plurality of interconnect metal pads arranged thereon. An interconnect solder structure electrically connects each of the plurality of interconnect metal pads. The chip is devoid of the interconnect solder structures and interconnect metal pads at one or more corners of the chip. Rather, a dummy solder structure connects the IC chip to the substrate at each of the one or more corners of the IC chip, and the dummy solder structure is directly under at least one side of the IC chip at the one or more corners of the IC chip. The dummy solder structure has a larger volume than a volume of each of the plurality of interconnect solder structures. The dummy solder structure eliminates a chip-underfill interface at corner(s) of the chip where delamination would occur.
    Type: Grant
    Filed: October 24, 2019
    Date of Patent: November 9, 2021
    Assignee: MARVELL ASIA PTE, LTD.
    Inventors: Manish Nayini, Richard S. Graf, Janak G. Patel, Nazmul Habib
  • Patent number: 11121108
    Abstract: A flip chip package includes a substrate having a die attach surface, and a die mounted on the die attach surface with an active surface of the die facing the substrate. The die includes a base, a passivation layer overlying the base, a topmost metal layer overlying the passivation, and a stress buffering layer overlying the topmost metal layer, wherein at least two openings are disposed in the stress buffering layer to expose portions of the topmost metal layer. The die is interconnected to the substrate through a plurality of conductive pillar bumps on the active surface. At least one of the conductive pillar bumps is electrically connected to one of the exposed portions of the topmost metal layer through one of the at least two openings.
    Type: Grant
    Filed: May 31, 2020
    Date of Patent: September 14, 2021
    Assignee: MediaTek Inc.
    Inventors: Tzu-Hung Lin, Thomas Matthew Gregorich
  • Patent number: 11121050
    Abstract: In order to prevent cracks from occurring at the corners of semiconductor dies after the semiconductor dies have been bonded to other substrates, an opening is formed adjacent to the corners of the semiconductor dies, and the openings are filled and overfilled with a buffer material that has physical properties that are between the physical properties of the semiconductor die and an underfill material that is placed adjacent to the buffer material.
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: September 14, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuan-Yu Huang, Chih-Wei Wu, Li-Chung Kuo, Long Hua Lee, Sung-Hui Huang, Ying-Ching Shih, Pai Yuan Li
  • Patent number: 11049800
    Abstract: In a described example, a method for making a packaged semiconductor device includes laser ablating a first groove with a first width and a first depth into a mounting surface of a substrate between landing pads. A first pillar bump on an active surface of a semiconductor device is bonded to a first landing pad; and a second pillar bump on the semiconductor device is bonded to a second landing pad. A channel forms with the active surface of the semiconductor device forming a first wall of the channel, the first pillar bump forms a second wall of the channel, the second pillar bump forming a third wall of the channel, and a surface of the first groove forms a fourth wall of the channel. The channel is filled with mold compound and at least a portion of the substrate and the semiconductor device are covered with mold compound.
    Type: Grant
    Filed: February 25, 2020
    Date of Patent: June 29, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Dolores Babaran Milo, Cherry Lyn Marquez Aranas
  • Patent number: 10811365
    Abstract: Semiconductor devices having metallization structures including crack-inhibiting structures, and associated systems and methods, are disclosed herein. In one embodiment, a semiconductor device includes a metallization structure formed over a semiconductor substrate. The metallization structure can include a bond pad electrically coupled to the semiconductor substrate via one or more layers of conductive material, and an insulating material—such as a low-? dielectric material—at least partially around the conductive material. The metallization structure can further include a crack-inhibiting structure positioned beneath the bond pad between the bond pad and the semiconductor substrate. The crack-inhibiting structure can include (a) a metal lattice extending laterally between the bond pad and the semiconductor substrate and (b) barrier members extending vertically between the metal lattice and the bond pad.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: October 20, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Shams U. Arifeen, Hyunsuk Chun, Sheng Wei Yang, Keizo Kawakita
  • Patent number: 10727191
    Abstract: A semiconductor structure includes a first contact pad over a passivation layer, wherein the first contact pad is in a circuit region. The semiconductor structure further includes a plurality of second contact pads over the passivation layer, wherein each second contact pad of the plurality of second contact pads is in a non-circuit region. The semiconductor structure further includes a first buffer layer over the first contact pad and over a first second contact pad of the plurality of second contact pads. The semiconductor structure further includes a second buffer layer over the first buffer layer, the first contact pad, the first second contact pad and a portion of a second second contact pad of the plurality of second contact pads, wherein the second buffer layer exposes a portion of the second second contact pad of the plurality of second contact pads.
    Type: Grant
    Filed: December 24, 2018
    Date of Patent: July 28, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Gulbagh Singh, Chih-Ming Lee, Chi-Yen Lin, Wen-Chang Kuo, C. C. Liu
  • Patent number: 10727114
    Abstract: Integrated circuits including at least two electrically conductive interconnect lines and methods of manufacturing generally include a surface of the integrated circuit. At least two electrically conductive interconnect lines are separated by a space of less than 90 nm and are formed on the surface. Each of the at least two interconnect lines includes a metal cap, a copper conductor having an average grain size greater than a line width of the interconnect. A liner layer is provided, wherein the liner layer and the metal cap encapsulate the copper conductor. A dielectric layer overlaying the at least two electrically conductive interconnect lines and extending along sidewalls thereof is provided, wherein the dielectric layer is configured to provide an airgap between the at least two interconnect lines at the spacing.
    Type: Grant
    Filed: January 13, 2017
    Date of Patent: July 28, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Robert L. Bruce, Alfred Grill, Eric A. Joseph, Teddie P. Magbitang, Hiroyuki Miyazoe, Deborah A. Neumayer
  • Patent number: 10656738
    Abstract: A touch panel includes at least one touch sensing layer, a first metal layer, a second metal layer, a through hole, a metal film, and a conductive structure. The first and second metal layers are respectively located above and below the touch sensing layer. The through hole penetrates through the first metal layer, the touch sensing layer, and the second metal layer. The through hole has a first opening and a second opening. The metal film is on a bottom surface of the second metal layer and covers the second opening of the through hole. The conductive structure is located on the metal film and in the through hole. An end of the conductive structure adjacent to the first opening has a microstructure. The microstructure extends to a top surface of the first metal layer and surrounds the first opening of the through hole.
    Type: Grant
    Filed: January 7, 2019
    Date of Patent: May 19, 2020
    Assignees: INTERFACE TECHNOLOGY (CHENGDU) CO., LTD., INTERFACE OPTOELECTRONICS (SHENZHEN) CO., LTD., GENERAL INTERFACE SOLUTION LIMITED
    Inventor: Yi-Hung Ho
  • Patent number: 10381312
    Abstract: Disclosed herein are a semiconductor package and a method of manufacturing the same. The semiconductor package according to embodiments of the present disclosure includes a wiring including a plurality of layers including an insulating layer and a wiring layer, a semiconductor chip mounted on the wiring and electrically connected to the wiring layer through a bonding pad, a cover member configured to cover side surfaces of the semiconductor chip and the wiring and be in contact with at least one wiring layer, and an encapsulant configured to seal the cover member. Accordingly, the cover member covers the semiconductor chip and is in contact with the wiring formed under the semiconductor chip, thereby reducing electromagnetic interference, minimizing noise between operations of the semiconductor package, and improving a signal speed.
    Type: Grant
    Filed: May 11, 2017
    Date of Patent: August 13, 2019
    Assignee: NEPES CO., LTD.
    Inventors: Il-Hwan Kim, Jun-Kyu Lee, Min-A Yoon, Dong-Hoon Oh, Tae-Won Kim
  • Patent number: 10340295
    Abstract: A flexible display device includes a substrate and a border unit. The substrate has a display area and a border area that surrounds the display area. The border unit is located in the border area and includes a first metal layer on the substrate, an insulation layer covering the first metal layer and the substrate, a second metal layer on the insulation layer, a protection layer covering the second metal layer and the insulation layer, a semiconductor layer between the insulation layer and the protection layer, a planarization layer covering the protection layer, and a third metal layer on the planarization layer. The third metal layer has a first part, a second part, and a third part that is between and physically connected to the first and second parts. A notch is defined by the first, second, and third parts.
    Type: Grant
    Filed: August 7, 2018
    Date of Patent: July 2, 2019
    Assignee: E Ink Holdings Inc.
    Inventors: Yi-Lung Wen, Jia-Hung Chen, Kuang-Heng Liang, Chi-Ming Wu