Abstract: One example provides a circuit structure comprising a liquid metal conductive path enclosed in an encapsulant, a polymer circuit support comprising a polymer having a functional species available for a condensation reaction, and a cross-linking agent covalently bonding the encapsulant to the polymer circuit support via the functional species.

Abstract: A system, method, and apparatus for layered bonded structures formed from reactive bonding between zinc metal and zinc peroxide are disclosed herein. In particular, the present disclosure teaches a layered bonded structure wherein two structures are bonded together with a layer including zinc oxide. The zinc oxide is formed through a method that includes processing the two structures by contacting the structures under pressure and applying heat to the structures to promote a reaction with zinc peroxide and zinc metal on one or both of the two structures.

Abstract: A resin-sealed semiconductor device 10 of the present invention includes: a mesa-type semiconductor element 100 which includes a mesa-type semiconductor base body having a pn-junction exposure portion in an outer peripheral tapered region which surrounds a mesa region, and a glass layer which covers at least the outer peripheral tapered region; and a molding resin 40 which seals the mesa-type semiconductor element 100, wherein the mesa-type semiconductor element 100 includes a glass layer which substantially contains no Pb as the glass layer. The resin-sealed semiconductor device of the present invention can acquire higher resistance to a reverse bias at a high temperature than a conventional resin-sealed semiconductor device, although the resin-sealed semiconductor device of the present invention has the structure where the mesa-type semiconductor element is molded with a resin in the same manner as the conventional resin-sealed semiconductor device.

Abstract: A glass composition for protecting a semiconductor junction is made of fine glass particles prepared from a material in a molten state obtained by melting a glass raw material which contains at least ZnO, SiO2, B2O3, Al2O3 and at least two oxides of alkaline earth metals selected from a group consisting of BaO, CaO and MgO and substantially contains none of Pb, As, Sb, Li, Na and K, the glass composition for protecting a semiconductor junction containing no filler.

Abstract: Acoustic wave devices and methods of coating a protective film of alumina (Al2O3) on the acoustic wave devices are disclosed herein. The protective film is applied through an atomic layer deposition (ALD) process. The ALD process can deposit very thin layers of alumina on the surface of the acoustic wave devices in a precisely controlled manner. Thus, the uniform film does not significantly distort the operation of the acoustic wave device.

Abstract: A resin-sealed semiconductor device includes a mesa-type semiconductor element which includes a mesa-type semiconductor base body having a pn junction exposure portion in an outer peripheral tapered region surrounding a mesa region, and a glass layer which covers at least the outer peripheral tapered region; and a molding resin which seals the mesa-type semiconductor element, wherein the glass layer is formed by forming a layer made of a predetermined glass composition for protecting a semiconductor junction which substantially contains no Pb such that the layer covers the outer peripheral tapered region and, subsequently, by baking the layer made of the glass composition for protecting a semiconductor junction.

Abstract: Provided is a glass composition for protecting a semiconductor junction which contains at least SiO2, B2O3, Al2O3, ZnO and at least two oxides of alkaline earth metals selected from a group consisting of CaO, MgO and BaO, and substantially contains none of Pb, As, Sb, Li, Na and K, wherein an average linear expansion coefficient within a temperature range of 50° C. to 550° C. falls within a range of 3.33×10?6 to 4.13×10?6. A semiconductor device having high breakdown strength can be manufactured using such a glass material containing no lead in the same manner as a conventional case where “a glass material containing lead silicate as a main component” is used.

Abstract: A sealing glass, a sealing material, and a sealing material paste, which suppress metal deposition by reducing glass components (metal oxides) without decreasing the reactivity with and the adhesion to a semiconductor substrate. The sealing glass, contains a low temperature melting glass containing, by mass ratio: from 0.1 to 5% of at least one metal oxide selected from the group consisting of Fe, Mn, Cr, Co, Ni, Nb, Hf, W, Re, a rare earth element, and optionally Mo; and from 5 to 100 ppm by mass ratio of K2O, wherein the low temperature melting glass has a softening point of at most 430° C. The sealing material device, contains the sealing glass and an inorganic filler in an amount of from 0 to 40% by volume ratio. The sealing material paste contains a mixture of the sealing material and a vehicle.

Abstract: An assembly includes an integrated circuit die coupled to another component of the assembly with an alkali silicate glass material. The alkali silicate material may include particles for modifying the thermal, mechanical, and/or electrical characteristics of the material.

Abstract: A system and method for determining underfill expansion is provided. An embodiment comprises forming cover marks along a top surface of a substrate, attaching a semiconductor substrate to the top surface of the substrate, placing an underfill material between the semiconductor substrate and the substrate, and then using the cover marks to determine the expansion of the underfill over the top surface of the substrate. Additionally, cover marks may also be formed along a top surface of the semiconductor substrate, and the cover marks on both the substrate and the semiconductor substrate may be used together as alignment marks during the alignment of the substrate and the semiconductor substrate.

Abstract: A semiconductor device includes a carrier and a first chip attached to the carrier. The semiconductor device includes a sintered insulation material over at least a portion of the carrier and the first chip.

Abstract: A manufacturing method of a semiconductor device includes: sealing a semiconductor chip with a sealing resin containing a filler; exposing a part of the filler; etching at least a part of the exposed filler; and forming a metal film at least at a part of a surface of the sealing resin including inner surfaces of holes formed at the surface of the sealing resin by the etching.

Abstract: A packaging layer (200) for a wafer level assembly is fabricated from a glass material comprising both inorganic and organic components. This allows matching between the coefficient of thermal expansion of the packaging layer and that of other materials in the wafer assembly, particularly electrical interconnect materials. It is also possible to introduce properties to support such methods as photolithographic and low temperature processing of the packaging layer. This can improve fabrication accuracy and allows the packaging layer to be used with structures in a wafer assembly which might be damaged by high temperature processing, such as active optoelectronic devices and integrated circuits. Another major advantage is that the glass material can be used to provide optical characteristics as well as mechanical protection. The refractive index and other optical properties can be preselected and thus the glass material can be used for instance for waveguiding and index matching.

Abstract: Semiconductor component and method for production of a semiconductor component. The invention relates to a semiconductor component having a semiconductor chip, which is arranged on a substrate, in one embodiment on a chip carrier, and an encapsulation material, which at least partially surrounds the semiconductor chip. The chip carrier is at least partly provided with a layer of polymer foam.

Abstract: A semiconductor die is attached to a substrate by a glass frit layer. Gas that might be trapped between the die and the glass frit layer during firing of the glass frit can escape through passages that are formed against the bottom surface of the die by topographies that extend away from and which are substantially orthogonal to the bottom of the die.

Abstract: A patterned adhesive layer including holes is employed to attach a coreless substrate layer to a stiffner. The patterned adhesive layer is confined to kerf regions, which are subsequently removed during singulation. Each hole in the patterned adhesive layer has an area that is greater than the area of a bottomside interconnect footprint of the coreless substrate. The patterned adhesive layer may include a permanent adhesive that is thermally curable or ultraviolet-curable. The composition of the stiffner can be tailored so that the thermal coefficient of expansion of the stiffner provides tensile stress to the coreless substrate layer at room temperature and at the bonding temperature. The tensile stress applied to the coreless substrate layer prevents or reduces warpage of the coreless substrate layer during bonding. Upon dicing, bonded stacks of a semiconductor chip and a coreless substrate can be provided without adhesive thereupon.

Abstract: A glass to be used in a scattering layer of an organic LED element, and an organic LED element using the scattering layer are provided. The organic LED element of the present invention includes, a transparent substrate, a first electrode provided on the transparent electrode, an organic layer provided on the first electrode, and a second electrode provided on the organic layer, and further includes a scattering layer including, in terms of mol % on the basis of oxides, 15 to 30% of P2O5, 5 to 25% of Bi2O3, 5 to 27% of Nb2O5, and 10 to 35% of ZnO and having a total content of alkali metal oxides including Li2O, Na2O and K2O of 5% by mass or less.

Abstract: A bonding structure that a bonding region can endure a high temperature environment and the bonding can be maintained with high reliability is provided as a bonding material capable of maintaining reliable bonding in high temperature environment in place of solder including Pb. In the bonding structure for a first member and a second member, solder and glass are used to bond the first member and the second member together and the glass seals the solder. Thereby, electrical conductivity is ensured and the outflow of melting solder in high temperatures can be inhibited to improve the durability.

Abstract: A sealing glass, a sealing material, and a sealing material paste, which suppress metal deposition by reducing glass components (metal oxides) without decreasing the reactivity with and the adhesion to a semiconductor substrate. The sealing glass, contains a low temperature melting glass containing, by mass ratio: from 0.1 to 5% of at least one metal oxide selected from the group consisting of Fe, Mn, Cr, Co, Ni, Nb, Hf, W, Re, a rare earth element, and optionally Mo; and from 5 to 100 ppm by mass ratio of K2O, wherein the low temperature melting glass has a softening point of at most 430° C. The sealing material device, contains the sealing glass and an inorganic filler in an amount of from 0 to 40% by volume ratio. The sealing material paste contains a mixture of the sealing material and a vehicle.

Abstract: A semiconductor component is disclosed. In one embodiment, the semiconductor component includes a semiconductor chip, which is arranged on a substrate, and a housing, which at least partially surrounds the semiconductor chip. The substrate is at least partly provided with a layer of polymer foam.

Abstract: A wiring structure having a wiring-terminal-connection adhesive that includes a curing agent capable of generating a free radical upon heating, a radically polymerizable substance and silicone particles.

Abstract: Disclosed is a method of making a flat panel display device. The flat panel display device includes a first substrate, an array of pixels formed on the first substrate, a second substrate opposing the first substrate, and a frit formed between the first substrate and the second substrate to encapsulate the array of pixels. On the first substrate, a buffer layer is formed, a first insulating film is formed on the buffer layer, and a first metal line is formed on the first insulating film. A second insulating film is formed, a second metal line is formed on the second insulating film, and a protective film formed on the upper of the second insulating film. A portion of the protective layer is etched to expose a portion of the second electrode. The frit overlaps with the portion of the second electrode.

Abstract: A solid state device has a solid state component, a power receiving/supplying portion that mounts the solid state component thereon for receiving/supplying electrical power from/to the solid state component, and a glass sealing portion that seals the solid state component. The glass sealing portion is formed of a B2O3—SiO2—Li2O—Na2O—ZnO—Nb2O5 based glass, which is composed of 21 wt % to 23 wt % of B2O3, 11 wt % to 13 wt % of SiO2, 1 wt % to 1.5 wt % of Li2O, and 2 wt % to 2.5 wt % of Na2O.

Abstract: A semiconductor device is disclosed. One aspect provides a semiconductor device that includes a semiconductor chip including a first face and a second face opposite the first face, an encapsulant including inorganic particles encapsulating the semiconductor chip, a first metal layer attached to the first face of the semiconductor chip, a second metal layer attached the second face of the semiconductor chip, and electrically conducting material configured to connect the first metal layer with the second metal layer.

Abstract: A potting compound for electronic components comprises a first composition of asphalt and sand and a second composition that attenuates the forces normally applied by the first composition when it is used alone. The force attenuator preferably comprises solvent-refined heavy paraffinic petroleum oil from about 0.1 to 20 wt % of the compound.

Abstract: A light emitting diode (10) includes an LED chip (14) and an encapsulant (16) enclosing the LED chip. The LED chip has a light emitting surface (141), and the encapsulant has a light output surface (161) over the light emitting surface. The light output surface defines a plurality of annular, concentric grooves (163). Each groove is cooperatively enclosed by a first groove wall (165) and a second groove wall (166). The first groove wall is a portion of a circumferential side surface of a cone, and a conical tip of the cone is located on the light emitting surface of the LED chip.

Abstract: A vacuum package has a chamber in which pressure is reduced to less than the atmospheric pressure, a functional component sealed in the chamber, and a material forming at least a part of the chamber. The material has at least one through hole to evacuate the chamber. In a cross section perpendicular to the material taken along the through hole, an edge portion of the material forming the through hole has an obtuse angle. The through hole is sealed with a sealing material.

Abstract: A semiconductor device is disclosed. One aspect provides a semiconductor device that includes a semiconductor chip including a first face and a second face opposite the first face, an encapsulant including inorganic particles encapsulating the semiconductor chip, a first metal layer attached to the first face of the semiconductor chip, a second metal layer attached the second face of the semiconductor chip, and electrically conducting material configured to connect the first metal layer with the second metal layer.

Abstract: A packaged die includes a substrate having an upper surface and a micro device on the upper surface and an encapsulation cover comprising one or more grooves on its lower surface. The lower surface of the encapsulation cover and the upper surface of the substrate are bonded together to form a plurality of air-tight closed-loop interfaces and encapsulate the micro device.

Abstract: A micro structure includes a seed electrode layer on a substrate and a plurality of conductive layers on the seed electrode layer. The combined thickness of the seed electrode layer and the plurality of conductive layers can be more than 0.1 mm and the lateral dimensions of the seed electrode layer and the plurality of conductive layers vary less than 20% along the direction normal to a surface of the substrate and the micro structure has striations on an outer surface.

Abstract: A package structure and fabrication method thereof. The structure includes a substrate having a terminal, a chip overlying the substrate, the chip having an active surface, having a center region and periphery region, the periphery region having an electrode thereon, a patterned cover plate overlying the chip and exposing the electrode, a conductive material electrically connecting the electrode and terminal, and an encapsulant covering the terminal, conductive material, and electrode, but exposing the cover plate overlying the center region of the chip.

Abstract: Tungsten-doped tin-fluorophosphate glasses are described herein which exhibit excellent humidity resistance, thermal resistance, and have a low glass transition temperature which makes them suitable for low temperature sealing applications, such as for encapsulating electronic components. In one embodiment, these glasses comprise 55-75% Sn, 4-14% P, 6-24% O, 4-22% F, and 0.15-15% W on a weight percent elemental basis.

Abstract: A semiconductor light emitting device is provided with a separately fabricated wavelength converting element. The wavelength converting element, of e.g., phosphor and glass, is produced in a sheet that is separated into individual wavelength converting elements, which are bonded to light emitting devices. The wavelength converting elements may be grouped and stored according to their wavelength converting properties. The wavelength converting elements may be selectively matched with a semiconductor light emitting device, to produce a desired mixture of primary and secondary light.

Abstract: A semiconductor device includes: a substrate; a semiconductor element mounted on the substrate; a sealing structure for sealing the semiconductor element, the sealing structure being mounted on the substrate; and an adhesive for bonding the sealing structure and the substrate, wherein the sealing structure has a groove for storing the adhesive.

Abstract: A circuit with embedding components (13) is produced by placing the components (13) on a substrate (14) and applying sheets (15) of prepreg. The prepreg sheets (15) have apertures to accommodate the -components, the number of sheets and arrangement of apertures being chosen to accommodate a variety of component X, Y and Z dimensions. A top layer with Cu foil (16(b)) is applied. The assembly is pressed in an operation analogous to conventional multilayer board lamination pressing. This causes all of the prepreg resin to flow to completely embed the components without raids or damage. Electrical connections are made by drilling and plating vias.

Abstract: An object of the invention is to provide glass for semiconductor encapsulation and an outer tube for semiconductor encapsulation which are friendly to environment and allow semiconductor electronic parts to have a heat resistance of 700° C. or higher as normal maximum temperature, and semiconductor electronic parts. The glass for semiconductor encapsulation according to the invention contains essentially no lead and the temperature at which viscosity reaches 1010 dPa·s is 700° C. or higher. According to such a constitution, since the glass contains essentially no lead, no harmful ingredients are discharged in the production of the outer tube for semiconductor encapsulation and in the production of the semiconductor electronic parts and thus the glass is friendly to environment. Moreover, since the temperature at which viscosity reaches 1010 dPa·s is 700° C. or higher, semiconductor electronic parts such as a bead thermistor using the same has a heat resistance of 700° C.

Abstract: A micromechanical component includes a cap wafer made up of at least a first silicon substrate and a thin glass substrate, and having a functional wafer made up of at least a second silicon substrate, at least one electrical contact surface being disposed on the functional wafer. the cap wafer is joined at the glass substrate to the functional wafer by anodic bonding. the electrical contact surface is disposed on a side of the functional wafer facing the cap wafer, and the cap wafer has at least one recess, such that an access is provided to the electrical contact surface. A method for encapsulating a micromechanical component having a cap wafer, by anodically bonding the cap wafer to a functional wafer.

Abstract: Ball grid array packages for semiconductor die include a thermally conductive container and a substrate that substantially enclose a semiconductor die. The die is positioned with respect to the container by thermally conductive supports formed in the container or attached to the container. The die contacts the supports so that the die and the container form a cavity that is at least partially filled with a thermally conductive material such as a conductive epoxy to promote thermal conduction between the die and the container. The die electrically connects to the substrate with bond wires that extend through an aperture in the substrate and attach to bond pads provided on the substrate. The aperture is typically filled with a protective layer of resin, epoxy, or other material that also encapsulates the bond wires.

Abstract: An encapsulating epoxy resin molding material, comprising (A) an epoxy resin, (B) a curing agent, and (C) an inorganic filler, wherein the inorganic filler (C) has an average particle size of 12 ?m or less and a specific surface area of 3.0 m2/g or more.

Abstract: An object of the invention is to provide glass for semiconductor encapsulation and an outer tube for semiconductor encapsulation which are friendly to environment and allow semiconductor electronic parts to have a heat resistance of 700° C. or higher as normal maximum temperature, and semiconductor electronic parts. The glass for semiconductor encapsulation according to the invention contains essentially no lead and the temperature at which viscosity reaches 1010 dPa·s is 700° C. or higher. According to such a constitution, since the glass contains essentially no lead, no harmful ingredients are discharged in the production of the outer tube for semiconductor encapsulation and in the production of the semiconductor electronic parts and thus the glass is friendly to environment. Moreover, since the temperature at which viscosity reaches 1010 dPa·s is 700° C. or higher, semiconductor electronic parts such as a bead thermistor using the same has a heat resistance of 700° C.

Abstract: An epoxy resin composition for encapsulating an optical semiconductor element, which has small internal stress and also can obtain good light transmittance within a broad temperature range. An epoxy resin composition for encapsulating an optical semiconductor element comprising the following component (A): (A) an epoxy resin complex which comprises an epoxy resin as the matrix component and silicon dioxide particles (a) dispersed therein: (a) silicon dioxide particles having an average particle size of from 5 to 40 nm measured by the small angle neutron scattering (SANS).

Abstract: A semiconductor device is provided which is capable of suppressing decreased yields and increased costs, maintaining excellent optical characteristics, reducing secular changes in characteristics to ensure high erliability. After implanting a dopant into a polycrystalline silicon film and activating the implanted dopant and forming a source region, drain region, and channel region, a substrate is exposed to hydrogen gas plasma with a substrate temperature kept within a range between 350° C. and 420° C. and with treating time of 3 minutes to 60 minutes taken. This exposure suppresses a content of occluded water contained in silicon dioxide making up a primary protecting film, which prevents the diffusion of water being an impurity at operational temperatures of a thin film transistor and adverse characteristics on operational characteristics.

Abstract: A light emitting diode (LED) package structure including a first substrate, an LED chip, a second substrate, and a thermoelectric cooling device is provided. The first substrate has a first surface and a corresponding second surface. The LED chip suitable for emitting a light is arranged on the first surface of the first substrate, and is electrically connected to the first substrate. The second substrate is below the first substrate, and has a third surface and a corresponding fourth surface. The third surface faces the second surface. The thermoelectric cooling device is arranged between the second surface of the first substrate and the third surface of the second substrate for conducting heat generated by the LED chip during operation.

Abstract: A protective disk for protecting a semiconductor wafer during processing includes an adhesive layer configured to adhere to the semiconductor wafer and a support layer coupled to the adhesive layer configured to provide strength and stiffness to the semiconductor wafer during processing. In one aspect of the invention, the protective disk is soluble in a mildly alkaline or mildly acidic solution. In another aspect, the adhesive layer comprises a high molecular weight polymer. In another aspect, the support layer comprises a polymer and a filler. The present invention may enable a robust, cost-effective, high-volume, automated process for thinning semiconductor wafers below 150 ?m, and for subsequent process steps of stress relief and transfer to a dicing frame for die singulation. Additionally, the invention enables use of existing toolsets and processes to produce thinner substrates than conventionally achievable.

Abstract: An optoelectronic component with an optoelectronic transducer is produced with the novel method. The optoelectronic component has a coupling region, which is formed in a radiation-transparent molding of the optoelectronic component. On the base of a clearance of the coupling region, the optoelectronic component has a radiation-optical functional surface, which is formed from the housing material and introduced into the molding with the aid of a profile milling cutter.

Abstract: An adhesive sheet for producing a semiconductor device, which includes a base layer and an adhesive layer and is used in the process for producing the semiconductor device including the step of sealing a semiconductor element connected to an electric conductor with a sealing resin on the adhesive layer, wherein the adhesive layer of the adhesive sheet includes a rubber component and an epoxy resin component and the ratio of the rubber component in organic materials in the adhesive layer is from 5 to 40% by weight. According to this adhesive sheet, pollution is not caused by silicon components, a sufficient elastic modulus can be kept even at high temperature, and a problem that paste remains is not easily caused.

Abstract: An integrated circuit device having a semiconductor device and an encapsulating material on at least a portion of the semiconductor device and a method for encapsulating an integrated circuit device is disclosed. The encapsulating material includes a plurality of nanoparticles.

Abstract: The lead-free glass tubing of the SiO2—B2O3—R2O—BaO—ZnO—TiO2 system has a composition, in percent by weight on an oxide basis, consisting essentially of: SiO2, 34 to 52; B2O3, 10 to 25; Al2O3, 0 to 25; Li2O, 2 to 6; Na2O, 4 to 10; K2O, 2 to 6; CaO, 0 to 4; BaO, 1 to 5; ZnO, 4 to 12; TiO2, 2 to 6, and at least one refining agent in an effective amount for refining. An encapsulated diode consisting of a diode encapsulated with this lead-free glass tubing is also disclosed.

Abstract: A package of a semiconductor device comprising an integrated circuit (10) generally comprises an inner layer (21) and an outer layer (16), which layers (16,21) have a mutual interface (24). An improved stability of the package is realized in that the interface (24) encloses a delamination area (22), which area (22) is isolated from any bond pads (18) of the integrated circuit (10). The delamination area (22) may be created by a pattern-wise activation of a surface of the inner layer (21). A quantity of a curable polymer may be disposed on this surface to achieve this.

Abstract: A semiconductor device comprises a semiconductor chip in which a multilayer interconnection structure having an interlayer insulation film with a low relative dielectric constant is formed on a silicon substrate and a sealing resin layer which coats the semiconductor chip. The sealing resin layer meets, in coefficient of linear expansion (?) at room temperature, Young's modulus (E) at room temperature and thickness (h) thereof, a relationship of the following formula (1) E<0.891/{(???s)2×h}??(1) where E represents the Young's modulus (GPa) of the sealing resin at room temperature; ? represents the coefficient of linear expansion (ppm) of the sealing resin at room temperature; ?s represents the coefficient of linear expansion (3.5 ppm) of the silicon substrate; and h represents the thickness (m) of the sealing resin on the device-formed surface of the semiconductor chip.