Abstract: A semiconductor encapsulation material is used to fabricate a semiconductor device. The semiconductor device includes a semiconductor chip and an encapsulating portion. The encapsulating portion is made of a cured product of the semiconductor encapsulation material. The encapsulating portion encapsulates the semiconductor chip. A stress index (SI), given by the following Formula (1), of the semiconductor encapsulation material is equal to or more than 8500. If a volume of the semiconductor chip is represented by Vc and a total volume of the semiconductor chip and the encapsulating portion is represented by Va, the volume Vc and the total volume Va satisfy the following Formula (2). In Formula (1), E? (T) represents a storage modulus, CTE (T) represents a coefficient of thermal expansion, and Mold temp. represents a molding temperature. SI = ? 35 ? ° ? C . Mold ? temp . [ E ? ( T ) × CTE ? ( T ) ] ? dT ( 1 ) Vc Va ? 0.3 .

Abstract: An electronic device package and manufacturing method thereof are provided. The electronic device package includes an electronic component including an active surface, a patterned conductive layer disposed on the active surface, an encapsulation layer disposed over the patterned conductive layer, and a buffer layer disposed between the patterned conductive layer and the encapsulation layer. The buffer layer is shaped and sized to alleviate a stress generated due to an interaction between the patterned conductive layer and the encapsulation layer.

Abstract: A semiconductor module includes a heat dissipating plate; an insulating substrate disposed on an upper surface of the heat dissipating plate; a semiconductor element disposed an upper surface of the insulating substrate; a frame-shaped case bonded to the upper surface of the heat dissipating plate via an adhesive so as to surround peripheries of the insulating substrate and the semiconductor element; and a sealing resin that fills an inner space defined by the frame-shaped case and the heat dissipating plate so as to seal the insulating substrate and the semiconductor element, wherein at an interface between the heat dissipating plate and the frame-shaped case, a recess communicating with the inner space is formed in at least one of the frame-shaped case and the heat dissipating plate, and the sealing resin is filled in the recess.

Abstract: A sealing structure (200) seals a light emitting unit (140) and includes a first inorganic film (210), a second inorganic film (220), a first resin-containing film (230), and a second resin-containing film (240). The film thickness of the first inorganic film (210) is equal to or greater than 1 nm and equal to or less than 300 nm. The first resin-containing film (230) is in contact with the first inorganic film (210) and includes a first resin. The second inorganic film (220) is positioned on an opposite side of the first inorganic film (210) with the first resin-containing film (230) interposed between the first and second inorganic films. The second resin-containing film (240) is positioned between the first resin-containing film (230) and the second inorganic film (220) and is in contact with the second inorganic film (220). The second resin-containing film (240) includes a second resin.

Abstract: Disclosed herein are integrated circuit (IC) package lids with polymer features, as well as related methods and devices. For example, in some embodiments, an IC package may include a package substrate, a lid, and a die between the package substrate and the lid. A foot or rib of the lid may include a polymer material.

Abstract: A power semiconductor module arrangement includes: a substrate arranged within a housing; at least one semiconductor body arranged on a top surface of the substrate; and a first layer arranged on a first surface within the housing. The first layer includes inorganic filler which is impermeable to corrosive gases and a casting material which fills spaces present in the inorganic filler.

Abstract: A method for manufacturing a circuit board (100) includes: providing a first single-sided circuit substrate (20) including an insulating base layer (11) and a circuit layer (13); forming first conductive posts (111) electrically connected to the circuit layer (13) in the insulating base layer (11) to obtain a second single-sided circuit substrate (13); providing a first adhesive layer (40), forming second conductive posts (401); providing one second single-sided circuit substrate (30), defining a receiving groove (31) to obtain a third single-sided circuit substrate (50); providing another first single-sided circuit substrate (20), mounting an electronic component (14) on the circuit layer (13) to obtain a surface mounted circuit substrate (60); stacking the first single-sided circuit substrate (20), the first adhesive layer (40), the second single-sided circuit substrate (30), at least one of the third single-sided circuit substrate (50), and the surface mounted circuit substrate (60) in that order; pressing

Abstract: Aspects of the present disclosure provide a method for forming a chiplet onto a semiconductor structure. For example, the method can include providing a first semiconductor structure having a first circuit and a first wiring structure formed on a first side thereof. The method can further include attaching the first side of the first semiconductor structure to a carrier substrate. The method can further include forming a stress film on a second side of the first semiconductor structure. The method can further include separating the carrier substrate from the first semiconductor structure. The method can further include cutting the stress film and the first semiconductor structure to define at least one chiplet. The method can further include bonding the at least one chiplet to a second semiconductor structure having a second circuit and a second wiring structure such that the second wiring structure is connected to the first wiring structure.

Abstract: A flexible laminate of photovoltaic cells is provided, including a layer of photovoltaic cells that are connected to one another; a front layer and a back layer configured to encapsulate the layer of photovoltaic cells; and an outer film of flexible material with anti-soiling properties disposed on the front layer, the outer film having an average roughness that is less than 1 ?m. There is also provided a method for decreasing or limiting soiling on a surface of a flexible laminate of photovoltaic cells, the method including applying an outer film of flexible material with anti-soiling properties to the front layer, the outer film having an average roughness that is less than 1 ?m.

Abstract: In an embodiment, a method includes forming a conductive feature adjacent to a substrate; treating the conductive feature with a protective material, the protective material comprising an inorganic core with an organic coating around the inorganic core, the treating the conductive feature comprising forming a protective layer over the conductive feature; and forming an encapsulant around the conductive feature and the protective layer. In another embodiment, the method further includes, before forming the encapsulant, rinsing the protective layer with water. In another embodiment, the protective layer is selectively formed over the conductive feature.

Abstract: An organic light-emitting diode display panel, a manufacturing method of an organic light-emitting diode display panel and a display device are provided. The organic light-emitting diode display panel includes: a substrate; a pixel definition layer, located on the substrate; and an encapsulation layer, located on the pixel definition layer, a desiccant is added to at least one of the pixel definition layer and the encapsulation layer.

Abstract: A sealing structure (200) seals a light emitting unit (140) and includes a first inorganic film (210), a second inorganic film (220), a first resin-containing film (230), and a second resin-containing film (240). The film thickness of the first inorganic film (210) is equal to or greater than 1 nm and equal to or less than 300 nm. The first resin-containing film (230) is in contact with the first inorganic film (210) and includes a first resin. The second inorganic film (220) is positioned on an opposite side of the first inorganic film (210) with the first resin-containing film (230) interposed between the first and second inorganic films. The second resin-containing film (240) is positioned between the first resin-containing film (230) and the second inorganic film (220) and is in contact with the second inorganic film (220). The second resin-containing film (240) includes a second resin.

Abstract: Semiconductor packages may include a semiconductor chip including a chip pad and a lower redistribution that includes a lower redistribution insulating layer and a lower redistribution pattern. The lower redistribution insulating layer may include a top surface facing the semiconductor chip. The semiconductor packages may also include a molding layer on a side of the semiconductor chip and including a bottom surface facing the lower redistribution structure and a conductive post in the molding layer. The conductive post may include a bottom surface contacting the lower redistribution. The top surface of the lower redistribution insulating layer may be closer to a top surface of the conductive post than a top surface of the molding layer. A roughness of the top surface of the molding layer may be greater than a roughness of the top surface of the conductive post.

Abstract: A method includes forming a release film over a carrier, forming a polymer buffer layer over the release film, forming a metal post on the polymer buffer layer, encapsulating the metal post in an encapsulating material, performing a planarization on the encapsulating material to expose the metal post, forming a redistribution structure over the encapsulating material and the metal post, and decomposing a first portion of the release film. A second portion of the release film remains after the decomposing. An opening is formed in the polymer buffer layer to expose the metal post.

Abstract: A vapor deposition apparatus for providing a deposition film on a substrate, the vapor deposition apparatus includes a plurality of first nozzle parts which injects a first raw material toward the substrate; a plurality of second nozzle parts which is alternately disposed together with the plurality of first nozzle parts and injects a second raw material toward the substrate; a diffuser unit which distributes the second raw material to the plurality of second nozzle parts; and a supply unit which supplies the second raw material to the diffuser unit.

Abstract: A semiconductor device package includes a substrate, a semiconductor device and an encapsulant. The substrate includes a passivation layer, a first conductive layer and a barrier layer. The passivation layer has a substantially vertical sidewall. The first conductive layer is disposed on the passivation layer. The barrier layer is disposed on the passivation layer and the first conductive layer. The barrier layer includes a substantially slant sidewall.

Abstract: Silicon (Si) based high temperature coatings and base materials and methods of making those materials. More specifically, methods and materials having silicon, oxygen and carbon containing polymer derived ceramic liquids that form filled and unfiled coatings, including high temperature crack resistant coatings.

Abstract: Dielectric breakdown resistance of a power module including a SiC-IGBT and a SiC diode is improved. The power module includes a SiC-IGBT 110 and a SiC diode 111, and a film thickness of a resin layer 323 covering an upper portion of an electric field relaxation region 320 of the SiC-IGBT 110 is larger than a chip thickness of the SiC-IGBT 110, that is, for example, 200 ?m or more.

Abstract: A semiconductor package includes semiconductor dies, an encapsulant, a high-modulus dielectric layer and a redistribution structure. The encapsulant encapsulates the semiconductor dies and is made of a first material. The high-modulus dielectric layer extends on the encapsulant and the semiconductor dies. The high-modulus dielectric layer is made of a second material. The redistribution structure extends on the high-modulus dielectric layer. The redistribution structure includes conductive patterns embedded in at least a pair of dielectric layers. The dielectric layers of the pair are made of a third material. The elastic modulus of the first material is higher than the elastic modulus of the third material. The elastic modulus of the second material is higher than the elastic modulus of the third material.

Abstract: Wafer-level methods for manufacturing one or more uniform layers of material on one or more surfaces of a plurality of optoelectronic modules include assembling a wafer assembly, injecting a formable material into the wafer assembly, ejecting excess formable material form the wafer assembly, and hardening one or more formable material layers on one or more surfaces of the plurality of optoelectronic modules such that the hardened one or more formable material layers are the one or more uniform layers of material.

Abstract: A thermoelectric conversion material contains a matrix composed of a semiconductor and nanoparticles disposed in the matrix, and the nanoparticles have a lattice constant distribution ?d/d of 0.0055 or more.

Abstract: An electronic component module includes a substrate; an electronic element disposed on a first surface of the substrate; an encapsulant encapsulating the electronic element; a first shielding member disposed on a first surface of the encapsulant to surround the electronic element; a second shielding member disposed on a second surface of the encapsulant and spaced apart from the first shielding member; a shielding layer covering the first shielding member and the second shielding member; and a connection member connecting the electronic element to the second shielding member.

Abstract: A display apparatus includes a substrate, an emission layer on the substrate; a planarization layer between the substrate and the emission layer; and a thin-film transistor between the substrate and the planarization layer. The emission layer includes a light-emitting diode (“LED”) electrically connected to the thin-film transistor, and a pixel separation member which surrounds the LED and is in contact with side surfaces of the LED.

Abstract: A semiconductor device includes a semiconductor chip including a substrate having a first surface and a second surface arranged opposite to the first surface; and a microelectromechanical systems (MEMS) element, including a sensitive area, disposed at the first surface of the substrate. The semiconductor device further includes at least one electrical interconnect structure electrically connected to the first surface of the substrate, and a flexible carrier electrically connected to the at least one electrical interconnect structure, where the flexible carrier wraps around the semiconductor chip and extends over the second surface of the substrate such that a folded cavity is formed around the semiconductor chip.

Abstract: Provided is an ink jet recording head having a flow path member. The flow path member is made of a thermoset product of a thermosetting molding composition containing a solid epoxy resin composition containing an epoxy resin and a phenolic resin, each solid at ordinary temperatures, and an alumina filler.

Abstract: The present disclosure, in some embodiments, relates to a semiconductor structure. The semiconductor structure includes a substrate and a first conductive pad arranged over the substrate. A boundary structure is on an upper surface of the substrate around the first conductive pad. The boundary structure has one or more sidewalls defining an opening with a round shape over the first conductive pad.

Abstract: The invention provides a semiconductor package. The semiconductor package includes a semiconductor die and a conductive pillar bump structure and a conductive plug. The semiconductor die has a die pad thereon. The conductive pillar bump structure is positioned overlying the die pad. The conductive pillar bump structure includes an under bump metallurgy (UBM) stack having a first diameter and a conductive plug on the UBM stack. The conductive plug has a second diameter that is different than the first diameter.

Abstract: According to one embodiment, an electronic device includes first to third members, first and second elements. The second member is between the first and third members. The first element is between the first and second members. The second element is between the second and third members. The first member includes first nonmagnetic layers and a first magnetic layer. The first magnetic layer is provided between one of the first nonmagnetic layers and an other one of the first nonmagnetic layers. The second member includes second nonmagnetic layers and a second magnetic layer. The second magnetic layer is provided between one of the second nonmagnetic layers and an other one of the second nonmagnetic layers. The third member includes third nonmagnetic layers and a third magnetic layer. The third magnetic layer is provided between one of the third nonmagnetic layers and an other one of the third nonmagnetic layers.

Abstract: An assay device (10) is provided. The device comprises an integrated circuit (IC) (16) comprising a plurality of ISFETs (18); an over-moulded layer (17) which partially covers the IC, such that the plurality of ISFETs remain uncovered; and a film (20) provided across substantially the entire IC. The film acts as a passivation and/or sensing layer for each of the ISFETs. In addition, the film acts as a barrier layer to encase the over-moulded layer.

Abstract: A light having a housing portion and a base portion and wherein the housing portion is removably engaged with the base portion. The base portion may be engaged with an insulating device or other container and the light may be configured to turn on when the insulating device lid is opened.

Abstract: Semiconductor devices having interconnects incorporating negative expansion (NTE) materials are disclosed herein. In one embodiment a semiconductor device includes a substrate having an opening that extends at least partially through the substrate. A conductive material having a positive coefficient of thermal expansion (CTE) partially fills the opening. A negative thermal expansion (NTE) having a negative CTE also partially fills the opening. In one embodiment, the conductive material includes copper and the NTE material includes zirconium tungstate.

Abstract: Provided are a thermal interface material layer and a package-on-package device including the same. The package-on-package device may include a thermal interface material layer interposed between lower and upper semiconductor packages and configured to have a specific physical property. Accordingly, it is possible to prevent a crack from occurring in a lower semiconductor chip, when a solder ball joint process is performed to mount the upper semiconductor package on the lower semiconductor package.

Abstract: An embodiment includes an apparatus comprising: a semiconductor die; package molding that is molded onto and conformal with a first die surface of the semiconductor die and at least two sidewalls of the semiconductor die, the package molding including: (a)(i) a first surface contacting the semiconductor die, (a)(ii) a second surface opposite the first surface, and (a)(iii) an aperture that extends from the first surface to the second surface; and a polymer substantially filling the aperture; wherein the package molding includes a first thermal conductivity (watts per meter kelvin (W/(m·K)) and the polymer includes a second thermal conductivity that is greater than the first thermal conductivity. Other embodiments are described herein.

Abstract: A technique relates to a method of optimizing self-aligned double patterning. Predefined locations for required metal cuts are provided in order to form metal wires from metal fills that have been cut. Extended locations for extended metal cuts are provided in order to cut adjacent metal fills. The adjacent metal fills are the metal fills that are adjacent to the predefined locations for the required metal cuts, and the extended metal cuts extend beyond the required metal cuts. The required metal cuts into the metal fills are performed and the extended metal cuts into the adjacent metal fills are performed.

Abstract: An hydrophobic epoxy resin composition including at least one ortho-substituted glycidyl ether, at least one ortho, ortho?-disubstituted glycidyl ether, at least one ortho, meta?-disubstituted glycidyl ether, at least one amine/aniline curing agent, and at least one organic solvent.

Abstract: Resin sheets which includes a support and a resin composition layer in contact on the support, and which are characterized in that an extracted water conductivity A of a cured product of the resin composition layer when extracted at 120° C. for 20 hours is 50 ?S/cm or less and an extracted water conductivity B of the cured product of the resin composition layer when extracted at 160° C. for 20 hours is 200 ?S/cm or less, can provide a thin insulating layer having excellent insulating properties.

Abstract: A thermoplastic resin composition of the present invention comprises: a thermoplastic resin comprising a (meth)acrylic resin and an aromatic vinyl-based resin; and a siloxane compound represented by the chemical formula 1. The thermoplastic resin composition has excellent scratch resistance, mar resistance, colorability, appearance characteristics and the like.

Abstract: Provided are an encapsulation film, an organic electronic device including the same, and a method of manufacturing the organic electronic device. Therefore, provided is the pressure-sensitive adhesive composition, which can form a structure capable of effectively blocking moisture or water entering the organic electronic device from the outside, and have excellent processability in a process of manufacturing a panel and excellent heat retention under a high-temperature and high-humidity condition.

Abstract: There is provided a circuit module where a sufficient amount of underfill resin may be supplied to corner portions of a semiconductor chip. A circuit module includes a circuit board provided with a plurality of electrode pads on a surface of the board, a semiconductor chip arranged on the board, the chip including a surface and a back surface, where each of a plurality of solder bumps and provided on the back surface is solder joined to a corresponding one of the plurality of electrode pads, and an underfill provided between the surface of the board and the back surface of the chip. Furthermore, the chip includes an eaves portion of a predetermined thickness at an outer periphery of the surface, and the underfill forms a fillet extending from a bottom surface of the eaves portion to the surface of the board along a side wall of the chip.

Abstract: A package on package (PoP) device includes a first package, a thermal interface material, and a second package coupled to the first package. The first package includes a first integrated device and a first encapsulation layer that at least partially encapsulates the first integrated device, where the first encapsulation layer includes a first cavity located laterally with respect to the first integrated device. The thermal interface material (TIM) is coupled to the first integrated device such that the thermal interface material (TIM) is formed between the first integrated device and the second package. The thermal interface material (TIM) is formed in the first cavity of the first encapsulation layer.

Abstract: The present invention relates to electrical insulation enamels which contain a polymer comprising a base polymer and modifying units which are incompatible with the base polymer after the polymer has cured and lead to the formation of separate phases at the surface, and to processes for the production thereof. The electrical insulation enamels have a low coefficient of friction and frictional resistance and are preferably suitable for the coating of wires.

Abstract: A conductor in a laminar structure, such as a printed circuit board or thin-film stack, is closely flanked by at least one open trench filled with an ambient medium (e.g., air, another gas, vacuum) of a lower dielectric loss than the conductor's surrounding dielectric. The trench may be made by any suitably precise method such as laser scribing, chemical etching or mechanical displacement. A thin layer of dielectric may be left on the sides of the conductor to prevent oxidation or other reactions that may reduce conductivity. When the conductor carries a signal, part of an electric and/or magnetic field that would ordinarily travel through the surrounding dielectric encounters the low-loss ambient medium (e.g. air) in the trench. The effective dielectric loss surrounding the conductor is lowered, reducing signal attenuation and crosstalk, particularly at high frequencies.

Abstract: Copolymers, as well as compounds, compositions, articles of manufacture, and methods of making thereof, are disclosed. The copolymers may generally exhibit flexibility properties and may generally have a high refractive index. The copolymers may generally be made by providing a dihydrodisiloxane and an aliphatic vinyl alcohol and combining the dihydrodisiloxane and the aliphatic vinyl alcohol under conditions that allow for hydrogenation of the aliphatic vinyl alcohol and result in coupling of the aliphatic vinyl alcohol to the dihydrodisiloxane to produce a hydroxyl substituted siloxane.

Abstract: A method of packaging a semiconductor die includes the steps of mounting the semiconductor die on a carrier, electrically connecting electrical contact pads of the semiconductor die to external electrical contacts, and encapsulating the die with a mold compound to form a packaged die. The packaged die is then thinned by using a dicing saw blade to trim the mold compound off of the top, non-active side of the package using a series of vertical cuts. This thinning step can be performed at the same time as a normal dicing step so no additional equipment or process steps are needed. Further, packages of varying thicknesses can be assembled simultaneously.

Abstract: A halogen-free resin composition, a copper clad laminate using the same, and a printed circuit board using the same are introduced. The halogen-free resin composition comprising (A) 100 parts by weight of epoxy resin; (B) 3 to 15 parts by weight of diaminodiphenyl sulfone (DDS); and (C) 5 to 70 parts by weight of phenolic co-hardener. The halogen-free resin composition features specific ingredients and proportion to thereby achieve satisfactory maximum preservation period of the prepreg manufactured from the halogen-free resin composition, control the related manufacturing process better, and attain satisfactory laminate properties, such as a high degree of water resistance, a high degree of heat resistance, and satisfactory dielectric properties, and thus is suitable for producing a prepreg or a resin film to thereby be applicable to copper clad laminates and printed circuit boards.

Abstract: A buffer element and a manufacturing method thereof, a backlight module, and a display device are disclosed. When the buffer element is applied to the backlight module, the problem caused by thermal expansion of the light guide plate can be effectively solved without needing to reserve a gap in the backlight module, the relative movement of the light guide plate is avoided and the optical quality of the backlight module is improved. The buffer element comprises a buffer body, wherein the buffer body comprises a curable adhesive, and a negative thermal expansion material dispersed in the curable adhesive.

Abstract: A battery electrode includes an electrochemically active material and a binder covering the electrochemically active material. The binder includes a self-healing polymer and conductive additives dispersed in the self-healing polymer to provide an electrical pathway across at least a portion of the binder.

Abstract: A printed circuit board including a substrate of electrically insulating material and a pattern of electrically conducting paths formed on at least one side of the substrate. One or more electronic components mounted to the substrate in connection with the electrically conductive paths. At least one of the components including a base solder connection between a base surface and a facing conducting surface of the component. The base solder connection is substantially obscured from view from the side of the substrate to which the component is attached and an opening is provided extending through the substrate beneath the base surface of the component so that the base solder connection is visible through the opening.

Abstract: An optical semiconductor device includes a metal lead frame including first and second plate portions, an optical semiconductor element mounted on the metal lead frame, and a reflector provided around the optical semiconductor element. A material for the reflector is an epoxy resin composition containing: (A) an epoxy resin; (B) a curing agent; (C) a white pigment; (D) an inorganic filler; and (E) at least one of a carboxylic acid and water. Components (C) and (D) are present in a total proportion of 69 to 94 wt % based on the amount of the overall epoxy resin composition, and the component (E) is present in a proportion of 4 to 23 mol % based on the total amount of the components (B) and (E). The resin composition has a higher glass transition temperature, and is excellent in moldability and blocking resistance and substantially free from warpage.

Abstract: An insulating substrate includes a base portion that is made of metal and serves as a radiating surface, an insulating layer, and a circuit pattern. The insulating substrate has convex warpage in the radiating surface at ambient temperature. A power semiconductor element is mounted on the circuit pattern. A sealing material has a thickness greater than a thickness of the insulating substrate. The sealing material has a linear expansion coefficient greater than a linear expansion coefficient of the insulating substrate in an in-plane direction of a mounting surface of the insulating substrate. A heat conduction layer is located on the radiating surface of the base portion and is solid at ambient temperature and is liquid at a temperature higher than or equal to a phase-change temperature higher than ambient temperature.