With Specified Encapsulant Patents (Class 257/788)
  • Patent number: 11605607
    Abstract: In an embodiment, a method includes forming a conductive feature adjacent to a substrate; treating the conductive feature with a protective material, the protective material comprising an inorganic core with an organic coating around the inorganic core, the treating the conductive feature comprising forming a protective layer over the conductive feature; and forming an encapsulant around the conductive feature and the protective layer. In another embodiment, the method further includes, before forming the encapsulant, rinsing the protective layer with water. In another embodiment, the protective layer is selectively formed over the conductive feature.
    Type: Grant
    Filed: March 19, 2021
    Date of Patent: March 14, 2023
    Inventors: Hung-Chun Cho, Hung-Jui Kuo, Yu-Hsiang Hu, Sih-Hao Liao
  • Patent number: 11594584
    Abstract: An organic light-emitting diode display panel, a manufacturing method of an organic light-emitting diode display panel and a display device are provided. The organic light-emitting diode display panel includes: a substrate; a pixel definition layer, located on the substrate; and an encapsulation layer, located on the pixel definition layer, a desiccant is added to at least one of the pixel definition layer and the encapsulation layer.
    Type: Grant
    Filed: February 15, 2019
    Date of Patent: February 28, 2023
    Inventors: Bin Wan, Min Li, Ya Zeng, Yulong Sun
  • Patent number: 11522163
    Abstract: A sealing structure (200) seals a light emitting unit (140) and includes a first inorganic film (210), a second inorganic film (220), a first resin-containing film (230), and a second resin-containing film (240). The film thickness of the first inorganic film (210) is equal to or greater than 1 nm and equal to or less than 300 nm. The first resin-containing film (230) is in contact with the first inorganic film (210) and includes a first resin. The second inorganic film (220) is positioned on an opposite side of the first inorganic film (210) with the first resin-containing film (230) interposed between the first and second inorganic films. The second resin-containing film (240) is positioned between the first resin-containing film (230) and the second inorganic film (220) and is in contact with the second inorganic film (220). The second resin-containing film (240) includes a second resin.
    Type: Grant
    Filed: April 21, 2021
    Date of Patent: December 6, 2022
    Assignee: Pioneer Corporation
    Inventor: Shinichi Tanisako
  • Patent number: 11462462
    Abstract: Semiconductor packages may include a semiconductor chip including a chip pad and a lower redistribution that includes a lower redistribution insulating layer and a lower redistribution pattern. The lower redistribution insulating layer may include a top surface facing the semiconductor chip. The semiconductor packages may also include a molding layer on a side of the semiconductor chip and including a bottom surface facing the lower redistribution structure and a conductive post in the molding layer. The conductive post may include a bottom surface contacting the lower redistribution. The top surface of the lower redistribution insulating layer may be closer to a top surface of the conductive post than a top surface of the molding layer. A roughness of the top surface of the molding layer may be greater than a roughness of the top surface of the conductive post.
    Type: Grant
    Filed: February 11, 2020
    Date of Patent: October 4, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jaekyung Yoo, Jaeeun Lee, Yeongkwon Ko, Teakhoon Lee
  • Patent number: 11437361
    Abstract: A method includes forming a release film over a carrier, forming a polymer buffer layer over the release film, forming a metal post on the polymer buffer layer, encapsulating the metal post in an encapsulating material, performing a planarization on the encapsulating material to expose the metal post, forming a redistribution structure over the encapsulating material and the metal post, and decomposing a first portion of the release film. A second portion of the release film remains after the decomposing. An opening is formed in the polymer buffer layer to expose the metal post.
    Type: Grant
    Filed: September 12, 2019
    Date of Patent: September 6, 2022
    Inventors: Yi-Jen Lai, Lin Chung-Yi, Hsi-Kuei Cheng, Chen-Shien Chen, Kuo-Chio Liu
  • Patent number: 11408072
    Abstract: A vapor deposition apparatus for providing a deposition film on a substrate, the vapor deposition apparatus includes a plurality of first nozzle parts which injects a first raw material toward the substrate; a plurality of second nozzle parts which is alternately disposed together with the plurality of first nozzle parts and injects a second raw material toward the substrate; a diffuser unit which distributes the second raw material to the plurality of second nozzle parts; and a supply unit which supplies the second raw material to the diffuser unit.
    Type: Grant
    Filed: February 8, 2019
    Date of Patent: August 9, 2022
    Inventors: Jin-Kwang Kim, Seung-Yong Song, Myung-Soo Huh, Suk-Won Jung, Choel-Min Jang, Jae-Hyun Kim, Sung-Chul Kim
  • Patent number: 11367676
    Abstract: A semiconductor device package includes a substrate, a semiconductor device and an encapsulant. The substrate includes a passivation layer, a first conductive layer and a barrier layer. The passivation layer has a substantially vertical sidewall. The first conductive layer is disposed on the passivation layer. The barrier layer is disposed on the passivation layer and the first conductive layer. The barrier layer includes a substantially slant sidewall.
    Type: Grant
    Filed: September 12, 2019
    Date of Patent: June 21, 2022
    Inventor: Shun Sing Liao
  • Patent number: 11351652
    Abstract: Silicon (Si) based high temperature coatings and base materials and methods of making those materials. More specifically, methods and materials having silicon, oxygen and carbon containing polymer derived ceramic liquids that form filled and unfiled coatings, including high temperature crack resistant coatings.
    Type: Grant
    Filed: March 9, 2017
    Date of Patent: June 7, 2022
    Assignee: Melior Innovations, Inc.
    Inventors: Douglas M. Dukes, Michael J. Mueller, Michael Molnar, Brian L. Benac
  • Patent number: 11296191
    Abstract: Dielectric breakdown resistance of a power module including a SiC-IGBT and a SiC diode is improved. The power module includes a SiC-IGBT 110 and a SiC diode 111, and a film thickness of a resin layer 323 covering an upper portion of an electric field relaxation region 320 of the SiC-IGBT 110 is larger than a chip thickness of the SiC-IGBT 110, that is, for example, 200 ?m or more.
    Type: Grant
    Filed: October 2, 2017
    Date of Patent: April 5, 2022
    Assignee: HITACHI, LTD.
    Inventors: Ryuusei Fujita, Naoki Watanabe, Yuan Bu
  • Patent number: 11270921
    Abstract: A semiconductor package includes semiconductor dies, an encapsulant, a high-modulus dielectric layer and a redistribution structure. The encapsulant encapsulates the semiconductor dies and is made of a first material. The high-modulus dielectric layer extends on the encapsulant and the semiconductor dies. The high-modulus dielectric layer is made of a second material. The redistribution structure extends on the high-modulus dielectric layer. The redistribution structure includes conductive patterns embedded in at least a pair of dielectric layers. The dielectric layers of the pair are made of a third material. The elastic modulus of the first material is higher than the elastic modulus of the third material. The elastic modulus of the second material is higher than the elastic modulus of the third material.
    Type: Grant
    Filed: May 8, 2020
    Date of Patent: March 8, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hao-Cheng Hou, Chien-Hsun Lee, Chung-Shi Liu, Jung-Wei Cheng, Tsung-Ding Wang, Yi-Yang Lei
  • Patent number: 11171249
    Abstract: Wafer-level methods for manufacturing one or more uniform layers of material on one or more surfaces of a plurality of optoelectronic modules include assembling a wafer assembly, injecting a formable material into the wafer assembly, ejecting excess formable material form the wafer assembly, and hardening one or more formable material layers on one or more surfaces of the plurality of optoelectronic modules such that the hardened one or more formable material layers are the one or more uniform layers of material.
    Type: Grant
    Filed: July 24, 2018
    Date of Patent: November 9, 2021
    Assignee: ams Sensors Singapore Pte. Ltd.
    Inventors: Robert Lenart, Sonja Gantner-Hanselmann, Özkan Ahishali
  • Patent number: 11139422
    Abstract: A thermoelectric conversion material contains a matrix composed of a semiconductor and nanoparticles disposed in the matrix, and the nanoparticles have a lattice constant distribution ?d/d of 0.0055 or more.
    Type: Grant
    Filed: April 11, 2018
    Date of Patent: October 5, 2021
    Inventors: Masahiro Adachi, Makoto Kiyama, Yoshiyuki Yamamoto, Ryo Toyoshima
  • Patent number: 10937710
    Abstract: An electronic component module includes a substrate; an electronic element disposed on a first surface of the substrate; an encapsulant encapsulating the electronic element; a first shielding member disposed on a first surface of the encapsulant to surround the electronic element; a second shielding member disposed on a second surface of the encapsulant and spaced apart from the first shielding member; a shielding layer covering the first shielding member and the second shielding member; and a connection member connecting the electronic element to the second shielding member.
    Type: Grant
    Filed: October 17, 2019
    Date of Patent: March 2, 2021
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Suk Youn Hong, Han Su Park, Jong Woo Choi
  • Patent number: 10930789
    Abstract: A display apparatus includes a substrate, an emission layer on the substrate; a planarization layer between the substrate and the emission layer; and a thin-film transistor between the substrate and the planarization layer. The emission layer includes a light-emitting diode (“LED”) electrically connected to the thin-film transistor, and a pixel separation member which surrounds the LED and is in contact with side surfaces of the LED.
    Type: Grant
    Filed: May 22, 2018
    Date of Patent: February 23, 2021
    Inventor: Sangil Park
  • Patent number: 10910283
    Abstract: A semiconductor device includes a semiconductor chip including a substrate having a first surface and a second surface arranged opposite to the first surface; and a microelectromechanical systems (MEMS) element, including a sensitive area, disposed at the first surface of the substrate. The semiconductor device further includes at least one electrical interconnect structure electrically connected to the first surface of the substrate, and a flexible carrier electrically connected to the at least one electrical interconnect structure, where the flexible carrier wraps around the semiconductor chip and extends over the second surface of the substrate such that a folded cavity is formed around the semiconductor chip.
    Type: Grant
    Filed: June 24, 2020
    Date of Patent: February 2, 2021
    Inventor: Dirk Hammerschmidt
  • Patent number: 10850512
    Abstract: Provided is an ink jet recording head having a flow path member. The flow path member is made of a thermoset product of a thermosetting molding composition containing a solid epoxy resin composition containing an epoxy resin and a phenolic resin, each solid at ordinary temperatures, and an alumina filler.
    Type: Grant
    Filed: February 15, 2019
    Date of Patent: December 1, 2020
    Inventor: Isao Imamura
  • Patent number: 10804234
    Abstract: The present disclosure, in some embodiments, relates to a semiconductor structure. The semiconductor structure includes a substrate and a first conductive pad arranged over the substrate. A boundary structure is on an upper surface of the substrate around the first conductive pad. The boundary structure has one or more sidewalls defining an opening with a round shape over the first conductive pad.
    Type: Grant
    Filed: April 12, 2019
    Date of Patent: October 13, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chien Ling Hwang, Yeong-Jyh Lin, Bor-Ping Jang, Hsiao-Chung Liang
  • Patent number: 10756040
    Abstract: The invention provides a semiconductor package. The semiconductor package includes a semiconductor die and a conductive pillar bump structure and a conductive plug. The semiconductor die has a die pad thereon. The conductive pillar bump structure is positioned overlying the die pad. The conductive pillar bump structure includes an under bump metallurgy (UBM) stack having a first diameter and a conductive plug on the UBM stack. The conductive plug has a second diameter that is different than the first diameter.
    Type: Grant
    Filed: January 26, 2018
    Date of Patent: August 25, 2020
    Assignee: MediaTek Inc.
    Inventors: Ta-Jen Yu, Chi-Yuan Chen, Wen-Sung Hsu
  • Patent number: 10699979
    Abstract: According to one embodiment, an electronic device includes first to third members, first and second elements. The second member is between the first and third members. The first element is between the first and second members. The second element is between the second and third members. The first member includes first nonmagnetic layers and a first magnetic layer. The first magnetic layer is provided between one of the first nonmagnetic layers and an other one of the first nonmagnetic layers. The second member includes second nonmagnetic layers and a second magnetic layer. The second magnetic layer is provided between one of the second nonmagnetic layers and an other one of the second nonmagnetic layers. The third member includes third nonmagnetic layers and a third magnetic layer. The third magnetic layer is provided between one of the third nonmagnetic layers and an other one of the third nonmagnetic layers.
    Type: Grant
    Filed: March 12, 2019
    Date of Patent: June 30, 2020
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Akira Kikitsu, Yoshinari Kurosaki, Kenichiro Yamada
  • Patent number: 10634642
    Abstract: An assay device (10) is provided. The device comprises an integrated circuit (IC) (16) comprising a plurality of ISFETs (18); an over-moulded layer (17) which partially covers the IC, such that the plurality of ISFETs remain uncovered; and a film (20) provided across substantially the entire IC. The film acts as a passivation and/or sensing layer for each of the ISFETs. In addition, the film acts as a barrier layer to encase the over-moulded layer.
    Type: Grant
    Filed: May 15, 2017
    Date of Patent: April 28, 2020
    Inventor: Zahid Ansari
  • Patent number: 10618709
    Abstract: A light having a housing portion and a base portion and wherein the housing portion is removably engaged with the base portion. The base portion may be engaged with an insulating device or other container and the light may be configured to turn on when the insulating device lid is opened.
    Type: Grant
    Filed: March 24, 2017
    Date of Patent: April 14, 2020
    Assignee: YETI Coolers, LLC
    Inventors: Roy Joseph Seiders, Christopher M. Keller, Kyle Thomas Miller, Steve Charles Nichols
  • Patent number: 10546777
    Abstract: Semiconductor devices having interconnects incorporating negative expansion (NTE) materials are disclosed herein. In one embodiment a semiconductor device includes a substrate having an opening that extends at least partially through the substrate. A conductive material having a positive coefficient of thermal expansion (CTE) partially fills the opening. A negative thermal expansion (NTE) having a negative CTE also partially fills the opening. In one embodiment, the conductive material includes copper and the NTE material includes zirconium tungstate.
    Type: Grant
    Filed: February 5, 2018
    Date of Patent: January 28, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Hongqi Li, Anurag Jindal, Jin Lu, Shyam Ramalingam
  • Patent number: 10431522
    Abstract: Provided are a thermal interface material layer and a package-on-package device including the same. The package-on-package device may include a thermal interface material layer interposed between lower and upper semiconductor packages and configured to have a specific physical property. Accordingly, it is possible to prevent a crack from occurring in a lower semiconductor chip, when a solder ball joint process is performed to mount the upper semiconductor package on the lower semiconductor package.
    Type: Grant
    Filed: December 28, 2017
    Date of Patent: October 1, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Min-Ok Na, Jongkook Kim, Hyo-Chang Ryu, Jin-woo Park, BongJin Son, Jangwoo Lee
  • Patent number: 10424559
    Abstract: An embodiment includes an apparatus comprising: a semiconductor die; package molding that is molded onto and conformal with a first die surface of the semiconductor die and at least two sidewalls of the semiconductor die, the package molding including: (a)(i) a first surface contacting the semiconductor die, (a)(ii) a second surface opposite the first surface, and (a)(iii) an aperture that extends from the first surface to the second surface; and a polymer substantially filling the aperture; wherein the package molding includes a first thermal conductivity (watts per meter kelvin (W/(m·K)) and the polymer includes a second thermal conductivity that is greater than the first thermal conductivity. Other embodiments are described herein.
    Type: Grant
    Filed: December 22, 2016
    Date of Patent: September 24, 2019
    Assignee: Intel Corporation
    Inventors: Feras Eid, Nader N. Abazarnia, Johanna M. Swan, Taesha D. Beasley, Sasha N. Oster, Tannaz Harirchian, Shawna M. Liff
  • Patent number: 10381338
    Abstract: A technique relates to a method of optimizing self-aligned double patterning. Predefined locations for required metal cuts are provided in order to form metal wires from metal fills that have been cut. Extended locations for extended metal cuts are provided in order to cut adjacent metal fills. The adjacent metal fills are the metal fills that are adjacent to the predefined locations for the required metal cuts, and the extended metal cuts extend beyond the required metal cuts. The required metal cuts into the metal fills are performed and the extended metal cuts into the adjacent metal fills are performed.
    Type: Grant
    Filed: May 24, 2017
    Date of Patent: August 13, 2019
    Inventors: Albert M. Chu, Lawrence A. Clevenger, Ximeng Guan, Myung-Hee Na
  • Patent number: 10344160
    Abstract: An hydrophobic epoxy resin composition including at least one ortho-substituted glycidyl ether, at least one ortho, ortho?-disubstituted glycidyl ether, at least one ortho, meta?-disubstituted glycidyl ether, at least one amine/aniline curing agent, and at least one organic solvent.
    Type: Grant
    Filed: August 10, 2015
    Date of Patent: July 9, 2019
    Assignee: The United States of America as Represented by the Secretary of the Navy
    Inventors: Joseph W Tsang, Michael Garrison
  • Patent number: 10257928
    Abstract: Resin sheets which includes a support and a resin composition layer in contact on the support, and which are characterized in that an extracted water conductivity A of a cured product of the resin composition layer when extracted at 120° C. for 20 hours is 50 ?S/cm or less and an extracted water conductivity B of the cured product of the resin composition layer when extracted at 160° C. for 20 hours is 200 ?S/cm or less, can provide a thin insulating layer having excellent insulating properties.
    Type: Grant
    Filed: March 29, 2017
    Date of Patent: April 9, 2019
    Assignee: Ajinomoto Co., Inc.
    Inventors: Shigeo Nakamura, Shiro Tatsumi, Ikumi Sawa
  • Patent number: 10196519
    Abstract: A thermoplastic resin composition of the present invention comprises: a thermoplastic resin comprising a (meth)acrylic resin and an aromatic vinyl-based resin; and a siloxane compound represented by the chemical formula 1. The thermoplastic resin composition has excellent scratch resistance, mar resistance, colorability, appearance characteristics and the like.
    Type: Grant
    Filed: November 3, 2015
    Date of Patent: February 5, 2019
    Assignee: Lotte Advanced Materials Co., Ltd.
    Inventors: Byeong Yeol Kim, Yoen Kyoung Kim, Dong Hyun Park, Yeon Wook Chung, Dong Hui Chu, Young Chul Kwon, Kang Yeol Park
  • Patent number: 10074827
    Abstract: Provided are an encapsulation film, an organic electronic device including the same, and a method of manufacturing the organic electronic device. Therefore, provided is the pressure-sensitive adhesive composition, which can form a structure capable of effectively blocking moisture or water entering the organic electronic device from the outside, and have excellent processability in a process of manufacturing a panel and excellent heat retention under a high-temperature and high-humidity condition.
    Type: Grant
    Filed: February 4, 2016
    Date of Patent: September 11, 2018
    Assignee: LG CHEM, LTD.
    Inventors: Hyun Jee Yoo, Hyun Suk Kim, Jung Ok Moon, Se Woo Yang
  • Patent number: 10074583
    Abstract: There is provided a circuit module where a sufficient amount of underfill resin may be supplied to corner portions of a semiconductor chip. A circuit module includes a circuit board provided with a plurality of electrode pads on a surface of the board, a semiconductor chip arranged on the board, the chip including a surface and a back surface, where each of a plurality of solder bumps and provided on the back surface is solder joined to a corresponding one of the plurality of electrode pads, and an underfill provided between the surface of the board and the back surface of the chip. Furthermore, the chip includes an eaves portion of a predetermined thickness at an outer periphery of the surface, and the underfill forms a fillet extending from a bottom surface of the eaves portion to the surface of the board along a side wall of the chip.
    Type: Grant
    Filed: October 30, 2015
    Date of Patent: September 11, 2018
    Assignee: International Business Machines Corporation
    Inventors: Akihiro Horibe, Sayuri Hada, Kuniaki Sueoka
  • Patent number: 10002857
    Abstract: A package on package (PoP) device includes a first package, a thermal interface material, and a second package coupled to the first package. The first package includes a first integrated device and a first encapsulation layer that at least partially encapsulates the first integrated device, where the first encapsulation layer includes a first cavity located laterally with respect to the first integrated device. The thermal interface material (TIM) is coupled to the first integrated device such that the thermal interface material (TIM) is formed between the first integrated device and the second package. The thermal interface material (TIM) is formed in the first cavity of the first encapsulation layer.
    Type: Grant
    Filed: August 2, 2016
    Date of Patent: June 19, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Michael James Solimando, William Stone, John Holmes, Christopher Healy, Rajendra Pendse, Sun Yun
  • Patent number: 9944823
    Abstract: The present invention relates to electrical insulation enamels which contain a polymer comprising a base polymer and modifying units which are incompatible with the base polymer after the polymer has cured and lead to the formation of separate phases at the surface, and to processes for the production thereof. The electrical insulation enamels have a low coefficient of friction and frictional resistance and are preferably suitable for the coating of wires.
    Type: Grant
    Filed: August 10, 2011
    Date of Patent: April 17, 2018
    Inventors: Wolfgang Bremser, Jorg Ressel, Johann Reicher
  • Patent number: 9935353
    Abstract: A conductor in a laminar structure, such as a printed circuit board or thin-film stack, is closely flanked by at least one open trench filled with an ambient medium (e.g., air, another gas, vacuum) of a lower dielectric loss than the conductor's surrounding dielectric. The trench may be made by any suitably precise method such as laser scribing, chemical etching or mechanical displacement. A thin layer of dielectric may be left on the sides of the conductor to prevent oxidation or other reactions that may reduce conductivity. When the conductor carries a signal, part of an electric and/or magnetic field that would ordinarily travel through the surrounding dielectric encounters the low-loss ambient medium (e.g. air) in the trench. The effective dielectric loss surrounding the conductor is lowered, reducing signal attenuation and crosstalk, particularly at high frequencies.
    Type: Grant
    Filed: September 23, 2015
    Date of Patent: April 3, 2018
    Assignee: Intel Corporation
    Inventors: Gong Ouyang, Shaowu Huang, Kai Xiao
  • Patent number: 9840595
    Abstract: Copolymers, as well as compounds, compositions, articles of manufacture, and methods of making thereof, are disclosed. The copolymers may generally exhibit flexibility properties and may generally have a high refractive index. The copolymers may generally be made by providing a dihydrodisiloxane and an aliphatic vinyl alcohol and combining the dihydrodisiloxane and the aliphatic vinyl alcohol under conditions that allow for hydrogenation of the aliphatic vinyl alcohol and result in coupling of the aliphatic vinyl alcohol to the dihydrodisiloxane to produce a hydroxyl substituted siloxane.
    Type: Grant
    Filed: June 17, 2013
    Date of Patent: December 12, 2017
    Assignee: Empire Technology Development LLC
    Inventor: Mark Allan Tapsak
  • Patent number: 9812339
    Abstract: A method of packaging a semiconductor die includes the steps of mounting the semiconductor die on a carrier, electrically connecting electrical contact pads of the semiconductor die to external electrical contacts, and encapsulating the die with a mold compound to form a packaged die. The packaged die is then thinned by using a dicing saw blade to trim the mold compound off of the top, non-active side of the package using a series of vertical cuts. This thinning step can be performed at the same time as a normal dicing step so no additional equipment or process steps are needed. Further, packages of varying thicknesses can be assembled simultaneously.
    Type: Grant
    Filed: April 24, 2017
    Date of Patent: November 7, 2017
    Assignee: NXP B.V.
    Inventors: Pimpa Boonyatee, Pitak Seantumpol, Paradee Jitrungruang
  • Patent number: 9650512
    Abstract: A halogen-free resin composition, a copper clad laminate using the same, and a printed circuit board using the same are introduced. The halogen-free resin composition comprising (A) 100 parts by weight of epoxy resin; (B) 3 to 15 parts by weight of diaminodiphenyl sulfone (DDS); and (C) 5 to 70 parts by weight of phenolic co-hardener. The halogen-free resin composition features specific ingredients and proportion to thereby achieve satisfactory maximum preservation period of the prepreg manufactured from the halogen-free resin composition, control the related manufacturing process better, and attain satisfactory laminate properties, such as a high degree of water resistance, a high degree of heat resistance, and satisfactory dielectric properties, and thus is suitable for producing a prepreg or a resin film to thereby be applicable to copper clad laminates and printed circuit boards.
    Type: Grant
    Filed: August 10, 2013
    Date of Patent: May 16, 2017
    Assignee: Elite Electronic Material (Kunshan) Co., Ltd
    Inventors: Rong-Tao Wang, Li-Chih Yu, Yu-Te Lin, Yi-Jen Chen, Wenjun Tian, Ziqian Ma, Wenfeng Lu
  • Patent number: 9625643
    Abstract: A buffer element and a manufacturing method thereof, a backlight module, and a display device are disclosed. When the buffer element is applied to the backlight module, the problem caused by thermal expansion of the light guide plate can be effectively solved without needing to reserve a gap in the backlight module, the relative movement of the light guide plate is avoided and the optical quality of the backlight module is improved. The buffer element comprises a buffer body, wherein the buffer body comprises a curable adhesive, and a negative thermal expansion material dispersed in the curable adhesive.
    Type: Grant
    Filed: June 24, 2014
    Date of Patent: April 18, 2017
    Inventor: Gang Liu
  • Patent number: 9490045
    Abstract: A battery electrode includes an electrochemically active material and a binder covering the electrochemically active material. The binder includes a self-healing polymer and conductive additives dispersed in the self-healing polymer to provide an electrical pathway across at least a portion of the binder.
    Type: Grant
    Filed: November 8, 2013
    Date of Patent: November 8, 2016
    Assignee: The Board of Trustees of the Leland Stanford Junior University
    Inventors: Chee Keong Tee, Chao Wang, Hui Wu, Yi Cui, Zhenan Bao
  • Patent number: 9462680
    Abstract: A printed circuit board including a substrate of electrically insulating material and a pattern of electrically conducting paths formed on at least one side of the substrate. One or more electronic components mounted to the substrate in connection with the electrically conductive paths. At least one of the components including a base solder connection between a base surface and a facing conducting surface of the component. The base solder connection is substantially obscured from view from the side of the substrate to which the component is attached and an opening is provided extending through the substrate beneath the base surface of the component so that the base solder connection is visible through the opening.
    Type: Grant
    Filed: February 27, 2013
    Date of Patent: October 4, 2016
    Inventor: Tony Rocco
  • Patent number: 9450158
    Abstract: An optical semiconductor device includes a metal lead frame including first and second plate portions, an optical semiconductor element mounted on the metal lead frame, and a reflector provided around the optical semiconductor element. A material for the reflector is an epoxy resin composition containing: (A) an epoxy resin; (B) a curing agent; (C) a white pigment; (D) an inorganic filler; and (E) at least one of a carboxylic acid and water. Components (C) and (D) are present in a total proportion of 69 to 94 wt % based on the amount of the overall epoxy resin composition, and the component (E) is present in a proportion of 4 to 23 mol % based on the total amount of the components (B) and (E). The resin composition has a higher glass transition temperature, and is excellent in moldability and blocking resistance and substantially free from warpage.
    Type: Grant
    Filed: May 27, 2014
    Date of Patent: September 20, 2016
    Inventors: Naoko Yoshida, Kazuhiro Fuke, Hidenori Onishi, Ryusuke Naito, Yuichi Fukamichi
  • Patent number: 9412679
    Abstract: An insulating substrate includes a base portion that is made of metal and serves as a radiating surface, an insulating layer, and a circuit pattern. The insulating substrate has convex warpage in the radiating surface at ambient temperature. A power semiconductor element is mounted on the circuit pattern. A sealing material has a thickness greater than a thickness of the insulating substrate. The sealing material has a linear expansion coefficient greater than a linear expansion coefficient of the insulating substrate in an in-plane direction of a mounting surface of the insulating substrate. A heat conduction layer is located on the radiating surface of the base portion and is solid at ambient temperature and is liquid at a temperature higher than or equal to a phase-change temperature higher than ambient temperature.
    Type: Grant
    Filed: October 28, 2015
    Date of Patent: August 9, 2016
    Inventors: Kenta Nakahara, Hiroshi Yoshida
  • Patent number: 9395626
    Abstract: There is provided a photosensitive resin composition containing (A) an alkali-soluble resin, (B) a compound which generates an acid when exposed to light, (C) a thermal crosslinking agent, and (D) a nitrogen-containing aromatic compound represented by the following formula (1): wherein R1 represents a hydrogen atom or a hydrocarbon group; R2 represents a hydrogen atom, an amino group or a phenyl group; and A and B each independently represent a nitrogen atom, or a carbon atom and a hydrogen atom bonded thereto.
    Type: Grant
    Filed: October 31, 2012
    Date of Patent: July 19, 2016
    Inventors: Akitoshi Tanimoto, Shigeru Nobe, Kei Kasuya, Hiroshi Matsutani, Shigeki Katogi, Yu Aoki, Shingo Tahara
  • Patent number: 9385258
    Abstract: An optoelectronic semiconductor device includes at least one radiation-emitting and/or radiation-receiving semiconductor chip including a radiation passage surface and a mounting surface opposite the radiation passage surface, wherein the mounting surface includes a first electrical contact structure and a second electrical contact structure electrically insulated from the first electrical contact structure, and wherein the radiation passage surface is free of contact structures, a reflective sheath surrounding the at least one semiconductor chip at least in sections, and a protective sheath surrounding the at least one semiconductor chip and/or the reflective sheath at least in sections.
    Type: Grant
    Filed: February 8, 2013
    Date of Patent: July 5, 2016
    Assignee: OSRAM Opto Semiconductors GmbH
    Inventors: Thomas Schlereth, Stephan Kaiser, Alexander Linkov
  • Patent number: 9318352
    Abstract: Disclosed herein are a power module package and a method for manufacturing the same. The power module package includes first and second lead frames disposed to face each other; ceramic coating layers formed on a portion of a first surface of both or one of both of the first and second lead frames; and semiconductor devices mounted on second surfaces of the first and second lead frames.
    Type: Grant
    Filed: August 22, 2013
    Date of Patent: April 19, 2016
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Kwang Soo Kim, Young Ki Lee, Seog Moon Choi, Jin Suk Son
  • Patent number: 9269647
    Abstract: A semiconductor package includes a substrate having an upper surface and a lower surface, a semiconductor chip which is mounted on the upper surface of the substrate, and in an upper surface of which a first recess portion is provided, a molding member formed such that the molding member exposes the upper surface of the semiconductor chip and covers the semiconductor chip on the upper surface of the substrate, and a first heat dissipating member formed in the first recess portion, wherein the first heat dissipating member includes moisture absorption particles and a heat dissipation molding member.
    Type: Grant
    Filed: May 28, 2015
    Date of Patent: February 23, 2016
    Inventor: Maohua Du
  • Patent number: 9184355
    Abstract: Provided are curable resin compositions capable of giving cured articles that have high light reflectivity, are satisfactorily resistant to heat and light, are tough, and less suffer from light reflectivity reduction with time. A curable resin composition for light reflection includes an alicyclic epoxy compound (A), rubber particles (B), a white pigment (C), a curing agent (D), and a curing accelerator (E). Another curable resin composition for light reflection includes an alicyclic epoxy compound (A), rubber particles (B), a white pigment (C), and a curing catalyst (F).
    Type: Grant
    Filed: June 18, 2012
    Date of Patent: November 10, 2015
    Inventors: Hiroyuki Hirakawa, Atsushi Sato
  • Patent number: 9184066
    Abstract: A chip arrangement is provided, the chip arrangement including: a carrier; a chip disposed over the carrier, the chip including one or more contact pads, wherein a first contact pad of the one or more contact pads is electrically contacted to the carrier; a first encapsulation material at least partially surrounding the chip; and a second encapsulation material at least partially surrounding the first encapsulation material.
    Type: Grant
    Filed: November 16, 2012
    Date of Patent: November 10, 2015
    Inventors: Ralf Otremba, Josef Hoeglauer, Juergen Schredl, Xaver Schloegel, Klaus Schiess, Bernd Roemer, Edward Fuergut
  • Patent number: 9159649
    Abstract: A microelectronic package comprises a die (110, 210) and a plurality of electrically conductive layers (120, 220) and electrically insulating layers (130, 230), including a first electrically insulating layer (131, 231) closer to the die than any other electrically insulating layer) and second (132, 232) and third electrically insulating layers (233). Each electrically insulating layer has a corresponding glass transition temperature, coefficient of thermal expansion, and modulus of elasticity. The modulus of elasticity of the second electrically insulating layer is greater than that for the first electrically insulating layer, while CTE1 for the second electrically insulating layer is greater than CTE1 for the first. CTE2 for the third electrically insulating layer is less than CTE2 for the first electrically insulating layer. In an embodiment an electrically insulating layer is a glass cloth layer (140) that is an outermost layer of the microelectronic package.
    Type: Grant
    Filed: December 20, 2011
    Date of Patent: October 13, 2015
    Assignee: Intel Corporation
    Inventors: Pramod Malatkar, Drew W. Delaney, Rahul N. Manepalli, Dilan Seneviratne
  • Patent number: 9024455
    Abstract: A semiconductor encapsulation adhesive composition comprising (a) an epoxy resin, (b) a curing agent and (c) an antioxidant.
    Type: Grant
    Filed: May 26, 2010
    Date of Patent: May 5, 2015
    Assignee: Hitachi Chemical Company, Ltd.
    Inventors: Kazutaka Honda, Tetsuya Enomoto, Yuuki Nakamura
  • Patent number: 9017822
    Abstract: There is provided a semiconductor device that suppresses the occurrence of resin burrs and has favorable electrical connectivity and bond strength, and a manufacturing method for such semiconductor device. A resin-coated metal part is manufactured by forming an organic coating by depositing a material including functional organic molecules on a wiring lead composed of a metallic material. Each of the functional organic molecules includes a main chain, a first functional group having a metal bonding property, and a second functional group. The first functional group and the second functional group are provided at different ends of the main chain. Thereafter the functional organic molecules self-assemble by bonding of the first functional groups to metal atoms of the wiring lead. After performing the organic coating formation step, resin is adhered to a predetermined surface area of the wiring lead having the organic coating formed thereon.
    Type: Grant
    Filed: March 2, 2007
    Date of Patent: April 28, 2015
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Takahiro Fukunaga, Ryoutarou Imura