Abstract: In the previously known methods for tuning the antenna resonant circuit, in the case of passive transponders, their range in a high-frequency carrier field is generally limited to a few cm as the supply voltage for the integrated circuit gained from the carrier field falls very quickly with increasing distance.

Abstract: A method is described for repairing failure points, regions or locations in an electronic device to have a perfect function when a semiconductor device including an LCD or other electronic device has defects. Described is a method of transferring a single or multi-layer thin film piece into a recess with the physical properties of the thin film piece unchanged.

Abstract: A semiconductor device for picking up an image includes a lens-mounting unit provided with a lens for picking up an image; a semiconductor chip having a light-receiving element formed on a circuit-forming surface thereof, the light-receiving element converting light from the lens into an image signal; a flexible substrate provided between the lens-mounting unit and the semiconductor chip so as to supply the image signal to an external circuit; and a shading plate blocking light transmitting through the flexible substrate toward the semiconductor chip so as to substantially remove an influence of the light on the light-receiving element.

Abstract: A semiconductor chip bearing an alignment mark, particularly useful for wire bonder alignment on chips having bonding surfaces over the active circuits. The marks are fabricated on diagonal corners of the chip, and each mark consists of a pair of touching squares which are rotated about 90 degrees from each other in the opposite chip corners. The unique positioning of the marks, as well as the rotation provides both gross chip position features useful in mounting the chip on a lead frame, as well as fine alignment set-up or teaching aids for wire bonding. The small, high visual contrast features of the alignment mark are fabricated simultaneously with the top active metallization of the IC chip, and are not covered by passivation coating or additional metal layers.

Abstract: A memory device and related methods are described. The memory device includes a plurality of cells, each cell including a MOSFET having a source coupled to a first end of a channel, a drain coupled to a second end of the channel, a gate formed on a gate insulator and extending from the source to the drain and a plurality of conductive islands, each surrounded by an insulator, formed in the channel. The islands have a maximum dimension of three nanometers. The surrounding insulator has a thickness of between five and twenty nanometers. Each island and surrounding insulator is formed in a pore extending into the channel. As a result, the memory cells are able to provide consistent, externally observable changes in response to the presence or absence of a single electron on the island.

Abstract: This invention relates to a heat conductive resin substrate which polybenzasol fibers are oriented in a thick direction and/or a direction of a surface of a resin substrate, further to the heat conductive resin substrate and a semiconductor package excellent in heat radiation ability which the semiconductor chips are mounted on the heat conductive resin substrate which the polybenzasol fibers are oriented in the thick direction (the Z direction) and/or the direction of the surface of the resin substrate, the heat conductive resin substance and the semiconductor package being provided with electrical insulation and high thermal conductivity, and being capable of controlling the thermal expansion coefficient.

Abstract: The present invention relates to a method for forming an insulating film with a low relative dielectric constant. A method for forming an insulating film in terms of a plasma chemical vapor deposition, characterized in that a Si supply gas, an oxygen supply gas, and a fluorine supply gas are used a material gas to form said insulating film, and said insulating film is formed under a film forming condition that a density of said insulating film to be formed is equal to or more than 2.25 g/cm3.

Abstract: A method of manufacturing an integrated circuit and an integrated circuit employing the same. In one embodiment, the method of manufacturing the integrated circuit includes (1) conformally mapping a micromagnetic device, including a ferromagnetic core, to determine appropriate dimensions therefor, (2) depositing an adhesive over an insulator coupled to a substrate of the integrated circuit and (3) forming the ferromagnetic core of the appropriate dimensions over the adhesive.

Abstract: A dot mark having at its center a peaked portion rising from a face to be marked is provided on a cut face or ground face of a semiconductor wafer with the face to be marked having surface roughness of 0.3 &mgr;m or less. The rising dot mark is 1 to 15 &mgr;m in maximum length along the face to be marked and 0.01 to 5 &mgr;m in height. With even such a fine size, the dot mark is superior in visibility. This makes it possible to provide a semiconductor base material in which all processing histories in a process for manufacturing a semiconductor wafer and a semiconductor, wafer ID, chip ID, and manufacturing number or the like can be recognized.

Abstract: A small circuit board, preferably having or providing capacitance is mounted on the surface of a main circuit board opposite the surface where a BGA or other integrated circuit is mounted, and within the footprint defined the integrated circuit package. Preferably the small circuit board is formed from multiple interleaved conductive and dielectric layers to provide inherent capacitance in the circuit board itself. Capacitance provided by the small circuit board can be configured by selecting the number and/or size and/or placement of the conductive layers. Discrete devices can be mounted on the small circuit board if desired.

Abstract: In a semiconductor device comprising patterns Pa1 through Pa3 which include (n+1) patterns (n is a natural number) for alignment arranged in a first direction which corresponds to a reading direction in pattern recognition, and patterns Pc1 formed in a mark proximity region Rc1, which include at least two patterns in at least the first direction, defining the pitches between the patterns Pa1 and Pa2 and between Pa2 and Pa3 as d1 and d2, respectively, defining the pitch between the patterns Pc1 in the first direction as dD, and defining the distance from the pattern Pa1 to the outside edge of the mark proximity region Rc1 as D, then, the dD is set so as to satisfy the relational expressions |(dD−d1)/d1|≧&agr; and |(dD−d2)/d2|&agr;(1>&agr;>0) in the mark proximity region Rc1 in which at least D≦d1+d2 is satisfied.

Abstract: Selective placement of polishing dummy feature patterns, rather than indiscriminate placement of polishing dummy feature patterns, is used. Both low frequency (hundreds of microns and larger) and high frequency (10 microns and less) of topography changes are examined. The polishing dummy feature patterns can be specifically tailored to a semiconductor device and polishing conditions used in forming the semiconductor device. When designing an integrated circuit, polishing effects for the active features can be predicted. After polishing dummy feature pattern(s) are placed into the layout, the planarity can be examined on a local level (a portion but not all of the device) and a more global level (all of the device, devices corresponding to a reticle field, or even an entire wafer).

Abstract: A part maintenance device of a semiconductor processing system and a method for operating the same wherein the abnormal operation of parts of the system is detected, thereby preventing the system breakdown and accident before their occurrence. The normal operation time of a part and the allowable limit value levels corresponding thereto are set and stored, the allowable limit value levels being a plurality of discrete levels (Step 101). Then, the system is actually driven (Step 102) and the actual operation time of the part is measured (Step 103). In the next, the allowable limit value levels of the normal operation time of the part and the actual normal operation time of the part are compared with each other thereby the need of the part maintenance being judged (Step 104). If it is judged that the part is OK, the part will be allowed to run continuously thereafter. If judged NG, a post-processing will be executed corresponding to the value level (Step 105).

Abstract: The present invention includes a first semiconductor element forming member formed in a first layer, a first measurement mark formed by the same manufacturing step as the first semiconductor element forming member, a second semiconductor element forming member formed in a second layer above the first layer, and a second measurement mark formed in the same manufacturing step as the second semiconductor element forming member for measuring registration accuracy between the first and second semiconductor element forming members. The first measurement mark has a pattern which receives same influence of aberration as the first semiconductor element forming member when irradiated with light, and the second measurement mark has a pattern which receives same influence of aberration as the second semiconductor element forming member when irradiated with light. Thus, a registration accuracy measurement mark taking into consideration the influence of aberration can be provided.

Abstract: A package for semiconductor devices is encapsulated in an insulating resin. Multiple conductive leads project from one side of the package. Alternating leads are provided with an insulating coating which projects along a portion of their length. Leads which are not insulated are bent so as to displace them from the plane of the coated leads and space them further away from the coated leads. The bent leads are displaced a sufficient distance to provide a separation in air consistent with spacing standards for high voltage devices.

Abstract: A circuit isolation technique that uses implanted ions in embedded portions of a wafer substrate to lower the resistance of the substrate under circuits formed on the wafer or portions of circuits formed on the wafer to prevent the flow of injected currents across the substrate. The embedded ions provide low resistance regions that allow injected currents from a circuit to flow directly to a ground potential in the same circuit rather than flowing across the substrate to other circuits. High energy implantation processes on the order of 1 MeV to 3 MeVs can be used to implant the ions in embedded regions. Multiple energy levels can be used to provide thick embedded layers either prior to or after application of an epitaxial layer. Various masking materials can be used to mask the isolation regions during the implantation process, including hard masking materials such as silicon dioxide or silicon nitride, poly-silicon or an amorphous silicon layer, and a photoresist layer.

Abstract: For an integrated semiconductor chip to operate reliably, it is necessary to homogenize a substrate potential as far as possible in all regions of the chip. In order to improve the substrate contact-connections on the chip, modular dummy structures are configured in such a way that, in addition to homogenizing the areal occupancy of the chip, they form extensive electrically conductive contact between the substrate and metal interconnects of a metallization plane of the chip. This achieves homogenization of the substrate potential and improvement of the wave guiding properties of wiring planes lying above the dummy structures without an additional process step or an additional chip area being required for this purpose.

Abstract: An improved alignment mark used by a laser trimming tool to locate fuses in an underlying integrated circuit is formed using conventional processing sequences. The design features high resolution and improved low noise characteristics. The alignment mark is etched in a shallow layer over a metal layer rather than in the metal itself. The edges which are sensed by the scanning alignment laser of the trimming tool have their elevated portions external to the alignment mark. The improved design replaces a prior art design in which the metal mark protruded from a deep area in the site region. Debris in deep areas adjacent to alignment marks etched in metal, is avoided by the improved design. The absence of this debris virtually eliminates noise in the alignment scan thereby greatly reducing alignment errors.

Abstract: An apparatus and method for use in raising cattle, and in particular bulls, wherein bulls are:

Abstract: Methods are disclosed for performing reticle-substrate alignments in the context of charged-particle-beam (CPB) microlithography. More specifically, the subject methods pertain to detecting an amount of relative rotation between the “transfer-receiving” (e.g., substrate) side and the “transfer-originating” (e.g., reticle) side in one operation simply by detecting marks that are disposed near an axis of the CPB-optical system. A charged particle beam is passed through an alignment mark(s) situated relative to an alignment axis of the reticle and thus indicates reticle orientation. One or more respective index marks are defined on the substrate relative to an alignment axis of the substrate, thereby indicating substrate orientation. E.g., two index marks can be provided on the substrate, one convex and the other concave, but otherwise similarly shaped. The index marks can be situated linearly aligned with each other or at an angle to each other.

Abstract: A ball grid array substrate includes a circumferential edge provided with a plurality of charts each having a plurality of lattices corresponding to positions of chips on the ball grid array substrate for indicating positions of defective chips in different packaging procedures whereby positions of the defective chips can be easily observed.

Abstract: A method for fabricating a monolithic micro-optical component. The construction of the micro-optical components is accomplished by using standard semiconductor fabrication techniques. The method comprises the steps of depositing an etch stop layer (44) onto a semiconductor substrate (42); depositing an optical component layer (46) onto the etch stop layer (44); coating the entire surface of the optical component layer with a photoresist material; applying a photoresist mask (50) to the photoresist material on the optical component layer (46); selectively etching away the optical component layer (46) to form at least one optical column (52); forming a pedestal (54) for each of the optical columns (52) by selectively etching away the etch stop layer (44); and finally polishing each of the optical columns (52), thereby forming monolithic optical components (56).

Abstract: A novel method and apparatus for indicating a degree of manufacture of an insert molded component useable in an end use assembly by forming a removable appendage protruding from the insert molded component, or article, manufactured to an intermediate degree, the insert molded component having a lead frame at least partially embedded in a molded housing member, and the removable appendage coupled to at least one or both of the lead frame and the molded housing member, the lead frame having at least two electrical conductors coupled separably by a tie member, the removable appendage removable upon or after electrical isolation of the electrical conductors in a subsequent processing step, whereby the presence of the removable appendage is indicative that the electrical conductors are not electrically isolated, or that the insert molded component has not been tested or inspected subsequent to electrical isolation of the electrical conductors, and whereby the removable appendage is configured to prevent use of the

Abstract: For use with an integrated circuit having a substrate and an insulator coupled to the substrate, a micromagnetic device and method of manufacturing therefor. In one embodiment, the micromagnetic device includes an adhesive coupled to the insulator and a ferromagnetic core, coupled to the adhesive that forms a bond between the insulator and the ferromagnetic core, having an anisotropic property.

Abstract: The present invention aims to provide a highly reliable semiconductor element with high performance, and a fabrication method for such highly reliable semiconductor with excellent mass producibility. The photovoltaic elements comprise an electric conductor, semiconductor regions and a transparent conductor layer, which are sequentially formed on a substrate. The shunt resistance in the semiconductor element is rendered in the range from 1.times.10.sup.3 .OMEGA.cm.sup.2 to 1.times.10.sup.6 .OMEGA.cm.sup.2 by performing a forming treatment and a short circuit passivation treatment after forming the transparent conductor layer, and then selectively covering with insulation the defective portions with a cationic or anionic electrodeposited resin, or performing a forming treatment, after forming the semiconductor layers, then selectively covering with insulation the defective portions with a cationic or anionic electrodeposited resin, and then forming the transparent conductor layer.

Abstract: An alignment mark for determining a position of a thin film resistor formed on a semiconductor chip. The alignment mark is disposed on a capacitor formation region of the semiconductor chip. Because aluminum wiring members of the semiconductor chip are not disposed adjacent to the alignment mark within the capacitor formation region, the alignment mark can be precisely recognized. As a result, the position of the thin film resistor can be also precisely determined.

Abstract: A semiconductor device in which a flat inner lead is connected to a semiconductor pellet so that a side edge of the inner lead is connected to the semiconductor pellet. The lead includes a constricted portion that is twisted so that the side edge faces a surface of the pellet to which the lead is connected. A lead frame is arranged so that the side edge can be twisted into position.

Abstract: A micromechanical memory sensor. The sensor comprises a latch member mechanically latching upon detection of a threshold value of a variable condition and circuitry for detecting such latching. A sensor further includes a resetting mechanism for electrically unlatching the latch member whereby the sensor latched purely mechanically is electrically reset for repeat use.

Abstract: A fiducial for aligning an integrated circuit die. In one embodiment, the fiducial is configured to be exposed by laser chemical etching through a silicon substrate through the back side of a C4 packaged integrated circuit die. The presently described fiducial includes floating diffusion regions disposed in the substrate. An oxide layer free of metal contacts is disposed over the diffusion regions within the fiducial region of the integrated circuit. A metal pattern layer is disposed beneath the oxide layer to provide alignment information. The metal pattern layer is configured to be visible through the oxide layer after the silicon substrate has been removed from the fiducial region. A light block is disposed between the metal pattern layer and an underlying epoxy underfill layer to minimize the risk of an excessive amount of light from being exposed to the underlying epoxy layer, which minimizes the risk of the epoxy layer from damaging the integrated circuit from excessive light exposure.

Abstract: Gettering enclosures for semiconductor packages, comprising an enclosure having a cavity for accommodating a semiconductor device; a gettering chamber (disposed above the semiconductor device) communicating with the cavity, comprising a getter precursor secured to the cavity and spaced from a wall of the cavity, wherein the wall is transparent to laser light so as to allow a beam of laser light to strike the getter precursor and sputter same on the walls of the gettering chamber.

Abstract: An integrated circuit includes a substrate and at least two circuits, such as a digital circuit and an analog circuit. The substrate is preferably derived from a bulk substrate wafer. The integrated circuit preferably comprises at least two islands in the substrate for noise isolation between the circuits. The two islands are buried-layers that are implanted, by preference, using conventional MeV techniques. A method of manufacturing an integrated circuit includes a substrate and at least two circuits. The method comprises the step of implanting at least two islands in the substrate for noise isolation between the circuits. The implanting is accomplished by conventional masking and high-energy implantation, such as MeV.

Abstract: A balanced frequency responsive circuit comprising circuit components formed in a semiconductor chip having first and second on-chip contact terminals which connect to first and second off-chip contact terminals, respectively, and a balanced parallel resonator circuit coupled to the contact terminals. The resonator circuit comprises a capacitance portion and an inductance portion. Part of the capacitance portion is on-chip connected between the first and second on-chip contact terminals. Another part of the capacitance portion and the inductance portion are off-chip series connected between the first and second off-chip contact terminals such that the contact terminals are comprised in a single resonant loop, essentially producing no spurious resonance signals.

Abstract: A method for manufacturing an electronic component by seal-molding with resin a die pad mounted by an electronic element thereon and loads of input-and-output terminals which are supported by a lead frame having an outer frame and removing such sealed electronic component with mold materials from the outer frame of the lead frame which includes suspending pins for supporting the leads and a first mold holder disconnected from the leads, the method including the steps of resin molding a first mold member on the leads and the first mold holder to join the leads and the first mold member with the first mold member, cutting the suspending pins between the first mold member and the outer frame, resin-molding a second mold member on the first mold member to cover the cut ends of the suspending pins, and cutting the first mold holder between the second mold member and the outer frame to remove thus molded electronic component from the lead frame.

Abstract: A device and method are described for defining a region on a wall of a semiconductor structure, such as a sidewall of a trench formed in a semiconductor substrate. The method includes the steps of forming a vertical structure above the semiconductor structure and spaced parallel to the wall; providing within the vertical structure an area of one of transparence, reflection or refraction; and projecting light at a given angle to the wall, wherein only a portion of the light passes the vertical structure via the area provided therein to impinge upon the wall of the semiconductor structure, and thereby define the region on the wall. As an alternative, the area can comprise an aperture in the vertical structure such that the vertical structure can be employed as a mask to direct selective ion implantation of the wall.

Abstract: In a semiconductor single crystalline substrate provided with a protecting film to prevent autodoping on the reverse surface thereof, for growing a vapor-phase epitaxial layer on the main obverse surface thereof, a width of a chamfer is set for locating an edge-crown occurred in consequence of a vapor-phase epitaxial growth on the chamfer, and a gap of a distance is formed between a periphery of the protecting film and an innermost part of the chamfer on the reverse surface.

Abstract: An integrated circuit package comprises a power supply conductor film having a potential and conductor columns insulated from and passed through the power supply conductor film. A power supply conductor column comprises one of the conductor columns connected to a power supply having a potential different from the power supply conductor film. The other conductor columns are signal conductor columns for exchanging signals with mounted integrated circuits. An insulation space between the power supply conductor film and the power supply conductor column is greater than an insulation space between the power supply conductor film and a signal conductor column. Thereby, a probability of short-circuit occurrence in the power supply conductor film across the power supply conductor column is lowered.

Abstract: A phase shifting mask has a light shielding region and a light transmitting region including a light transmitting area and a first phase shifting area which is disposed between the light transmitting area and the light shielding region. The light transmitting region also includes a second phase shifting area disposed between the light shielding region and the first phase shifting area for producing a difference in phase between light that has passed through the second phase shifting area and light that has passed through the first phase shifting area. The phase shifting mask allows an optimum exposure light intensity to be set easily even if the phase shifting area width is large, and also makes it possible to form a desired pattern image on a wafer even if there is a positional misalignment between the light shielding region and the light transmitting area.

Abstract: A memory card includes two types of memory integrated circuits (ICs) and two connectors located on opposite sides of the card. One connector is electrically connected to one type of memory ICs, and the other connector is electrically connected to the other type of memory ICs. This allows two kinds of functions to coexist within a single memory card. The two types of memory ICs are a dynamic random access memory (DRAM) IC and a read-only memory (ROM) IC, respectively.

Abstract: Disclosed is an alignment mark for the X directional alignment of a chip area on a semiconductor wafer, for example. The alignment mark comprises recesses and projections formed on a semiconductor substrate. The recesses or projections are repeatedly arranged in the X direction. The X directional width of the recesses or projections is set smaller than the X directional width of a grain on a metal film formed on the recesses and projections or the average particle size, as viewed from above the semiconductor substrate. The projections may be formed by a insulating layer formed on the semiconductor substrate.

Abstract: An electronic element is provided which includes a pair of electrodes (referred to as facing electrodes) formed within the groove of an insulating film on the substrate, the end portions of the electrodes being separated and facing each other in the groove. When a voltage of a predetermined value or more is applied between the facing electrodes, there occurs a cold cathode emission which causes a flow of electrons from one of the electrodes to the other. At that time, the facing electrodes are melted by heat generated by the applied voltage, and either a short circuit or insulation between the facing electrodes, is attained, depending on the selected structure of the element. In this way, the electronic element of the present invention can perform the protection of semiconductor devices and semiconductor circuits. Also, the electronic element of the present invention can perform the operation of selecting a desired load resistance to be applied to a specific circuit.

Abstract: A circuit die (10) has circuit modules (12a-12f). Adjacent the circuit modules (12a-12f) is a plurality of redundant circuits regions (14a-14i). Each of the redundant circuit regions (14a-14i) has one or more redundant circuits, such as redundant circuits (16k-16n). The redundant circuits (16k-16n) are identified and oriented via one of a binary, a ternary, or a quaternary circuit identifier comprised of symbols, such as symbols (18, 24, 44, and 56). The symbols (18, 24, 44, and 56) are capable of being lithographically defined in a small surface area and therefore minimize the surface area consumed by the redundant circuits regions (14a-14i). The redundant circuits (16k-16n) are preferably used by focused ion beam (FIB) equipment to replace, repair, or supplement various electrically functional portions of the circuit modules (12a-12f).

Abstract: Carbonaceous materials based on the fullerene molecules have been developed which allow for high conductivity (comparable to or higher than those attained by n-type doped polyacetylene). The fullerene materials are soluble in common solvents.

Abstract: A contact structure is formed atop a semiconductor wafer at a level whereat it is desired to terminate polishing of a layer overlying the contact structure. When the contact structure becomes exposed to a polishing slurry, an electrical characteristic, such as resistance or impedance, is registered by measuring apparatus. In one embodiment, two or more contact structures are formed atop the wafer, vias are formed through the wafer, and the vias are filled, thereby providing a conductive path from the contact structures to the back side of the wafer. The measuring apparatus probes the filled vias on the back side of the wafer. A change in resistance/impedance indicates that the contact structures have become exposed during polishing, and polishing is terminated. In another embodiment of the invention, one or more contact structures are formed atop the wafer. The measuring apparatus is connected to a probe in the polishing slurry, and to the wafer itself, such as to the back side of the wafer.

Abstract: A semiconductor device has structures to reduced stress notching effects in conductive lines. In one form, the semiconductor device includes a semiconductor die which has a plurality of active conductive lines thereon. The plurality of conductive lines collectively has a first and a second outside edge. In close proximity to each of the first and the second outside edges is a stress reducing line. Each of the stress reducing lines is a non-active structure (in other words does not transmit signals) and functions to reduce stress concentrations on the plurality of active conductive lines which are imposed by overlying insulating and passivation layers. As a result of weakened stress concentrations, the amount of stress notching in the active conductive lines is reduced.

Abstract: An improved mask and method of forming a deep and width trench in a substrate and the resulting structure is disclosed. A substrate material such as silicon has deposited thereon a first layer of sacrificial material as a first component of an etch mask, the sacrificial material being a material such as polysilicon that is either etched by or absorbs the same ions which reactively ion etch the substrate. A second layer of material, which resists reactive ion etching, such as silicon dioxide, is deposited over the first layer of material as a second component of the etch mask. The silicon dioxide is patterned in the form of the trench to be formed in the substrate. The layer polysilicon material is then reactive ion etched and the reactive ion etching continued to form a trench in the silicon substrate. The polysilicon acts as a sacrificial material being etched by any ions that are reflected from the silicon dioxide or are directed at an angle such that they strike the layer of polysilicon material.

Abstract: A high bandwidth RF sampler using equivalent time sampling comprising an RF coplanar waveguide integrated with sampling diodes on a gallium arsenide substrate. A monolithic, integrated nonlinear transmission line is integrated on the same substrate to receive sample pulses. These pulses are reshaped by the nonlinear transmission line to have a very fast edge. This edge is differentiated by a shunt inductance of a short circuit termination of a slot line portion of the RF signal coplanar waveguide. The resulting delta function sample pulses cause the sample diodes and integrated capacitors to develop an intermediate output frequency which is a replica of the RF signal at a lower frequency and no voltage conversion loss. RF signals of up to 300 Ghz can be sampled using this circuit.

Abstract: In a semiconductor device encapsulation assembly (50; 60), a semiconductor device (21), preferably a pressure transducer, is mounted on a base (11) in a cavity (20) formed by the base and surrounding walls (15). Electrical connections, preferably wire bonds (27), connect the semiconductor device to conductor paths (28) on the base within the cavity. An encapsulation material comprising a thixotropic fluorosiloxane material (51; 61) is applied in the cavity and completely covers the semiconductor device and the electrical connections. This structure enables the semiconductor device to withstand typical automotive contaminants, such as mild acids and gasoline, while also preventing erratic semiconductor device operation due to bubbles which may be drawn into the encapsulation material.

Abstract: Lead frames, in which at least one part of the surface of a metal member which is a part of the lead frame is provided with an anodic oxide film of copper or a copper alloy, and in which a member composed substantially of a resin film or a resin plate is connected to the lead frame through this anodic oxide film by gluing or pressing under heat exhibit good adhesion between the metal member and the resin film or plate. Similarly, lead frames constructed with at least two metal members, having a portion of the surface provided with an anodic oxide film of copper or a copper alloy, and in which these metal members are joined together through this anodic oxide film exhibit good adhesion between the metal members.

Abstract: An apparatus for monitoring the current in an integrated circuit provided with a current conductor which is to supply current to a semiconductor structure at least temporarily and to supply current to other parts of the circuit. The current conductor is locally split into a first and a second parallel partial current conductor, with the semiconductor structure connected to the first partial current conductor. The first and second partial current conductors are connected to respective first and second connection contacts across which a voltage drop can be derived which is a measure of the value of the current flowing through the semiconductor structure.