Abstract: Disclosed is an adhesive composition used for adhesion of a semiconductor chip which contains a radiation polymerizable compound, a photoinitiator, and a thermosetting resin. When the adhesive composition forming an adhesive layer is brought to a B-stage by irradiation with light, the surface of the adhesive layer has a tack force of 200 gf/cm2 or less at 30° C. and 200 gf/cm2 or more at 120° C.

Abstract: A semiconductor device and a manufacturing method therefor, wherein, during lift-off, no cracks due to internal stresses occur in the compound semiconductor layer. A method for manufacturing a semiconductor device having a structure in which a semiconductor layer is bonded on a supporting substrate, including: a device region formation step of forming a device region including the semiconductor layer on a growth substrate through a lift-off layer; a columnar member formation step of forming a columnar member on the growth substrate; a bonding step of bonding the tops of the semiconductor layer and the columnar member to a supporting substrate; a lift-off step of separating the bottom face of the semiconductor layer from the growth substrate by removing the lift-off layer, and not separating the columnar member from the growth substrate; and a step of separating the columnar member from the supporting substrate.

Abstract: The method for manufacturing a film-like adhesive according to the present invention includes: applying an adhesive composition comprising (A) a radiation-polymerizable compound, (B) a photoinitiator and (C) a thermosetting resin, and having a solvent content of 5% by mass or lower and being liquid at 25° C., on a base material to thereby form an adhesive composition layer; and irradiating the adhesive composition layer with light to thereby form the film-like adhesive.

Abstract: An arrangement comprising at least one power semiconductor module and a transport packaging, wherein the power semiconductor module has a base element, a housing and connection elements and the transport packaging has a generally planar cover layer, a cover film and at least one trough-like plastic shaped body for each power semiconductor module. The at least one plastic shaped body only partly encloses the respective power semiconductor module and a part of the plastic shaped body does not directly contact the power semiconductor module. Furthermore, a first side of the at least one power semiconductor module becomes situated directly or indirectly on the first main surface of the cover layer, while the cover film covers the further sides of the power semiconductor module directly and/or indirectly, and bears at least partly against the plastic shaped body.

Abstract: In one embodiment, an adhesive layer is formed by applying a liquid adhesive to a semiconductor wafer whose wafer shape is maintained by a surface protective film attached to a first surface. A supporting sheet having a tacky layer is attached to a second surface of the semiconductor wafer. After the surface protective film is peeled, the supporting sheet is expanded to cleave the adhesive layer including the adhesive filled into the dicing grooves. The first surface of the semiconductor wafer is cleaned while an expansion state of the supporting sheet is maintained. Tack strength of portions corresponding to the dicing grooves of the tacky layer is selectively reduced before cleaning.

Abstract: A composition for a patternable adhesive film, a patternable adhesive film having the same, and a method of manufacturing a semiconductor package using the patternable adhesive film are provided. The composition contains a binder resin, a radical-polymerizable acrylate monomer, a photo-radical initiator, and a thermal-radical initiator without an epoxy resin. The composition may have good patternability, adhesiveness, and low-temperature stability, and be rapidly cured at a low temperature.

Abstract: A dicing die bonding film including a bonding layer; and a pressure-sensitive adhesive layer adjoining the bonding layer, the pressure-sensitive adhesive layer having a storage modulus of about 400 to about 600 kPa at 25° C. and a peel strength of about 200 to about 350 mN/25 mm with respect to the bonding layer as measured according to KS-A-01107 standard.

Abstract: A method of manufacturing a semiconductor wafer bonding product according to the present invention includes: a step of preparing a spacer formation film including a support base having a sheet-like shape and a spacer formation layer provided on the support base and having photosensitivity; a step of attaching the spacer formation layer to a semiconductor wafer having one surface from a side of the one surface; a step of forming a spacer by subjecting exposure and development to the spacer formation layer to be patterned and removing the support base; a step of bonding a transparent substrate to a region of the spacer, with which the removed support base made contact, so as to be included within the region. This makes it possible to manufacture a semiconductor wafer bonding product in which the semiconductor wafer and the transparent substrate are bonded together through the spacer uniformly and reliably.

Abstract: To provide a semiconductor substrate, a semiconductor device, a light emitting device and an electronic device which have a low price, a long lifetime, and a high luminescent efficiency, and moreover are capable of being bent. A graphite substrate having heat resistance and having flexibility with respect to external force, and a first semiconductor layer, provided on the graphite substrate, which is made of a nitride of the Group XIII are included, and a method such as pulse sputter deposition can be used in forming the first semiconductor layer on the graphite substrate, to thereby allow inexpensive manufacture to be possible. In addition, since the nitride of the Group XIII is an inorganic substance, it has a long lifetime, and thus a high luminescent efficiency can be obtained. Moreover, since the graphite substrate has flexibility with respect to external force, it can also be bent.

Abstract: The die bonding resin paste of the invention comprises a polyurethaneimide resin represented by the following general formula (I), a thermosetting resin, a filler and a printing solvent. [wherein R1 represents a divalent organic group containing an aromatic ring or aliphatic ring, R2 represents a divalent organic group with a molecular weight of 100-10,000, R3 represents a tetravalent organic group containing 4 or more carbon atoms, and n and m each independently represent an integer of 1-100.

Abstract: A thin film integrated circuit which is mass produced at low cost and a method for manufacturing a thin film integrated circuit according to the invention includes the steps of: forming a peel-off layer over a substrate; forming a base film over the peel-off layer; forming a plurality of thin film integrated circuits over the base film; forming a groove at the boundary between the plurality of thin film integrated circuits; and introducing a gas or a liquid containing halogen fluoride into the groove, thereby removing the peel-off layer; thus, the plurality of thin film integrated circuits are separated from each other.

Abstract: To provide a photosensitive adhesive which is sufficiently excellent in terms of all the properties of attachment, pattern formability, thermocompression bondability and high-temperature adhesion, and which has thermocompression bondability for adherends after patterning by exposure and development, and is capable of alkali development, as well as a film adhesive, an adhesive sheet, an adhesive pattern, a semiconductor wafer with an adhesive layer and a semiconductor device, which employ the same. A photosensitive adhesive comprising (A) an imide group-containing resin with a fluoroalkyl group, (B) a radiation-polymerizable compound, (C) a photoinitiator and (D) a thermosetting component.

Abstract: Provided is an adhesive composition having both excellent storability and excellent connection reliability. The adhesive composition comprises (a) a polyimide soluble in organic solvents, (b) an epoxy compound, (c) particles of a curing accelerator, and (d) inorganic particles, the amounts of the organic-solvent-soluble polyimide (a) and the curing-accelerator particles (c) being 15-90 parts by weight and 0.1-50 parts by weight, respectively, per 100 parts by weight of the epoxy compound (b), and the content of the inorganic particles (d) being 30-80 wt. % of the total amount of (a) to (d).

Abstract: A nitride semiconductor wafer is planar-processed by grinding a bottom surface of the wafer, etching the bottom surface by, e.g., KOH for removing a bottom process-induced degradation layer, chamfering by a rubber whetstone bonded with 100 wt %-60 wt % #3000-#600 diamond granules and 0 wt %-40 wt % oxide granules, grinding and polishing a top surface of the wafer, etching the top surface for eliminating a top process-induced degradation layer and maintaining a 0.5 ?m-10 ?m thick edge process-induced degradation layer.

Abstract: An in-line capacitor, having a pair of inner conductor segments, each of the inner conductor segments having a mating surface. A dielectric spacer positioned between the mating surfaces, each of the mating surfaces having corresponding folds formed thereon.

Abstract: A method for manufacturing a semiconductor device having fluorocarbon layers as insulating layers includes the steps of forming a first fluorocarbon (CFx1) layer using plasma excited by microwave power and forming a second fluorocarbon (CFx2) layer using plasma excited by an RF power.

Abstract: Techniques are provided for efficient wafer layout, which include the use of an offset grid to optimize use of available wafer space. As such, the number of identical die that can be fabricated on the wafer can be increased, relative to a standard perpendicular grid. By adding additional registration marks, an increase in flexibility of where each row/column of fields can be printed is enabled. This increased level of freedom in-turn allows for the optimization of the number of die that each row/column can contain, and translates directly into an increase in the number of yielding die per wafer. In addition, techniques are provided that allow for the dicing of individual die in a non-Cartesian coordinated manner. However, conventional singulation techniques can be used as well, given attention to the offset grid lines.

Abstract: An interlevel dielectric layer, such as a silicon oxide layer, is selectively etched using a plasma etch chemistry including a silicon species and a halide species and also preferably a carbon species and an oxygen species. The silicon species can be generated from a silicon compound, such as SixMyHz, where “Si” is silicon, “M” is one or more halogens, “H” is hydrogen and x?1, y?0 and z?0. The carbon species can be generated from a carbon compound, such as C?M?H?, where “C” is carbon, “M” is one or more halogens, “H” is hydrogen, and ??1, ??0 and ??0. The oxygen species can be generated from an oxygen compound, such as O2, which can react with carbon to form a volatile compound.

Abstract: The invention relates to multi-planar logic components in a three-dimensional (3D) integrated circuit (IC) apparatus configuration. A multi-planar integrated circuit connected by through silicon vias is configured to connect microprocessor, FPGA and memory components. The integrated circuit components may be on tiles of layers of the 3D IC.

Abstract: In the manufacture of semiconductor devices, cracking of a resin member caused during cutting and defects in the external appearance are prevented.

Abstract: A film frame aligner for automatically aligning a film frame includes a film frame support, a film frame pusher for pushing the film frame, and a film frame location mechanism for locating at least one notch in the film frame.

Abstract: Semiconductor structures including a movable switching element having a base disposed on a conductive pad, a body extending from the base, and an end laterally adjacent and spaced apart from a conductive contact are disclosed. Upon application of a threshold voltage, the movable switching element may deform toward the conductive contact via an electrical field, establishing electrical contact between the conductive pad and the conductive contact. Various methods may be used to form such semiconductor structures, and switching devices including such semiconductor structures. Memory devices and electronic systems include such switching devices.

Abstract: Synchronization between command and address signals commonly coupled to a plurality of memory devices to be operated in parallel and a clock signal coupled to the memory devices is achieved, while suppressing an increase in the clock wiring length. A semiconductor device has a data processing device mounted on a wiring substrate and a plurality of memory devices accessed in parallel by the data processing device. The data processing device outputs the command and address signals as a first frequency from command and address terminals, and outputs a clock signal as a second frequency from a clock terminal. The second frequency is set to multiple times of the first frequency, and an output timing equal to or earlier than a cycle starting phase of the clock signal output from the clock terminal can be selected to the command and address signals output from the command and address terminals.

Abstract: A scribe line structure is disclosed. The scribe line structure includes a semiconductor substrate having a die region, a die seal ring region, disposed outside the die region, a scribe line region disposed outside the die seal ring region and a dicing path formed on the scribe line region. Preferably, the center line of the dicing path is shifted away from the center line of the scribe line region along a first direction.

Abstract: Semiconductor nanoparticles having high luminescence properties that are preferable for applications and uses of biotechnology are provided. With the use of electric charges on the surfaces of particles, the particles and selected polymers are allowed to electrostatically bind to each other, such that the surfaces of the particles are coated. The polymers are allowed to crosslink to each other, resulting in the improved durability of the particles. Further, functional groups contained in the polymers are exposed on the surfaces of the particles. Accordingly, semiconductor nanoparticles that are preferably utilized for applications such as staining and labeling of biopolymers have been synthesized.

Abstract: A shadow mask deposition system includes a plurality of identical shadow masks arranged in a number of stacks to form a like number of compound shadow masks, each of which is disposed in a deposition vacuum vessel along with a material deposition source. Materials from the material deposition sources are deposited on the substrate via openings in corresponding compound shadow masks, each opening being formed by the whole or partial alignment of apertures in the shadow masks forming the compound shadow mask, to form an array of electronic elements on the substrate.

Abstract: A double-faced adhesive film including: a supporting film; a first adhesive layer laminated on one surface of the supporting film; and a second adhesive layer laminated on the other surface of the supporting film, wherein the glass transition temperatures, after curing, of the first adhesive layer and the second adhesive layer are each 100° C. or lower, and the first adhesive layer and the second adhesive layer are the layers capable of being formed by a method including the steps of directly applying a varnish to the supporting film and drying the applied varnish.

Abstract: The present invention provides a die bond film for adhering, onto a semiconductor element that is electrically connected to an adherend with a bonding wire, another semiconductor element and that enables loading of the other semiconductor element and improvement in the manufacturing yield of a semiconductor device by preventing deformation and cutting of the bonding wire, and a dicing die bond film. The die bond film of the present invention is a die bond film for adhering, onto a semiconductor element that is electrically connected to an adherend with a bonding wire, another semiconductor element, in which at least a first adhesive layer that enables a portion of the bonding wire to pass through inside thereof by burying the portion upon press bonding and a second adhesive layer that prevents the other semiconductor element from contacting with the bonding wire are laminated.

Abstract: Disclosed is a semiconductor device that includes: a semiconductor substrate; a first insulating film formed above the semiconductor substrate and having a relative dielectric constant of 3.8 or less; a conductor which covers a side face of the first insulating film at least near four corners of the semiconductor substrate, and at least an outer side face of which has a conductive barrier layer; and a second insulating film covering the outer side face of the conductor and having a relative dielectric constant of over 3.8. Also disclosed is a semiconductor device that includes: a conductor covering a side face of the first insulating film at least near four corners of the semiconductor substrate; and a corrosion resistant conductor formed at least near the four corners of the semiconductor substrate to extend from directly under the second insulating film to directly under the conductor.

Abstract: A positive tone photosensitive composition comprising: (A) an alkali-soluble resin having a phenolic hydroxyl group; (B) a phenol resin modified by a compound having an unsaturated hydrocarbon group containing 4 to 100 carbon atoms; (C) a compound that generates an acid by the action of light; (D) a thermal cross-linker that crosslinks the ingredient (A) and the ingredient (B) by heating; and (E) a solvent.

Abstract: The present invention provides a semiconductor-device copper-alloy bonding wire which has an inexpensive material cost, ensures a superior ball joining shape, wire joining characteristic, and the like, and a good loop formation characteristic, and a superior mass productivity. The semiconductor-device copper-alloy bonding wire contains at least one of Mg and P in total of 10 to 700 mass ppm, and oxygen within a range from 6 to 30 mass ppm.

Abstract: The present invention relates to a method for producing a structure serving as an etching mask on the surface of a substrate. In this case, a first method involves forming a first partial structure on the surface of the substrate, which has structure elements that are arranged regularly and are spaced apart essentially identically. A second method involves forming spacers on the surface of the substrate, which adjoin sidewalls of the structure elements of the first partial structure, cutouts being provided between the spacers. A third method step involves introducing filling material into the cutouts between the spacers, a surface of the spacers being uncovered. A fourth method step involves removing the spacers in order to form a second partial structure having the filling material and having structure elements that are arranged regularly and are spaced apart essentially identically. The structure to be produced is composed of the first partial structure and the second partial structure.

Abstract: A method of cleaning a substrate includes contacting a surface of a semiconductor substrate with a composition comprising a superacid. The semiconductor substrate may be a wafer.

Abstract: The adhesive composition of the invention comprises (A) a thermoplastic resin with a Tg of no higher than 100° C. and (B) a thermosetting component, wherein the (B) thermosetting component includes (B1) a compound with an allyl group and (B2) a compound with a maleimide group.

Abstract: Semiconductor process technology and devices are provided, including a method for forming a high quality group III nitride layer on a silicon substrate and to a device obtainable therefrom. According to the method, a pre-dosing step is applied to a silicon substrate, wherein the substrate is exposed to at least 0.01 ?mol/cm2 of one or more organometallic compounds containing Al, in a flow of less than 5 ?mol/min. The preferred embodiments are equally related to the semiconductor structure obtained by the method, and to a device comprising said structure.

Abstract: Disclosed is a method for dicing a semiconductor wafer. The method for dicing a semiconductor wafer prevents a die from being contaminated with silicon dust, generated during the dicing of the wafer, and thus prevents defects in a subsequent wire bonding step, such as defects in bonding wire, contamination of a semiconductor device, etc. The method for dicing a semiconductor wafer comprises the steps of: applying a fluorine-containing polymer coating agent onto one surface of a wafer having a circuit pattern formed thereon to form a polymer coating layer, before dicing the wafer.

Abstract: A semiconductor device having a specific contact angle for immersion lithography is disclosed. The semiconductor device includes a substrate and a top layer disposed on the substrate. The top layer used in an immersion lithography process includes a composition such that a fluid droplet that occurs during the immersion lithographic process and is not part of an exposure fluid puddle, will have a contact angle between about 40° and about 80° with a surface of the top layer.

Abstract: A method (and structure) of quantum computing. Two independent magnitudes of a three-state physical (quantum) system are set to simultaneously store two real, independent numbers as a qubit. The three-state physical (quantum) system has a first energy level, a second energy level, and a third energy level capable of being degenerate with respect to one another, thereby forming basis states for the qubit.

Abstract: A structure for memorizing tensile stress in a semiconductor device includes a gate electrode of the semiconductor device; a silicon spacer adjacent to the gate electrode; and a capping layer encapsulating the gate electrode and the silicon spacer, wherein the silicon spacer and capping layer are configured to cause a tensile stress to be memorized in the gate electrode during an annealing process. A method for memorizing tensile stress in a semiconductor device includes forming a silicon spacer adjacent to a gate electrode of the semiconductor device; forming a capping layer over the silicon spacer and the gate electrode; and annealing the semiconductor device, wherein the silicon spacer and capping layer cause a tensile stress to be memorized in the gate electrode during annealing. A disposable silicon spacer is configured to induce a tensile stress in a semiconductor device during a stress memorization technique process.

Abstract: An object thereof is to provide a thermosetting die-bonding film that is capable of preventing warping of an adherend by suppressing curing contraction of the film after die bonding, and a dicing die-bonding film. The present invention relates to a thermosetting die-bonding film for adhering and fixing a semiconductor element onto an adherend, wherein the gel fraction in an organic component after thermal curing is performed by a heat treatment at 120° C. for 1 hour is 20% by weight or less, and the gel fraction in the organic component after thermal curing is performed by a heat treatment at 175° C. for 1 hour is in a range of 10 to 30% by weight.

Abstract: The present invention provides a film for a semiconductor device, which is capable of preventing interface delamination between each of the films, a film lifting phenomenon, and transfer of the adhesive film onto the cover film even during transportation or after long-term storage in a low temperature condition. The film for a semiconductor device of the present invention is a film in which an adhesive film and a cover film are sequentially laminated on a dicing film, in which a peel force F1 between the adhesive film and the cover film in a T type peeling test is within a range of 0.025 to 0.075 N/100 mm, a peel force F2 between the adhesive film and the dicing film is within a range of 0.08 to 10 N/100 mm, and F1 and F2 satisfy a relationship of F1<F2.

Abstract: A semiconductor device includes a wafer and a dicing saw tape that is laminated to a back surface of the wafer. An active surface of the wafer is opposite the back surface of the wafer. The semiconductor device further includes a lamination tape disposed in contact with the wafer. The lamination tape includes an under-film layer contacting the active surface of the wafer. The lamination tape further includes an adhesive layer contacting the under-film layer.

Abstract: A sensing system includes a nanowire, a passivation layer established on at least a portion of the nanowire, and a barrier layer established on the passivation layer.

Abstract: A geometric diode, method and device applications are described. The geometric diode is produced including a device body formed from an electrically conductive material having an equilibrium mobile charge density, and having a device surface configuration. The material has a charge carrier mean free path with a mean free path length and the device body size is selected based on said the free path length to serve as an electrically conductive path between first and second electrodes delimited by the device surface configuration that is asymmetric with respect to a forward flow of current in a forward direction from the first electrode to the second electrode as compared to a reverse current flow in an reverse direction from the second electrode to the first electrode. A system includes an antenna for receiving electromagnetic radiation coupled with the geometric diode antenna to receive the electromagnetic radiation to produce an electrical response.

Abstract: A substrate for fixing an integrated circuit element includes: a plurality of metal columns that are aligned in a longitudinal direction and a lateral direction in a planar view, each of the plurality of metal columns having a first face and a second face facing opposite direction to the first face; and a connecting part that connects the plurality of metal columns one another at a part of each of the plurality of metal columns between the first face and the second face. In the substrate, a recognition mark is formed on the first face of one of the plurality of metal columns.

Abstract: A method, structure, system of aligning a substrate to a photomask. The method comprising: directing light through a clear region of the photomask in a photolithography tool, through a lens of the tool and onto a set of at least three diffraction mirror arrays on the substrate, each diffraction mirror array of the set of at least three diffraction mirror arrays comprising a single row of mirrors, all mirrors in any particular diffraction mirror array spaced apart a same distance, mirrors in different diffraction mirror arrays spaced apart different distances; measuring an intensity of light diffracted from the set of at least three diffraction mirror arrays onto an array of photo detectors; and adjusting a temperature of the photomask or photomask and lens based on the measured intensity of light.

Abstract: A nitride semiconductor wafer is planar-processed by grinding a bottom surface of the wafer, etching the bottom surface by, e.g., KOH for removing a bottom process-induced degradation layer, chamfering by a rubber whetstone bonded with 100 wt %-60 wt % #3000-#600 diamond granules and 0 wt %-40 wt % oxide granules, grinding and polishing a top surface of the wafer, etching the top surface for eliminating a top process-induced degradation layer and maintaining a 0.5 ?m-10 ?m thick edge process-induced degradation layer.

Abstract: A cadmium sulfide nanocrystal, wherein the cadmium sulfide nanocrystal shows maximum luminescence peaks at two or more wavelengths and most of the atoms constituting the nanocrystal are present at the surface of the nanocrystal to form defects.

Abstract: A semiconductor nanocrystal, wherein the semiconductor nanocrystal shows maximum luminescence peaks at two or more wavelengths and most of the atoms constituting the nanocrystal are present at the surface of the nanocrystal to form defects.

Abstract: Synchronization between command and address signals commonly coupled to a plurality of memory devices to be operated in parallel and a clock signal coupled to the memory devices is achieved, while suppressing an increase in the clock wiring length. A semiconductor device has a data processing device mounted on a wiring substrate and a plurality of memory devices accessed in parallel by the data processing device. The data processing device outputs the command and address signals as a first frequency from command and address terminals, and outputs a clock signal as a second frequency from a clock terminal. The second frequency is set to multiple times of the first frequency, and an output timing equal to or earlier than a cycle starting phase of the clock signal output from the clock terminal can be selected to the command and address signals output from the command and address terminals.