Abstract: In a method for manufacturing a semiconductor device, an impurity diffusion region is formed within a semiconductor substrate. Then, a chemical dry etching process or a heating process is carried out to remove a contamination layer from the impurity diffusion region. Then, a silicon layer is selectively grown on the impurity diffusion region.

Abstract: A process for creating a capacitor structure, for a DRAM device, in which the capacitance has been increased via use of a high dielectric constant capacitor dielectric layer, and via the use of a storage node electrode, comprised of a top surface HSG layer, has been developed. The process features deposition of an HSG TiN layer, used as part of a storage node structure, resulting in an increase in storage node electrode surface area, and thus an increase in capacitance.

Abstract: A semiconductor device, comprising: an insulating layer formed on a semiconductor body; a barrier metal layer comprising titanium nitride formed on the insulating layer; and a n aluminum based alloy layer formed on the barrier metal layer, provided that the aluminum based alloy crystals constituting the aluminum based alloy layer have the crystallographic <111> axis thereof inclined by an angle of from 0 to 5 degrees with respect to the normal of the barrier metal layer on the insulating layer. Also claimed is a process for fabricating the semiconductor device.

Abstract: An oxide hard mask is formed between a deep ultraviolet photoresist and an anti-reflective coating to prevent interactions with the photoresist, thereby preventing reduction of a critical dimension of a patterned conductive layer. Embodiments include depositing a substantially nitrogen free oxide layer on the anti-reflective coating, such as a silicon oxide derived from tertaethyl orthosilicate by plasma enhanced chemical vapor deposition.

Abstract: An integrated circuit field effect transistor includes a multilayer gate electrode having a first conductive layer and a second conductive layer on the first conductive layer, wherein the second conductive layer is wider than the first conductive layer. The first conductive layer may be formed of titanium nitride and the second conductive layer may be formed of tungsten, copper and/or titanium silicide. The first conductive layer may be recessed relative to the second conductive layer by wet etching using a solution of hydrogen peroxide or hydrogen peroxide and sulfuric acid.

Abstract: A process for producing a semiconductor device comprising the steps of forming a titanium film having a (002) orientation, forming a titanium nitride film on the titanium film to such a thickness as allows the titanium nitride film to follow the orientation of the titanium film, and forming an aluminum alloy film on the titanium nitride film, thereby to form a layer structure for wiring including the aluminum alloy film having a (111) orientation.

Abstract: A new method and structure for an improved contact using doped silicon is provided. The structures are integrated into several higher level embodiments. The improved contact has low contact resistivity. Improved junctions are thus provided between an IGFET device and subsequent metallization layers. The improvements are obtained through the use of a silicon-germanium (Si--Ge) alloy. The alloy can be formed from depositing germanium onto the substrate and subsequently annealing the contact or by selectively depositing the preformed alloy into a contact opening. The above advantages are incorporated with relatively few process steps.

Abstract: A process of manufacturing a gate stack whereby the integrity of both the gate sidewalls and the substrate surface is maintained. Nitride spacers are constructed on the sidewalls of a gate which has been etched only to the top of the polysilicon layer. This allows more of the polysilicon sidewall to be exposed during subsequent reoxidation while at the same time minimizing effects such as bird's beak resulting during reoxidation. After the nitride spacers are constructed the subsequent etch is performed in two steps in order to minimize degradation of the substrate surface in underlying active regions.

Abstract: An interconnection layer extends across at least a macro cell region and at least a circuit region other than the macro cell region, the macro cell region and the circuit region being monolithically integrated into a semiconductor device, wherein the interconnection layer in the macro cell region is thinner than the interconnection layer in the circuit region.

Abstract: A method for selective conductivity etching of a silicon carbide (SiC) semiconductor includes forming a p-type SiC layer on a substrate layer, forming an n-type SiC layer on the p-type SiC layer, and photoelectrochemically etching selected portions of the n-type SiC layer by applying a bias voltage to the n-type SiC layer in a hydrofluoric acid (HF) solution while exposing the layer to a pattern of UV light. The bias potential is selected so that the n-type SiC layer will photo-corrode and the p-type SiC layer will be inert and act as an etch stop. The light pattern exposure of the n-type SiC layer may be done by applying a photolithographic mask to the layer, by projecting a collimated light beam through a patterned mask, or by scanning with a focused micrometer-sized laser beam on the semiconductor surface.

Abstract: A wiring structure of a semiconductor device buries an aperture, for example, a contact hole or via hole. The wiring structure includes a semiconductor substrate, an insulating layer formed on the semiconductor substrate and having an aperture formed therein, a diffusion barrier film formed on the inner sidewalls of the aperture and which has a smooth surface without having grain boundaries made of a refractory metal or refractory metal compound, and a metal layer formed on the diffusion barrier film. The metal layer formed on the smooth sidewalls of the diffusion barrier film is made of a uniformly and continuously formed aluminum film having an excellent step coverage. Accordingly, the method for forming the wiring structure effectively buries a contact hole having a high aspect ratio and enhances the reliability of a manufactured device.

Abstract: A method for using low dielective SiOF in a process to manufacture semiconductor products, comprising the steps of: obtaining a layer of SiOF; and depleting fluorine from a surface of the SiOF layer. In a preferred embodiment, the depleting step comprises the step of treating the surface of the layer of SiOF with a plasma containing hydrogen. It is further preferred that the treated surface be passivated. The invention also encompasses a semiconductor chip comprising an integrated circuit with at least a first and second layers, and with a dielective layer of SiOF disposed between the layers, wherein the SiOF dielective layer includes a first region at one edge thereof which is depleted of fluorine to a predetermined depth.

Abstract: An electrode structure for a semiconductor device is formed on the semiconductor device, consisting of silicon formed on a substrate to detect a physical quantity of the substrate and converting it into an electric signal, and transfers the converted electric signal to the outside. The electrode structure for the semiconductor device has a barrier layer consisting of a high-melting metal nitride and formed on a contact area of the semiconductor device and an electrode wiring formed on the barrier layer. The barrier layer has different composition ratios of the high-melting metal nitride in correspondence to each stage in the thickness of the barrier layer, in which the composition ratios are a composition ratio making a powerful bond performance at a bonding border area with the electrode wiring, and a composition ratio in which a metal element of the electrode wiring does not diffuse into the semiconductor in the barrier layer.

Abstract: Disclosed is a gate electrode stack structure that uses a refractory metal silicon nitride layer as a diffusion barrier. The gate electrode stack has several layers, including a gate oxide layer over the semiconductor substrate, a polysilicon layer over the gate oxide layer, and the diffusion barrier between the polysilicon layer and a layer of electrically conductive material above. The diffusion barrier, which is preferably composed of a substantially amorphous refractory metal silicon nitride such as tungsten silicon nitride, of does not oxidize when an oxidation process is applied to the gate electrode stack. Moreover, the diffusion barrier substantially prevents diffusion of the electrically conductive material into the polysilicon during heating processes. The refractory metal silicon nitride maintains a bulk resistivity less than 2,000 microhm-cm, thereby preserving satisfactory conductivity in the gate electrode stack.

Abstract: An integrated circuit fabrication process is provided in which copper is used as the contact plug material for a via. The via is a hole etched through an interlevel dielectric which is disposed upon a semiconductor topography, e.g., a silicon-based substrate having junctions therein. An inert implant may form an implant region within the semiconductor topography lying underneath the via. The process for forming the copper plug involves depositing a diffusion barrier upon the interlevel dielectric and within the via. Copper is then deposited via chemical vapor deposition upon the diffusion barrier such that the copper fills the entire via and forms a layer above the via. The copper is etched from all areas except from within the via, thereby forming a copper plug in the via. The resulting surface is then subjected to chemical-mechanical polishing before the diffusion barrier is removed from areas exclusive of the via.

Abstract: A semiconductor device and manufacturing method thereof having a diffusion barrier layer formed on a semiconductor wafer, whose surface region is provided with a silylation layer, wherein the silylation layer is formed on the diffusion barrier layer which is formed on the semiconductor wafer, by a plasma process using silicon hydride or by a reactive sputtering method using SiH.sub.4. When the metal layer is formed on the silylation layer, the wettability between the diffusion barrier layer and the metal is enhanced and large grains are formed, thereby increasing the step coverage for the contact hole of the metal layer or for the via hole. Additionally, when heat treatment is performed after the metal layer is formed on the silylation layer, the reflow characteristic of the metal layer becomes good, to thereby facilitate the filling of the contact hole or the via hole easy.

Abstract: A TiSi.sub.2 /TiN clad LI strap process and structure are disclosed which combine the advantages of both TiSi.sub.2 and TiN LI processes. According to the invention, the retention of a thin TiN layer between the local interconnect and contacts provides a diffusion barrier against counterdoping and relaxes the thermal budget for subsequent processing.

Abstract: A process of manufacturing a gate stack is disclosed whereby the integrity of both the gate sidewalls and the substrate surface is maintained. Nitride spacers are constructed on the sidewalls of a gate which has been etched only to the top of the polysilicon layer. This allows more of the polysilicon sidewall to be exposed during subsequent reoxidation while at the same time minimizing effects such as bird's beak resulting during reoxidation. After the nitride spacers are constructed the subsequent etch is performed in two steps in order to minimize degradation of the substrate surface in underlying active regions.

Abstract: A titanium film is formed in a contact hole defined in a silicon substrate. The titanium film is transformed into a titanium silicide film and a first titanium nitride film by high-temperature lamp anneal. Further, a second titanium nitride film is stacked on the first titanium nitride film. Conditions are applied under which the titanium nitride films are formed into a granular crystal of primarily a (200) orientation. Therefore, barrier characteristics of the titanium nitride films to silicon atoms is not compromised even in the case of a subsequent high-temperature thermal treatment.

Abstract: An integrated circuit wherein a planarization step has been performed before the primary metal deposition step, but after deposition of the adhesion and barrier layers. Thus the adhesion and barrier layers are present on the sidewalls of contact holes, but do not underlie the whole extent of the primary metallization.

Abstract: A method of manufacturing a semiconductor device includes forming a reflection reducing film on a film having a high reflectance and forming a photoresist on the first reflection reducing film. When the photoresist is patterned by selectively exposing the photoresist to an exposure light through a photomask by photolithography technology, the photoresist is not exposed by a light reflected by the film having high reflectance, thereby allowing a pattern of the photoresist to be formed which corresponds to the photomask.

Abstract: Methods are provided for the construction of metal-to-metal connections between non-adjacent layers in a structure, such as a semiconductor device. A first metal conductor layer is provided along a substrate. An anti-reflection cap is provided in overlying relation with said first conductor layer. At least a portion of the dielectric layer and the anti-reflection cap is removed to define a passage which extends from an upper surface of the dielectric layer to the first metal conductor. The passage is substantially filled with a fill metal, and a second metal conductor layer is applied over at least a portion of the dielectric layer and the substantially filled passage to electrically connect the first and second metal conductors. A diffusion liner can optionally be applied to the passage prior to application of the fill metal. The passage fill metal and second conductor layer can be integrally formed, and the fill metal and at least one of the conductor layers are formed from the same matrix metal.

Abstract: Capping a low resistivity metal conductor line or via with a refractory metal allows for effectively using chemical-mechanical polishing techniques because the hard, reduced wear, properties of the refractory metal do not scratch, corrode, or smear during chemical-mechanical polishing. Superior conductive lines and vias are created using a combination of both physical vapor deposition (e.g., evaporation or collimated sputtering) of a low resistivity metal or alloy followed by chemical vapor deposition (CVD) of a refractory metal and subsequent planarization. Altering a ratio of SiH.sub.4 to WF.sub.6 during application of the refractory metal cap by CVD allows for controlled incorporation of silicon into the tungsten capping layer. Collimated sputtering allows for creating a refractory metal liner in an opening in a dielectric which is suitable as a diffusion barrier to copper based metalizations as well as CVD tungsten.

Abstract: A barrier metal layer comprises a titanium film having a surface nitrided and modified by a nitrogen compound containing nitrogen atoms, and a titanium nitride film formed on a surface of the titanium film. The titanium film and titanium nitride film are interposed between a base layer, or a lower layer of a semiconductor device, and a metal film or an upper layer of the semiconductor device.

Abstract: Two metallization schemes of PtSi/TiW/TiW(N)/Au (Type I) and PtSi/TiW/TiW(N)/TiW/Au (Type II) and associated process are described for microcircuit interconnections. The metallization schemes and process are capable of IC-interconnections with a metal-pitch as small as 1.5 .mu.m, or even smaller. The metallization schemes are reliable for continuous high temperature and high current operations.

Abstract: Generally, according to the present invention, the sidewall of the adhesion layer (e.g. TiN 36) in a lower electrode is pre-oxidized after deposition of an unreactive noble metal layer (e.g. Pt 38) but before deposition of an HDC material (e.g. BST 42). An important aspect of the present invention is that the pre-oxidation of the sidewall generally causes a substantial amount of the potential sidewall expansion (and consequent noble metal layer deformation) to occur before deposition of the HDC material. One embodiment of the present invention is a microelectronic structure comprising a supporting layer having a principal surface, and an adhesion layer overlying the principal surface of the supporting layer, wherein the adhesion layer comprises a top surface and an expanded, oxidized sidewall (e.g. TiO.sub.2 40).

Abstract: A semiconductor apparatus having at least a compound film containing nitrogen and a method for production of the same, wherein the compound film containing nitrogen is formed under conditions where the ratio of the flow rates of the nitrogen with respect to an inert gas is 0.125 to 1.0.

Abstract: The present invention provides a conductive structure for use in semiconductor devices. The structure can be used to interconnect the various diffusion regions or electrodes of devices formed on a processed semiconductor substrate to a layer of metal, to interconnect overlying layers of metal or to provide the gate electrode of an FET device formed on the surface of a semiconductor substrate. Various embodiments of the invention are described, but in broad form the active metallurgy of the present invention comprises a thin continuous layer to titanium--titanium nitride and a thick layer of a refractory metal, e.g. tungsten, overlying the titanium nitride layer.

Abstract: A semiconductor device includes a substrate, an insulation film formed above the substrate and containing silicon-fluorine bonds, and a titanium-based metal wiring layer formed on the insulation film, the titanium-based metal wiring layer containing fluorine which is diffused from the insulation film and has a fluorine concentration of less than 1.times.10.sup.20 atoms/cm.sup.3.

Abstract: An improvement in a metal stack used for interconnecting structures in an integrated circuit. The improvement comprises the entrapping in a titanium layer of nitrogen at the interface where the titanium layer contacts a bulk conductor layer such as an aluminum-copper alloy layer. The entrapped nitrogen prevents the formation of any substantial amount of titanium aluminide thereby reducing current densities and also improving the electromigration properties of the stack. As currently preferred, the nitrogen is entrapped in approximately the first 30.ANG. of the titanium layer.

Abstract: On a p.sup.+ diffused region which is to be a lower electrode of a capacitor, a silicon nitride film which is a capacitor insulating layer is formed. An upper electrode is formed on this silicon nitride film. The upper electrode has a non-doped polycrystalline silicon film and a silicide layer. Non-doped polycrystalline silicon film is formed in contact with silicon nitride film. Silicide layer is formed on a surface of non-doped polycrystalline silicon film. Thus, a capacitor structure is obtained in which a larger capacitance and a higher breakdown voltage can be assured, so that it would not operate inaccurately even when it is integrated to a higher degree.

Abstract: A method of manufacture of a semiconductor device on a silicon semiconductor substrate comprises formation of a first stress layer on the semiconductor substrate, formation of an interconnect layer over the first stress layer, formation of a second stress layer on the interconnect layer, formation of an inter-metal dielectric (IMD) layer over the second stress layer, patterning and etching a via opening through the inter-metal dielectric layer and the second stress layer exposing a contact area on the surface of the metal interconnect layer, and heating the device at a temperature sufficient to squeeze the metal interconnect layer up into the via.

Abstract: A multilayer interconnect structure for a semiconductor device. The structure comprises a lower patterned metallization layer, a higher patterned metallization layer, and filled holes for electrically interconnecting these two layers. The two metallization layers are formed out of aluminum or an aluminum alloy by high-temperature aluminum sputtering or aluminum reflow techniques. A suction-preventing layer is formed either at the bottoms of the contact holes or on the surface of the lower metallization layer to prevent the material of the lower metallization layer from being sucked into the overlying contact holes.

Abstract: A multilevel interconnect structure which has a first horizontal metallic conductor disposed on the top of a previously formed first contact/via dielectric where the contact/via dielectric contains a contact/via hole. A horizontal interconnect is deposited over the first contact/via dielectric and has a first surface defined by the thickness and linewidth of the horizontal interconnect. A vertical metallic conductor is deposited in the contact/via hole to form a contact/via plug which extends through the dielectric and contacts the first surface of the horizontal interconnect. The process may be used to form additional levels and to form a plurality of similar horizontal and vertical metallic interconnects.

Abstract: A semiconductor memory device includes, a) a semiconductor substrate; b) a field effect transistor gate positioned outwardly of the semiconductor substrate; c) opposing active areas formed within the semiconductor substrate on opposing sides of the gate; d) a capacitor electrically connected with one of the active areas; e) a bit line; f) a dielectric insulating layer positioned intermediate the bit line and the active areas; g) a bit line plug extending through the insulating layer and electrically interconnecting the bit line with the other active area, the bit line plug comprising an electrically conductive annular ring. Integrated circuitry, beyond memory devices, utilizing an annular interconnection ring are also disclosed. Such constructions having additional radially inward insulating annular rings and conductive rings are also disclosed. A method of forming a bit line over capacitor array of memory cells having such rings is also disclosed.

Abstract: The present invention is directed to improving the throughput of the process for fabricating multilayer interconnects. Tungsten plugs, formed in contact/via openings etched in an interlayer dielectric, have been widely used in industry to form interconnection between different metal layers. An adhesion layer comprising a Ti/TiN stack is typically employed to support the adhesion of the tungsten plug in the contact/via openings. The present invention is directed to a process involving the formation of a Ti/TiN landing pad at the base of contact/via openings prior to the deposition of the interlayer dielectric. The process of the present invention enables the removal of the Ti under-layer and the reduction of the TiN thickness in the Ti/TiN stack. The throughput of the process for fabricating multilayer interconnects is thus greatly improved while the integrity of the devices are maintained.

Abstract: In a semiconductor device having a wiring groove in alignment with a contact hole, a wiring structure includes a diffusion preventing film formed on the bottom and side walls of the wiring groove, the diffusion preventing film being composed of a barrier metal for preventing diffusion of Cu and an element which cooperates with Cu so as to form a eutectic Cu-alloy having a eutectic temperature of not higher than 850.degree. C. A Cu film is formed on the diffusion preventing film so as to fill up the wiring groove, so that Cu and the above mentioned element actually form the eutectic Cu-alloy having the eutectic temperature of not higher than 850.degree. C.

Abstract: A semiconductor structure comprising two gate stacks of equal height but different composition. The two gate stacks each comprise two layers, with the first layer of each gate stack comprising the same material and the second layer of each gate stack comprising a different material. Each gate stack has an upper surface a distance `X` above the upper planar surface of a substrate of the semiconductor structure. Thus, the two gate stacks of different composition are of identical height.

Abstract: A Ti.sub.x N.sub.y layer, not necessarily stoichiometric, is interposed between a titanium or aluminum interconnect layer to improve adhesion and prevent re-entrant undercutting and lifting of the interconnect layer during the process of patterning and plasma etching to form interconnect lines on a substrate, such as an oxide.

Abstract: A barrier metal integrated circuit structure, including relatively thin, highly nitrided layers of TiW (i.e., TiW:N) straddling a central conductor layer, and in turn each being straddled by adjacent layers of relatively thick substantially un-nitrided TiW material, and a method for its fabrication including deposition of layers of TiW and TiW:N, the latter in a N.sub.2 dominated atmosphere and/or under backbias conditions effective for establishing at least a saturated level of nitrogen into the TiW:N, resulting in an effective barrier to migration of conductor materials from the conductor layer.

Abstract: A new method of fabricating a polycide gate is described. A gate polysilicon layer is provided a gate oxide layer on the surface of a substrate. A thin conducting diffusion barrier is deposited overlying the gate polysilicon layer. A of tungsten silicide is deposited overlying the thin diffusion barrier layer wherein a reaction gas in the deposition contains fluorine atoms and wherein fluorine atoms are incorporated into the tungsten layer. The gate polysilicon, thin conducting barrier, and tungsten silicide layers are patterned form the polycide gate structures. The wafer is annealed complete formation of the polycide gate structures wherein number of fluorine atoms from the tungsten silicide layer into the gate polysilicon layer are minimized by presence of the thin conducting diffusion barrier layer wherein because the diffusion of the fluorine atoms is the thickness of the gate oxide layer does not This prevents the device from degradation such as voltage shift and saturation current descrease.

Abstract: A diffusion barrier trilayer 42 is comprised of a bottom layer 44, a seed layer 46 and a top layer 48. The diffusion barrier trilayer 42 prevents reaction of metallization layer 26 with the top layer 48 upon heat treatment, resulting in improved sheet resistance and device speed.

Abstract: A multilevel interconnect structure which has a first horizontal metallic conductor disposed on the top of a previously formed first contact/via dielectric where the contact/via dielectric contains a contact/via hole. A horizontal, interconnect is deposited over the first contact/via dielectric and has a first surface defined by the thickness and linewidth of the horizontal interconnect. A vertical metallic conductor is deposited in the contact/via hole to form a contact/via plug which extends through the dielectric and contacts the first surface of the horizontal interconnect. The process may be used to form additional levels and to form a plurality of similar horizontal and vertical metallic interconnects.

Abstract: A method of manufacturing a code pattern on a semiconductor substrate with an array of substantially parallel buried bit lines integral therewith and with word lines above the buried bit lines, includes: forming a titanium nitride layer above the word lines, forming and patterning a code mask above the titanium nitride layer, implanting impurities into the substrate through openings in the code mask to form the code pattern, and performing rapid thermal annealing of the implant. The step height of the titanium nitride layer is employed to form the code identification on the substrate.

Abstract: A TiSi.sub.2 /TiN clad LI strap process and structure are disclosed which combine the advantages of both TiSi.sub.2 and TiN LI processes. According to the invention, the retention of a thin TiN layer between the local interconnect and contacts provides a diffusion barrier against counterdoping and relaxes the thermal budget for subsequent processing.

Abstract: The present invention is directed to a technology that simplifies the process of fabricating multilayer interconnects and reduces capacitance in integrated circuits employing multilayer interconnects. The novel landing pad technology of the present invention simplifies the current process steps involved in the formation of multilayer interconnects. The same contact/via etch, the same PVD TiN deposition, etc., can be modularized and repeated to build up multilayer metalization. The process of the present invention for forming multilayer interconnects involves the formation of Ti/TiN stack interconnect structures that can be used as local interconnects and contact landing pads on the same level. The contact landing pads facilitate the use of a borderless contact approach which enables a reduction in the size of the source-drain area. As the source-drain area is reduced, junction capacitance decreases, and packing density can be increased.

Abstract: An Al layer which serves as a lead-out electrode is formed on a semiconductor chip. An insulating layer is formed on the semiconductor chip and the Al layer. The insulating layer has an opening formed in that portion thereof which is located on the Al layer, thereby exposing a portion of the Al layer. A multi-level metal layer (barrier metal layer) is formed on the exposed portion of the Al layer and on that portion of the insulating layer which is located along the edge of the opening. A metallic nitride region is provided between a first-level metal layer in the multi-level metal layer and the insulating layer so as to be selectively formed at or under a peripheral portion of the first-level metal layer. A bump electrode is provided on the multi-level metal layer. The resultant semiconductor device is mounted on a circuit board by flip chip bonding, with the bump electrode interposed therebetween.

Abstract: A semiconductor having multi-layer metalization which has a metal layer between aluminum alloy and metal nitride layers, that prevents failure of interconnects when electromigration causes a discontinuity in the aluminum alloy layer. In a one embodiment, the metal of the metal layer and the metal of the nitride layer are both the same metal, such as titanium. In a method of manufacturing the semiconductor device, an insulating layer is formed on a surface of a semiconductor substrate, and in vacuum chambers, the alloy layer is formed on the insulating layer, a metal layer is formed on the alloy layer, and a metal nitride layer is formed on the metal layer in an nitrogen atmosphere. Sputtering, such as DC magnetron sputtering, RF-bias sputtering, or thermal evaporation deposition, may be used to apply the respective nitride, metal and alloy layers.

Abstract: A multilayer semiconductor structure includes a conductive via. The conductive via includes a pellet of metal having a high resistance to electromigration. The pellet is made from a conformal layer of copper or gold deposited over the via to form a copper or gold reservoir or contact located in the via. A barrier layer is provided between the reservoir and an insulating layer to prevent the pellet from diffusing into the insulating layer. The pellet can be formed by selective deposition or by etching a conformal layer. The conformal layer can be deposited by sputtering, collimated sputtering, chemical vapor deposition (CVD), dipping, evaporating, or by other means. The barrier layer and pellet may be etched by anisotropic dry etching, plasma-assisted etching, or other layer removal techniques.

Abstract: A process for applying a TiN contact/via adhesion layer to high aspect ratio contact/via openings etched in a dielectric comprises providing a first layer of TiN on the bottom of the contact/via openings and then depositing the second layer of TiN on the first layer of TiN and on the sidewalls of the contact/via openings. The second layer of TiN serves as the contact/via adhesion layer for structurally supporting the adhesion of a tungsten plug in the contact/via openings. In the case where a contact is etched in the dielectric down to a junction with a titanium silicide layer on top, the first layer of TiN on the bottom of the contact opening is provided by a rapid thermal anneal in a nitrogen-containing atmosphere which converts the top part of the titanium silicide layer in the contact into a barrier TiN layer.