With Titanium Nitride Portion Or Region Patents (Class 257/915)
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Patent number: 5623166Abstract: An aluminum-nickel-chromium (Al-Ni-Cr) layer used as an interconnect within a semiconductor device is disclosed. The Al-Ni-Cr layer has about 0.1-0.5 weight percent nickel and about 0.02-0.1 weight percent chromium. Usually, the nickel or chromium concentrations are no greater than 0.5 weight percent. The layer is resistant to electromigration and corrosion. The low nickel and chromium concentrations allow the layer to be deposited and patterned similar to most aluminum-based layers.Type: GrantFiled: December 5, 1994Date of Patent: April 22, 1997Assignee: Motorola, Inc.Inventors: Johnson O. Olowolafe, Hisao Kawasaki, Chii-Chang Lee
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Patent number: 5621681Abstract: A ferroelectric memory device of an MFIS FET structure using a yttrium oxide film as a buffer film and a manufacturing method of the memory device are provided. The MFIS FET includes a p-type silicon substrate, a field oxide film formed in a device isolation region of the silicon substrate, a gate yttrium oxide film formed on the surface of the silicon substrate, a gate ferroelectric film formed on the gate yttrium oxide film, a gate TiN electrode formed on the gate ferroelectric film, and an n-type source/drain region formed in the silicon substrate of both sides of the gate TiN electrode. In this way, single crystals of the gate yttrium oxide film are easily formed resulting in the formation of a good-quality ferroelectric film on the yttrium oxide film.Type: GrantFiled: March 22, 1996Date of Patent: April 15, 1997Assignee: Samsung Electronics Co., Ltd.Inventor: Jong Moon
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Patent number: 5621235Abstract: A TiSi.sub.2 /TiN clad LI strap process and structure are disclosed which combine the advantages of both TiSi.sub.2 and TiN LI processes. According to the invention, the retention of a thin TiN layer between the local interconnect and contacts provides a diffusion barrier against counterdoping and relaxes the thermal budget for subsequent processing.Type: GrantFiled: June 7, 1995Date of Patent: April 15, 1997Assignee: Texas Instruments IncorporatedInventor: Shin-Puu Jeng
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Patent number: 5619071Abstract: A novel high performance and reliable interconnection structure for preventing via delamination. The interconnection structure of the present invention comprises a via connection which extends into and undercuts an underlying interconnection line to lock the via connection into the interconnection line.Type: GrantFiled: August 15, 1995Date of Patent: April 8, 1997Assignee: Intel CorporationInventors: Alan M. Myers, Peter K. Charvat, Thomas A. Letson, Shi-ning Yang, Peng Bai
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Patent number: 5594278Abstract: A semiconductor device includes an inter-level insulating film formed on a semiconductor substrate. Wiring layers are formed at different depths inside the interlevel insulating film. Open aperture portions have different depths and are formed in the inter-level insulating film so as to reach each of the wiring layers. A titanium nitride film (first conductor layer) is formed on the inner surface of each of the open aperture portions and on the inter-level insulating film. A silicon oxide film (insulating film) is formed on the titanium nitride film and hardly on the inner surface of each of the open aperture portions. A tungsten film (second conductor layer) is formed inside each of the open aperture portions. An aluminum wiring (third conductor layer) is formed on the tungsten film.Type: GrantFiled: April 20, 1995Date of Patent: January 14, 1997Assignee: Nippon Steel CorporationInventor: Tomoyuki Uchiyama
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Patent number: 5592024Abstract: A semiconductor device comprises a semiconductor substrate in which a semiconductor element is formed, an interlayer insulating film formed on the semiconductor substrate, an insulating barrier layer, formed on the interlayer insulating film by plasma nitriding, for preventing diffusion of a metal constituting a wiring layer, a conductive barrier layer, formed on the insulating barrier layer, for preventing diffusion of the metal, and a wiring layer formed of the metal on the conductive barrier layer. A bottom portion of the wiring layer is protected by the conductive barrier layer and the insulating barrier layer. Therefore, the diffusion of the metal constituting the wiring layer can be surely prevented.Type: GrantFiled: October 28, 1994Date of Patent: January 7, 1997Assignee: Kabushiki Kaisha ToshibaInventors: Hisako Aoyama, Kyoichi Suguro, Hiromi Niiyama, Hitoshi Tamura, Hisataka Hayashi, Tomonori Aoyama, Gaku Minamihaba, Tadashi Iijima
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Patent number: 5589712Abstract: A semiconductor integrated circuit device includes a substrate formed with semiconductor elements and a metal wiring having a laminated structure and provided on the substrate. The metal wiring includes a first layer including aluminum as a main component, and a second layer formed on the first layer. The second layer includes titanium and nitrogen as main components. The second layer includes more titanium than nitrogen in number of atoms. A third layer may be formed between the first and second layers. The third layer includes a compound of aluminum and titanium as a main component. A fourth layer may further be formed between the second and third layers. The fourth layer includes titanium as a main component and is free of aluminum.Type: GrantFiled: December 2, 1994Date of Patent: December 31, 1996Assignee: Ricoh Company, Ltd.Inventors: Ikue Kawashima, Katsunari Hanaoka
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Patent number: 5585673Abstract: Capping a low resistivity metal conductor line or via with a refractory metal allows for effectively using chemical-mechanical polishing techniques because the hard, reduced wear, properties of the refractory metal do not scratch, corrode, or smear during chemical-mechanical polishing. Superior conductive lines and vias are created using a combination of both physical vapor deposition (e.g., evaporation or collimated sputtering) of a low resistivity metal or alloy followed by chemical vapor deposition (CVD) of a refractory metal and subsequent planarization. Altering a ratio of SiH.sub.4 to WF.sub.6 during application of the refractory metal cap by CVD allows for controlled incorporation of silicon into the tungsten capping layer. Collimated sputtering allows for creating a refractory metal liner in an opening in a dielectric which is suitable as a diffusion barrier to copper based metalizations as well as CVD tungsten.Type: GrantFiled: November 22, 1994Date of Patent: December 17, 1996Assignee: International Business Machines CorporationInventors: Rajiv V. Joshi, Jerome J. Cuomo, Hormazdyar M. Dalal, Louis L. Hsu
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Patent number: 5578872Abstract: A method is provided for patterning a submicron semiconductor layer of an integrated circuit, and an integrated circuit formed according to the same. A first conductive structure is formed over the integrated circuit. A dielectric is formed over the first conductive structure having a contact opening exposing a portion of the underlying first conductive layer. A barrier layer is formed in the bottom of the contact opening. A second, substantially conformal conductive layer is formed by chemical vapor deposition over the dielectric layer; along the sidewalls and in the bottom of the contact opening. A third conductive layer is then formed over the second conductive layer wherein the third conductive layer does not fill the contact opening. The second and third conductive layers are etched to form an interconnect substantially over the contact opening.Type: GrantFiled: April 7, 1995Date of Patent: November 26, 1996Assignee: SGS-Thomson Microelectronics, Inc.Inventors: Fusen E. Chen, Girish A. Dixit, Robert O. Miller
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Patent number: 5572071Abstract: The invention relates to a wiring structure for a semiconductor device and a method for manufacturing the same, which fills up a contact hole of below one half micron. An insulating layer is formed on a semiconductor substrate, and a contact hole is formed in the insulating layer. On the insulating layer, a first metal is deposited via a CVD method to form a CVD metal layer or a CVD metal plug filling up the contact hole. Then, the thus-obtained CVD metal layer or the CVD metal plus is heat-treated in a vacuum at a high temperature below the melting point of the first metal, thereby planarizing the surface of the CVD metal layer. A second metal is deposited via a sputtering method on the CVD metal layer or on the CVD metal plug to thereby form a sputtered metal layer. The contact hole is filled up with the first metal by the CVD method and then a reliable sputtered metal layer is deposited via a sputtering method. The wiring layer can be used for semiconductor devices of the next generation.Type: GrantFiled: June 7, 1995Date of Patent: November 5, 1996Assignee: Samsung Electronics Co., Ltd.Inventor: Sang-in Lee
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Patent number: 5572072Abstract: The invention relates to a wiring structure for a semiconductor device and a method for manufacturing the same, which fills up a contact hole of below one half micron. An insulating layer is formed on a semiconductor substrate, and a contact hole is formed in the insulating layer. On the insulating layer, a first metal is deposited via a CVD method to form a CVD metal layer or a CVD metal plug filling up the contact hole. Then, the thus-obtained CVD metal layer or the CVD metal plus is heat-treated in a vacuum at a high temperature below the melting point of the first metal, thereby planarizing the surface of the CVD metal layer. A second metal is deposited via a sputtering method on the CVD metal layer or on the CVD metal plug to thereby form a sputtered metal layer. The contact hole is filled up with the first metal by the CVD method and then a reliable sputtered metal layer is deposited via a sputtering method. The wiring layer can be used for semiconductor devices of the next generation.Type: GrantFiled: November 16, 1994Date of Patent: November 5, 1996Assignee: Samsung Electronics Co., Ltd.Inventor: Sang-in Lee
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Patent number: 5569961Abstract: The invention relates to a wiring structure for a semiconductor device and a method for manufacturing the same, which fills up a contact hole of below one half micron. An insulating layer is formed on a semiconductor substrate, and a contact hole is formed in the insulating layer. On the insulating layer, a first metal is deposited via a CVD method to form a CVD metal layer or a CVD metal plug filling up the contact hole. Then, the thus-obtained CVD metal layer or the CVD metal plus is heat-treated in a vacuum at a high temperature below the melting point of the first metal, thereby planarizing the surface of the CVD metal layer. A second metal is deposited via a sputtering method on the CVD metal layer or on the CVD metal plug to thereby form a sputtered metal layer. The contact hole is filled up with the first metal by the CVD method and then a reliable sputtered metal layer is deposited via a sputtering method. The wiring layer can be used for semiconductor devices of the next generation.Type: GrantFiled: June 7, 1995Date of Patent: October 29, 1996Assignee: Samsung Electronics Co., Ltd.Inventor: Sang-in Lee
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Patent number: 5567987Abstract: The invention relates to a wiring structure for a semiconductor device and a method for manufacturing the same, which fills up a contact hole of below one half micron. An insulating layer is formed on a semiconductor substrate, and a contact hole is formed in the insulating layer. On the insulating layer, a first metal is deposited via a CVD method to form a CVD metal layer or a CVD metal plug filling up the contact hole. Then, the thus-obtained CVD metal layer or the CVD metal plug is heat-treated in a vacuum at a high temperature below the melting point of the first metal, thereby planarizing the surface of the CVD metal layer. A second metal is deposited via a sputtering method on the CVD metal layer or on the CVD metal plug to thereby form a sputtered metal layer. The contact hole is filled up with the first metal by the CVD method and then a reliable sputtered metal layer is deposited via a sputtering method. The wiring layer can be used for semiconductor devices of the next generation.Type: GrantFiled: June 7, 1995Date of Patent: October 22, 1996Assignee: Samsung Electronics Co., Ltd.Inventor: Sang-in Lee
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Patent number: 5565708Abstract: A semiconductor device comprising conductors electrically connected through a contact hole interlayer insulation layer with a trilayer barrier layer comprising a titanium silicide layer, titanium silicide layer formed on the titanium silicide by collimation sputtering, and a thermally nitrided titanium formed on the titanium nitride layer. The use of a trilayer barrier layer enables through the capacity of the collimation sputtering apparatus to be increased, prevents particles from occurring, and formation of a low resistance electrical connection between conductors, in addition to preventing diffusion from the titanium nitride layer and the second titanium layer to the thermally nitrided titanium layer, and between conductors.Type: GrantFiled: May 15, 1995Date of Patent: October 15, 1996Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Akihiko Ohsaki, Sumio Yamaguchi, Atsushi Ishii, Kazuyoshi Maekawa, Masahiko Fujisawa
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Patent number: 5561326Abstract: An integrated circuit device includes a barrier layer as an underlying layer for a wiring conductor layer. The barrier layer is formed of titanium oxide-titanium nitride or titanium nitride or composite layers of titanium, 2-titanium nitride and titanium nitride. The barrier layer may contain oxygen or carbon. A method of manufacturing an integrated circuit device includes steps of introducing a gas to the vicinity of a substrate disposed within a vacuum chamber, and forming a titanium oxide-titanium nitride thin film or titanium nitride film or the composite film by depositing titanium in vapor phase by using a cluster-type ion source while irradiating the substrate with nitrogen ions. A thin film forming apparatus comprises a cluster type ion source and a gas ion source.Type: GrantFiled: March 30, 1995Date of Patent: October 1, 1996Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Hiroki Ito, Hisao Yoshida, Teruo Ina
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Patent number: 5554866Abstract: Generally, according to the present invention, the sidewall of the adhesion layer (e.g. TiN 36) in a lower electrode is pre-oxidized after deposition of an unreactive noble metal layer (e.g. Pt 38) but before deposition of an HDC material (e.g. BST 42). An important aspect of the present invention is that the pre-oxidation of the sidewall generally causes a substantial amount of the potential sidewall expansion (and consequent noble metal layer deformation) to occur before deposition of the HDC material. One embodiment of the present invention is a microelectronic structure comprising a supporting layer having a principal surface, and an adhesion layer overlying the principal surface of the supporting layer, wherein the adhesion layer comprises a top surface and an expanded, oxidized sidewall (e.g. TiO.sub.2 40).Type: GrantFiled: June 7, 1995Date of Patent: September 10, 1996Assignee: Texas Instruments IncorporatedInventors: Yasushiro Nishioka, Scott R. Summerfelt, Kyung-ho Park, Pijush Bhattacharya
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Patent number: 5539216Abstract: A monolithic semiconductor body (26) resides in an opening (16) formed in an insulating layer (14). The monolithic semiconductor body (26) includes an elongated region (20) filling the opening (16) in the insulating layer (14) and contacting a semiconductor region (12). The monolithic semiconductor body (26) further includes a surface region (24) overlying the elongated region (20) and a portion of the surface (22) of the insulating layer (14) adjacent to the opening (16). The monolithic semiconductor body (26) is fabricated by first depositing a layer of semiconductor material into the opening (16), then planarizing the surface of the insulating layer (14). Next, a selective deposition process is carried out to form the surface region (24) using the semiconductor material in the opening (16) as a nucleation site. The radius of curvature of the surface region (24) is determined by the amount of controlled overgrowth during the selective deposition process.Type: GrantFiled: October 27, 1994Date of Patent: July 23, 1996Assignee: Motorola, Inc.Inventors: Bich-Yen Nguyen, Marius Orlowski, Philip J. Tobin, Jim Hayden, Jack Higman
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Patent number: 5539256Abstract: A metallic interconnection has a laminate structure including a Ti film, a TiN film, a Cu--Ti compound film and a Cu alloy film containing Cu and a small amount of other metallic elements, the films being consecutively formed on a SiO.sub.2 film located on a semiconductor substrate. A W film covers the surface of the laminate structure. The Cu--Ti compound film is formed by sputtering a Ti and a Cu alloy targets followed by a subsequent heat treatment or by sputtering Cu--Ti alloy target and a subsequent heat treatment. The Cu--Ti compound film increases the adhesion force between the Cu alloy film and the TiN film while the W film protects the metallic interconnection against oxidation and corrosion.Type: GrantFiled: February 23, 1995Date of Patent: July 23, 1996Assignee: NEC CorporationInventor: Kaoru Mikagi
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Patent number: 5534730Abstract: A natural oxide film formed on an impurity region exposed in the formation of a through-hole is reduced by a titanium silicide layer formed by a CVD method. The natural oxide film is reduced at the time of forming the titanium silicide film. The silicon used for forming the titanium silicide film is supplied from a gas including silicon. Therefore, the titanium silicide film can be prevented from intruding excessively into the impurity region.Type: GrantFiled: April 19, 1995Date of Patent: July 9, 1996Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Kenichi Mori, Katsuhiro Tsukamoto
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Patent number: 5523624Abstract: A method is provided for patterning a submicron semiconductor layer of an integrated circuit, and an integrated circuit formed according to the same. A conductive structure is formed on the integrated circuit. A dielectric layer is formed over the integrated circuit. A contact opening is formed in the dielectric layer exposing a portion of the underlying first conductive structure. A barrier layer is formed on the dielectric layer and in the contact opening. A substantially conformal layer is formed over the barrier layer and in the contact opening. The conformal layer is partially etched away wherein the conformal layer remains only in a bottom portion of the contact opening. A second conductive layer is formed over the barrier layer and the remaining conformal layer.Type: GrantFiled: August 26, 1993Date of Patent: June 4, 1996Assignee: SGS-Thomson Microelectronics, Inc.Inventors: Fusen E. Chen, Robert O. Miller, Girish A. Dixit
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Patent number: 5486717Abstract: A memory cell region is provided with a pair of driver transistors as well as a pair of access transistors. Each of the access transistors is formed of a field effect transistor having a gate electrode layer. An insulating layer is formed over the driver transistors and access transistors, and is provided with contact holes located within the memory cell region and reaching the gate electrode layers. Conductive layers are formed on the insulating layer, and are in contact with the gate electrode layers through the contact holes. Thereby, a memory cell structure of an SRAM has a small planar layout area and thus is suitable to high integration.Type: GrantFiled: September 21, 1994Date of Patent: January 23, 1996Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Nobuyuki Kokubo, Kazuya Ikeda
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Patent number: 5475267Abstract: An aluminum interconnection film has a three layered structure of an aluminum alloy film, a tungsten film, and a titanium nitride film. An aluminum interconnection film and an aluminum interconnection film are electrically connected through a through hole formed in a silicon oxide film, one embodiment using a tungsten plug for the electrical connection. Because light reflectivity of the titanium nitride film is low, the exposed area of the resist can be kept within a predetermined area even if photolithography is carried out above a step where light is irregularly reflected. Therefore, it is possible to form a through hole of a desired dimension even if the through hole is formed above the step. Even if the titanium nitride film is etched and removed in forming the through hole, the aluminum alloy film is not exposed since the etching speed of the silicon oxide film is considerably slower than that of the tungsten film.Type: GrantFiled: December 8, 1994Date of Patent: December 12, 1995Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Atsushi Ishii, Yoshifumi Takata, Akihiko Ohsaki, Kazuyoshi Maekawa
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Patent number: 5459353Abstract: A first interlayer dielectric film layer is formed on a P-type semiconductor substrate. The first interlayer dielectric film is made of a BPSG film formed by the method of atmospheric pressure chemical vapor deposition. First connection holes are formed at specified positions of the first interlayer dielectric film layer. A first conductive film layer is formed in a region including at least the first connection holes. The first conductive film layer is composed of three layers by sequentially laminating a barrier metal film, an aluminum alloy film, and an anti-reflection film. On the first conductive film layer formed in a specified pattern, a second interlayer dielectric film layer is formed. The second interlayer dielectric film layer is composed of a lower layer of silicon oxide film, an intermediate layer of silicon oxide film made of inorganic silica or organic silica, and an upper layer of silicon oxide film. Specified positions of the second interlayer dielectric film layer are selectively removed.Type: GrantFiled: January 5, 1995Date of Patent: October 17, 1995Assignee: Matsushita Electronics CorporationInventor: Masato Kanazawa
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Patent number: 5442213Abstract: According to a semiconductor device and a method of manufacturing thereof, a sidewall spacer is formed at a sidewall of a contact hole, in a recess portion defined by the sidewall of the contact hole and a buried conductive layer, having a film thickness gradually increasing from a top face corner of an interlayer insulation film to the surface of the buried conductive layer. Therefore, a semiconductor device that can achieve favorable breakdown voltage and anti-leak characteristics between a lower electrode layer and an upper electrode layer forming a capacitor of a DRAM.Type: GrantFiled: June 7, 1994Date of Patent: August 15, 1995Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Tomonori Okudaira, Takeharu Kuroiwa, Nobuo Fujiwara, Keiichiro Kashihara
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Patent number: 5440173Abstract: A method for connecting a silicon substrate to an electrical component via a platinum conductor. The resulting structure may be heated in the presence of oxygen to temperatures in excess of 800.degree. C. without destroying the electrical connection between the silicon substrate and components connected to the platinum conductor. The present invention utilizes a TiN or TiW buffer layer to connect the platinum conductor to the silicon substrate. The buffer layer is deposited as a single crystal on the silicon substrate. The platinum layer is then deposited on the buffer layer. The region of the platinum layer in contact with the buffer layer is also a single crystal.Type: GrantFiled: September 17, 1993Date of Patent: August 8, 1995Assignee: Radiant TechnologiesInventors: Joseph T. Evans, Jr., Jeff A. Bullington
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Patent number: 5434448Abstract: A programmable semiconductor contact structure and method are provided. A semiconductor substrate has a first patterned conductive layer for forming an interconnect. A first insulating layer overlies the first patterned conductive layer. An opening is formed through the insulating layer to the first patterned conductive layer to form the contact via. A buffer layer overlies portions of the first insulating layer and covers the opening. A second conductive layer overlies the buffer layer. A third conductive layer then overlies the integrated circuit. The buffer layer is a material, such as amorphous silicon, which functions as an anti-fuse and can be programmed by application of a relatively high programming voltage.Type: GrantFiled: September 16, 1994Date of Patent: July 18, 1995Assignee: SGS-Thomson Microelectronics, Inc.Inventor: Che-Chia Wei
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Patent number: 5426330Abstract: A device includes a substrate, at least one dielectric layer positioned on said substrate, and metalization positioned in an opening in the at least one dielectric layer and extending a predetermined distance towards the substrate from a surface which is substantially coplanar with a surface of the at least one dielectric layer. The metalization includes a low resistivity metal or alloy encapsulated by a refractory metal or alloy having a resistivity greater than that of the low resistivity metal or alloy and having a columnar structure. The metalization has a plurality of sides in cross-section, at least three sides of the plurality of sides being substantially formed of a refractory metal or alloy having a common composition, at least two sides of the plurality of sides extending substantially the predetermined distance, and all of the plurality of sides being formed within the opening in the at least one dielectric layer.Type: GrantFiled: September 21, 1993Date of Patent: June 20, 1995Assignee: International Business Machines CorporationInventors: Rajiv V. Joshi, Jerome J. Cuomo, Hormazdyar M. Dalal, Louis L. Hsu
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Patent number: 5404047Abstract: Composite bond pad structure and geometry increases bond pad density and reduces lift-off problems. Bond pad density is increased by laying out certain non-square bond pads which are shaped, sized and oriented such that each bond pad closely conforms to the shape of the contact footprint made therewith by a bond wire or lead frame lead and aligns to the approach angle of the conductive line to which it is connected. Alternating, interleaved, complementary wedge-shaped bond pads are discussed. Bond pad liftoff is reduced by providing an upper bond pad, a lower bond pad and an insulating component between the upper and lower bond pads. At least one opening is provided through the insulating component, extending from the bottom bond pad to the upper bond pad. The at least one opening is aligned with a peripheral region of the bottom bond pad and is filled with conductive material.Type: GrantFiled: December 18, 1992Date of Patent: April 4, 1995Assignee: LSI Logic CorporationInventors: Michael D. Rostoker, Dorothy A. Heim
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Patent number: 5382817Abstract: A semiconductor device capable of improving pressure-resistant and leakage-resistant characteristics of a stacked type capacitor formed on a planarized insulating layer. The semiconductor device includes a plug electrode layer 313 of at least one material selected from the group consisting of TiN, Ti, W, and WN, buried in a contact hole 311a of an interlayer insulating films 311 and extending on and along the upper surface of interlayer insulating film 311. As a result, creation of a stepped portion on platinum layer 314 constituting a capacitor lower electrode to be formed on the plug electrode 313 is prevented, and the thickness of a PZT film 315 to be formed on platinum layer 314 is not disadvantageously made thin at the stepped portion.Type: GrantFiled: February 19, 1993Date of Patent: January 17, 1995Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Keiichiro Kashihara, Hiromi Itoh
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Patent number: 5369304Abstract: A plurality of doped areas (12, 13, 14) are formed on a surface of a semiconductor wafer. A titanium nitride layer (17) is used for covering the plurality of doped areas (12, 13, 14) and for providing electrical connection between the doped areas (12, 13, 14). The titanium nitride layer (17) substantially prevents dopants from diffusing into the titanium nitride ( 17 ) and subsequently counterdoping the doped areas (12, 13, 14) during subsequent high temperature processing operations.Type: GrantFiled: August 14, 1992Date of Patent: November 29, 1994Assignee: Motorola, Inc.Inventors: Israel A. Lesk, Francine Y. Robb, Lewis E. Terry, Frank S. d'Aragona
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Patent number: 5360996Abstract: A process is described for forming, over a silicon surface, a titanium nitride barrier layer having a surface of (111) crystallographic orientation. The process comprises: depositing a first titanium layer over a silicon surface; sputtering a titanium nitride layer over the titanium layer; depositing a second titanium layer over the sputtered titanium nitride layer; and then annealing the structure in the presence of a nitrogen-bearing gas, and in the absence of an oxygen-bearing gas, to form the desired titanium nitride having a surface of (111) crystallographic orientation and a sufficient thickness to provide protection of the underlying silicon against spiking of the aluminum. When an aluminum layer is subsequently formed over the (111) oriented titanium nitride surface, the aluminum will then assume the same (111) crystallographic orientation, resulting in an aluminum layer having enhanced resistance to electromigration.Type: GrantFiled: May 21, 1993Date of Patent: November 1, 1994Assignee: Applied Materials, Inc.Inventors: Jaim Nulman, Kenny K. Ngan
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Patent number: 5341016Abstract: A composite semiconductor structure which replaces polysilicon for conductive device elements and provides lower resistance interconnections between devices. The preferred structure is a conductive adhesion layer deposited in place of polysilicon in contact with a conductive metal layer traversing the interconnection. The preferred material for the adhesion layer is tungsten nitride, and for the metal layer--tungsten. If polysilicon is retained for device elements, the adhesion and metal layers may be placed in contact with the polysilicon element and along the interconnect structure providing an interconnect with lower resistance. Increased adhesion may be obtained by adding a cap layer of dielectric material atop the metal layer.Type: GrantFiled: June 16, 1993Date of Patent: August 23, 1994Assignee: Micron Semiconductor, Inc.Inventors: Kirk D. Prall, Gurtej S. Sandhu, Scott G. Meikle
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Patent number: 5319245Abstract: A method for fabrication of local interconnects in an integrated circuit, and an integrated circuit formed according to the same, is disclosed. According to the disclosed embodiment, a first and a second conductive structure are formed over the integrated circuit. An insulating layer is formed over the integrated. A first photoresist layer is formed over the insulating layer, patterned and developed. The insulating layer is etched to expose selected regions of the first and second conductive structures. A refractory metal layer is formed over the integrated circuit. A barrier layer is formed over the refractory metal layer, and optionally a refractory metal silicide layer is formed over the barrier layer. A second photoresist layer is formed over the barrier layer, patterned and developed.Type: GrantFiled: November 23, 1992Date of Patent: June 7, 1994Assignee: SGS-Thomson Microelectronics, Inc.Inventors: Fusen Chen, Fu-Tai Liou, Girish Dixit
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Patent number: 5313100Abstract: An aluminum interconnection film has a three layered structure of an aluminum alloy film, a tungsten film, and a titanium nitride film. An aluminum interconnection film and an aluminum interconnection film are electrically connected through a through hole formed in a silicon oxide film. Because light reflectivity of the titanium nitride film is low, the exposed area of the resist can be kept within a predetermined area even if photolithography is carried out above a step where light is irregularly reflected. Therefore, it is possible to form a through hole of a desired dimension even if the through hole is formed above the step. Even if the titanium nitride film is etched and removed in forming the through hole, the aluminum alloy film is not exposed since the etching speed of the silicon oxide film is considerably slower than that of the tungsten film. The problem of denatured layer formation and residue formation caused by exposure of aluminum alloy film does not occur.Type: GrantFiled: April 20, 1992Date of Patent: May 17, 1994Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Atsushi Ishii, Yoshifumi Takata, Akihiko Ohsaki, Kazuyoshi Maekawa
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Patent number: 5281850Abstract: A multilevel metallization structure for a semiconductor device having an antireflective film and a migration resistant film. The antireflective film is formed on a lower metallization and an dielectric inter-level film is formed on the antireflective film. The dielectric inter-level film has an opening hole for exposing the surface of the lower metallization. The migration resistant film is formed on the dielectric inter-level film and the surfaces of side walls of the opening hole. The upper metallization is formed on the migration resistant film and inside the opening hole so as to directly connect to the lower metallization.Type: GrantFiled: July 31, 1992Date of Patent: January 25, 1994Assignee: Oki Electric Industry Co., Ltd.Inventor: Jun Kanamori
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Patent number: 5268590Abstract: A CMOS device and a method for its fabrication are disclosed. In one embodiment the CMOS device includes an NMOS transistor and a PMOS transistor each of which has silicided source and drain regions and a silicon gate electrode which includes a titanium nitride barrier layer. The NMOS transistor and PMOS transistors are coupled together by a silicon layer which is capped by a layer of titanium nitride barrier material. The source and drain regions are silicided with cobalt or other metal silicide which is prevented from reacting with the silicon gate electrode and interconnect by the presence of the titanium nitride barrier layer.Type: GrantFiled: October 8, 1992Date of Patent: December 7, 1993Assignee: Motorola, Inc.Inventors: James R. Pfiester, Thomas C. Mele, Young Limb
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Patent number: 5262662Abstract: A dynamic random access memory (DRAM) storage cell having a storage contact capacitor comprising a tungsten and TiN storage node capacitor plate and the method for fabricating the same. At least a portion of the storage node capacitor plate is formed vertically in the DRAM. The TiN is controllably etched to increase the area of the storage node capacitor plate. An upper poly layer functions as the cell plate and is insulated from the storage node capacitor plate by a dielectric layer.Type: GrantFiled: August 6, 1992Date of Patent: November 16, 1993Assignee: Micron Technology, Inc.Inventors: Fernando Gonzalez, Roger R. Lee
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Patent number: 5202579Abstract: A semiconductor device having a multilayer interconnection structure includes a tungsten plug buried in a contact hole formed in an interlayer insulating film covering first aluminum interconnection with a first titanium film and a first titanium nitride film interposed therebetween, and second aluminum interconnection formed thereon with a second titanium film and a second titanium nitride film interposed therebetween. According to this structure, remaining particles of an alterated layer of aluminum formed on the surface of the first aluminum interconnection are removed, and the first aluminum interconnection reacts with the first titanium film to form an intermetallic compound, so that mixing of the interface between them is carried out. Coverage of the contact hole is improved by burying the tungsten plug.Type: GrantFiled: January 21, 1992Date of Patent: April 13, 1993Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Hiroyuki Fujii, Shigeru Harada
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Patent number: 5175608Abstract: A thin film forming method and apparatus, wherein a negative voltage is applied alternately to a target and a substrate to perform film formation and reverse sputter alternately. Further, a coil is mounted between the target and the substrate and a high frequency current is made to flow therethrough to generate plasma. A negative base voltage smaller in absolute value than that during sputter may be applied to the substrate to make Ar ions flow into the substrate while it is subjected to reverse sputter. Thus, a film whose step coverage is 0.3 or more is possible. It becomes also possible to maintain a stable discharge and perform reverse sputter in a high vacuum region. The pressure of an Ar atmosphere may be lowered to 10.sup.-3 Torr or less. An aluminum wiring film whose peak value of x-ray diffraction strength at a (111) plane is 150 Kcps or more is possible.Type: GrantFiled: August 30, 1990Date of Patent: December 29, 1992Assignee: Hitachi, Ltd.Inventors: Masayasu Nihei, Jin Onuki, Yasushi Koubuchi, Kunio Miyazaki, Tatsuo Itagaki
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Patent number: 5172211Abstract: A load resistor for use in a semiconductor integrated circuit consists of two portions of conductive material, typically strips of either a silicide or a composite polycrystalline silicon layer and silicide layer formed thereon, formed on a semiconductor substrate and separated from each other by a selected distance. An electrically conductive dopant diffusion barrier is formed on the first and second portions of conductive material. A polycrystalline silicon material is then placed on the structure such that one portion of the polycrystalline silicon material is in ohmic contact through the diffusion barrier with the first portion of conductive material and the other portion of the polycrystalline silicon material is in ohmic contact through the diffusion barrier with the second portion of conductive material. Typically the polycrystalline silicon material is placed on an insulation layer formed on the semiconductor substrate in the portion of the substrate between the two portions of conductive material.Type: GrantFiled: January 12, 1990Date of Patent: December 15, 1992Assignee: Paradigm Technology, Inc.Inventors: Norman Godinho, Frank T. W. Lee, Hsiang-Wen Chen, Richard F. Motta, Juine-Kai Tsang, Joseph Tzou, Jai-man Balk, Ting-Pwu Yen