Abstract: A method for cleaning etch residues that may include treating an etched surface with an aqueous lanthanoid solution, wherein the aqueous lanthanoid solution removes an etch residue that includes a majority of hydrocarbons and at least one element selected from the group consisting of carbon, oxygen, fluorine, nitrogen and silicon. In one example, the aqueous solution may be cerium ammonium nitrate (Ce(NH4)(NO3)),(CAN).

Abstract: Methods of treating metal-containing thin films, such as films comprising titanium carbide, with a silane/borane agent are provided. In some embodiments a film including titanium carbide is deposited on a substrate by an atomic layer deposition (ALD) process. The process may include a plurality of deposition cycles involving alternating and sequential pulses of a first source chemical that includes titanium and at least one halide ligand, a second source chemical that includes metal and carbon, where the metal and the carbon from the second source chemical are incorporated into the thin film, and a third source chemical, where the third source chemical is a silane or borane that at least partially reduces oxidized portions of the titanium carbide layer formed by the first and second source chemicals. The treatment can form a capping layer on the metal carbide film.

Abstract: Methods in accordance with this invention form a microelectronic structure by forming a carbon nano-tube (“CNT”) layer, and forming a boron nitride layer (“BN liner”) above the CNT layer, wherein the BN liner comprises: (1) a first portion disposed above and in contact with the CNT layer; and/or (2) a second portion disposed in and/or around one or more carbon nano-tubes in the CNT layer. Numerous other aspects are provided.

Abstract: A pH sensor may include a reference electrode including a p-channel field effect transistor (FET) whose gate includes a diamond surface having a hydrogen ion insensitive terminal, and a working electrode.

Abstract: One embodiment of the disclosure can provide a storage layer of a resistive memory element comprising a resistance changeable material. The resistance changeable material can include carbon. Contact layers can be provided for contacting the storage layer. The storage layer can be disposed between a bottom contact layer and a top contact layer. The resistance changeable material can be annealed at a predetermined temperature over a predetermined annealing time for rearranging an atomic order of the resistance changeable material.

Abstract: In a semiconductor diamond device, there is provided an ohmic electrode that is chemically and thermally stable and has an excellent low contact resistance and high heat resistance. A nickel-chromium alloy, or a nickel-chromium compound, containing Ni and Cr such as Ni6Cr2 or Ni72Cr18Si10, which is chemically and thermally stable, is formed on a semiconductor diamond by a sputtering process and so forth, to thereby obtain the semiconductor diamond device provided with an excellent ohmic electrode. If heat treatment is applied after forming the nickel-chromium alloy or compound, it is improved in characteristics.

Abstract: In one embodiment, a tunable resistor/transistor includes a porous material that is electrically coupled between a source electrode and a drain electrode, wherein the porous material acts as an active channel, an electrolyte solution saturating the active channel, the electrolyte solution being adapted for altering an electrical resistance of the active channel based on an applied electrochemical potential, wherein the active channel comprises nanoporous carbon arranged in a three-dimensional structure. In another embodiment, a method for forming the tunable resistor/transistor includes forming a source electrode, forming a drain electrode, and forming a monolithic nanoporous carbon material that acts as an active channel and selectively couples the source electrode to the drain electrode electrically.

Abstract: A field effect transistor device includes: a reservoir bifurcated by a membrane of three layers: two electrically insulating layers; and an electrically conductive gate between the two insulating layers. The gate has a surface charge polarity different from at least one of the insulating layers. A nanochannel runs through the membrane, connecting both parts of the reservoir. The device further includes: an ionic solution filling the reservoir and the nanochannel; a drain electrode; a source electrode; and voltages applied to the electrodes (a voltage between the source and drain electrodes and a voltage on the gate) for turning on an ionic current through the ionic channel wherein the voltage on the gate gates the transportation of ions through the ionic channel.

Abstract: Provided is a light emitting device formed of an indirect transition semiconductor configured from a semiconductor material having high exciton binding energy, wherein an active layer of the indirect transition semiconductor or an active region by a pn junction is formed, the light emitting device has an electrode for injecting current into the active layer or the active region, and the internal quantum efficiency is 10% or more.

Abstract: A method of forming a pattern structure and a method of fabricating a semiconductor device using the pattern structure, are provided the method of forming the pattern structure includes forming a mask on an underlying layer formed on a lower layer. The underlying layer is etched using the mask as an etching mask, thereby forming patterns on the lower layer. The patterns define at least one opening. A sacrificial layer is formed in the opening and the mask is removed. The sacrificial layer in the opening is partially etched when the mask is removed.

Abstract: An organic planarizing layer (OPL) is formed atop a semiconductor substrate which includes a plurality of gate lines thereon. Each gate line includes at least a high k gate dielectric and a metal gate. A patterned photoresist having at least one pattern formed therein is then positioned atop the OPL. The at least one pattern in the photoresist is perpendicular to each of the gate lines. The pattern is then transferred by etching into the OPL and portions of each of the underlying gate lines to provide a plurality of gate stacks each including at least a high k gate dielectric portion and a metal gate portion. The patterned photoresist and the remaining OPL layer are then removed utilizing a sequence of steps including first contacting with a first acid, second contacting with an aqueous cerium-containing solution, and third contacting with a second acid.

Abstract: A graphene electronic device may include a silicon substrate, connecting lines on the silicon substrate, a first electrode and a second electrode on the silicon substrate, and an interlayer dielectric on the silicon substrate. The interlayer dielectric may be configured to cover the connecting lines and the first and second electrodes and the interlayer dielectric may be further configured to expose at least a portion of the first and second electrodes. The graphene electronic device may further include an insulating layer on the interlayer dielectric and a graphene layer on the insulating layer, the graphene layer having a first end and a second end. The first end of the graphene layer may be connected to the first electrode and the second end of the graphene layer may be connected to the second electrode.

Abstract: Methods in accordance with this invention form a microelectronic structure by forming a carbon nano-tube (“CNT”) layer, and forming a carbon layer (“carbon liner”) above the CNT layer, wherein the carbon liner comprises: (1) a first portion disposed above and in contact with the CNT layer; and/or (2) a second portion disposed in and/or around one or more carbon nano-tubes in the CNT layer. Numerous other aspects are provided.

Abstract: An organic planarizing layer (OPL) is formed atop a semiconductor substrate which includes a plurality of gate lines thereon. Each gate line includes at least a high k gate dielectric and a metal gate. A patterned photoresist having at least one pattern formed therein is then positioned atop the OPL. The at least one pattern in the photoresist is perpendicular to each of the gate lines. The pattern is then transferred by etching into the OPL and portions of each of the underlying gate lines to provide a plurality of gate stacks each including at least a high k gate dielectric portion and a metal gate portion. The patterned photoresist and the remaining OPL layer are then removed utilizing a sequence of steps including first contacting with a first acid, second contacting with an aqueous cerium-containing solution, and third contacting with a second acid.

Abstract: In some aspects, a method of fabricating a memory cell is provided that includes fabricating a steering element above a substrate, and fabricating a reversible-resistance switching element coupled to the steering element by fabricating a carbon nano-tube (“CNT”) seeding layer by depositing a silicon-germanium layer above the substrate, patterning and etching the CNT seeding layer, and selectively fabricating CNT material on the CNT seeding layer. Numerous other aspects are provided.

Abstract: An organic electronic device which has stable physical properties and which allows easy production is provided. The organic electronic device has a conductive path including fine particles, a first organic semiconductor molecule which has a first conductive type and binds at least two of the fine particles together, and a second organic semiconductor molecule which has a second conductive type and is captured in a state of noncovalent bond in a molecule recognition site that exists among the fine particles.

Abstract: A method and apparatus is provided for forming a resistive memory device having good adhesion among the components thereof. A first conductive layer is formed on a substrate, and the surface of the first conductive layer is treated to add adhesion promoting materials to the surface. The adhesion promoting materials may form a layer on the surface, or they may incorporate into the surface or merely passivate the surface of the first conductive layer. A variable resistance layer is formed on the treated surface, and a second conductive layer is formed on the variable resistance layer. Adhesion promoting materials may also be included at the interface between the variable resistance layer and the second conductive layer.

Abstract: Wide bandgap devices are formed on a diamond substrate, such as for light emitting diodes as a replacement for incandescent light bulbs and fluorescent light bulbs. In one embodiment, diodes (or other devices) are formed on diamond in at least two methods. A first method comprises growing a wide bandgap material on diamond and building devices on that grown layer. The second method involves bonding a wide bandgap layer (device or film) onto diamond and building the device onto the bonded layer. These devices may provide significantly higher efficiency than incandescent or fluorescent lights, and provide significantly higher light or energy density than other technologies. Similar methods and structures result in other wide bandgap semiconductor devices.

Abstract: Nanotube switching devices having nanotube bridges are disclosed. Two-terminal nanotube switches include conductive terminals extending up from a substrate and defining a void in the substrate. Nantoube articles are suspended over the void or form a bottom surface of a void. The nanotube articles are arranged to permanently contact at least a portion of the conductive terminals. An electrical stimulus circuit in communication with the conductive terminals is used to generate and apply selected waveforms to induce a change in resistance of the device between relatively high and low resistance values. Relatively high and relatively low resistance values correspond to states of the device. A single conductive terminal and a interconnect line may be used. The nanotube article may comprise a patterned region of nanotube fabric, having an active region with a relatively high or relatively low resistance value. Methods of making each device are disclosed.

Abstract: A diamond substrate having a contact, wherein the contact comprises a diamond-like-carbon (DLC) layer on at least part of a surface of the diamond substrate; and at least one metal layer on at least part of the surface of the DLC layer. Methods for producing the same and devices comprising such a substrate are also described.

Abstract: In accordance with aspects of the invention, a method of forming a memory cell is provided, the method including forming a steering element above a substrate, and forming a memory element coupled to the steering element, wherein the memory element comprises a carbon-based material having a thickness of not more than ten atomic layers. The memory element may be formed by repeatedly performing the following steps: forming a layer of a carbon-based material, the layer having a thickness of about one monolayer, and subjecting the layer of carbon-based material to a thermal anneal. Other aspects are also described.

Abstract: A first wiring pattern is formed on a surface of a first support plate; a semiconductor chip is disposed on the first wiring pattern; and electrode terminals of the semiconductor chip are electrically connected to the first wiring pattern at required positions. Post electrodes connected to a second wiring pattern of a wiring-added post electrode component integrally connected by a second support plate are collectively fixed and electrically connected to the first wiring pattern formed on the first support plate at predetermined positions. After sealing with resin, the first and second support plates are separated; a glass substrate is affixed on a front face side; and external electrodes connected to the second wiring pattern are formed on a back face side.

Abstract: In one embodiment an anti-fuse structure is provided that includes a first dielectric material having at least a first anti-fuse region and a second anti-fuse region, wherein at least one of the anti-fuse regions includes a conductive region embedded within the first dielectric material. The anti-fuse structure further includes a first diamond like carbon layer having a first conductivity located on at least the first dielectric material in the first anti-fuse region and a second diamond like carbon layer having a second conductivity located on at least the first dielectric material in the second anti-fuse region. In this embodiment, the second conductivity is different from the first conductivity and the first diamond like carbon layer and the second diamond like carbon layer have the same thickness. The anti-fuse structure also includes a second dielectric material located atop the first and second diamond like carbon layers.

Abstract: A method of forming a pattern structure and a method of fabricating a semiconductor device using the pattern structure, are provided the method of forming the pattern structure includes forming a mask on an underlying layer formed on a lower layer. The underlying layer is etched using the mask as an etching mask, thereby forming patterns on the lower layer. The patterns define at least one opening. A sacrificial layer is formed in the opening and the mask is removed. The sacrificial layer in the opening is partially etched when the mask is removed.

Abstract: An amorphous carbon film forming apparatus includes a supporting electrode that is connected to ground and supports a substrate, a counter electrode that is disposed so as to face the supporting electrode and has a mixed-gas injection orifice, a chamber containing the supporting electrode and the counter electrode, and a DC pulse generator having a pulse source that applies a DC pulse voltage between the supporting electrode and the counter electrode. An amorphous carbon film is formed by supplying a mixed gas between the supporting electrode and the counter electrode such that the percentage of the acetylene gas relative to the carrier gas is 0.05% by volume or more and 10% by volume or less, and by generating plasma while a DC pulse voltage having a pulse width of 0.1 ?sec or more and 5.0 ?sec or less is applied to the counter electrode.

Abstract: In one aspect, a method includes forming a silicon dioxide layer on a surface of a diamond layer disposed on a gallium nitride (GaN)-type layer. The method also includes etching the silicon dioxide layer to form a pattern. The method further includes etching portions of the diamond exposed by the pattern.

Abstract: The present invention is contemplated for providing a diamond semiconductor device where an impurity-doped diamond semiconductor is buried in a selected area, and a method of manufacturing the same. That is, a diamond semiconductor device having an impurity-doped diamond area selectively buried in a recessed portion formed in a diamond substrate; and a method of manufacturing a diamond semiconductor device, including the steps of selectively forming an recessed portion on the {100}-facet diamond semiconductor substrate, wherein the bottom face of the recessed portion is surrounded by the {100} facet and the side face of the recessed portion is surrounded by the {110} facet, and forming an impurity-doped diamond area by epitaxially growing diamond in the <111> direction while doping with impurities and burying the recessed portion.

Abstract: A method for fabricating a device using an oxide semiconductor, including a process of forming the oxide semiconductor on a substrate and a process of changing the conductivity of the oxide semiconductor by irradiating a predetermined region thereof with an energy ray.

Abstract: A process for producing a carbon nanotube resistor that is capable of providing a highly reliable resistor or fuse. The process comprises the step of introducing a carbon nanotube in a volatile solvent to a first concentration and conducting ultrasonic treatment thereof to thereby obtain an initial solution; the dilution step of stepwise diluting the initial solution with a volatile solvent under ultrasonication so as to adjust the same to a second concentration, thereby obtaining a coating solution; and the step of applying the coating solution between a fist electrode and a second electrode, wherein the first concentration is 1(E10?4 g/ml or higher and the second concentration lower than 1(E10?5 g/ml.

Abstract: A method for arraying nano material includes preparing a substrate coated with a dispersion solution where nano materials are dispersed and arraying the nano materials in the dispersion solution, in a uniform direction using a charged body.

Abstract: Reduction of damage to a semiconductor device due to a marking process while inhibiting deterioration of a mark can not be achieved in conventional processes for manufacturing semiconductor devices. A process for manufacturing the semiconductor device 100 involves irradiating the marking film 21 with an energy beam through the transparent protective film 31 after the protective film 31 is formed, and such irradiation causes a chemical modification of the material of the marking film 21 to create the marks. According to the above-described process for manufacturing the semiconductor device 100, the region for the marking or the upper surface of the marking film 21 is sheathed by the protective film 31, so that a damage to the semiconductor chip 11 due to the generations of dust, exothermic heat, gas, stress or the like during the marking operation can be reduced. This allows achieving the process for manufacturing the semiconductor device 100 that provides a manufacture of better quality of the marks.

Abstract: The present invention is directed to a method for fabricating a thermal management substrate having a Silicon (Si) layer on a polycrystalline diamond film, or on a diamond-like-carbon (DLC) film. The method comprises acts of fabricating a separation by implantation of oxygen (SIMOX) wafer; depositing a polycrystalline diamond film onto the SIMOX wafer; and removing various layers of the SIMOX wafer to leave a Si overlay layer that is epitaxially fused with the polycrystalline diamond film. In the case of the DLC film, the method comprises acts of ion-implanting a Si wafer; depositing an amorphous DLC film onto the Si wafer; and removing various layers of the Si wafer to leave a Si overlay structure epitaxially fused with the DLC film.

Abstract: A method for fabricating a device using an oxide semiconductor, including a process of forming the oxide semiconductor on a substrate and a process of changing the conductivity of the oxide semiconductor by irradiating a predetermined region thereof with an energy ray.

Abstract: The invention relates to a polymer transistor arrangement, an integrated circuit arrangement and a method for producing a polymer transistor arrangement. The polymer transistor arrangement contains a polymer transistor formed in and/or on a substrate. The polymer transistor contains a first source/drain region, a second source/drain region, a channel region between the first and second source/drain regions, a gate region and a gate-insulating layer between channel region and gate region. A drive circuit of the polymer transistor arrangement is set up in such a way that it provides the source/drain regions and the gate region with electrical potentials such that the junction between at least one of the source/drain regions and the channel region can be operated as a diode.

Abstract: The invention provides a method of manufacturing a semiconductor device having a semiconductor resistor layer, which reduces a difference between a theoretical resistance value and a measured resistance value. An interlayer insulation film is formed on the whole surface of a semiconductor substrate, and then the interlayer insulation film is selectively etched to form contact holes partially exposing a polysilicon resistor layer, a source region and a drain region. The patterning size of the polysilicon resistor layer is designed by defining the lengths between the adjacent contact holes on the polysilicon resistor layer as the lengths of resistor elements. Then, ion implantation is performed to the polysilicon resistor layer through the contact holes to form low resistance regions (regions where high concentration of impurities are implanted) on the polysilicon resistor layer.

Abstract: In some aspects, a microelectronic structure is provided that includes (1) a first conducting layer; (2) a first dielectric layer formed above the first conducting layer and having a feature that exposes a portion of the first conducting layer; (3) a graphitic carbon film disposed on a sidewall of the feature defined by the first dielectric layer and in contact with the first conducting layer at a bottom of the feature; and (4) a second conducting layer disposed above and in contact with the graphitic carbon film. Numerous other aspects are provided.

Abstract: A display device able to raise a light resistance of pixel transistors without depending upon a light shielding structure and a method of production of same, wherein an average crystal grain size of a polycrystalline silicon film 111 forming an active layer of the pixel transistors is controlled to be relatively small so as to suppress a photo-leakage current. The smaller the crystal grain size, the larger the included crystal defects. Carriers excited by light irradiation are smoothly captured by a defect level, and an increase of a photo-leakage current is suppressed. On the other hand, the average crystal grain size of the polycrystalline silicon film 111 constituting the peripheral transistors is controlled so as to become relatively large. The larger the crystal grain size, the larger the mobility of the carriers, and the higher the drivability of the peripheral transistors.

Abstract: A heterostructure having a heterojunction comprising: a diamond layer; and a boron aluminum nitride (B(x)Al(1?x)N) layer disposed in contact with a surface of the diamond layer, where x is between 0 and 1.

Abstract: Integrated circuit transistors may be fabricated by simultaneously removing a photoresist layer on a first active area of an integrated circuit substrate and a carbon-containing layer on a second active area of the integrated circuit substrate, to expose a nitride stress-generating layer on the second active area. A single mask may be used to define the second active area for removal of the photoresist layer on the first active area and for implanting source/drain regions into the second active area.

Abstract: This invention discloses a manufacturing method and a structure for a chip heat dissipation. This heat dissipation structure includes a bottom plate of circuit structure, a die of central processing unit and a cap. The cover is often used in conducting the waste heat generated from the chip. The cover can be made of a special thermal conduction material, including a metal and a bracket structure of carbon element which have high thermal conductivity so as to improve the efficiency of heat conduction. The corresponding manufacturing method for this heat conduction material can be made with chemical vapor deposition, physical vapor deposition, electroplating or the other materials preparation method. The bracket structure of carbon element can be coated on the metal surface and also can be mixed into the metal.

Abstract: A method of manufacturing an array substrate of a transflective liquid crystal display is provided. Utilizing backward exposure and half-tone photo-mask to reduce the number of photo-masks used in the manufacturing process, only three to four photo-masks are used to manufacture a transflective liquid crystal display.

Abstract: The present invention is directed towards processes for covalently attaching molecular wires and molecular electronic devices to carbon nanotubes and compositions thereof. Such processes utilize diazonium chemistry to bring about this marriage of wire-like nanotubes with molecular wires and molecular electronic devices.

Abstract: The present invention provides apparatus and a method of fabricating the apparatus. The apparatus includes a substrate having a surface and an organic field-effect transistor (OFET) located adjacent the surface of the substrate. The OFET comprising a gate, a channel, a source electrode, and a drain electrode. The channel comprises a densified layer of organic molecules with conjugated multiple bonds, axes of the organic molecules being oriented substantially normal to the surface.

Abstract: A fingerprint detection device has a fingerprint sensor chip and a diamond-like carbon (DLC) film covering the outermost surface of the sensor chip. The DLC film provides sufficient strength and enhanced electrostatic discharge withstand voltage to the fingerprint sensor chip. Thus, the DLC film protects the fingerprint sensor chip without any conventional protective cover. The DLC film is less scratchable and less stainable. Since the fingerprint detection device has no protective cover, the device can be provided in a thin and compact form. In addition, the device has high reliability.

Abstract: A display device able to raise a light resistance of pixel transistors without depending upon a light shielding structure and a method of production of same, wherein an average crystal grain size of a polycrystalline silicon film 111 forming an active layer of the pixel transistors is controlled to be relatively small so as to suppress a photo-leakage current. The smaller the crystal grain size, the larger the included crystal defects. Carriers excited by light irradiation are smoothly captured by a defect level, and an increase of a photo-leakage current is suppressed. On the other hand, the average crystal grain size of the polycrystalline silicon film 111 constituting the peripheral transistors is controlled so as to become relatively large. The larger the crystal grain size, the larger the mobility of the carriers, and the higher the drivability of the peripheral transistors.