Abstract: In a described example, an apparatus includes: a semiconductor die having bond pads on a device side surface, the semiconductor die having a ground plane spaced from the bond pads by a spacing distance. The bond pads have an upper surface for receiving a ball bond, and an outer boundary, the bond pads having vertical sides extending from the upper surface to a bottom surface, the bottom surface formed over the device side surface of the semiconductor die. A protective overcoat (PO) is formed overlying the ground plane and overlying the vertical sides of the bond pads, and overlying a portion of the upper surface of the bond pads, and having an opening exposing the remaining portion of the upper surface of the bond pads, the protective overcoat having a dielectric constant of less than 3.8.

Abstract: There is provided a technique of cleaning an inside of a process container, including: (a) removing substances adhered in a process container set at a first temperature by supplying a first gas at a first flow rate into the process container and exhausting the inside of the process container; (b) physically desorbing and removing residual fluorine in the process container set at a second temperature by supplying a second gas at a second flow rate into the process container and exhausting the inside of the process container; and (c) chemically desorbing and removing residual fluorine in the process container set at a third temperature by supplying a third gas at a third flow rate into the process container and exhausting the inside of the process container.

Abstract: Systems, devices, and methods for characterizing semiconductor devices and thin film materials. The device consists of multiple probe tips that are integrated on a single substrate. The layout of the probe tips could be designed to match specific patterns on a CMOS chip or sample. The device provides for detailed studies of transport mechanisms in thin film materials and semiconductor devices.

Abstract: A system-in-package (SIP) incorporating die-in-die cavity packaging may include hybrid dies fabricated by milling or otherwise creating a cavity through the additive surfaces of a primary application specific integrated circuit (ASIC) die configured for flip-chip bonding and encapsulating a secondary die such as a Flash/non-volatile memory module, analog-digital converter (ADC), or other processing circuit into the cavity. The primary and secondary dies are then connected by the addition of redistribution layers. The resulting hybrid die may then be vertically integrated into the SIP along with additional memory modules or dies.

Abstract: A method of manufacturing a memory device including following steps is provided. A first dielectric layer and a first conductive layer are formed in order on the substrate. A first opening and a second opening on the first opening are formed in the substrate, the first dielectric layer and the first conductive layer. An isolation structure is formed in the first opening. A second dielectric layer is formed on the substrate to conformally cover a top surface of the first conductive layer and a surface of the second opening. A heat treatment is performed on the second dielectric layer to enhance the bonding between the second dielectric layer and the first conductive layer. An etching process is performed, so as to remove a portion of the second dielectric layer and expose a top surface of the isolation structure.

Abstract: Membrane transducer structures and thin-film encapsulation methods for manufacturing the same are provided. In one example, the thin film encapsulation methods may be implemented to co-integrate processes for thin-film encapsulation and formation of microelectronic devices and microelectromechanical systems (MEMS) that include the membrane transducers.

Abstract: An electronic sensor forms a grid to detect surface features of a proximally located object, such as a fingerprint. The grid includes a plurality of parallel drive lines connectable to a drive source and a plurality of parallel pickup lines oriented substantially perpendicular to the drive lines and overlapping the drive lines. The drive lines are separated from the pickup lines by an insulating dielectric layer. The overlaps where the drive lines and pickup lines cross define impedance-sensitive electrode pairs which act as pixels at which surface features of the proximally located object are detected. One or more conductive probes extend from one or more corresponding impedance-sensitive electrode pairs, through an overlay layer of insulating material, to the sensing surface.

Abstract: A pixel of a complementary metal-oxide-semiconductor (CMOS) image sensor includes a semiconductor substrate having a first surface and a third surface formed by removing part of the semiconductor substrate from a second surface, an active region which is formed between the first surface and the third surface and which contains a photoelectric conversion element generating charges in response to light incident on the substrate at the third surface, and a trench-type isolation region formed from either of the first and third surfaces to isolate the active region from an adjacent active region. The trench-type isolation region is filled with first material in a process that leaves a void in the material, the void is filled or partially filled with second material, and then a layer of third material is formed over the resulting structure composed of the first and second materials.

Abstract: A method includes providing a structure having a first, second and third hardmask layer and a mandrel layer disposed respectively over a dielectric stack. An array of mandrels, a beta trench and a gamma trench are patterned into the structure. First inner spacers are formed on sidewalls of the beta trench and second inner spacers are formed on sidewalls of the gamma trench. The first and second inner spacers form a portion of a pattern. The pattern is etched into the dielectric stack to form an array of mandrel and non-mandrel metal lines extending in a Y direction and being self-aligned in an X direction. The portion of the pattern formed by the first and second inner spacers forms a first pair of cuts in a mandrel line and a second pair of cuts in a non-mandrel line respectively. The cuts are self-aligned in the Y direction.

Abstract: The present invention relates to an ultrasound transducer device comprising at least one cMUT cell (30) for transmitting and/or receiving ultrasound waves, the cMUT cell (30) comprising a cell membrane (30a) and a cavity (30b) underneath the cell membrane. The device further comprises a substrate (10) having a first side (10a) and a second side (10b), the at least one cMUT cell (30) arranged on the first side (10a) of the substrate (10). The substrate (10) comprises a substrate base layer (12) and a plurality of adjacent trenches (17a) extending into the substrate (10) in a direction orthogonal to the substratesides (10a, 10b), wherein spacers (12a) are each formed between adjacent trenches (17a). The substrate (10) further comprises a connecting cavity (17b) which connects the trenches (17a) and which extends in a direction parallel to the substrate sides (10a, 10b), the trenches (17a) and the connecting cavity (17b) together forming a substrate cavity (17) in the substrate (10).

Abstract: A method for fabricating a semiconductor device comprises removing a portion of a substrate to form a first cavity in the substrate and depositing an insulator material in the first cavity. A sacrificial pattern is formed on a portion of the insulator material in the first cavity and the substrate. Exposed portions of the substrate are removed to form a fin in the substrate. A gate stack is formed over a portion of the fin.

Abstract: A tunnel field-effect transistor (TFET) is configured by disposing a III-V compound semiconductor nano wire on a (111) plane of a IV semiconductor substrate exhibiting p-type conductivity, and arbitrarily disposing electrodes of a source, drain and gate. Alternatively, the tunnel field-effect transistor is configured by disposing a III-V compound semiconductor nano wire on a (111) plane of a IV semiconductor substrate exhibiting n-type conductivity, and arbitrarily disposing electrodes of a source, drain and gate. The nano wire is configured from a first region and a second region. For instance, the first region is intermittently doped with a p-type dopant, and the second region is doped with an n-type dopant.

Abstract: A pixel of a complementary metal-oxide-semiconductor (CMOS) image sensor includes a semiconductor substrate having a first surface and a third surface formed by removing part of the semiconductor substrate from a second surface, an active region which is formed between the first surface and the third surface and which contains a photoelectric conversion element generating charges in response to light incident on the substrate at the third surface, and a trench-type isolation region formed from either of the first and third surfaces to isolate the active region from an adjacent active region. The trench-type isolation region is filled with first material in a process that leaves a void in the material, the void is filled or partially filled with second material, and then a layer of third material is formed over the resulting structure composed of the first and second materials.

Abstract: An ultrasonic transducer includes: a first electrode layer disposed on an upper substrate and a support; a second electrode layer which is disposed on a lower surface of the upper substrate and is separated from the first electrode layer; an upper electrode disposed on an upper surface of a membrane to contact an upper surface of the first electrode layer; a trench formed through the upper electrode, the membrane, the support, and the upper substrate; and a pad substrate disposed under the upper substrate and including bonding pads that electrically connect to the first and second electrode layers, respectively.

Abstract: There is set forth herein a method of fabricating a contact interface formation. A layer of Ti metal can be deposited on a substrate and a layer of Ni metal can be deposited over the layer of Ti metal. An annealing process can be performed to form a contact interface formation having Ti in reacted form and Ni in reacted form.

Abstract: A production method of a semiconductor element of a direct-converting x-ray detector is disclosed, wherein at least one intermediate layer is applied to a semiconductor layer and at least one contact layer is applied to an exposed intermediate layer by chemically currentless deposition of a contact material from a solution in each instance. The materials for the individual layers are selected such that the electrochemical potential of the materials of the at least one intermediate layer is greater than the electrochemical potential of at least one element of the semiconductor layer and the electrochemical potential of the contact material of the contract layer is greater than the electrochemical potential of the materials of the intermediate layers. Semiconductor elements produced in accordance with the method, an x-ray detector with semiconductor elements, an x-ray system with an x-ray detector and also a CT system with an x-ray detector are also disclosed.

Abstract: A spintronic device and a method for making said spintronic device. The spintronic device includes an epitaxial crystalline ferromagnetic oxide formed directly on the semiconductor material thereby allowing spin-polarized current to be efficiently injected from the ferromagnetic oxide into the semiconductor material. A host crystal lattice includes multiple sets of stacked oxide layers of material A and B of a perovskite structure with a formula of ABO3. After an oxide layer of B is grown, magnetic ions are introduced to intermix with the B material, which may replace some of the ions of the B material. The process of growing additional stacked oxide layers of material A and B and introducing further magnetic ions after the deposition of the oxide layer of B continues until enough magnetic ions are sufficiently close to one another that they align in the same direction thereby forming a ferromagnetic oxide on the semiconductor material.

Abstract: The present disclosure relates to a method of forming a plurality of MEMs device having a plurality of cavities with different pressures on a wafer package system, and an associated apparatus. In some embodiments, the method is performed by providing a work-piece having a plurality of microelectromechanical system (MEMs) devices. A cap wafer is bonded onto the work-piece in a first ambient environment having a first pressure. The bonding forms a plurality of cavities abutting the plurality of MEMs devices, which are held at the first pressure. One or more openings are formed in one or more of the plurality of cavities leading to a gas flow path that could be held at a pressure level different from the first pressure. The one or more openings in the one or more of the plurality of cavities are then sealed in a different ambient environment having a different pressure, thereby causing the one or more of the plurality of cavities to be held at the different pressure.

Abstract: A thin-film transistor includes a metal electrode and a zinc oxide-based barrier film that blocks a material from diffusing out of the metal electrode. The zinc oxide-based barrier film is made of zinc oxide doped with indium oxide, the content of the indium oxide ranging, by weight, 1 to 50 percent of the zinc oxide-based barrier film. A zinc oxide-based sputtering target for deposition of a barrier film of a thin-film transistor is made of zinc oxide doped with indium oxide, the content of the indium oxide ranging, by weight, 1 to 50 percent of the zinc oxide-based sputtering target.

Abstract: A method for producing a MEMS device having improved charge elimination characteristics includes providing a substrate having one or more layers, and applying a first charge elimination layer onto at least one portion of one given layer of the substrate. The method may then (1) apply a sacrificial layer onto the first charge elimination layer, (2) apply a second charge elimination layer onto at least a portion of the sacrificial layer, and (3) deposit a movable layer onto at least a portion of the second charge elimination layer. To form a structure within the movable layer the method may etch the movable layer. The method may then etch the sacrificial layer to release the structure.

Abstract: The semiconductor device has a sensor unit including a sensing part, and a semiconductor substrate. The semiconductor substrate is bonded to the sensor unit through an insulation film such that the sensing part is disposed in an air-tightly sealed chamber provided between a recessed portion of the semiconductor substrate and the sensor unit. A surface of the semiconductor substrate provided on a periphery of the recessed portion includes a boundary region at a perimeter of the recessed portion and a bonding region on a periphery of the boundary region. The bonding region has an area greater than an area of the boundary region. The bonding region of the semiconductor substrate is bonded to the sensor unit through the insulation film.

Abstract: A spintronic device and a method for making said spintronic device. The spintronic device includes an epitaxial crystalline ferromagnetic oxide formed directly on the semiconductor material thereby allowing spin-polarized current to be efficiently injected from the ferromagnetic oxide into the semiconductor material. A host crystal lattice includes multiple sets of stacked oxide layers of material A and B of a perovskite structure with a formula of ABO3. After an oxide layer of B is grown, magnetic ions are introduced to intermix with the B material, which may replace some of the ions of the B material. The process of growing additional stacked oxide layers of material A and B and introducing further magnetic ions after the deposition of the oxide layer of B continues until enough magnetic ions are sufficiently close to one another that they align in the same direction thereby forming a ferromagnetic oxide on the semiconductor material.

Abstract: A semiconductor package may include a circuit board chip having a through-hole, a semiconductor device mounted on the circuit board chip, and an encapsulant. The encapsulant encapsulates the semiconductor device, fills the through-hole and has an external pattern that is the complement of a mold within which the encapsulant was formed. The external pattern on one side of the package reflects a mold shape that retards the flow of encapsulant material relative to the flow of encapsulant material on the opposite side of the package.

Abstract: A light emitting diode (LED) package is provided. According to an embodiment, a light emitting apparatus includes a substrate; at least two distinct electrodes on the substrate; a light emitting device on one of the at least two distinct electrodes, wherein the at least two distinct electrodes are electrically separated from each other and spaced from each other; a guide unit on the substrate and around the light emitting device, wherein the guide unit includes an inner side surface, an outer side surface, a top surface and a bottom surface; and lenses including a first lens and a second lens on the substrate, wherein at least one of the lenses includes a convex shape and a portion of the at least one of the lenses is located higher than the top surface of the guide unit.

Abstract: This invention comprises a method to make small MTJ element using hybrid etching and oxygen plasma immersion ion implantation. The method has no removal of the magnetic free layer (or memory layer) and hence prevents any possible physical damage near the free layer edges. After photolithography patterning, alternative Ta, Ru, Ta etchings are performed before it stops on an MgO intermediate layer above the free layer. Then an oxygen plasma immersion ion implantation is performed to completely oxidize the exposed portion of the free layer, leaving the hard mask covered portion unchanged which define the lateral width of the MTJ element.

Abstract: An embodiment of an electronic device includes first and second semiconductor bodies. The first semiconductor body houses a first conductive strip having a first end portion and a second end portion, and houses a first conduction terminal electrically coupled to the first end portion and facing a surface of the first semiconductor body. The second semiconductor body houses a second conductive strip having a third end portion and a fourth end portion, and houses a second conduction terminal electrically coupled to the third end portion and facing a surface of the second semiconductor body. The first and second semiconductor bodies are arranged relative to one another so that the respective surfaces face one another, and the first conduction terminal and the second conduction terminal are coupled to one another by means of a conductive element so as to form a loop of an inductor.

Abstract: An exemplary embodiment of the present invention provides an organic light emitting diode, comprising a substrate, a first electrode, an organic material layer, and a second electrode, wherein a trench comprising a concave part and a convex part is provided on the substrate, the first electrode is provided on the substrate on which the trench is formed by being deposited, and an auxiliary electrode is provided on the first electrode. The organic light emitting diode according to the exemplary embodiment of the present invention may increase surface areas of the first electrode and the auxiliary electrode formed on the substrate, thereby implementing a low resistance electrode. In addition, since a line width of the electrode is not increased, it is possible to prevent a decrease of an opening ratio of the organic light emitting diode.

Abstract: The method of manufacturing a light absorbing layer for a solar cell by performing thermal treatment on a specimen configured to include thin films of one or more of copper, indium, and gallium on a substrate and element selenium, includes steps of: (a) heating a wall of a chamber up to a predefined thin film formation temperature in order to maintain a selenium vapor pressure; (b) mounting the specimen and the element selenium on the susceptor at the room temperature and loading the susceptor in the chamber; and (c) heating the specimen in the lower portion of the susceptor and, at the same time, heating the element selenium in the upper portion of the susceptor, wherein, in the step (c), in order for liquefied selenium not to be condensed on the specimen which is loaded at the room temperature and is not yet heated, the temperature of the element selenium and the specimen loaded in the chamber are individually controlled, so that the selenium vapor pressure of an inner space of the chamber does not exceed a

Abstract: A MEMS device includes a silicon substrate and a structural dielectric layer. The silicon substrate has a cavity. The structural dielectric layer is disposed on the silicon substrate. The structural dielectric layer has a space above the cavity of the silicon substrate and holds a plurality of structure elements within the space, including: a conductive backplate, over the silicon substrate, having a plurality of venting holes and a plurality of protrusion structures on top of the conductive backplate; and a diaphragm, located above the conductive backplate by a distance, wherein a chamber is formed between the diaphragm and the conductive backplate, and is connected to the cavity of the silicon substrate through the venting holes. A first side of the diaphragm is exposed by the chamber and faces to the protrusion structures of the conductive backplate and a second side of the diaphragm is exposed to an environment space.

Abstract: A method for fabricating a field effect transistor (FET) device includes forming a plurality of semiconductor fins on a substrate, removing a semiconductor fin of the plurality of semiconductor fins from a portion of the substrate, forming an isolation fin that includes a dielectric material on the substrate on the portion of the substrate, and forming a gate stack over the plurality of semiconductor fins and the isolation fin.

Abstract: Provided are methods of forming field effect transistors. The method includes preparing a substrate with a first region and a second region, forming fin portions on the first and second regions, each of the fin portions protruding from the substrate and having a first width, forming a first mask pattern to expose the fin portions on the first region and cover the fin portions on the second region, and changing widths of the fin portions provided on the first region.

Abstract: A method for manufacturing a solid-state image pickup device is provided. The image pickup apparatus includes a photoelectric conversion portion disposed on the semiconductor substrate, a first insulating film over the photoelectric conversion portion, functioning as an antireflection film, a second insulating film on the first insulating film, disposed corresponding to the photoelectric conversion portion, and a waveguide having a clad and a core whose bottom is disposed on the second insulating film. The method includes forming an opening by anisotropically etching part of a member disposed over the photoelectric conversion portion, thereby forming the clad, and forming the core in the opening. In the method, the etching is performed under conditions where the etching rate of the second insulating film is lower than the etching rate of the member.

Abstract: Some embodiments relate to method of fabricating a sensor. The method includes providing a substrate wafer that includes a suspended beam; adding an adhesive layer to the substrate wafer such that the adhesive layer covers portions of the substrate without covering the suspended beam; positioning a cover wafer onto the adhesive layer such that the suspend beam is exposed to ambient air through openings in the cover wafer; and functionalizing the suspended beam by contacting the suspended beam with materials through the opening in the cover wafer.

Abstract: Magnetic tunnel junctions (MTJ) suitable for spin transfer torque memory (STTM) devices, include perpendicular magnetic layers and one or more anisotropy enhancing layer(s) separated from a free magnetic layer by a crystallization barrier layer. In embodiments, an anisotropy enhancing layer improves perpendicular orientation of the free magnetic layer while the crystallization barrier improves tunnel magnetoresistance (TMR) ratio with better alignment of crystalline texture of the free magnetic layer with that of a tunneling layer.

Abstract: A method for forming a sensor includes forming a base-region barrier in contact with a base substrate. The base-region barrier includes a monocrystalline semiconductor having a same dopant conductivity as the base substrate. An emitter and a collector are formed in contact with and on opposite sides of the base-region barrier to form a bipolar junction transistor. The collector, the emitter and the base-region barrier are planarized to form a level surface opposite the base substrate such that when the level surface is exposed to charge, the charge is measured during operation of the bipolar junction transistor.

Abstract: An electronic MEMS device is formed by a chip having with a main face and bonded to a support via an adhesive layer. A cavity extends inside the chip from its main face and is closed by a flexible film covering the main face of the chip at least in the area of the cavity. The support has a depressed portion facing the cavity and delimited by a protruding portion facing the main face of the chip. Inside the depressed portion, the adhesive layer has a greater thickness than the projecting portion so as to be able to absorb any swelling of the flexible film as a result of the expansion of the gas contained inside the cavity during thermal processes.

Abstract: The inventive concept provides light emitting devices and methods of manufacturing a light emitting device. The light emitting device may include a transparent substrate including a first region and a second region, a first transparent electrode disposed on a first surface of the transparent substrate, a second transparent electrode facing and spaced apart from the first transparent electrode, an organic light emitting layer disposed between the first and second transparent electrodes, an assistant electrode disposed between the first and second transparent electrodes and selectively masking the second region, and a light path changing structure disposed on a second surface of the transparent substrate and selectively masking the second region.

Abstract: Device structures, fabrication methods, and design structures for tunnel field-effect transistors. A drain comprised of a first semiconductor material having a first band gap and a source comprised of a second semiconductor material having a second band gap are formed. A tunnel barrier is formed between the source and the drain. The second semiconductor material exhibits a broken-gap energy band alignment with the first semiconductor material. The tunnel barrier is comprised of a third semiconductor material with a third band gap larger than the first band gap and larger than the second band gap. The third band gap is configured to bend under an external bias to assist in aligning a first energy band of the first semiconductor material with a second energy band of the second semiconductor material.

Abstract: Method for making thin crystalline or polycrystalline layers. The method includes electrochemically etching a crystalline silicon template to form a porous double layer thereon, the double layer including a highly porous deeper layer and a less porous shallower layer. The shallower layer is irradiated with a short laser pulse selected to recrystallize the shallower layer resulting in a crystalline layer. Silicon is deposited on the recrystallized shallower layer and the silicon is irradiated with a short laser pulse selected to crystalize the silicon leaving a layer of crystallized silicon on the template. Thereafter, the layer of crystallized silicon is separated from the template. The process of the invention can be used to make optoelectronic devices.

Abstract: An optoelectronic semiconductor component includes a semiconductor layer sequence having at least one active layer, and a photonic crystal that couples radiation having a peak wavelength out of or into the semiconductor layer sequence, wherein the photonic crystal is at a distance from the active layer and formed by superimposition of at least two lattices having mutually different reciprocal lattice constants normalized to the peak wavelength.

Abstract: A light emitting diode (LED) package is provided. The LED package includes a printed circuit board (PCB), an electrode pad, an LED, a wire, and first and second moldings. The electrode pad and the LED are formed on the PCB. The wire electrically connects the LED with the electrode pad. The first molding is formed on the LED and the second molding is formed on the first molding.

Abstract: An inexpensive light emitting device and inexpensive electric equipment are provided. A substrate on which a semiconductor element or a light emitting element is formed and a color filter are manufactured by separate manufacturing processes, and they are bonded to each other to complete the light emitting device. Thus, the yield of the light emitting device is improved and the manufacture period is shortened.

Abstract: Embodiments discussed herein generally disclose novel alternative methods that can be employed to overcome the gradient stress formed in refractory materials to be used for thin film MEMS cantilever switches. The use of a ‘split layer’ cantilever fabrication method, as described herein enables thin film MEMS cantilever switches to be fabricated resulting in low operating voltage devices while maintaining the mechanical rigidity of the landing portion of the final fabricated cantilever switch.

Abstract: An optical bus (130) of an integrated circuit (100) comprises: a polymer waveguide (112), a micromirror (114, 116), and an optical coupler (120). The polymer waveguide (112) is disposed in a via (110) formed through at least one die layer (102, 104, 106) of the integrated circuit (100) comprising an active circuit (210). The micromirror (114) is disposed adjacent to the via (110) and optically coupled to the polymer waveguide (112). The optical coupler (120) is connected to the polymer waveguide (112) to couple the active circuit (210) to the optical bus (130). A stacked integrated circuit (100) is described comprising such an optical bus (130). A method (800) of fabricating a rear 45° micromirror on a silicon substrate that can be used in the optical bus (130) is also described. Furthermore, alignment/lock mechanisms for use in a stacked integrated circuit comprising first and second silicon substrates are described.

Abstract: A disclosed method of fabricating a hybrid nanopillar device includes forming a mask on a substrate and a layer of nanoclusters on the hard mask. The hard mask is then etched to transfer a pattern formed by the first layer of nanoclusters into a first region of the hard mask. A second nanocluster layer is formed on the substrate. A second region of the hard mask overlying a second region of the substrate is etched to create a second pattern in the hard mask. The substrate is then etched through the hard mask to form a first set of nanopillars in the first region of the substrate and a second set of nanopillars in the second region of the substrate. By varying the nanocluster deposition steps between the first and second layers of nanoclusters, the first and second sets of nanopillars will exhibit different characteristics.

Abstract: There is provided a semiconductor light emitting device including: a light transmissive substrate; a light emitting part; first and second electrodes electrically connected to the first and second conductivity type semiconductor layers, respectively; and a rear reflective part including a reflective metallic layer, and a light transmissive dielectric layer interposed between the light transmissive substrate and the reflective metallic layer.

Abstract: A laser processing method of converging laser light into an object to be processed made of silicon so as to form a modified region and etching the object along the modified region so as to form the object with a through hole comprises an etch resist film producing step of producing an etch resist film resistant to etching on an outer surface of the object; a laser light converging step of converging the laser light at the object after the etch resist film producing step so as to form the modified region along a part corresponding to the through hole in the object and converging the laser light at the etch resist film so as to form a defect region along a part corresponding to the through hole in the etch resist film; and an etching step of etching the object after the laser light converging step so as to advance the etching selectively along the modified region and form the through hole.

Abstract: Micro-Electro-Mechanical System (MEMS) structures, methods of manufacture and design structures are disclosed. The method includes forming at least one fixed electrode on a substrate. The method further includes forming a Micro-Electro-Mechanical System (MEMS) beam with a varying width dimension, as viewed from a top of the MEMS beam, over the at least one fixed electrode.

Abstract: A simple and cost-effective manufacturing method for hybrid integrated components including at least one MEMS element, a cap for the micromechanical structure of the MEMS element, and at least one ASIC substrate, using which a high degree of miniaturization may be achieved. The micromechanical structure of the MEMS element and the cap are manufactured in a layered structure, proceeding from a shared semiconductor substrate, by applying at least one cap layer to a first surface of the semiconductor substrate, and by processing and structuring the semiconductor substrate proceeding from its other second surface, to produce and expose the micromechanical MEMS structure. The semiconductor substrate is then mounted with the MEMS-structured second surface on the ASIC substrate.

Abstract: In a method for fabricating a semiconductor device, a conductive layer is formed on a substrate, where the substrate has a bottom layer formed thereon. A magnetic tunnel junction layer is formed on the conductive layer. The magnetic tunnel junction layer is patterned using an etching gas containing oxygen. An insulating layer is formed by oxidizing the conductive layer exposed outside the patterned magnetic tunnel junction layer using the etching gas.