Abstract: A method for manufacturing passive components is disclosed. First, a substrate is provided, and a connecting region, a capacitor region and an inductance region are defined in the substrate. The substrate includes a first metal layer and an insulating layer on the first metal layer. Subsequently, the insulating layer is etched, and then the first metal layer is etched. Thus, an outer connecting pad in the connecting region and a bottom electrode in the capacitor region are formed simultaneously, and a part of the insulating layer on the bottom electrode remains. Thereafter, a dielectric layer is deposited, and then a dual damascene copper process is performed to form an inductance structure and a top electrode of a capacitor in the dielectric layer simultaneously. Next, a passive layer is deposited and an etching process is thereafter performed to expose the outer connecting pad.

Abstract: A circuit element that may generate or be affected by noise or electromagnetic interference may be substantially surrounded by one or more encircling plugs. The encircling plug may be closed by an interconnection layer. The plug may be grounded to reduce the electromagnetic interference or noise generated by or coupled to said passive circuit element.

Abstract: An RF structure that includes an optimum padset for wire bonding and a high performance inductor that contains relatively thick metal inductor wires, both of which are located atop the final interconnect level of an interconnect structure. Specifically, the RF structure includes a dielectric layer having metal inductor wires of a first thickness and a metal bond pad having a major area of a second thickness located on a surface thereof, wherein the first thickness is greater than the second thickness. In the inventive RF structure, the majority of the metal bond pad is thinned for wire bonding, while maintaining the fill metal wire thickness in the other areas of the structure for inductor performance requirements, such as, for example, low resistivity. Methods for fabricating the aforementioned RF structure are also provided.

Abstract: A semiconductor resistor, method of making the resistor and method of making an IC including resistors. Buried wells are formed in the silicon substrate of a silicon on insulator (SOI) wafer. At least one trench is formed in the buried wells. Resistors are formed along the sidewalls of the trench and, where multiple trenches form pillars, in the pillars between the trenches by doping the sidewalls with an angled implant. Resistor contacts are formed to the buried well at opposite ends of the trenches and pillars, if any.

Abstract: A method for manufacturing an inductor according to the embodiment comprises the steps of: forming a first photoresist pattern; forming an impurity region forming the inductor by implanting an impurity ion to the substrate by means of the first photoresist pattern and a pad region applying current across the impurity region; forming a second photoresist pattern so that a position spaced by a predetermined interval from the impurity region is opened; and forming a guard impurity region in the position spaced from the impurity region by implanting the same impurity ion as the impurity ion by means of the second photoresist pattern.

Abstract: Embodiments relate to a semiconductor device and a fabrication method thereof. According to embodiments, the semiconductor device may includes a first substrate including an inductor cell, a second substrate including a RF (radio frequency) device circuit having a transistor and a wire, and a connection electrode for electrically connecting the inductor cell and the RF device circuit. The first and second substrates may be fabricated independently of each other.

Abstract: The present invention extends the above referenced continuation-in-part application by in addition creating high quality electrical components, such as inductors, capacitors or resistors, on a layer of passivation or on the surface of a thick layer of polymer. In addition, the process of the invention provides a method for mounting discrete electrical components at a significant distance removed from the underlying silicon surface.

Abstract: The present invention extends the above referenced continuation-in-part application by in addition creating high quality electrical components, such as inductors, capacitors or resistors, on a layer of passivation or on the surface of a thick layer of polymer. In addition, the process of the invention provides a method for mounting discrete electrical components at a significant distance removed from the underlying silicon surface.

Abstract: An integrated circuit chip comprising a bond wire and a mass of magnetic material provided on the bond wire, wherein the mass of magnetic material increases the inductance of the bond wire.

Abstract: An embodiment is a magnetic via. More specifically, an embodiment is a magnetic via that increases the inductance of, for example, an integrated inductor or transformer while mitigating eddy currents therein that may limit the operation of the inductor or transformer at high frequency.

Abstract: A deep n-well is formed beneath the area of an inductor coil. The use of a deep n-well lessens the parasitic capacitance by placing a diode in series with the interlayer dielectric cap. The deep n-well also reduces substrate noise. Once the n-well is implanted and annealed, a cross hatch of shallow trench isolation is patterned over the n-well. The shallow trench isolation reduces and confines the inductively coupled surface currents to small areas that are then isolated from the rest of the chip.

Abstract: A microelectronic device including, in one embodiment, a plurality of active devices located at least partially in a substrate, at least one dielectric layer located over the plurality of active devices, and an inductor located over the dielectric layer. At least one of the plurality of active devices is located within a columnar region having a cross-sectional shape substantially conforming to a perimeter of the inductor. The at least one of the plurality of active devices may be biased based on a desired Q factor of the inductor or and/or an operating frequency of the microelectronic device.

Abstract: According to one aspect of the present invention, a method is provided for forming a microelectronic assembly. The method comprises forming first and second trenches on a semiconductor substrate, filling the first and second trenches with an etch stop material, forming an inductor on the semiconductor substrate, forming an etch hole in at least one of the etch stop layer and the semiconductor substrate to expose the substrate between the first and second trenches, isotropically etching the substrate between the first and second trenches through the etch hole to create a cavity within the substrate, and forming a sealing layer over the etch hole to seal the cavity.

Abstract: A first method of reducing semiconductor device substrate effects comprising the following steps. O+or O2+are selectively implanted into a silicon substrate to form a silicon-damaged silicon oxide region. One or more devices are formed over the silicon substrate proximate the silicon-damaged silicon oxide region within at least one upper dielectric layer. A passivation layer is formed over the at least one upper dielectric layer. The passivation layer and the at least one upper dielectric layer are patterned to form a trench exposing a portion of the silicon substrate over the silicon-damaged silicon oxide region. The silicon-damaged silicon oxide region is selectively etched to form a channel continuous and contiguous with the trench whereby the channel reduces the substrate effects of the one or more semiconductor devices.

Abstract: The present invention discloses a fabrication method and structure of spiral RF inductor on porous glass substrate. Thick porous silicon layer is natively formed on a silicon wafer by anodic etching the silicon material to a high degree of porosity. The porous silicon is than thermally oxidized at high temperature converting it into porous glass texture. The oxidation rate can be rapid due to open pore character of the etched structure, which allows oxidizing agents to penetrate deeply into the wafer. If the porosity is large enough, the pores will not be sealed by the expansion of oxide during the oxidation, which results a porous structure of glass-and-air mixture of low relative dielectric constant slightly over a value of 2. The final holes appear on the wafer surface can be sealed by CVD coating step, if necessary. This ultra-flat, low-k, silicon-based substrate allows RF spiral inductor to be made on its surface with excellently low loss, or high Q value.

Abstract: A system and method is described for manufacturing an out of plane integrated circuit inductor. A plurality of parallel metal bars are formed on a substrate and covered with a first passivation layer. A ferromagnetic core is then deposited over the first passivation layer with its length perpendicular to the plurality of parallel metal bars. A second passivation layer is deposited over the ferromagnetic core and vias are etched through the passivation layers to the alternate ends of the underlying parallel metal bars. A plurality of cross connection metal bars are then formed on the second passivation layer with vertical portions that fill the vias and connect the alternate ends of the plurality of parallel metal bars to form an inductor coil. A third passivation layer is then deposited over the cross connection metal bars.

Abstract: According to one aspect of the present invention, a method is provided for forming a microelectronic assembly. The method comprises forming first and second trenches on a semiconductor substrate, filling the first and second trenches with an etch stop material, forming an inductor on the semiconductor substrate, forming an etch hole in at least one of the etch stop layer and the semiconductor substrate to expose the substrate between the first and second trenches, isotropically etching the substrate between the first and second trenches through the etch hole to create a cavity within the substrate, and forming a sealing layer over the etch hole to seal the cavity.

Abstract: A semiconductor device having a termination structure, which includes at least one spiral resistor disposed within a spiral trench and connected between two power poles of the device.

Abstract: A semiconductor device includes a semiconductor substrate including an active element or an integrated circuit and a plurality of connection electrodes to be electrically connected to the integrated circuit; a first resin layer formed on a surface of the semiconductor substrate on which the connection electrodes are formed in such a manner avoiding the connection electrodes; a connection wiring layer formed between the semiconductor substrate and the first resin layer and connected to one of the plurality of connection electrodes; a Cu wiring layer connected at one end thereof to the connection wiring layer and formed on the surface of the first resin layer; a passive element composed of the connection wiring layer and the Cu wiring layer; a second resin layer for covering a surface of the Cu wiring layer; and an external terminal electrically connected to some of the plurality of connection electrodes and formed such that a portion of the second resin layer protrudes from the second resin layer.

Abstract: An RF structure that includes an optimum padset for wire bonding and a high performance inductor that contains relatively thick metal inductor wires, both of which are located atop the final interconnect level of an interconnect structure. Specifically, the RF structure includes a dielectric layer having metal inductor wires of a first thickness and a metal bond pad having a major area of a second thickness located on a surface thereof, wherein the first thickness is greater than the second thickness. In the inventive RF structure, the majority of the metal bond pad is thinned for wire bonding, while maintaining the full metal wire thickness in the other areas of the structure for inductor performance requirements, such as, for example, low resistivity. Methods for fabricating the aforementioned RF structure are also provided.

Abstract: High quality epitaxial layers of monocrystalline materials can be grown overlying monocrystalline substrates such as large silicon wafers by forming a compliant substrate for growing the monocrystalline layers. An accommodating buffer layer comprises a layer of monocrystalline oxide spaced apart from a silicon wafer by an amorphous interface layer of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. The accommodating buffer layer is lattice matched to both the underlying silicon wafer and the overlying monocrystalline material layer. Any lattice mismatch between the accommodating buffer layer and the underlying silicon substrate is taken care of by the amorphous interface layer. In addition, formation of a compliant substrate may include utilizing surfactant enhanced epitaxy, epitaxial growth of single crystal silicon onto single crystal oxide, and epitaxial growth of Zintl phase materials.

Abstract: The present invention is an apparatus and system for reducing bondpad capacitance of an integrated circuit. Circuitry of the present invention may produce a negative capacitance approximately equal in magnitude to the capacitance associated with the bondpad and thereby effectively eliminate the bondpad capacitance. Values of the components of the circuitry may be selectively and independently chosen to synthesize a variable range of negative capacitance and thus produce a negative capacitance approximately equal in magnitude to a unique capacitance associated with the bondpad of a variety of integrated circuits.

Abstract: A method of manufacturing an integrated circuit on a semiconductor wafer. The method comprising forming a bottom plate of a capacitor 50a and a bottom portion of an induction coil 50a, forming an etch stop layer 250?, forming a ferromagnetic capacitor top plate 20a and a ferromagnetic core 20b, forming a top portion of the induction coil 50b plus vias 50c that couple the top portion of the induction coil 50b to the bottom portion of the induction coil 50c.

Abstract: An inductor and a method of forming and the inductor, the method including: (a) forming a dielectric layer on a top surface of a substrate; (b) forming a lower trench in the dielectric layer; (c) forming a resist layer on a top surface of the dielectric layer; (d) forming an upper trench in the resist layer, the upper trench aligned to the lower trench, a bottom of the upper trench open to the lower trench; and (e) completely filling the lower trench at least partially filling the upper trench with a conductor in order to form the inductor. The inductor including a top surface, a bottom surface and sidewalls, a lower portion of said inductor extending a fixed distance into a dielectric layer formed on a semiconductor substrate and an upper portion extending above said dielectric layer; and means to electrically contact said inductor.

Abstract: A high Q inductive clement with low losses, high inductance and high efficiency is disclosed. The high Q inductive element with one or more inductive loops is formed over a silicon micro structure with thin support elements formed by deep plasma etching in bulk silicon. The support elements, which may have different configurations, such as walls or columns, provide mechanical stability to the inductive loops and reduce the parasitic capacitance and the losses to the substrate.