Abstract: A semiconductor device may include a semiconductor substrate, a crack-blocking layer and a crack-blocking portion. The semiconductor substrate may include a plurality of chip regions and a scribe lane region configured to surround each of the plurality of the chip regions. A trench may be defined by one or more inner surfaces of the semiconductor device to be formed in the scribe lane region. The crack-blocking layer may be on an inner surface of the trench. The crack-blocking layer may be configured to block a spreading of a crack, which is generated in the scribe lane region during a cutting of the semiconductor substrate along the scribe lane region, from spreading into any of the chip regions. The crack-blocking portion may at least partially fill the trench and may be configured to block the spreading of the crack from the scribe lane region into any of the chip regions.

Abstract: A semiconductor device includes a semiconductor substrate; and a multilevel wiring structure on the semiconductor substrate, the multilevel wiring structure including at least an intermediate metal layer over the semiconductor substrate and an uppermost metal layer over the intermediate metal layer, and the multilevel wiring structure being divided into a main circuit portion and a scribe portion surrounding the main circuit portion; wherein the scribe portion of the multilevel wiring layer includes at least a metal pad exposed in the intermediate metal layer.

Abstract: A semiconductor device including a test pad contact and a method of manufacturing the semiconductor device are disclosed. In an embodiment, a semiconductor device may include a first metal feature and a second metal feature disposed in a single top metal layer over a substrate. A test pad may be formed over and electrically connected to the first metal feature. A first passivation layer may be formed over the second metal feature and the test pad and may cover top and side surfaces of the test pad. A first via may be formed penetrating the first passivation layer and contacting the test pad and a second via may be formed penetrating the first passivation layer and contacting the second metal feature.

Abstract: A method of processing a wafer includes a plasma etching step of supplying an etching gas in a plasma state to the wafer to remove processing strains, debris, or modified layers. The plasma etching step includes turning an etching gas into a plasma state outside of a vacuum chamber which houses the wafer therein and delivering the etching gas in the plasma state into the vacuum chamber through a supply nozzle connected to the vacuum chamber.

Abstract: An arrangement for testing integrated circuits includes an integrated test circuit and a cluster which has at least one integrated circuit and a second integrated circuit. The first integrated circuit is provided in a first component region of a wafer, and the second integrated circuit in a second component region. The first component region and the second component region are spaced a distance apart by a scribe line of the wafer. The integrated test circuit is connected to the first integrated circuit via a first test line section, and the second integrated circuit is connected to the first test line section via a first connecting line that has a first well in the semiconductor material, the first well extending continuously in the wafer from the first component region over the scribe line to the second component region, the first well being electrically insulated from a substrate of the wafer.

Abstract: A land grid array (LGA) package including a substrate having a plurality of lands formed on a first surface of the substrate, a semiconductor chip mounted on a second surface of the substrate, a connection portion connecting the semiconductor chip and the substrate, and a support layer formed on part of a surface of a first land.

Abstract: A semiconductor wafer contains a plurality of semiconductor die. A plurality of interconnect bump pads is formed over the semiconductor die. A plurality of sacrificial bump pads is formed in proximity to and diagonally offset with respect to the interconnect bump pads. The sacrificial bump pads have a different diameter than the interconnect bump pads. A conductive link is formed between each interconnect bump pad and proximate sacrificial bump pad. The sacrificial bump pads, interconnect bump pads, and conductive link are formed concurrently or during bump formation. The wafer is electrically tested by contacting the sacrificial bump pads. The electrical test identifies known good die and defective die. The sacrificial bump pads and a portion of the conductive link are removed after wafer probing. Bumps are formed over the interconnect bump pads. The semiconductor wafer can be sold or transferred to a third party after wafer probing without bumps.

Abstract: An embodiment of a die comprising: a semiconductor body including a front side, a back side, and a lateral surface; an electronic device, formed in said semiconductor body and including an active area facing the front side; a vertical conductive connection, extending through the semiconductor body and defining a conductive path between the front side and the back side of the semiconductor body; and a conductive contact, defining a conductive path on the front side of the semiconductor body, between the active area and the vertical conductive connection, wherein the vertical conductive connection is formed on the lateral surface of the die, outside the active area.

Abstract: A test pattern of a semiconductor device includes a plurality of active regions defined in a semiconductor substrate and arranged in parallel with each other, a plurality of gate patterns formed over the plurality of active regions, a plurality of gate contacts formed over the plurality of gate patterns, first junction contacts formed over respective end portions of odd-numbered active regions among the plurality of active regions, second junction contacts formed over respective end portions of even-numbered active regions among the plurality of active regions, and a contact pad configured to couple the first junction contacts and the plurality of gate contacts.

Abstract: A method of layout of pattern includes the following processes. A graphic data of a first wiring in a first area of a semiconductor wafer is extracted. The first area is a semiconductor chip forming area. The first area is surrounded by a scribed area of the semiconductor wafer. The first area includes a second area. The second area is bounded with the scribed area. The second area has a second distance from a boundary between the semiconductor chip forming area and the scribed area to an boundary between the first area and the second area. A first dummy pattern in the first area is laid out. The first dummy pattern has at least a first distance from the first wiring. A second dummy pattern in the second area is laid out. The second dummy pattern has at least the first distance from the first wiring. The second dummy pattern has at least a third distance from the first dummy pattern.

Abstract: A measuring method and device for characterizing a semiconductor component (1) having a pn junction and a measuring surface, which has a contacting subarea, covered by a metallization. The method including: A. Planar application of electromagnetic excitation radiation onto the measuring area of the semiconductor component (1) for separating charge carrier pairs in the semiconductor component (1), and B. spatially resolved measurement of electromagnetic radiation originating from the semiconductor component (1) using a detection unit. In one step A, a predetermined excitation subarea of the measuring surface has a predetermined intensity of the excitation radiation and at least one sink subarea of the measuring surface has an intensity of the excitation radiation which is less than the intensity applied to the excitation subarea. The excitation and sink subareas are disposed on opposite sides of said contacting subarea and adjoin it and/or entirely or partially overlap it.

Abstract: The disclosed WLCSP solution overcomes the limitations of fan-out WLCSP solutions, and other conventional solutions for WLCSP for small, high volume die, by increasing the width of scribe regions between die on a semiconductor substrate to accommodate bonding structures (e.g., solder balls) that partially extend beyond peripheral edges of the die. The scribe regions can be widened in x and y directions on the wafer. The widened scribe regions can be incorporated into the design of the mask set.

Abstract: A method includes providing on a substrate having at least two through substrate vias (“TSVs”) a plurality of test structures for de-embedding the measurement of the intrinsic characteristics of a device under test (DUT) including at least two of the TSVs; measuring the intrinsic characteristics [L] for a first and a second test structure on the substrate including two pads coupled with a transmission line of length L; using simultaneous solutions of ABCD matrix or T matrix form equations, and the measured intrinsic characteristics, solving for the intrinsic characteristics of the pads and the transmission lines; de-embedding the measurements of the third and fourth test structures using the intrinsic characteristics of the pads and the transmission lines; and using simultaneous solutions of ABCD matrix or T matrix form equations for BM_L and BM_LX, and the measured intrinsic characteristics, solving for the intrinsic characteristics of the TSVs.

Abstract: A semiconductor wafer having a multi-layer wiring structure is disclosed. The wafer comprises a plurality of chip die areas arranged on the wafer in an array and scribe line areas between the chip die areas. The scribe lines of a semiconductor wafer having USG top-level wiring layers above ELK wiring layers have at least one metal film structures substantially covering corner regions where two scribe lines intersect to inhibit delamination at the USG/ELK interface during wafer dicing operation.

Abstract: A process for alignment a subsequent layer over a previous layer comprising metal features or vias encapsulated in dielectric material comprising the steps of: thinning and planarizing the dielectric material to create a smooth surface of dielectric material and coplanar exposed ends of the via posts; imaging the smooth surface; discerning the position of the end of at least one feature, and using the position of the end of at least one via feature as a registration mark for aligning the subsequent layer.

Abstract: A field effect transistor (FET) having a source, a drain and a gate includes a first connection electrically connected to the gate near a first end of the gate, a second connection electrically connected to the gate near the first end of the gate, a third connection electrically connected to the gate near a second end of the gate, and a fourth connection electrically connected to the gate near the second end of the gate. By performing gate resistance measurements at different ambient temperatures, a thermal coefficient of gate resistance can be derived and then used to monitor the gate temperature, which is representative of the channel temperature.

Abstract: A semiconductor wafer has a first conductive layer formed over its active surface. A first insulating layer is formed over the substrate and first conductive layer. A second conductive layer is formed over the first conductive layer and first insulating layer. A UBM layer is formed around a bump formation area over the second conductive layer. The UBM layer can be two stacked metal layers or three stacked metal layers. The second conductive layer is exposed in the bump formation area. A second insulating layer is formed over the UBM layer and second conductive layer. A portion of the second insulating layer is removed over the bump formation area and a portion of the UBM layer. A bump is formed over the second conductive layer in the bump formation area. The bump contacts the UBM layer to seal a contact interface between the bump and second conductive layer.

Abstract: A semiconductor device in which it is possible to suppress short-circuiting between pads for chip arising from dicing processing is provided. The semiconductor device includes a semiconductor substrate, multiple first pads, and multiple second pads. The first pads are formed in an element formation region and the second pads are formed in a dicing line region surrounding the element formation region. The dicing line region includes a first region for which second pads are prone to electrically short-circuit to each other and a second region for which second pads are less prone to electrically short-circuit to each other. Some first pads arranged in positions opposite the first region are arranged farther away from one side of the outer edge of the element formation region than the remaining first pads arranged in positions opposite the second region are.

Abstract: A method for manufacturing a solid-state imaging device includes: forming pixels that receive incident light in a pixel array area of a substrate; forming pad electrodes in a peripheral area located around the pixel array area of the substrate; forming a carbon-based inorganic film on an upper surface of each of the pad electrodes including a connection surface electrically connected to an external component; forming a coated film that covers upper surfaces of the carbon-based inorganic films; and forming an opening above the connection surface of each of the pad electrodes to expose the connection surface.

Abstract: A method of manufacturing a layered chip package that includes a main body, and wiring disposed on a side surface of the main body. The main body includes a plurality of layer portions. The method includes fabricating a plurality of substructures, and completing the layered chip package by fabricating the main body using the plurality of substructures and by forming the wiring on the main body.

Abstract: A probe comprises: contact parts to be electrically connected to input/output terminals of an IC device built in a semiconductor wafer under test; interconnect parts at the front ends of which the contact parts are provided; a plurality of beam parts on the top surface of which the interconnect parts are provided along the longitudinal direction; and a base part supporting the plurality of beam parts all together in a cantilever fashion, the beam parts are supported by the base part at a rear end region of the beam parts, and grooves are provided between the adjoining beam parts in the rear end region.

Abstract: A method for fabricating and testing a wafer includes forming metal traces with metal pads, wherein forming the metal traces include forming a TiW layer on a passivation layer and on pads, next forming a seed layer on the TiW layer, next forming a photoresist layer on the seed layer, next forming a metal layer on the seed layer exposed by openings in the photoresist layer, next removing the photoresist layer, next removing the seed layer not under the metal layer, and then etching the TiW layer not under the metal layer with an etchant containing H2O2 at a temperature of between 35 and 50° C., or with an etchant containing H2O2 and with ultrasonic waves applied to the etchant, next contacting probe tips of a probe card with some of the metal pads, next cleaning the probe tips until repeating the step of contacting the probe tips with some of the metal pads at greater than 100 times, and then after cleaning the probe tips, repeating the step of contacting the probe tips with some of the metal pads.

Abstract: A method includes providing on a substrate having at least two through substrate vias (“TSVs”) a plurality of test structures for de-embedding the measurement of the intrinsic characteristics of a device under test (DUT) including at least two of the TSVs; measuring the intrinsic characteristics [L] for a first and a second test structure on the substrate including two pads coupled with a transmission line of length L; using simultaneous solutions of ABCD matrix or T matrix form equations, and the measured intrinsic characteristics, solving for the intrinsic characteristics of the pads and the transmission lines; de-embedding the measurements of the third and fourth test structures using the intrinsic characteristics of the pads and the transmission lines; and using simultaneous solutions of ABCD matrix or T matrix form equations for BM_L and BM_LX, and the measured intrinsic characteristics, solving for the intrinsic characteristics of the TSVs.

Abstract: A crack prevention ring at the exterior edge of an integrated circuit prevents delamination and cracking during the separation of the integrated circuits into individual die. The crack prevention ring extends vertically into a semiconductor workpiece to at least a metallization layer of the integrated circuit. The crack prevention ring may be formed simultaneously with the formation of test pads of the integrated circuits. The crack prevention ring may be partially or completely filled with conductive material. An air pocket may be formed within the crack prevention ring beneath a passivation layer of the integrated circuit. The crack prevention ring may be removed during the singulation process.

Abstract: The present invention relates generally to assembly techniques. According to the present invention, the alignment and probing techniques to improve the accuracy of component placement in assembly are described. More particularly, the invention includes methods and structures to detect and improve the component placement accuracy on a target platform by incorporating alignment marks on component and reference marks on target platform under various probing techniques. A set of sensors grouped in any array to form a multiple-sensor probe can detect the deviation of displaced components in assembly.

Abstract: A method of layout of pattern includes the following processes. A graphic data of a first wiring in a first area of a semiconductor wafer is extracted. The first area is a semiconductor chip forming area. The first area is surrounded by a scribed area of the semiconductor wafer. The first area includes a second area. The second area is bounded with the scribed area. The second area has a second distance from a boundary between the semiconductor chip forming area and the scribed area to an boundary between the first area and the second area. A first dummy pattern in the first area is laid out. The first dummy pattern has at least a first distance from the first wiring. A second dummy pattern in the second area is laid out. The second dummy pattern has at least the first distance from the first wiring. The second dummy pattern has at least a third distance from the first dummy pattern.

Abstract: A method of fabricating a semiconductor device, including forming a circuit block in a peripheral edge portion of a semiconductor chip, forming a circuit block pad on the circuit block to provide an electrical interface for the circuit block, and forming a bonding pad laterally offset from the circuit block and the circuit block pad, the bonding pad being electrically connected to the circuit block pad and providing a bonding wire pad for the circuit block.

Abstract: A semiconductor chip includes a semiconductor substrate; a plurality of low-k dielectric layers over the semiconductor substrate; a first passivation layer over the plurality of low-k dielectric layers; and a second passivation layer over the first passivation layer. A first seal ring is adjacent to an edge of the semiconductor chip, wherein the first seal ring has an upper surface substantially level to a bottom surface of the first passivation layer. A second seal ring is adjacent to the first seal ring and on an inner side of the semiconductor chip than the first seal ring. The second seal ring includes a pad ring in the first passivation layer and the second passivation layer. A trench ring includes at least a portion directly over the first seal ring. The trench ring extends from a top surface of the second passivation layer down to at least an interface between the first passivation layer and the second passivation layer.

Abstract: The generation of a chip identifier supporting at least one integrated circuit, which includes providing a cutout of at least one conductive path by cutting the chip, the position of the cutting line relative to the chip conditioning the identifier.

Abstract: A semiconductor wafer contains a plurality of semiconductor die. The wafer has contact pads formed over its surface. A passivation layer is formed over the wafer. A stress buffer layer is formed over the passivation layer. The stress buffer layer is patterned to expose the contact pads. A metal layer is deposited over the stress buffer layer. The metal layer is a common voltage bus for the semiconductor device in electrical contact with the contact pads. An adhesion layer, barrier layer, and seed layer is formed over the wafer in electrical contact with the contact pads. The metal layer is mounted to the seed layer. Solder bumps or other interconnect structures are formed over the metal layer. A second passivation layer is formed over the metal layer. In an alternate embodiment, a wirebondable layer can be deposited over the metal layer and wirebonds connected to the metal layer.

Abstract: A semiconductor device includes: a semiconductor element having first and second surfaces, wherein the semiconductor element includes at least one electrode, which is disposed on one of the first and second surfaces; and first and second metallic layers, wherein the first metallic layer is disposed on the first surface of the semiconductor element, and wherein the second metallic layer is disposed on the second surface of the semiconductor element. The one electrode is electrically coupled with one of the first and second metallic layers, which is disposed on the one of the first and second surfaces. The one electrode is coupled with an external circuit through the one of the first and second metallic layers.

Abstract: A semiconductor light-emitting device includes: a first semiconductor layer having a first major surface, a second major surface which is an opposite side from the first major surface, and a side surface; a second semiconductor layer provided on the second major surface of the first semiconductor layer and including a light-emitting layer; electrodes provided on the second major surface of the first semiconductor layer and on a surface of the second semiconductor layer on an opposite side from the first semiconductor layer; an insulating layer having a first surface formed on the second major surface side of the first semiconductor layer and a second surface which is an opposite side from the first surface; an external terminal which is a conductor provided on the second surface side of the insulating layer; and a phosphor layer provided on the first major surface of the first semiconductor layer and on a portion of the first surface of the insulating layer, the portion being adjacent to the side surface of t

Abstract: A semiconductor substrate has a plurality of groove portions formed along scribe lines. The semiconductor substrate includes: insulating layers formed in the plurality of groove portions; a rectangular unit region in contact with at least any one of the plurality of groove portions; and a wiring electrode including an extended terminal portion extended from the unit region to the inside of the groove portion. The semiconductor substrate is manufactured by forming a plurality of groove portions along scribe lines; embedding an insulating material in the plurality of groove portions and planarizing a surface to form insulating layers; and forming a wiring electrode including an extended terminal portion extended from a rectangular unit region in contact with at least any one of the plurality of groove portions to the inside of the groove portion.

Abstract: A semiconductor device includes a circuit block formed in a peripheral edge portion of a semiconductor chip, a circuit block pad formed on the circuit block providing an electrical connection for said circuit block, and a bonding pad laterally offset from the circuit block and the circuit block pad, the bonding pad being electrically connected to the circuit block pad and electrically connected to a lead frame by a bonding wire, the laterally offset bonding pad thereby functioning as a substitute wire bonding pad for the circuit block.

Abstract: The present disclosure provides a method for making a semiconductor device having metal gate stacks. The method includes forming a high k dielectric material layer on a semiconductor substrate; forming a metal gate layer on the high k dielectric material layer; forming a top gate layer on the metal gate layer; patterning the top gate layer, the metal gate layer and the high k dielectric material layer to form a gate stack; performing an etching process to selectively recess the metal gate layer; and forming a gate spacer on sidewalls of the gate stack.

Abstract: A process for the production of a MWT silicon solar cell comprising the steps: (1) providing a p-type silicon wafer with (i) holes forming vias between the front-side and the back-side of the wafer and (ii) an n-type emitter extending over the entire front-side and the inside of the holes, (2) applying a conductive metal paste to the holes of the silicon wafer to provide at least the inside of the holes with a metallization, (3) drying the applied conductive metal paste, and (4) firing the dried conductive metal paste, whereby the wafer reaches a peak temperature of 700 to 900° C., wherein the conductive metal paste has no or only poor fire-through capability and comprises (a) at least one particulate electrically conductive metal selected from the group consisting of silver, copper and nickel and (b) an organic vehicle.

Abstract: A probe having a sufficient height is manufactured by selectively depositing, over the main surface of a wafer, a copper film in a region in which a metal film is to be formed and a region which will be outside an adhesion ring when a probe card is fabricated; forming the metal film, polyimide film, interconnect, another polyimide film, another interconnect and a further polyimide film; and then removing the wafer and copper film. According to the present invention, when probe testing is performed using a prober (thin film probe) having the probe formed in the above-described manner while utilizing the manufacturing technology of semiconductor integrated circuit devices, it is possible to prevent breakage of the prober and a wafer to be tested.

Abstract: Multi-purpose poly edge test structure. According to an embodiment, the present invention provides a test structure. The test structure includes a doped silicon substrate, the doped silicon substrate being grounded, the doped silicon substrate including a first gate structure and a second gate structure, the first and second gate structures overlaying the doped silicon substrate. The test structure also includes a first conducting pad being electrically coupled to the first gate structure. The test structure also includes a second conducting pad being electrically coupled to the second gate structure.

Abstract: Embodiments of the invention generally provide apparatus and methods of screen printing a pattern on a substrate. In one embodiment, a patterned layer is printed onto a surface of a substrate along with a plurality of alignment marks. The locations of the alignment marks are measured with respect to a feature of the substrate to determine the actual location of the patterned layer. The actual location is compared with the expected location to determine the positional error of the patterned layer placement on the substrate. This information is used to adjust the placement of a patterned layer onto subsequently processed substrates.

Abstract: If the size of a single crystal silicon layer attached is not appropriate, even when a large glass substrate is used, the number of panels to be obtained cannot be maximized. Therefore, in the present invention, a substantially quadrangular single crystal semiconductor substrate is formed from a substantially circular single crystal semiconductor wafer, and a damaged layer is formed by irradiation with an ion beam into the single crystal semiconductor substrate. A plurality of the single crystal semiconductor substrates are arranged so as to be separated from each other over one surface of a supporting substrate. By thermal treatment, a crack is generated in the damaged layer and the single crystal semiconductor substrate is separated while a single semiconductor layer is left over the supporting substrate. After that, one or a plurality of display panels is manufactured from the single crystal semiconductor layer bonded to the supporting substrate.

Abstract: A layer sequence (400), comprising an aluminum layer (300), a nickel layer (301), and a nickel layer protection layer (302; 701). The aluminum layer (300) is formable on a substrate (200), the nickel layer (301) is formed on the aluminum layer (300), and the nickel layer protection layer (302; 701) is formed on the nickel layer (301).

Abstract: A wafer level integration module and method for fabricating are disclosed according to a construction whereby semiconductor functional device fabrication is carried out only after interconnect structures are processed on a bare wafer. The fabrication and processing include forming interconnect structures in a first side of a wafer. An insulation layer is deposited on the first side of the wafer. A conductive layer is deposited on the insulation layer so as to fill the interconnect structures and contact the insulation layer on the walls thereof. The conductive layer on the interconnect structures forms interconnection contacts on the first side of the wafer and interconnection vias extending into the wafer. The conductive layer including the interconnection contacts is exposed on the first side of the wafer. A semiconductor functional device is fabricated on the first side of the wafer and interconnected with the interconnection contacts during the fabricating.

Abstract: According to one embodiment of the present invention, a method of manufacturing a semiconductor device includes below steps. A step of preparing a phase shift mask and a normal photomask. A step of stacking a first wiring layer on a semiconductor substrate, and further stacking, on the first wiring layer, a second wiring layer. The second wiring layer includes a second wiring and third wiring. A step of stacking an interlayer insulating film on the second wiring layer. A step of forming, in the interlayer insulating film, a first opening in which the second wiring is exposed, and a second opening in which the third wiring is exposed by photolithography using the normal photomask. A step of burying a metal in the first opening and the second opening. A step of providing a pad to be overlaid on the first and second openings.

Abstract: In order to block hydrogen ions produced when forming an interlayer insulating film by HDP-CVD or the like to thereby suppress an adverse effect of the hydrogen ions on a device, in a semiconductor device including a contact layer, a metal interconnection and an interlayer insulating film on a semiconductor substrate having a gate electrode formed thereon, the interlayer insulating film is formed on the metal interconnection by bias-applied plasma CVD using source gas containing hydrogen atoms, and a silicon oxynitride film is provided in the underlayer of the metal interconnection and the interlayer insulating film.

Abstract: Bonding pad structures and integrated circuits having the same are provided. An exemplary embodiment of a bond pad structure comprises a bond pad layer. A passivation layer partially covers the bond pad layer from edges thereof and exposes a bonding surface, wherein the passivation layer is formed with a recess on at least one edge of the bonding surface to thereby define a probe needle contact area for probe needle testing and a wire bonding area for wire bonding on the bonding surface, and the probe needle contact area and the wire bonding area have a non-overlapping relationship.

Abstract: A method of fabricating a packaging structure includes cutting a panel of packaging substrate into a plurality of packaging substrate blocks each having a plurality of packaging substrate units; mounting and packaging a semiconductor chip on each of the packaging substrate unit to form package blocks each having multiple packaging structure units; and cutting package blocks to form a plurality of package units. In the method, the alignment difference between the packaging structure units in each package block is minimized by appropriately cutting and forming substrate blocks to achieve higher precision and better yield, and also packaging of semiconductor chips can be performed on all package units in the substrate blocks, thereby integrating fabrication with packaging at one time to improve production efficiency and reduce the overall costs as a result.

Abstract: Disclosed are methods for providing wafer parasitic current control to a semiconductor wafer (1240) having a substrate (1240), at least one active layer (1240) and at least one surface layer (1240), Current control can be achieved through the formation of patterns (1240) surrounding contacts (1215), said patterns (1240) including insulating implants and/or sacrificial layers formed between active devices represented by said contacts (1215). Current flows through active regions (1260) associated with said contacts (1215) and active devices. Methods of and systems for wafer level burn-in (WLBI) of semiconductor devices are also disclosed. Current control at the wafer level is important when using WLBI methods and systems.

Abstract: An electronic device has an element formed in the chip region of a substrate, a plurality of interlayer insulating films formed on the substrate, a wire formed in the interlayer insulating films in the chip region, and a plug formed in the interlayer insulating films in the chip region and connecting to the wire. A seal ring extending through the plurality of interlayer insulating films and continuously surrounding the chip region is formed in the peripheral portion of the chip region. A stress absorbing wall extending through the plurality of interlayer insulating films and discretely surrounding the seal ring is formed outside the seal ring.

Abstract: Disclosed herein is a semiconductor device, including: a semiconductor substrate; an integrated circuit formed on a first main surface of the semiconductor substrate; a penetrating electrode that penetrates the semiconductor substrate in the thickness direction and has its one end electrically connected to the integrated circuit; a bump electrode formed on a second main surface of the semiconductor substrate and electrically connected to another end of the penetrating electrode; and a test pad electrode formed on the second main surface of the semiconductor substrate and electrically connected to the bump electrode.

Abstract: A process of cleaning wire bond pads associated with OLED devices, including the steps of depositing on the wire bond pads one or more layers of ablatable material, and ablating the one or more layers with a laser, thereby exposing a clean wire bond pad.